Semiconductor equipment

Abstract

To provide a semiconductor device that can reduce leakage current.SOLUTION: A semiconductor device according to an embodiment comprises a first electrode, a first semiconductor area of a first conductivity type, a second semiconductor area of a second conductivity type, a third semiconductor area of the first conductivity type, an electric conductor, a gate electrode, and a second electrode. The electric conductor is provided in the first semiconductor area with an insulating part therebetween. The electric conductor includes a first conductive part and a second conductive part. The first conductive part has a first surface intersecting a first direction and a second surface stretching from the first surface and inclined with respect to the first surface. The second conductive part is provided on the first conductive part. In a second direction, the length of the first conductive part is longer than the length of the second conductive part. The first conductive part includes a first portion and a second portion. The first portion has the first surface and the second surface, and its length in the second direction increases toward the upper part. The second portion is provided on the first portion, and its length in the second direction decreases toward the upper part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a semiconductor device. [Background Art]

[0002] Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are used, for example, in power conversion. For semiconductor devices, reduction of leakage current is required. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Laid-Open No.2021-108322 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of reducing leakage current. [Means for Solving the Problem]

[0005] A semiconductor device according to an embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a conductor, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode and is electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on a part of the second semiconductor region. The conductor is provided in the first semiconductor region via an insulating portion. The conductor includes a first conductive portion and a second conductive portion. The first conductive portion has a first surface intersecting a first direction toward the first semiconductor region from the first electrode, and a second surface connected to the first surface and inclined with respect to the first surface. The second conductive portion is provided on the first conductive portion. In a second direction perpendicular to the first direction, the length of the first conductive portion is longer than the length of the second conductive portion. The first conductive portion includes a first part and a second part. The first portion has a first surface and a second surface, and its length in the second direction increases as it extends upward. The second portion is provided on top of the first portion, and its length in the second direction decreases as it extends upward. The gate electrode is provided in the insulating portion and faces the second semiconductor region in the second direction via a gate insulating layer. The second electrode is provided on top of the second semiconductor region and the third semiconductor region and is electrically connected to the second semiconductor region and the third semiconductor region. [Brief explanation of the drawing]

[0006] [Figure 1] This is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. [Figure 2] This is a cross-sectional view, enlarged from a portion of Figure 1. [Figure 3] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6]This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] This is a cross-sectional view showing a part of a semiconductor device related to a reference example. [Figure 8] This graph schematically illustrates the characteristics of a semiconductor device. [Figure 9] This is a perspective cross-sectional view showing a part of a semiconductor device according to a modified embodiment. [Figure 10] This is a perspective cross-sectional view showing a part of a semiconductor device according to a modified embodiment. [Modes for carrying out the invention]

[0007] Each embodiment of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n - , p + The notations "+" and "-" indicate the relative levels of each impurity concentration. Specifically, a "+" indicates a relatively higher impurity concentration than a notation without either "+" or "-", while a "-" indicates a relatively lower impurity concentration than a notation without either. When both p-type and n-type impurities are present in a given region, these notations represent the relative levels of the net impurity concentration after the impurities have compensated for each other. Each embodiment described below may be implemented by reversing the p-type and n-type of each semiconductor region.

[0008] Figure 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. As shown in Figure 1, the semiconductor device 100 according to this embodiment is n- An n-type (first conductivity type) drift region 1 (first semiconductor region), a p-type (second conductivity type) base region 2 (second semiconductor region), an n + -type source region 3 (third semiconductor region), a p + -type contact region 4, an n + -type drain region 5, a conductor 10, an insulating portion 21, a gate electrode 30, a drain electrode 41 (first electrode), and a source electrode 42 (second electrode). The semiconductor device 100 is, for example, a MOSFET.

[0009] An XYZ orthogonal coordinate system is used in the description of the embodiment. The direction from the drain electrode 41 toward the n - -type drift region 1 is defined as the Z direction (first direction). One direction orthogonal to the Z direction is defined as the X direction (second direction). A direction orthogonal to both the X direction and the Z direction is defined as the Y direction. In addition, the direction from the drain electrode 41 toward the n - -type drift region 1 is referred to as "up", and the opposite direction is referred to as "down". These directions are based on the relative positional relationship between the drain electrode 41 and the n - -type drift region 1, and are unrelated to the direction of gravity.

[0010] The drain electrode 41 is provided on the lower surface of the semiconductor device 100. The n + -type drain region 5 is provided on the drain electrode 41 and is electrically connected to the drain electrode 41. The n - -type drift region 1 is provided on the n + -type drain region 5. The n-type impurity concentration in the n - -type drift region 1 is lower than the n-type impurity concentration in the n + -type drain region 5. The n - -type drift region 1 is electrically connected to the drain electrode 41 via the n + -type drain region 5.

[0011] The p-type base region 2 is provided on the n - -type drift region 1. The n + -type source region 3 is provided on a part of the p-type base region 2. The p +The p-shaped contact region 4 is located on another part of the p-shaped base region 2. + The concentration of p-type impurities in the contact region 4 is higher than the concentration of p-type impurities in the p-type base region 2.

[0012] The conductor 10 is connected to the insulating portion 21 via n - It is provided in the drift region 1. The gate electrode 30 is provided in the insulating portion 21 and is located on the conductor 10. The gate electrode 30 is provided in the insulating portion 21 and faces the p-type base region 2 in the X direction via the gate insulating layer 31. The gate insulating layer 31 is part of the insulating portion 21. In the illustrated example, the gate electrode 30 is n - Part of the shape drift region 1 and n + It also faces a portion of the shape source region 3.

[0013] The source electrode 42 is n + Shape source region 3 and p + The shape is provided on the contact area 4, n + Shape source region 3 and p + It is electrically connected to the contact region 4. In the illustrated example, a portion of the source electrode 42 extends downward, and a pair of n are aligned in the X direction. + It is provided between the p-shaped source regions 3. The p-shaped base region 2 is p + The gate electrode 30 is electrically connected to the source electrode 42 via the contact region 4. The gate electrode 30 is electrically isolated from the source electrode 42 by the gate insulating layer 31.

[0014] p-type base region 2, n + Shape source region 3, p + Each of the contact region 4, the conductor 10, and the gate electrode 30 extends in the Y direction, and multiple portions are provided in the X direction. The Y-direction end of the conductor 10 is pulled upward and electrically connected to the source electrode 42. Alternatively, the insulating portion 21 may not be provided between the conductor 10 and the gate electrode 30, and the conductor 10 may be electrically connected to the gate electrode 30.

[0015] Figure 2 is an enlarged cross-sectional view of a portion of Figure 1. As shown in Figure 2, the lower surface of the conductor 10 includes a first surface S1, a second surface S2, and a third surface S3. The first surface S1 is parallel to the XY plane. The second surface S2 and the third surface S3 are connected to the first surface S1 and are inclined with respect to the X and Z directions. The position of the first surface S1 in the X direction is between the position of the second surface S2 in the X direction and the position of the third surface S3 in the X direction.

[0016] The conductor 10 more specifically includes a first conductive portion 11, a second conductive portion 12, and a third conductive portion 13. The first conductive portion 11 is located at the lower end of the conductor 10. The second conductive portion 12 is provided on top of the first conductive portion 11. The third conductive portion 13 is provided on top of the second conductive portion 12.

[0017] The first conductive portion 11 has a first surface S1 to a third surface S3. The width (length in the X direction) W1 of the first conductive portion 11 is longer than the width W2 of the second conductive portion 12. The width W2 of the second conductive portion 12 is shorter than the width W3 of the third conductive portion 13. The width W2 of the second conductive portion 12 may be the same as the width W3 of the third conductive portion 13.

[0018] The first conductive portion 11 includes a first portion 11a and a second portion 11b. The first portion 11a has first surfaces S1 to third surfaces S3. The second portion 11b is provided on top of the first portion 11a. The width of the first portion 11a increases towards the top. The width of the second portion 11b decreases towards the top. For example, the length of the first portion 11a in the Z direction is shorter than the length of the second portion 11b in the Z direction.

[0019] As shown in the diagram, a void V may be provided in the first conductive portion 11. The void V provided in the first conductive portion 11 extends in the Y direction. Alternatively, multiple voids V may be scattered in the Y direction.

[0020] The operation of the semiconductor device 100 will be explained. With a positive voltage applied to the drain electrode 41 relative to the source electrode 42, a voltage above a threshold is applied to the gate electrode 30. This forms a channel (inversion layer) in the p-type base region 2, and the semiconductor device 100 turns on. Electrons flow through the channel from the source electrode 42 to the drain electrode 41. When the voltage applied to the gate electrode 30 falls below the threshold, the channel in the p-type base region 2 disappears, and the semiconductor device 100 turns off.

[0021] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 41 relative to the source electrode 42 increases. At this time, the potential difference between the drain electrode 41 and the source electrode 42, or the potential difference between the drain electrode 41 and the gate electrode 30, causes the insulating part 21 and n - From the interface with the shape drift region 1, n - The depletion layer expands toward the drift region 1. This expansion of the depletion layer can increase the breakdown voltage of the semiconductor device 100. Alternatively, while maintaining the breakdown voltage of the semiconductor device 100, n - By increasing the n-type impurity concentration in the drift region 1, the on-resistance of the semiconductor device 100 can be reduced.

[0022] An example of the materials used for each component of the semiconductor device 100 will be described. n - Shape drift region 1, p-shaped base region 2, n + Shape source region 3, p + Shaped contact area 4, and n + The drain region 5 contains a semiconductor material. As the semiconductor material, silicon, silicon carbide, gallium nitride, or gallium arsenide can be used. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity.

[0023] The insulating portion 21 includes an insulating material. For example, the insulating portion 21 includes silicon oxide, silicon nitride, or silicon oxynitride. The conductor 10 and the gate electrode 30 include a conductive material such as polysilicon. The conductor 10 and the gate electrode 30 may have n-type or p-type impurities added to them. The drain electrode 41 and the source electrode 42 include a metal such as titanium, tungsten, or aluminum.

[0024] Figures 3 to 6 are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. Referring to Figures 3 to 6, an example of a method for manufacturing the semiconductor device 100 according to this embodiment will be described. First, n + A semiconductor substrate Sub containing a shaped semiconductor layer 5a is prepared. As shown in Figure 3(a), n + By epitaxially growing silicon on the shaped semiconductor layer 5a, n - A shaped semiconductor layer 1a is formed.

[0025] As shown in Figure 3(b), n is produced by photolithography and reactive ion etching (RIE). - Multiple trenches T1 are formed on the upper surface of the semiconductor layer 1a. During RIE execution, an anisotropic, slow etching gas is used. This allows the lower surface of the trenches T1 to be curved. On this curved surface, silicon {100} planes, {110} planes, etc., are exposed. Sulfur hexafluoride (SF6) can be used as the etching gas.

[0026] As shown in Figure 4(a), n -An insulating layer 21a is formed along the upper surface of the semiconductor layer 1a and the inner surface of the trench T1. The insulating layer 21a is formed by thermal oxidation. During this process, oxidation proceeds along the

[0100] and

[0110] directions of silicon. As a result, a flat surface S1a, an inclined surface S2a, and an inclined surface S3a are formed on the lower surface of the trench T2 surrounded by the insulating layer 21a. The {100} plane of silicon oxide is exposed on the flat surface S1a. The {110} plane of silicon oxide is exposed on the inclined surfaces S2a and S3a. In addition, when the insulating layer 21a is formed, the width of the bottom of the trench T2 becomes wider than that of the top. This is thought to be due to the stress during thermal oxidation, as will be described later.

[0027] For silicon and silicon oxide, the {100} plane represents one of the equivalent (100), (010), or (001) planes. Similarly, the {110} plane represents one of the equivalent (110), (011), or (101) planes.

[0028] A conductive layer 10a is formed on the insulating layer 21a to fill the trenches T2. The conductive layer 10a is formed by chemical vapor deposition (CVD) of a conductive material such as polysilicon. During the formation of the conductive layer 10a, a void V is formed at the bottom of the trenches T2. A portion of the conductive layer 10a is removed by chemical dry etching (CDE) or the like to recess the upper surface of the conductive layer 10a. This forms multiple conductive layers 10a, each separated and provided within the multiple trenches T2. As shown in Figure 4(b), an insulating layer 21b is formed on the insulating layer 21a and the multiple conductive layers 10a by CVD. The conductive layer 10a has a first surface S1 that is in contact with a flat surface S1a. The conductive layer 10a also has a second surface S2 and a third surface S3 that are in contact with inclined surfaces S2a and S3a, respectively.

[0029] Wet etching causes the upper surfaces of insulating layer 21a and insulating layer 21b to recede. This results in n - The upper surface of the semiconductor layer 1a and a portion of the side surface of the trench T1 are exposed. Due to thermal oxidation, the exposed n -An insulating layer 31a is formed on the upper surface of the semiconductor layer 1a and on the side surface of the trench T1. The thickness of the insulating layer 31a is less than the thickness of the insulating layer 21a. A conductive layer 30a is formed on top of the insulating layer 31a. As shown in Figure 5(a), the upper surface of the conductive layer 30a is recessed by CDE or wet etching, and the conductive layer 30a is formed inside each trench T1.

[0030] between trench T1s - p-type and n-type impurities are sequentially ion-implanted into the upper part of the p-type semiconductor layer 1a, forming a p-type semiconductor region 2a and n + A semiconductor region 3a is formed. As shown in Figure 5(b), an insulating layer 31b is formed to cover multiple conductive layers 30a.

[0031] insulating layer 31b, insulating layer 31a, and n + An aperture OP is formed that penetrates the p-type semiconductor region 3a and reaches the p-type semiconductor region 2a. P-type impurities are ion-implanted into the p-type semiconductor region 2a through the aperture OP, as shown in Figure 6(a), p + A shaped semiconductor region 4a is formed.

[0032] A metal layer 42a is formed on the insulating layer 31b to embed the opening OP. Then, n + The lower surface of the semiconductor substrate Sub is ground until the shaped semiconductor layer 5a reaches a predetermined thickness. As shown in Figure 6(b), a metal layer 41a is formed on the ground lower surface. Through these steps, the semiconductor device 100 shown in Figure 1 is manufactured.

[0033] n shown in Figure 6(b) - The semiconductor layer 1a is n as shown in Figure 1. - This corresponds to the p-type drift region 1. The p-type semiconductor region 2a corresponds to the p-type base region 2. + The semiconductor region 3a is n + This corresponds to source region 3. + The semiconductor region 4a is p + Corresponds to contact area 4. + The semiconductor layer 5a is n +The drain region 5 corresponds to the shape. The conductive layer 10a corresponds to the conductor 10. The insulating layers 21a and 21b correspond to the insulating part 21. The conductive layer 30a corresponds to the gate electrode 30. The insulating layers 31a and 31b correspond to the gate insulating layer 31. The metal layer 41a corresponds to the drain electrode 41. The metal layer 42a corresponds to the source electrode 42.

[0034] The advantages of the semiconductor device according to this embodiment will be explained. Figure 7 is a cross-sectional view showing a part of a semiconductor device according to a reference example. In the semiconductor device 100r shown in Figure 7, the conductor 10r has a bottom surface BS, a side surface SS1, and a side surface SS2. The bottom surface BS is parallel to the XY plane. The side surfaces SS1 and SS2 are parallel to the YZ plane. Therefore, the angle between the bottom surface BS and side surface SS1, and the angle between the bottom surface BS and side surface SS2 are right angles.

[0035] When the semiconductor device 100r is in the off state, the potential difference between the drain electrode 41 and the source electrode 42 causes n - An electric field is generated between the drift region 1 and the conductor 10r. At this time, electric field concentration occurs at the corner of the lower end of the conductor 10r. Due to the large electric field, a leakage current flows through the insulating portion 21.

[0036] Figure 8 is a graph that schematically shows the characteristics of a semiconductor device. In Figure 8, the horizontal axis represents the voltage Vds across the drain electrode 41 relative to the source electrode 42. The vertical axis represents the current Id flowing between the drain electrode 41 and the source electrode 42. The solid line shows the characteristics of the semiconductor device according to the reference example. The dashed line shows the characteristics of the desired semiconductor device.

[0037] In a desirable semiconductor device, the current Id is small until the voltage reaches the breakdown voltage Vbd. Once the voltage reaches the breakdown voltage Vbd, the current Id increases sharply. On the other hand, in the semiconductor device 100r according to the reference example, the current Id begins to rise at voltage V1. Voltage V1 is smaller than the breakdown voltage Vbd. This is due to the leakage current flowing through the insulating part 21. Furthermore, when the voltage Vds rises further and reaches voltage V2, the current Id increases sharply. This is due to avalanche breakdown occurring starting from the high-electric-field-strength portion in the insulating part 21. As shown in Figure 8, due to the leakage current flowing through the insulating part 21, the effective breakdown voltage of the semiconductor device 100 decreases from the original breakdown voltage Vbd to voltage V2.

[0038] In addressing this issue, the semiconductor device 100 according to the embodiment has a lower surface of the conductor 10 that includes a first surface S1 and a second surface S2. The first surface S1 is parallel to the X direction. The second surface S2, which is connected to the first surface S1, is inclined with respect to the X and Z directions. Therefore, the angle between the first surface S1 and the second surface S2 is less than 90 degrees. This reduces the electric field strength near the lower end of the conductor 10 compared to the semiconductor device 100r. As a result, leakage current can be suppressed in the insulating portion 21, and the breakdown voltage of the semiconductor device 100 can be improved.

[0039] If the angle between the first surface S1 and the second surface S2 is large, the effect of reducing the electric field strength weakens. On the other hand, if the angle is small, the width of the lower end of the conductor 10 increases. As a result, miniaturization of the conductor 10, insulating part 21, etc. becomes difficult, and the on-resistance of the semiconductor device 100 may increase. For this reason, the angle is preferably greater than 30 degrees and less than 60 degrees.

[0040] Furthermore, the lower surface of the conductor 10 includes a third surface S3 that is connected to the first surface S1. The third surface S3 is inclined with respect to the X and Z directions. Therefore, the angle between the first surface S1 and the third surface S3 is less than 90 degrees. This further reduces the electric field strength near the lower end of the conductor 10. Preferably, the angle between the first surface S1 and the third surface S3 is greater than 30 degrees and less than 60 degrees.

[0041] As shown in Figure 2, the conductor 10 includes a first conductive portion 11 and a second conductive portion 12. In the X direction, the length of the first conductive portion 11 is longer than the length of the second conductive portion 12. That is, the lower end of the conductor 10 bulges out. With this structure, the electric field strength near the first conductive portion 11 can be reduced, similar to the structures of the first surfaces S1 to the third surfaces S3.

[0042] The first conductive portion 11 preferably includes a void V, as shown in Figures 1 and 2. When a void V is provided, the conductor 10 becomes more easily deformed in response to the stress in the insulating portion 21 compared to when a void V is not provided. This reduces the stress in the insulating portion 21. - The stress applied to the shape drift region 1 decreases. As a result, the n due to stress - This can suppress the generation of crystal defects in shape drift region 1.

[0043] Preferably, the void V extends in the Y direction. In this case, the volume of the void V is larger compared to when multiple void Vs are scattered in the Y direction. This further reduces the stress in the insulating portion 21.

[0044] Furthermore, in the semiconductor device 100, the bottom of the insulating part 21 is connected to the conductor 10 and n in the Z direction. - It is located between the shaped drift region 1 and the side of the insulating portion 21, in the X direction, between the conductor 10 and n - It is located between the drift region 1. According to the embodiment, the thickness T2a at the bottom of the insulating portion 21 can be increased, and the difference between the thickness T1a at the side of the insulating portion 21 and the thickness T2a can be reduced. As a result, the electric field strength in the insulating portion 21 can be reduced, and the leakage current flowing through the insulating portion 21 can be reduced.

[0045] The reason for the increase in thickness T2a is thought to be as follows: When forming the insulating portion 21, a large compressive stress is generated at the bottom of the insulating portion 21. In the semiconductor device 100r shown in Figure 7, the angle between the bottom surface BS and the side surface SS1 is approximately right-angle, making it difficult to distribute the compressive stress at the bottom of the insulating portion 21. As a result, in the semiconductor device 100r, the thickness T2b at the bottom of the insulating portion 21 becomes smaller, and the difference between the thickness T1b and thickness T2b at the side of the insulating portion 21 becomes larger. On the other hand, in the semiconductor device 100, the second surface S2 connected to the first surface S1 is inclined with respect to the X and Z directions. The distribution of compressive stress is not easily hindered by the right-angle angle. As a result, the compressive stress at the bottom of the insulating portion 21 decreases, and the thickness T2a increases.

[0046] In particular, for silicon oxide, the compressive stress in the

[0110] direction is smaller than the compressive stress in the

[0100] direction. When the insulating portion 21 contains silicon oxide, the {110} plane of silicon oxide is present at the contact surface with the second surface S2 of the insulating portion 21. As a result, the compressive stress in the portion of the insulating portion 21 that is in contact with the second surface S2 is reduced. Consequently, the compressive stress at the bottom of the insulating portion 21 becomes more easily dispersed, and the thickness T2a increases.

[0047] (modified version) Figures 9 and 10 are perspective cross-sectional views showing a part of a semiconductor device according to an embodiment. The structure of the conductor 10 other than the lower end, the structure of the gate electrode 30, etc., can be modified as appropriate, not limited to the example shown in Figure 1. For example, as in the semiconductor device 110 shown in Figure 9, multiple gate electrodes 30 may be provided within a single insulating portion 21. In the illustrated example, a pair of gate electrodes 30 are provided above the conductor 10. When viewed from the Z direction, the conductor 10 is located between the pair of gate electrodes 30 in the X direction.

[0048] Alternatively, as shown in the semiconductor device 120 in Figure 10, the upper part of the conductor 10 may be located between the pair of gate electrodes 30 in the X direction.

[0049] In either configuration, the lower surface of the conductor 10 includes the first surface S1 to the third surface S3, which suppresses the flow of leakage current in the insulating portion 21 and improves the breakdown voltage of the semiconductor device.

[0050] The specific shape of the lower surface of the conductor 10 is not limited to the examples described above. For example, the lower surface of the conductor 10 may have a curved shape instead of the first surface S1, the second surface S2, and the third surface S3. In this case as well, the electric field strength near the lower end of the conductor 10 can be reduced.

[0051] Regarding the embodiments described above, the relative levels of impurity concentrations between each semiconductor region can be confirmed, for example, using a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between each semiconductor region can also be confirmed using SCM. The impurity concentration in each semiconductor region can be measured by secondary ion mass spectrometry (SIMS).

[0052] Electron backscatter diffraction (EBSD) can be used to analyze the crystal orientation of the insulating portion 21 in contact with the lower surface of the conductor 10. For example, EBSD is used to analyze the vicinity of the interface between the conductor 10 and the insulating portion 21. If the lower surface of the conductor 10 includes the first to third surfaces S1 to S3, the analysis results show that the intensity of the peak corresponding to the {100} plane of silicon oxide is greater than the intensity of the peaks corresponding to the other planes. If the lower surface of the conductor 10 has a curved shape, the analysis results show multiple peaks corresponding to multiple planes of silicon oxide.

[0053] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of symbols]

[0054] 1:n - Shape drift region, 1a:n - 1:p-type semiconductor layer, 2:p-type base region, 2a:p-type semiconductor region, 3:n + Source region, 3a:n + Semiconductor region, 4:p + Shaped contact area, 4a:p + Semiconductor region, 5:n + Shape of drain region, 5a:n + Shaped semiconductor layer, 10,10r: conductor, 10a: conductive layer, 11: first conductive part, 11a: first part, 11b: second part, 12: second conductive part, 13: third conductive part, 21: insulating part, 21a,21b: insulating layer, 30: gate electrode, 30a: conductive layer, 31: gate insulating layer, 31a,31b: insulating layer, 41: drain electrode, 41a: metal layer, 42: source electrode, 42a: metal layer, 100,100r: semiconductor device, BS: bottom surface, OP: opening, S1: first surface, S1a: flat surface, S2: second surface, S2a: inclined surface, S3: third surface, S3a: inclined surface, SS1,SS2: side surface, Sub: semiconductor substrate, T1,T2: trench, T1a, T1b, T2a, T2b: Thickness, V: Void

Claims

1. First electrode and A first semiconductor region of a first conductivity type is provided on the first electrode and electrically connected to the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on a part of the second semiconductor region, A conductor provided in the first semiconductor region via an insulating portion, wherein the conductor is A first conductive portion having a first surface that intersects with a first direction extending from the first electrode toward the first semiconductor region, and a second surface that is continuous with the first surface and inclined with respect to the first surface, A second conductive portion is provided on the first conductive portion, A third conductive part provided on the second conductive part, The length of the first conductive portion is longer than the length of the second conductive portion in a second direction perpendicular to the first direction, and the length of the second conductive portion is shorter than the length of the third conductive portion in the second direction. The first conductive part is, A first portion having the first surface and the second surface, the length in the second direction increasing as it extends upward, A second portion is provided above the first portion, and its length in the second direction becomes shorter as it extends upward, The conductor includes, A gate electrode is provided in the insulating portion and faces the second semiconductor region in the second direction via the gate insulating layer, A second electrode is provided on the second semiconductor region and the third semiconductor region and is electrically connected to the second semiconductor region and the third semiconductor region, A semiconductor device equipped with the following features.

2. On the surface of the insulating portion that is in contact with the first surface, there is a {100} surface of silicon oxide. The semiconductor device according to claim 1, wherein a {110} surface of silicon oxide is present on the surface in contact with the second surface of the insulating portion.

3. First electrode and A first semiconductor region of a first conductivity type is provided on the first electrode and electrically connected to the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on a part of the second semiconductor region, A conductor provided in the first semiconductor region via an insulating portion, A first conductive portion having a lower surface of the conductor including a first surface intersecting a first direction toward the first semiconductor region from the first electrode, and a second surface connected to the first surface and inclined with respect to the first surface, A second conductive portion is provided on the first conductive portion, A third conductive part provided on the second conductive part, The conductor includes, in a second direction perpendicular to the first direction, the length of the first conductive portion is longer than the length of the second conductive portion, in the second direction, the length of the second conductive portion is shorter than the length of the third conductive portion, the surface of the insulating portion in contact with the first surface has a {100} surface of silicon oxide, and the surface of the insulating portion in contact with the second surface has a {110} surface of silicon oxide, A gate electrode is provided in the insulating portion and faces the second semiconductor region in the second direction via the gate insulating layer, A second electrode is provided on the second semiconductor region and the third semiconductor region and is electrically connected to the second semiconductor region and the third semiconductor region, A semiconductor device equipped with the following features.

4. A semiconductor device according to any one of claims 1 to 3, wherein a void is provided at the lower end of the conductor.

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