Exposure head

Abstract

To form a driving circuit by a semiconductor process of a low withstand voltage, and reduce a chip size, while securing a forward voltage of a light-emitting element, in such a structure that the light-emitting element and the driving circuit are formed in one chip.SOLUTION: An exposure head 106 includes: a printed circuit board 202; a plurality of light-emitting element array chips 400-1 to 400-20 which include a plurality of light-emitting elements 602 for emitting light, and an analog part 801 for driving the light-emitting elements 602, are arranged on the printed circuit board 202 and have strip shapes; and a rod lens array 203 for condensing the light from the light-emitting elements 602 on a photosensitive drum 102. The analog part 801 is operated between a first potential and a second potential, and the light-emitting element 602 is operated between a third potential and a fourth potential. A potential difference between the third potential and the fourth potential is equal to or more than a potential difference between the first potential and the second potential.SELECTED DRAWING: Figure 11

Description

[[Technical Field]]

[0001] The present invention relates to an exposure head that exposes a photosensitive drum Do . [[Background Art]]

[0002] Conventionally, as an electrophotographic printer, a printer that forms a latent image by exposing a photosensitive drum with an exposure head using an LED, organic EL, or the like is generally known. Such an exposure head includes a light emitting element array arranged in the longitudinal direction of the photosensitive drum, and a rod lens array that forms an image of the light from the light emitting element array on the photosensitive drum. An LED or organic EL as a light emitting element is a light emitting element array in which the irradiation direction of light from the light emitting surface is parallel to the optical axis of the rod lens array.

[0003] Here, in the exposure head, the length of the light emitting element array is determined according to the width of the image forming area on the photosensitive drum, and the interval between the light emitting elements is determined according to the image resolution of the printer. For example, in a 1200 dpi printer, the pixel interval is 21.16 µm (digits after the third decimal place are omitted), so the interval between the light emitting elements is also 21.16 µm. A printer using such an exposure head uses fewer components compared to a laser scanning type printer that deflects and scans a laser beam with a polygon motor, so it is easy to reduce the size and cost of the apparatus.

[0004] In addition, in recent years, a technique for reducing the size of the apparatus by mounting a light emitting element and a driving circuit on the same chip is also known. For example, an exposure head in which a light emitting element and a driving circuit are integrated into one chip by forming a driving integrated circuit and electrodes on a Si substrate and then depositing an organic EL film thereon is known. Further, Patent Document 1 discloses an exposure head in which a TFT circuit and an organic EL are provided on a transparent glass substrate. [[Prior Art Documents]] [[Patent Documents]]

[0005] [Patent Document 1] Japanese Patent Publication No. 2015-112856 [Overview of the project] [Problems that the invention aims to solve]

[0006] However, in conventional exposure heads that integrate the light-emitting element and the drive circuit into a single chip, it is necessary to form the integrated circuit using a semiconductor process with a relatively high voltage resistance in order to ensure the forward voltage of the light-emitting element and obtain a predetermined amount of light emission. When forming the drive circuit using such a high voltage resistance semiconductor process, the size of the transistors becomes large, resulting in the problem of increased chip size.

[0007] The object of the present invention is to provide an exposure head that, in a configuration in which a light-emitting element and a drive circuit are formed on a single chip, can form the drive circuit using a low-voltage semiconductor process while ensuring the forward voltage of the light-emitting element, thereby reducing the chip size. [Means for solving the problem]

[0008] The exposure head according to the present invention is Rotating photoreceptor An exposure head for exposing, The photoreceptor comprises a plurality of light-emitting elements arranged along the rotation axis, a silicon substrate on which the plurality of light-emitting elements are provided, and a drive unit built into the silicon substrate that outputs a drive signal for driving the plurality of light-emitting elements, wherein each of the plurality of light-emitting elements has an anode terminal and a cathode terminal, and when each of the plurality of light-emitting elements emits light, the difference between the potential of the anode terminal and the potential of the cathode terminal is greater than the potential difference required for the operation of the drive unit. It is characterized by the following: [Effects of the Invention]

[0009] According to the present invention, in a configuration in which a light-emitting element and a driving circuit are formed on a single chip, the driving circuit can be formed using a low-voltage semiconductor process while ensuring the forward voltage of the light-emitting element, thereby reducing the chip size. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic diagram of an image forming apparatus according to Embodiment 1 of the present invention. [Figure 2] This is a schematic diagram of an exposure head and a photosensitive drum according to Embodiment 1 of the present invention. [Figure 3] This is a schematic diagram showing the configuration of an exposure head according to Embodiment 1 of the present invention. [Figure 4] This is a schematic diagram of a light-emitting element array chip of an exposure head according to Embodiment 1 of the present invention. [Figure 5] This is a cross-sectional view AA in Figure 4. [Figure 6] This is a schematic diagram showing the arrangement of light-emitting elements in a light-emitting element array chip of an exposure head according to Embodiment 1 of the present invention. [Figure 7] This is a schematic diagram showing a modified example of the arrangement of light-emitting elements in the light-emitting element array chip of an exposure head according to Embodiment 1 of the present invention. [Figure 8] This is a plan view showing the positional relationship between the light-emitting part and the rod lens of an exposure head according to Embodiment 1 of the present invention. [Figure 9] This is a block diagram showing the configuration of an exposure head according to Embodiment 1 of the present invention. [Figure 10] This is a block diagram showing the configuration of the light-emitting element array chip in an exposure head according to Embodiment 1 of the present invention. [Figure 11] This is a circuit diagram of the data holding section of the light-emitting element array chip of an exposure head according to Embodiment 1 of the present invention. [Figure 12] This is a block diagram showing the configuration of the analog section of the exposure head according to Embodiment 1 of the present invention. [Figure 13] This is a block diagram showing the configuration of the power supply unit supplied to the exposure head according to Embodiment 1 of the present invention. [Figure 14] This is a flowchart illustrating the operation of the exposure head according to Embodiment 1 of the present invention. [Figure 15] This is a timing chart of the power supply voltage supplied to the light-emitting element array chip of the exposure head according to Embodiment 1 of the present invention. [Figure 16] This is a timing chart of the light-emitting element array chip of an exposure head according to Embodiment 1 of the present invention. [Figure 17] This is a block diagram showing the configuration of the light-emitting element array chip in an exposure head according to Embodiment 2 of the present invention. [Figure 18]This is a block diagram showing the configuration of an analog section of an exposure head according to the second embodiment of the present invention. [Figure 19] This is a block diagram showing the configuration of a power supply section supplied to the exposure head according to the second embodiment of the present invention. [Figure 20] This is a flow chart of the operation of the exposure head according to the second embodiment of the present invention. [Figure 21] This is a timing chart of the power supply voltage supplied to the light emitting element array chip of the exposure head according to the second embodiment of the present invention. MODE FOR CARRYING OUT THE INVENTION

[0011] Embodiments will be described in detail below with reference to the drawings.

[0012] (First Embodiment) <Configuration of Image Forming Apparatus> The configuration of the image forming apparatus 1 according to the first embodiment of the present invention will be described in detail with reference to FIG. 1.

[0013] The image forming apparatus 1 includes a scanner section 100, an image forming section 103, a fixing section 104, a sheet feeding / conveying section 105, and a registration roller 110.

[0014] The scanner section 100 illuminates a document placed on a document platen, optically reads an image of the document, converts the read image into an electrical signal to generate image data, and outputs the generated image data to a printer control section (not shown).

[0015] The image-forming unit 103 operates under the control of the printer control unit to form an image on the sheet conveyed by the register roller 110, and then conveys the image-formed sheet to the fuser unit 104. The image-forming unit 103 has four image-forming units that perform a series of electrophotographic processes including charging, exposure, development, and transfer. The image-forming unit 103 forms a full-color image on the sheet using four image-forming units arranged in the order of cyan (C), magenta (M), yellow (Y), and black (K). Each of the four image-forming units sequentially performs the image-forming operations of magenta, yellow, and black after a predetermined time has elapsed since the start of cyan image-forming.

[0016] Specifically, the image-forming unit 103 includes a photosensitive drum 102, an exposure head 106, a charger 107, a developer 108, a transfer belt 111, and an optical sensor 113.

[0017] The photosensitive drum 102, which serves as the image carrier, is attached to the image forming apparatus 1 by mounting members (not shown) and rotated.

[0018] The exposure head 106 is attached to the image forming apparatus 1 by mounting members (not shown). The exposure head 106 consists of four exposure heads 106a, 106b, 106c, and 106d, corresponding to four imaging units. The exposure head 106 focuses the light emitted according to the image data onto the photosensitive drum 102 to expose it, thereby forming a latent image (electrostatic latent image) on the photosensitive drum 102. Details of the configuration of the exposure head 106 will be described later.

[0019] The charger 107 charges the photosensitive drum 102.

[0020] The developing unit 108 develops the latent image formed on the photosensitive drum 102 by supplying toner to the image and developing it, thereby forming a toner image (developer image) on the photosensitive drum 102.

[0021] The transfer belt 111 transports the sheet conveyed by the register roller 110 to the fixing unit 104. The toner image developed by the developer unit 108 is transferred to the sheet transported by the transfer belt 111.

[0022] The optical sensor 113 is positioned opposite the transfer belt 111 and detects the position of a test chart printed on the transfer belt 111 in order to derive the amount of color misalignment between each imaging unit. The optical sensor 113 outputs the detection result of the test chart position to an image controller unit (not shown). Based on the detection result of the test chart position input from the optical sensor 113, the image controller unit derives the amount of color misalignment between each imaging unit of the imaging unit 103 and performs control to correct the image position of each color. A full-color toner image without color misalignment is transferred onto the sheet by this control.

[0023] The fixing unit 104 is composed of a combination of rollers and incorporates a heat source such as a halogen heater (not shown). The fixing unit 104 melts and fixes the toner on the sheet onto which the toner image has been transferred by the imaging unit 103 using heat and pressure, and then discharges the toner-fixed sheet to the outside of the image forming apparatus 1 using the paper discharge roller 112.

[0024] The paper feeding / transportation unit 105 includes an internal paper feeding unit 109a, an internal paper feeding unit 109b, an external paper feeding unit 109c, and a manual feed unit 109d, and feeds sheets from the pre-specified paper feeding unit and transports them to the register roller 110.

[0025] The register roller 110 transports the sheet transported from the paper feeding / transporting unit 105 to the transfer belt 111 at the timing when the toner image formed in the image formation unit 103 is transferred onto the sheet.

[0026] The printer control unit controls the operation of the scanner unit 100, the image forming unit 103, the fuser unit 104, and the paper feeding / transport unit 105. The printer control unit communicates with the MFP control unit, which controls the entire MFP (the entire image forming apparatus 1), and controls the operation of the scanner unit 100, the image forming unit 103, the fuser unit 104, and the paper feeding / transport unit 105 while managing their states, in accordance with the instructions of the MFP control unit.

[0027] <Exposure head configuration> The configuration of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to Figures 2 and 3.

[0028] Figure 2(a) shows the arrangement of the exposure head 106 relative to the photosensitive drum 102, and Figure 2(b) shows how the light emitted from the light-emitting element group 201 is focused onto the photosensitive drum 102 by the rod lens array 203.

[0029] Figure 3(a) shows the side of the printed circuit board 202 opposite to the side on which the light-emitting element group 201 is mounted (hereinafter referred to as the "non-mounted light-emitting element side"), and Figure 3(b) shows the side on which the light-emitting element group 201 is mounted (hereinafter referred to as the "mounted light-emitting element side"). Figure 3(c) shows the boundary between the light-emitting element array chips 400-m (where m is an integer between 1 and 19) to 400-m+1.

[0030] The exposure head 106 comprises a group of light-emitting elements 201, a printed circuit board 202, a rod lens array 203, and a housing 204.

[0031] The light-emitting element group 201 is mounted on the light-emitting element mounting surface of the printed circuit board 202 and has a configuration in which 20 strip-shaped light-emitting element array chips 400-1 to 400-20 are arranged in two rows in a staggered pattern. The light-emitting element array chips 400-1 to 400-20 in each row are arranged along the longitudinal direction of the printed circuit board 202.

[0032] Within the light-emitting element array chips 400-1 to 400-20, which function as semiconductor chips, light-emitting elements 602 are arranged at a predetermined pitch along the longitudinal direction (main scanning direction) and the short direction (sub-scanning direction) of the light-emitting element array chips 400-1 to 400-20. Each of the light-emitting element array chips 400-1 to 400-20 has 748 light-emitting elements 602 arranged in the longitudinal direction (X) at a predetermined image resolution pitch. Here, the image resolution pitch is exemplified as 1200 dpi (approximately 21.16 μm). Furthermore, the distance from end to end of the 748 light-emitting elements 602 in each of the light-emitting element array chips 400-1 to 400-20 is exemplified as approximately 15.8 mm.

[0033] The light-emitting element group 201 has 20 light-emitting element array chips 400-1 to 400-20 arranged in the longitudinal direction, resulting in 14,960 exposureable light-emitting elements, enabling image formation corresponding to an image width of approximately 316 mm.

[0034] In this example, the image resolution pitch between light-emitting element 602-n and light-emitting element 602-1, located at the boundary of the light-emitting element array chips 400-1 to 400-20 shown in Figure 3(c), is also 1200 dpi (approximately 21.16 μm). The distance S between light-emitting element 602-n and light-emitting element 602-1 in the short direction is approximately 127 μm (6 pixels at 1200 dpi, 4 pixels at 800 dpi). The distance L between light-emitting element 602-n and light-emitting element 602-1 in the long direction is approximately 21.16 μm (1 pixel at 1200 dpi). Note that the distance S and distance L between light-emitting element 602-n and light-emitting element 602-1 are not limited to the values ​​mentioned above.

[0035] As shown in Figure 3(a), the printed circuit board 202 has a connector 305 and a driver IC (not shown) for driving the light-emitting element group 201 on the non-mounted side of the light-emitting element side. As shown in Figure 3(b), the light-emitting element group 201 is mounted on the light-emitting element mounting side of the printed circuit board 202.

[0036] Connector 305 is connected to a driver IC (not shown) and a power supply (not shown) located on the non-mounted side of the printed circuit board 202 via signal lines (not shown), and is also connected to the group of light-emitting elements 201.

[0037] The rod lens array 203 is positioned such that it is at a predetermined distance from the light-emitting element group 201 and also at a predetermined distance from the photosensitive drum 102, thereby imaging the light emitted from the light-emitting element group 201 onto the photosensitive drum 102.

[0038] The housing 204 is fitted with a rod lens array 203 and a printed circuit board 202.

[0039] The exposure head 106 having the above configuration is assembled individually at the factory, and then focus adjustment and light intensity adjustment are performed to adjust the spot at the light-gathering position to a predetermined size. In focus adjustment, the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the light-emitting element group 201 is the desired distance. In light intensity adjustment, each light-emitting element 602 of the light-emitting element group 201 is made to emit light individually and sequentially, and the drive current of each light-emitting element 602 is adjusted so that the light focused on the photosensitive drum 102 via the rod lens array 203 is the predetermined light intensity.

[0040] <Configuration of the light-emitting element array chip> The configuration of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to Figure 4.

[0041] The light-emitting element array chip 400 is a chip constructed by providing light-emitting elements 602 on a Si substrate, and comprises a light-emitting substrate 402, a light-emitting section 404, a circuit section 406, and a wire bonding pad (WB pad) 408.

[0042] The light-emitting substrate 402 is a Si substrate and is provided with a light-emitting section 404 and wire bonding pads 408. The light-emitting substrate 402 incorporates a circuit section 406 for controlling the light-emitting section 404. Here, Si substrates have advantages such as the ability to form high-speed and high-performance circuits at high density, as process technology for integrated circuit formation has been developed and they are already used as substrates for various integrated circuits, and they can be obtained inexpensively because large-diameter wafers are readily available.

[0043] The light-emitting unit 404 includes a light-emitting element 602. Details of the configuration of the light-emitting unit 404 will be described later.

[0044] The circuit section 406 has a circuit configuration that includes an analog drive circuit, a digital control circuit, or both an analog drive circuit and a digital drive circuit, and controls the light-emitting section 404.

[0045] The wire bonding pad 408 supplies power to the circuit section 406, or performs input / output of signals, etc., between the light-emitting element array chip 400 and the outside.

[0046] <Configuration of the light-emitting section> The configuration of the light-emitting section 404 of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to Figure 5.

[0047] The light-emitting section 404 is the portion where the light-emitting substrate 402 and the upper electrode 508 face each other, and the light-emitting layer 506 of that opposing portion. It is constructed by stacking a plurality of lower electrodes 504, light-emitting layers 506, and upper electrodes 508 on the light-emitting substrate 402 in that order.

[0048] The lower electrodes 504 are independent electrodes formed on the light-emitting substrate 402. The lower electrodes 504 have a width W in the X direction, and multiple lower electrodes 504 are formed with a predetermined spacing d between adjacent lower electrodes 504 in the X direction. The lower electrodes 504 are formed along with the circuit section 406 using Si integrated circuit processing technology, which has a high precision with a processing rule of about 0.2 μm, and are connected to a drive section (not shown) of the circuit section 406. This allows the lower electrodes 504 to be arranged with high precision and density, and since the light-emitting areas of the light-emitting elements 602 are substantially the same as the lower electrodes 504, it is possible to arrange the light-emitting elements 602 at high density.

[0049] The lower electrode 504 is preferably formed of a metal with high reflectivity to the emission wavelength of the light-emitting layer 506, and is formed of silver (Ag), aluminum (Al), or an alloy of silver and aluminum.

[0050] The light-emitting layer 506 is formed on the lower electrode 504 and is, for example, an organic EL film or an inorganic EL film. When the light-emitting layer 506 is an organic EL film, it is a laminated structure that optionally includes functional layers such as an electron transport layer, a hole transport layer, an electron injection layer, a hole injection layer, an electron blocking layer, and a hole blocking layer.

[0051] When the light-emitting layer 506 is formed of a material that is susceptible to moisture, such as an organic EL layer or an inorganic EL layer, it is desirable that it be sealed to prevent moisture from entering the light-emitting section 404. The light-emitting layer 506 prevents moisture from entering the light-emitting section 404 by a sealing film formed by laminating thin films of, for example, silicon oxide, silicon nitride, or aluminum oxide, or by laminating thin films of silicon oxide, silicon nitride, and aluminum oxide. As for the method of forming the sealing film, a method that has excellent covering performance for structures such as steps is preferred, and for example, atomic layer deposition (ALD) can be used.

[0052] The light-emitting layer 506 may be formed continuously or divided into sections approximately the same size as the lower electrode 504. Furthermore, the material, structure, and formation method of the sealing film described above are merely examples and are not limited to those examples; suitable options may be selected as appropriate.

[0053] The upper electrode 508 is a common electrode and is formed on the light-emitting layer 506. The upper electrode 508 is preferably transparent to the emission wavelength of the light-emitting layer 506, and a transparent electrode such as indium tin oxide (ITO) can be used.

[0054] The light-emitting unit 404 having the above configuration energizes the light-emitting layer 506 through a selected lower electrode 504 and an upper electrode 508 from among the plurality of lower electrodes 504, causing the light-emitting layer 506 at the location corresponding to the selected lower electrode 504 to emit light. As a result, the light-emitting unit 404 emits light through the upper electrode 508 on the side of the light-emitting layer 506 opposite to the light-emitting substrate 402.

[0055] By making the upper electrode 508 a transparent electrode such as indium tin oxide, the aperture ratio can be made substantially 100%, and the light emitted in the light-emitting layer 506 can be directly used as emitted light. Furthermore, by forming the lower electrode 504 using high-precision Si integrated circuit processing technology, the lower electrodes 504 can be arranged at high density, so that almost the entire area of ​​the light-emitting section 404 can be made to emit light, thereby increasing the utilization efficiency of the light-emitting section 404. Here, the area of ​​the light-emitting section 404 is the sum of the total area of ​​the multiple lower electrodes 504 and the total area of ​​the multiple intervals d.

[0056] <Arrangement of light-emitting elements in the light-emitting section> The arrangement of the light-emitting elements 602 of the light-emitting section 404 of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to Figures 6 to 8.

[0057] In Figure 6, Figure 6(a) shows an example in which multiple light-emitting elements 602 are arranged in a row, and Figure 6(b) is a schematic cross-sectional view of a light-emitting element row 604. Figure 7 shows an example in which multiple rows of light-emitting elements 604 are arranged in the Y direction of the figure to form a light-emitting section 404.

[0058] In Figures 6(a) and 6(b), W1 is the width of the light-emitting element 602 in the X direction, and d1 is the distance between adjacent light-emitting elements 602 in the X direction. Also, in Figure 7, W2 is the width of the light-emitting element 602 in the Y direction, and d2 is the distance between adjacent light-emitting elements 602 in the Y direction.

[0059] Furthermore, in Figure 6(b), for example, the light-emitting element 602-3 is the area enclosed by the dashed line.

[0060] The light-emitting element array 604 is composed of multiple light-emitting elements 602 arranged along the X direction at predetermined intervals (pitch). The predetermined intervals are, for example, 21 and 16 μm when the image resolution in the Y direction is 1200 dpi. In this example, W1 is 19.8 μm and d1 is 0.68 μm.

[0061] Here, if the light-emitting layer 506 is sufficiently thin, the light-emitting portion of the light-emitting element 602 is substantially the same as the lower electrode 504, and W1 can be considered as W in Figure 5, and d1 as d in Figure 5.

[0062] The light-emitting element array 604 is not limited to the case where the light-emitting elements 602 are arranged in the X direction to form a single row, as shown in Figure 6(a), but may also be arranged in the Y direction to form multiple rows, as shown in Figure 7. Figure 7 illustrates a case where 748 light-emitting elements 602 are arranged in the X direction (602-1~4_1~748) and 4 rows (604-1~4) in the Y direction, which is different from the X direction, on a matrix. Here, W2 is exemplified as 19.8 μm, the same as W1. Also, here, d2 is exemplified as 0.68 μm, the same as d1, and is arranged at a pitch of 21.16 μm (1200 dpi) in the Y direction.

[0063] The rod lens array 203 focuses the light emitted from the light-emitting element group 201 onto the photosensitive drum 102. Here, four rows of light-emitting element rows 604 are exemplified in the Y direction. The pitch of the light-emitting element 602 in the X direction is exemplified here as 21.16 μm, as shown in Figure 8. The diameter of the rod lens array 203 is exemplified here as 290 μm, as shown in Figure 8. In this example, one rod lens array 203 focuses the emitted light from multiple light-emitting elements 602.

[0064] <Circuit configuration of the exposure head> The circuit configuration of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to Figure 9.

[0065] Note that in the explanation using Figure 9, for the sake of simplicity, the circuit configuration of a single monochromatic exposure head 106 is described, but in reality, each of the four exposure heads 106, each with four colors, has the same circuit configuration. Furthermore, these four exposure heads 106 process simultaneously in parallel.

[0066] The exposure head 106 has an image controller unit 700 that transmits signals or data to the printed circuit board 202 to control the printed circuit board 202 and performs processing on the image data and processing on the exposure timing. The signals and data transmitted from the image controller unit 700 to the printed circuit board 202 are a clock signal, image data, a signal indicating the start of image data acquisition (hereinafter referred to as the "line synchronization signal"), and a communication signal.

[0067] Specifically, the image controller unit 700 includes an image data generation unit 701, a chip data conversion unit 702, a CPU 703, a synchronization signal generation unit 704, a +5V generation circuit 710, a -5V generation circuit 711, and a switch (SW) 714.

[0068] Here, the image controller unit 700 and the printed circuit board 202 are connected by a clock signal line 705, a line synchronization signal line 706, an image data signal line 707, a communication signal line 708, a +5V power supply line 712, and a -5V power supply line 713.

[0069] The clock signal line 705 connects the chip data conversion unit 702 to each of the light-emitting element array chips 400-1 to 400-20.

[0070] The line synchronization signal line 706 connects only the chip data conversion unit 702 and the light-emitting element array chip 400-1.

[0071] The image data signal line 707 connects the chip data conversion unit 702 to each of the light-emitting element array chips 400-1 to 400-20. Here, we will illustrate the number of image data signal lines 707 as four, the same as the number of columns in the light-emitting element row 604.

[0072] Communication signal line 708 connects the CPU 703 to each of the light-emitting element array chips 400-1 to 400-20.

[0073] The +5V power line 712 connects the +5V generation circuit 710 to each of the light-emitting element array chips 400-1 to 400-20.

[0074] The -5V power line 713 connects the switch (SW) 714 to each of the light-emitting element array chips 400-1 to 400-20.

[0075] The image data generation unit 701 generates image data for print output by performing dithering processing on image data input from the scanner unit 100 or received from outside the image forming apparatus 1 at the image resolution instructed by the CPU 703. For example, the image data generation unit 701 generates 1 line × 4 columns (number of light-emitting element rows) image data by performing dithering processing at an image resolution of 1200 dpi in both the main scanning direction and the sub-scanning direction. The image data generation unit 701 outputs the generated image data to the chip data conversion unit 702.

[0076] The chip data conversion unit 702, in synchronization with the line synchronization signal input from the synchronization signal generation unit 704, divides the image data input from the image data generation unit 701 into individual light-emitting element array chips 400-1 to 400-20. The chip data conversion unit 702 outputs the divided image data to each of the light-emitting element array chips 400-1 to 400-20 via the image data signal line 707. At the same time, the chip data conversion unit 702 outputs the line synchronization signal to the light-emitting element array chip 400-1 via the line synchronization signal line 706, and outputs the clock signal to the light-emitting element array chips 400-1 to 400-20 via the clock signal line 705.

[0077] The CPU 703 defines one line period as the period in which the surface of the photosensitive drum 102 moves by a predetermined pixel size in the rotational direction at a predetermined rotational speed of the photosensitive drum 102, and instructs the synchronization signal generation unit 704 on the time interval of the signal period.

[0078] The CPU 703 defines one line period as the period during which the surface of the photosensitive drum 102 moves in the rotational direction by a pixel size of 1200 dpi (approximately 21.16 μm) at a predetermined rotational speed of the photosensitive drum 102. Then, for example, when exposure is performed at a speed of 200 mm / sec in the transport direction, the CPU 703 instructs the synchronization signal generation unit 704 to set the time interval of the signal period as 105.8 μsec (decimal places omitted). At this time, the CPU 703 calculates the transport speed using a set value (fixed value) of the printing speed set in a speed control unit (not shown) that controls the speed of the photosensitive drum 102.

[0079] The CPU 703 instructs the image data generation unit 701 to set the image resolution. The CPU 703 outputs a power control signal to the switch 714, turning the switch 714 ON. The CPU 703 transmits and receives communication signals to and from each of the light-emitting element array chips 400-1 to 400-20 via the communication signal line 708. The CPU 703 sets a set value for the communication signal based on the head information stored in the head information storage unit 709 (described later), and outputs the communication signal with the set value to the light-emitting element array chips 400-1 to 400-20 via the communication signal line 708.

[0080] The synchronization signal generation unit 704 generates a line synchronization signal based on the time interval of the signal cycle instructed by the CPU 703, and outputs the generated line synchronization signal to the chip data conversion unit 702.

[0081] The +5V generation circuit 710 converts the +12V power supply voltage applied from the +12V power supply into a +5V voltage and supplies it to each of the light-emitting element array chips 400-1 to 400-20 via the +5V power supply line 712. A general switching regulator circuit can be used as the +5V generation circuit 710.

[0082] The -5V generation circuit 711 converts the +12V power supply voltage applied from the +12V power supply into a -5V voltage and supplies it to the switch 714. A general switching regulator circuit can be used as the -5V generation circuit 711.

[0083] The switch 714, acting as a switching element, switches whether or not to supply a -5V voltage to the light-emitting element array chip 400 by turning ON or OFF depending on whether or not a power control signal is input from the CPU 703. When the power control signal is input from the CPU 703, the switch 714 turns ON and supplies a -5V voltage to each of the light-emitting element array chips 400-1 to 400-20 via the -5V power line 713. The -5V power line 713 becomes floating when the switch 714 is OFF and no -5V voltage is supplied to the light-emitting element array chips 400-1 to 400-20.

[0084] The printed circuit board 202 includes light-emitting element array chips 400-1 to 400-20 and a head information storage unit 709.

[0085] Light-emitting element array chip 400-1 and light-emitting element array chip 400-2 are connected by signal line 708-1. Light-emitting element array chip 400-2 and light-emitting element array chip 400-3 are connected by signal line 708-2. Similarly, light-emitting element array chips 400-3, ... are connected in a daisy-chain fashion by signal lines 708-3, ...

[0086] Each of the light-emitting element array chips 400-1 to 400-20 generates a line synchronization signal for the next chip based on the input line synchronization signal and outputs it to the next light-emitting element array chip 400-1 to 400-20 via signal lines 708-1, ... Each of the light-emitting element array chips 400-1 to 400-20 illuminates the light-emitting element 602 based on the set values ​​of the input clock signal, line synchronization signal, image data, and communication signal.

[0087] The head information storage unit 709 is connected to the CPU 703 via a communication signal line 708. The head information storage unit 709 is a storage device that stores head information such as the amount of light emitted and mounting position information of the light-emitting element array chips 400-1 to 400-20.

[0088] <Circuit configuration of the light-emitting element array chip> The circuit configuration of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to Figures 10 to 13.

[0089] Since the circuit configurations of the light-emitting element array chips 400-1 to 400-20 are identical, the circuit configuration of light-emitting element array chip 400-1 will be described, and the circuit configurations of light-emitting element array chips 400-2 to 400-20 will be omitted. Also, since the clock signal is input to all blocks of the digital section 800, the clock signal line 705 is connected to all blocks of the digital section 800, but this is omitted from the description in Figure 10.

[0090] The light-emitting element array chip 400-1 comprises a light-emitting section 404 and a circuit section 406. The circuit section 406 comprises a digital section 800 and an analog section 801.

[0091] The digital unit 800 receives a clock signal, image data signal, and line synchronization signal from the chip data conversion unit 702, as well as a communication signal from the CPU 703. The digital unit 800 generates a drive signal (pulse signal) to cause the light-emitting element 602 to light up, synchronized with the clock signal and based on the set value set in the communication signal, the image data signal, and the line synchronization signal, and outputs the generated drive signal to the analog unit 801. The digital unit 800 generates a line synchronization signal for the next chip based on the line synchronization signal and outputs the generated line synchronization signal for the next chip, the light-emitting element array chip 400-2, via the signal line 708-1.

[0092] Specifically, the digital unit 800 includes a communication IF unit 802, a register unit 803, a line synchronization signal generation unit 804, an acquisition signal generation unit 805, and data holding units 806-001 to 748.

[0093] The communication interface unit 802 is connected to the CPU 703 via the communication signal line 708.

[0094] The register unit 803 receives the set value from the communication signal input from the CPU 703 via the communication IF unit 802. The register unit 803 reads the set value written by the CPU 703 and outputs the read set value to the analog unit 801 as drive current information and to the input signal generation unit 805 as delay time information. Here, the drive current information is the current setting value of the drive current that flows to the light-emitting unit 404 and is a digital value. The delay time information is the delay time that delays the output of the data latch signal and is a digital value.

[0095] The line synchronization signal generation unit 804 delays the line synchronization signal input from the line synchronization signal line 706 for a predetermined time to generate a line synchronization signal for the next chip, and outputs it to the light-emitting element array chip 400-2 via the signal line 708-1.

[0096] The input signal generation unit 805 outputs a data latch signal we001 to the data holding unit 806-001 at a timing delayed by the delay time information input from the register unit 803, based on the line synchronization signal input from the line synchronization signal line 706.

[0097] Each of the data holding units 806-001 to 748 receives a clock signal and a data latch signal wen (n=1 to 748), and when the data latch signal wen is received, it receives image data 1 to 4 for four columns.

[0098] As shown in Figure 11, the data holding units 806-001 to 748 include four flip-flop circuits 807 and four gate circuits 808 that latch the input image data 1 to 4, generate drive signals 1 to 4, and output them to the analog unit 801. The data holding units 806-001 to 748 also include one flip-flop circuit 809 that delays the input data latch signal wen by one clock cycle and outputs the delayed data latch signal we(n+1) to the next data holding unit 806-001 to 748.

[0099] The analog unit 801 controls the drive of the light-emitting unit 404 based on the drive current information input from the register unit 803 and the drive signals input from the data holding units 806-001 to 748.

[0100] Specifically, as shown in Figure 12, the analog section 801 includes a drive circuit 900 comprising a current setting DAC 901, a current control MOSFET 902, and a switching MOSFET 903.

[0101] The drive circuits 900 are connected one-to-one with each light-emitting element 602, and the number of drive circuits 900 is the same as the number of light-emitting elements 602. In this embodiment, 748 drive circuits 900 are provided for each light-emitting element array chip 400-1 to 400-20, in a total of 2992 circuits (448 x 4 rows). Since all drive circuits 900 have the same configuration, only the configuration of one drive circuit 900 will be described for simplicity.

[0102] The current setting DAC901 converts the digital value of the drive current to be flowed to the light-emitting unit 404, which is indicated by the drive current information input from the register unit 803 of the digital unit 800, into an analog voltage and outputs it to the gate terminal G of the current control MOSFET902.

[0103] The current control MOSFET 902 is a P-channel MOSFET, with its source terminal S connected to the power supply voltage VDD, its gate terminal G connected to the output terminal of the DAC 901, and its drain terminal D connected to the source terminal S of the switching MOSFET 903. The current control MOSFET 902 is configured such that the higher the analog voltage input from the current setting DAC 901, the greater the drive current of the light-emitting element 602 flowing from the source terminal S to the drain terminal D.

[0104] The switching MOSFET 903 is a P-channel MOSFET. The source terminal S of the switching MOSFET 903 is connected to the drain terminal D of the current control MOSFET 902, the gate terminal G is connected to the output terminal of the data holding unit 806, and the drain terminal D is connected to the anode terminal A of the light-emitting element 602 of the light-emitting unit 404. Two-level drive signals 1 to 4, either high-level or low-level, are input to the gate terminal G of the switching MOSFET 903 from the data holding units 806-001 to 748.

[0105] The switching MOSFET 903 turns ON when a Hi-level drive signal is input to its gate terminal G, and turns OFF when a Low-level drive signal is input to its gate terminal G. When the switching MOSFET 903 turns ON when a Hi-level drive signal is input to its gate terminal G, a current flows from the source terminal S to the drain terminal D, which is the drive current for the light-emitting element 602 controlled by the current control MOSFET 902.

[0106] Next, the power supply configurations for the digital section 800, the analog section 801, and the light-emitting element 602 will be explained in detail with reference to Figure 13.

[0107] In Figure 13, for the sake of simplicity, the internal blocks of the digital section 800 are omitted, and only one drive circuit 900 and one light-emitting element 602 within the analog section 801 are shown.

[0108] The digital section 800 is supplied with a +5V voltage from the +5V power supply line 712. The digital section 800 is connected to GND (0V) as its reference potential. Therefore, each block of the digital section 800 operates with voltages between +5V and 0V. In addition, a voltage in the range of 0V to 5V is applied to the gate terminal of the switching MOSFET 903.

[0109] The current setting DAC 901 of the analog section 801 is supplied with a +5V voltage from the +5V power supply line 712. The current setting DAC 901 is connected to GND (0V) as the reference potential. As a result, a voltage in the range of 0V to 5V is applied to the gate terminal of the current control MOSFET 902. In addition, the source terminal of the current control MOSFET 902 is supplied with a +5V voltage from the +5V power supply line 712 as the power supply voltage.

[0110] The light-emitting element 602 is, for example, an organic EL, with its anode terminal A connected to the drain terminal of a switching MOSFET 903 and its cathode terminal K connected to a -5V power supply line 713. A voltage of -5V is supplied to the cathode terminal K of the light-emitting element 602 from the -5V power supply line 713. Generally, a forward voltage of about 6V is generated in the light-emitting element 602 by a drive current of several μA. In this case, the potential of the anode terminal A of the light-emitting element 602 is about +1V, which is -5V plus +6V.

[0111] Since the drain-source voltage of the current control MOSFET 902 and the switching MOSFET 903 is approximately 1.5V each, adding the drain-source voltage of 1.5V × 2 = 3V to the forward voltage of the light-emitting element 602 (6V) results in approximately 9V. Therefore, the light-emitting element array chips 400-1 to 400-20 require a voltage of approximately 9V or more to make the light-emitting element 602 emit light. Since the light-emitting element array chips 400-1 to 400-20 can drive the light-emitting element 602 in a 10V range between +5V and -5V, the light-emitting element 602 can emit light.

[0112] Conventionally, in configurations where an EL film is deposited on top of a circuit board and stacked, it was necessary to use a semiconductor process of 9V or higher to form the light-emitting element array chip, taking into account the voltage between the drain and source of the MOSFET, in order to secure a forward voltage of 6V for the light-emitting element. In contrast, in this embodiment, +5V and -5V are supplied as power supply voltages to drive the light-emitting element 602 in the 10V range, and the digital section 800 and analog section 801 are constructed using a semiconductor process that provides +5V from GND. As a result, in this embodiment, the size of the current control MOSFET 902 and the switching MOSFET 903 can be reduced, and the chip size of the light-emitting element array chips 400-1 to 400-20 can be reduced.

[0113] <Operation of the exposure head> The operation of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to Figures 14 and 15.

[0114] The exposure head 106 starts operating when the main power supply of the image forming apparatus 1 is turned ON.

[0115] First, CPU 703 determines whether or not the user has requested a print job (S1).

[0116] CPU703 repeats the operation of step S1 if the user has not requested a print job (S1: No).

[0117] On the other hand, when the CPU 703 receives a print job request from the user (S1: Yes), it writes the setting values ​​to the register section 803 of the light-emitting element array chips 400-1 to 400-20 to set the registers (S2).

[0118] Next, the CPU 703 outputs a power control signal to the switch 714, supplying a voltage of -5V to the cathode electrodes of the light-emitting elements 602 of the light-emitting element array chips 400-1 to 400-20 (-5V ON) (S3).

[0119] Next, the CPU 703 starts outputting image data to the light-emitting element array chips 400-1 to 400-20 at a predetermined timing to expose the photosensitive drum 102 (S4).

[0120] Next, CPU 703 determines whether the printing job has finished (S5).

[0121] CPU 703 repeats the operation of step S5 if the print job has not finished (S5: No).

[0122] On the other hand, when the printing job is completed (S5:Yes), the CPU 703 stops sending a power control signal to the switch 714, thereby floating the potential of the cathode electrode of the light-emitting element 602 and ending its operation.

[0123] Next, the operation of the exposure head 106 will be explained in more detail with reference to Figure 15.

[0124] As shown in Figure 15, at time t=t0, the power supply of the image forming apparatus 1 is turned ON, and a power supply voltage of +12V is supplied to the +5V generation circuit 710 and the -5V generation circuit 711. As a result, the voltage of the +5V power supply line 712 becomes +5V after time t=t1 has elapsed. At this time, the -5V power supply line 713 is in a floating state (0V in Figure 15) because switch 714 is OFF.

[0125] At time t=t1, upon receiving a JOB request from the user, the CPU 703 outputs a power control signal to the switch 714, which causes the potential of the -5V power line 713 to become -5V, making the light-emitting element 602 ready to operate.

[0126] At time t=t2, the CPU 703 stops outputting the power control signal to switch 714 as the job is completed, turning switch 714 OFF and floating the -5V power line 713 (0V in Figure 15).

[0127] <Operation of the light-emitting element array chip> The operation of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to Figure 16.

[0128] The data holding unit 806-001 receives four columns of image data (D1[1] to D1[4]) simultaneously. When the data latch signal we001 is input from the acquisition signal generation unit 805, the data holding unit 806-001 latches the image data (D1[1] to D1[4]) and generates drive signals (P001[1] to P001[4]).

[0129] Furthermore, the data holding unit 806-001 outputs a data latch signal we002, which is the input data latch signal we001 delayed by one clock cycle, to the next data holding unit 806-002.

[0130] Similar to the data holding unit 806-001, the data holding unit 806-002 simultaneously receives image data for four columns (D2[1] to D2[4]). When the data latch signal we002 is input from the data holding unit 806-001, the data holding unit 806-002 latches the image data (D2[1] to D2[4]) and generates drive signals (P002[1] to P002[4]).

[0131] Furthermore, the data holding unit 806-002 outputs a data latch signal we003, which is the input data latch signal we002 delayed by one clock cycle, to the next data holding unit 806-003.

[0132] In this way, the data holding units 806-001 to 748 sequentially latch image data while sequentially outputting data latch signals.

[0133] The data holding units 806-001 to 748 latch image data and output the latched signal as a drive signal to the analog unit 801. Since the data holding units 806-001 to 748 latch four rows of image data with a single data latch signal, they simultaneously output drive signals for four rows (four pixels).

[0134] In this configuration, where the light-emitting element 602 and the analog unit 801 are formed on the same chip, a voltage (-5V) lower than the voltage supplied to the analog unit 801 (+5V and reference potential (GND)) is supplied to the cathode electrode of the light-emitting element 602. This allows the analog unit 801 to be formed using a semiconductor process with a relatively low breakdown voltage, thereby reducing the size of the analog unit 801 and thus the overall chip size.

[0135] Furthermore, when not exposed, the potential of the cathode electrode connected to the -5V power supply line 713 of the light-emitting element 602 is set to a floating state. This suppresses the leakage current from the current control MOSFET 902 and switching MOSFET 903 to the light-emitting element 602, which generate leakage current even in the OFF state when not exposed, thereby reducing power consumption.

[0136] In this embodiment, the analog unit 801 operates between a first potential of +5V and a second potential of 0V, and the light-emitting element 602 operates between a third potential of +1V and a fourth potential of -5V. Furthermore, the potential difference between the third potential of +1V and the fourth potential of -5V is greater than or equal to the potential difference between the first potential of +5V and the second potential of 0V. This allows the analog unit 801 to be formed using a low-voltage semiconductor process while ensuring the forward voltage of the light-emitting element 602 in a configuration where the light-emitting element 602 and the analog unit 801 are formed on a single chip, thereby reducing the chip size.

[0137] Furthermore, in this embodiment, the third potential +1V is lower than the first potential +5V, and the fourth potential -5V is lower than the second potential 0V. The potential difference between the second potential 0V and the fourth potential -5V is greater than or equal to the potential difference between the first potential +5V and the second potential 0V. The second potential 0V is the ground potential, the first potential +5V is a positive potential relative to the ground potential, and the fourth potential -5V is a negative potential relative to the ground potential.

[0138] Furthermore, in this embodiment, when the switch 714 is switched so that no current is supplied to the light-emitting element 602, the potential of the cathode terminal K of the light-emitting element 602 becomes a fifth potential of 0V, which is at least higher than the fourth potential of -5V. The fifth potential of 0V is equal to the second potential of 0V.

[0139] Furthermore, in this embodiment, the fourth potential -5V is lower than the first potential +5V. The second potential 0V is the ground potential. The third potential +1V is higher than the second potential 0V.

[0140] In this embodiment, the voltages are not limited to +5V and -5V; any voltage other than +5V and -5V can be supplied as long as it is a voltage that can drive the light-emitting element 602. For example, instead of only securing a 10V voltage range of +5V and -5V, a 10V voltage range of +4V and -6V may also be secured.

[0141] Furthermore, in this embodiment, 20 light-emitting element array chips 400-1 to 400-20 are provided on the printed circuit board 202, but the invention is not limited to this, and any number of light-emitting element array chips can be provided on the printed circuit board 202 as needed.

[0142] (Embodiment 2) The configuration of the image forming apparatus according to Embodiment 2 of the present invention is the same as that of the image forming apparatus 1 shown in Figure 1, so its description is omitted. Furthermore, the configuration of the exposure head according to this embodiment is the same as that shown in Figures 3 to 8, except for the circuit configuration of the exposure head, so the description of the configuration other than the circuit configuration of the exposure head is omitted.

[0143] While Embodiment 1 described above has a configuration in which the cathode electrodes of multiple light-emitting elements 602 are common, this embodiment has a configuration in which the anode electrodes of multiple light-emitting elements 602 are common.

[0144] <Circuit configuration of the exposure head> The circuit configuration of the exposure head according to Embodiment 2 of the present invention will be described in detail with reference to Figure 17.

[0145] In Figure 17, parts that have the same configuration as those in Figure 9 are denoted by the same reference numerals, and their descriptions are omitted.

[0146] The exposure head according to this embodiment has an image controller unit 1301 that transmits signals or data for controlling the printed circuit board 1302 to the printed circuit board 1302 and performs processing on image data and processing on exposure timing. The signals and data transmitted from the image controller unit 1301 to the printed circuit board 1302 are a clock signal, image data, a line synchronization signal, and a communication signal.

[0147] Specifically, the image controller unit 1301 includes an image data generation unit 701, a chip data conversion unit 702, a CPU 703, a synchronization signal generation unit 704, a +5V generation circuit 710, a switch 714, and a +10V generation circuit 1303.

[0148] Here, the image controller unit 1301 and the printed circuit board 1302 are connected by a clock signal line 705, a line synchronization signal line 706, an image data signal line 707, a communication signal line 708, a +5V power supply line 712, and a +10V power supply line 1304.

[0149] The +10V power line 1304 connects the switch 714 to each of the light-emitting element array chips 1400-1 to 1400-20.

[0150] The +10V generation circuit 1303 converts the +12V power supply voltage applied from an external +12V power supply into a +10V voltage and supplies it to the switch 714. A general switching regulator circuit can be used as the -5V generation circuit 711.

[0151] Switch 714 switches between supplying a +10V voltage to the light-emitting element array chip 1400 by turning it ON or OFF depending on whether or not a power control signal is input from the CPU 703. Switch 714 turns ON when a power control signal is input from the CPU 703 and supplies a +10V voltage to each of the light-emitting element array chips 1400-1 to 1400-20 via the +10V power line 1304. The +10V power line 1304 becomes floating when switch 714 is OFF and no +10V voltage is supplied to the light-emitting element array chips 1400-1 to 1400-20.

[0152] The printed circuit board 1302 includes a head information storage unit 709 and light-emitting element array chips 1400-1 to 1400-20. The arrangement and configuration of the light-emitting element array chips 1400-1 to 1400-20 on the printed circuit board 1302 is the same as that of the light-emitting element array chips 400-1 to 400-20 on the printed circuit board 302.

[0153] Light-emitting element array chip 1400-1 and light-emitting element array chip 1400-2 are connected by signal line 708-1. Light-emitting element array chip 1400-2 and light-emitting element array chip 1400-3 are connected by signal line 708-2. Similarly, light-emitting element array chips 1400-3, ... are connected in a daisy-chain fashion by signal lines 708-3, ...

[0154] Each of the light-emitting element array chips 1400-1 to 1400-20 generates a line synchronization signal for the next chip and outputs it to the next light-emitting element array chips 1400-2 to 1400-20 via signal lines 708-1, ... Each of the light-emitting element array chips 1400-1 to 1400-20 illuminates the light-emitting element 602 based on the set values ​​of the input clock signal, line synchronization signal, image data, and communication signal.

[0155] The head information storage unit 709 is connected to the CPU 703 via a communication signal line 708. The head information storage unit 709 is a storage device that stores head information such as the amount of light emitted and mounting position information of the light-emitting element array chips 1400-1 to 1400-20.

[0156] Note that the light-emitting sections of the light-emitting element array chips 1400-1 to 1400-20 have the same configuration as the light-emitting section 404 shown in Figure 5, so their explanation will be omitted.

[0157] <Circuit configuration of the light-emitting element array chip> The circuit configuration of the light-emitting element array chips 1400-1 to 1400-20 of the exposure head according to Embodiment 2 of the present invention will be described in detail with reference to Figure 18.

[0158] Since the circuit configurations of the light-emitting element array chips 1400-1 to 1400-20 are identical, the circuit configuration of light-emitting element array chip 1400-1 will be described, and the explanation of the circuit configurations of light-emitting element array chips 1400-2 to 1400-20 will be omitted. Also, in Figure 18, parts with the same configuration as in Figure 12 are denoted by the same reference numerals, and their explanations are omitted.

[0159] The light-emitting element array chip 1400-1 comprises a light-emitting section 404 and a circuit section 406. The circuit section 406 comprises a digital section 800 and an analog section 801.

[0160] In this embodiment, 748 drive circuits × 4 rows = 2992 drive circuits 900 are provided for each light-emitting element array chip 1400-1 to 1400-20. Since all drive circuits 900 have the same configuration, only the configuration of one drive circuit 900 will be described for simplicity.

[0161] The current control MOSFET 902 is a P-channel MOSFET. The source terminal of the current control MOSFET 902 is connected to the cathode of the light-emitting element 602, the gate terminal is connected to the output terminal of the current setting DAC 901, and the drain terminal is connected to the source terminal of the switching MOSFET 903. The current control MOSFET 902 is configured such that the current flowing from the source terminal to the drain terminal increases as the analog voltage input from the current setting DAC 901 increases.

[0162] The switching MOSFET 903 is a P-channel MOSFET, with its source terminal connected to the drain terminal of the current control MOSFET 902, its gate terminal connected to the output terminal of the data holding unit 806, and its drain terminal connected to GND. The gate terminal of the switching MOSFET 903 receives two drive signals 1 to 4, either high-level or low-level, from the data holding units 806-001 to 748.

[0163] The switching MOSFET 903 turns ON when a Hi-level drive signal is input to its gate terminal and turns OFF when a Low-level drive signal is input to its gate terminal. When the switching MOSFET 903 turns ON when a Hi-level drive signal is input to its gate terminal, a current flows from the source terminal to the drain terminal, which is the drive current for the light-emitting element 602 controlled by the current control MOSFET 902.

[0164] Next, the power supply configurations for the digital section 800, the analog section 801, and the light-emitting element 602 will be explained in detail with reference to Figure 19.

[0165] In Figure 19, parts with the same configuration as those in Figure 11 are denoted by the same reference numerals, and their descriptions are omitted. Also, in Figure 19, to simplify the explanation, the internal blocks of the digital section 800 are omitted, and only one drive circuit 900 and one light-emitting element 602 within the analog section 801 are shown.

[0166] The anode terminal A of the light-emitting element 602 is supplied with a voltage of +10V from the +10V power supply line 1304, and the cathode terminal is connected to the source terminal of the current control MOSFET 902. The light-emitting element 602 is, for example, an organic EL, and generally generates a forward voltage of about 6V with a drive current of a few μA. In other words, the potential of the cathode terminal K of the light-emitting element 602 is about +4V, which is +10V minus 6V.

[0167] Since the drain-source voltage of the current-controlling MOSFET 902 and the switching MOSFET 903 is approximately 1.5V each, adding the drain-source voltage of 1.5V × 2 = 3V to the forward voltage of the light-emitting element 602 (6V) results in approximately 9V. Therefore, the light-emitting element array chips 1400-1 to 1400-20 require a voltage of approximately 9V or more to make the light-emitting element 602 emit light. Since the light-emitting element array chips 1400-1 to 1400-20 can drive the light-emitting element 602 in a 10V range between GND (0V) and +10V, the light-emitting element 602 can be made to emit light.

[0168] Conventionally, in configurations where an EL film is deposited on top of a circuit board and then stacked, it was necessary to use a semiconductor process of 9V or higher to form the light-emitting element array chip, taking into account the voltage between the drain and source of the MOSFET, in order to ensure a forward voltage of 6V for the light-emitting element. In contrast, in this embodiment, the light-emitting element 602 is driven in the 10V range by supplying GND and +10V as the power supply voltage, and the digital section 800 and analog section 801 are constructed using a semiconductor process that provides +5V from GND. As a result, in this embodiment, the size of the current control MOSFET 902 and the switching MOSFET 903 can be reduced, and the chip size of the light-emitting element array chips 1400-1 to 1400-20 can be reduced.

[0169] <Operation of the exposure head> The operation of the exposure head 106 according to Embodiment 2 of the present invention will be described in detail with reference to Figures 20 and 21.

[0170] The exposure head 106 starts operating when the main power supply of the image forming apparatus 1 is turned ON.

[0171] First, the CPU 703 determines whether or not the user has requested a print job (S11).

[0172] If the CPU 703 has not received a print job request from the user (S11: No), it repeats the operation in step S11.

[0173] On the other hand, when the CPU 703 receives a print job request from the user (S11: Yes), it writes setting values ​​to the register section 803 of the light-emitting element array chips 1400-1 to 1400-20 to set the registers (S12).

[0174] Next, the CPU 703 outputs a power control signal to the switch 714, supplying a +10V voltage to the anode electrode of the light-emitting element 602 of the light-emitting element array chips 1400-1 to 1400-20 (+10V ON) (S13).

[0175] Next, the CPU 703 starts outputting image data to the light-emitting element array chips 1400-1 to 1400-20 at a predetermined timing to expose the photosensitive drum 102 (S14).

[0176] Next, CPU 703 determines whether the printing job has finished (S15).

[0177] If the print job has not finished (S15: No), CPU 703 repeats the operation of step S15.

[0178] On the other hand, when the printing job is completed (S15:Yes), the CPU 703 stops sending a power control signal to the switch 714, thereby floating the potential of the anode electrode of the light-emitting element 602 and ending its operation.

[0179] Next, the operation of the exposure head 106 will be explained in more detail with reference to Figure 21.

[0180] As shown in Figure 21, at time t=t10, the power supply of the image forming apparatus 1 is turned ON, and a power supply voltage of +12V is supplied to the +5V generation circuit 710 and the +10V generation circuit 1303. As a result, the voltage of the +5V power supply line 712 becomes +5V after time t=t10 has elapsed. At this time, the potential of the +10V power supply line 1304 is floating (0V in Figure 21) because switch 714 is OFF.

[0181] At time t=t11, upon receiving a JOB request from the user, the CPU 703 outputs a power control signal to the switch 714, which raises the potential of the +10V power line 1304 to +10V, making the light-emitting element 602 ready to operate.

[0182] At time t=t12, the CPU 703 stops outputting the power control signal to switch 714 as the job ends, turning switch 714 OFF and floating the potential of the +10V power line 1304 (0V in Figure 21).

[0183] In this configuration, where the light-emitting element 602 and the analog unit 801 are formed on the same chip, a voltage (+10V) higher than the voltage supplied to the analog unit 801 (+5V and reference potential (GND)) is supplied to the anode electrode of the light-emitting element 602. As a result, the analog unit 801 can be formed using a semiconductor process with a relatively low breakdown voltage, which reduces the size of the analog unit 801 and thus the overall chip size.

[0184] Furthermore, when not exposed, the potential of the anode electrode connected to the +10V power supply line 1304 of the light-emitting element 602 is set to a floating state. This suppresses the leakage current from the current control MOSFET 902 and switching MOSFET 903 to GND, which generate leakage current even in the OFF state when not exposed, thereby reducing power consumption.

[0185] In this embodiment, the analog unit 801 operates between a first potential of +5V and a second potential of 0V, and the light-emitting element 602 operates between a third potential of +10V and a fourth potential of +4V. Furthermore, the potential difference between the third potential of +10V and the fourth potential of +4V is greater than or equal to the potential difference between the first potential of +5V and the second potential of 0V. This allows the analog unit 801 to be formed using a low-voltage semiconductor process while ensuring the forward voltage of the light-emitting element 602 in a configuration where the light-emitting element 602 and the analog unit 801 are formed on a single chip, thereby reducing the chip size.

[0186] Furthermore, in this embodiment, the third potential +10V is higher than the first potential +5V, and the fourth potential +4V is higher than the second potential 0V. The potential difference between the first potential +5V and the third potential +10V is greater than or equal to the potential difference between the first potential +5V and the second potential 0V.

[0187] Furthermore, in this embodiment, when the switch 714 is switched so that no current is supplied to the light-emitting element 602, a fifth potential of 0V, which is lower than at least the first potential of +5V, is obtained. The fifth potential of 0V is equal to the second potential of 0V.

[0188] Furthermore, in this embodiment, the fourth potential +4V is lower than the first potential +5V. The second potential 0V is the ground potential. The third potential +10V is higher than the second potential 0V.

[0189] In this embodiment, the voltages are not limited to +5V and +10V; any voltage capable of driving the light-emitting element 602 may be used.

[0190] Furthermore, in this embodiment, 20 light-emitting element array chips 1400-1 to 1400-20 are provided on the printed circuit board 1302, but the invention is not limited to this, and any number of light-emitting element array chips can be provided on the printed circuit board 1302 as needed.

[0191] The present invention is not limited to the embodiments described above, and it goes without saying that various modifications are possible without departing from the spirit of the invention. [Explanation of symbols]

[0192] 1. Image forming apparatus 102 Photosensitive drum 103 Image creation section 104 Fixing section 105 Conveying section 106 Exposure Head 107 Charger 108 Developer 110 Regilora 111 Transfer Belt 112 Paper output roller 113 Optical Sensors 201 Light-emitting element group 202 Printed circuit board 203 Rod Lens Array 204 Housing 305 connector 400-1~400-20 Light-emitting element array chip 402 Light-emitting substrate 404 Light-emitting part 406 Circuit section 408 Wire bonding pad 504 Lower electrode 506 Emitting layer 508 Upper electrode 602 Light-emitting element 604 light-emitting element array

Claims

1. An exposure head for exposing a rotating photoreceptor, A plurality of light-emitting elements arranged along the rotation axis direction of the photoreceptor, A silicon substrate on which the plurality of light-emitting elements are provided, A drive unit is embedded in the silicon substrate and outputs a drive signal to drive the plurality of light-emitting elements, Equipped with, Each of the plurality of light-emitting elements is provided with an anode terminal and a cathode terminal. When each of the plurality of light-emitting elements emits light, the difference between the potential of the anode terminal and the potential of the cathode terminal is greater than the potential difference required for the operation of the drive unit. An exposure head characterized by the following features.

2. The drive unit is connected to a power supply potential that applies the potential necessary for the operation of the drive unit, and a reference potential that is lower than the power supply potential. The cathode terminal is subjected to a potential lower than the reference potential. The exposure head according to feature 1.

3. The exposure head according to claim 2, characterized in that the reference potential is the GND potential.

4. The exposure head according to claim 3, characterized in that the voltage applied to the cathode terminal is a negative potential.

5. The drive unit is connected to a power supply potential that applies the potential necessary for the operation of the drive unit. The anode terminal is subjected to a potential higher than the power supply potential. The exposure head according to feature 1.

6. The drive unit is connected to the power supply potential and a reference potential to which a potential lower than the power supply potential is applied. The exposure head according to feature 4.

7. The aforementioned reference potential is the GND potential. The exposure head according to feature 6.

8. The aforementioned plurality of light-emitting elements are organic ELs. The exposure head according to feature 1.

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