Indication device

Abstract

To provide a low-cost display device.SOLUTION: A display device has a pixel and an IC chip. The pixel has a first pixel circuit having a display element, and a second pixel circuit having a light-receiving element. In one IC chip, a control circuit, a data driver circuit, and a readout circuit are provided. The first and second pixel circuits are electrically connected to the readout circuit. The control circuit has a function of controlling driving of the data driver circuit or the readout circuit. The data driver circuit has a function of supplying image data to the first pixel circuit. The readout circuit has a function of, in the case where monitoring current flows in the first pixel circuit, outputting a monitoring signal corresponding to the monitoring current. The readout circuit has a function of outputting an imaging signal corresponding to imaging data acquired by the second pixel circuit.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device and a driving method thereof. Alternatively, one embodiment of the present invention relates to a semiconductor device and a driving method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. One embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, and a manufacturing method thereof.

[0003] Note that in this specification and the like, a semiconductor device generally refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of a semiconductor device. An imaging device, a display device, a liquid crystal display device, a light-emitting device, an input device, an input / output device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like), and an electronic device may include a semiconductor device.

Background Art

[0004] In recent years, portable information terminals such as smartphones and tablet terminals have been widely spread. Such portable information terminals often employ a display device including an active matrix display portion, a touch sensor, and the like. Patent Document 1 discloses a technique in which one IC serves both as a driver circuit for a display portion and a driver circuit for a touch sensor.

[0005] As display elements for pixels arranged in a matrix on the display section of a display device, light-emitting elements that utilize electroluminescence (EL) are attracting attention. Organic EL elements and inorganic EL elements are known examples of such light-emitting elements. Because these light-emitting elements emit light themselves, they offer higher visibility of displayed images than displays using liquid crystal elements. They also have advantages such as not requiring a backlight and having a fast response speed.

[0006] An organic EL element comprises a layer containing a light-emitting organic compound (hereinafter referred to as the EL layer) between a pair of electrodes. When a voltage is applied between the pair of electrodes, light is emitted from the EL layer. An example of a display device using such an organic EL element is disclosed in Patent Document 2. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2017-16098 [Patent Document 2] Japanese Patent Publication No. 2002-324673 [Overview of the project] [Problems that the invention aims to solve]

[0008] When using light-emitting elements such as organic EL elements as display elements, images can be displayed on the display unit by controlling the current flowing through the light-emitting elements. However, if the threshold voltage of the drive transistor, which is electrically connected to the light-emitting element and has the function of controlling the current flowing through the light-emitting element according to the image data written to the pixel, varies from pixel to pixel, display unevenness may occur. Therefore, it is preferable that a display device having a light-emitting element has a function to read out the magnitude of the current flowing between the drain and source of the drive transistor as monitor current data. By correcting the threshold voltage of the drive transistor based on the current value represented by the monitor current data, display unevenness can be reduced.

[0009] One method for giving a display device the function of a touch sensor is to provide a light-receiving element to each pixel on which a display element is located. By providing a light-receiving element in addition to a display element to each pixel, it becomes possible to detect fingers or other objects touching the display area on which the pixel is located.

[0010] If a display device with light-emitting elements is equipped with both a function to read monitor current data and a function such as a touch sensor, the display device can detect fingers touching the display area while reducing display unevenness, for example. On the other hand, in this case, the display device needs to be equipped not only with a data driver circuit that has the function of supplying image data to pixels, but also with a circuit that has the function of reading monitor current data and a circuit that has the function of reading imaging data acquired using a light-receiving element. Here, if, for example, the data driver circuit, the circuit that has the function of reading monitor current data and the circuit that has the function of reading imaging data are each provided on different ICs (semiconductor integrated circuits), the number of ICs provided in the display device will increase. This will increase the manufacturing cost of the display device.

[0011] One aspect of the present invention aims to provide a display device having a sensor function. Alternatively, it aims to provide a low-cost display device. Alternatively, it aims to provide a display device capable of displaying high-quality images. Alternatively, it aims to provide a display device whose drive can be easily controlled. Alternatively, it aims to provide a display device capable of displaying high-brightness images. Alternatively, it aims to provide a low-power display device. Alternatively, it aims to provide a highly reliable display device. Alternatively, it aims to provide a novel display device. Alternatively, it aims to provide a novel semiconductor device.

[0012] Alternatively, one of the objectives is to provide a method for driving a display device that functions as a sensor. Alternatively, one of the objectives is to provide a low-cost method for driving a display device. Alternatively, one of the objectives is to provide a method for driving a display device that can display high-quality images. Alternatively, one of the objectives is to provide a method for driving a display device that can be easily controlled. Alternatively, one of the objectives is to provide a method for driving a display device that can display high-brightness images. Alternatively, one of the objectives is to provide a low-power consumption method for driving a display device. Alternatively, one of the objectives is to provide a highly reliable method for driving a display device. Alternatively, one of the objectives is to provide a novel method for driving a display device. Alternatively, one of the objectives is to provide a novel method for driving a semiconductor device.

[0013] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0014] One aspect of the present invention is a display device comprising a pixel and an IC chip, wherein the pixel comprises a first pixel circuit having a display element and a second pixel circuit having a light-receiving element, a control circuit, a data driver circuit and a readout circuit are provided on one IC chip, the first pixel circuit and the readout circuit are electrically connected via a first wiring, the second pixel circuit and the readout circuit are electrically connected via a second wiring, the control circuit has the function of supplying a clock signal to the data driver circuit and the readout circuit, the data driver circuit has the function of supplying image data to the first pixel circuit, the readout circuit has the function of outputting a first signal corresponding to the potential of the first wiring, and the readout circuit has the function of outputting a second signal corresponding to the potential of the second wiring.

[0015] Alternatively, in the above embodiment, the readout circuit has an A / D conversion circuit, the A / D conversion circuit has a first transistor, a second transistor, and a comparator circuit, one of the source or drain of the first transistor is electrically connected to a first wire, one of the source or drain of the second transistor is electrically connected to a second wire, the other of the source or drain of the first transistor and the other of the source or drain of the second transistor are electrically connected to a first input terminal of the comparator circuit, and the first and second signals may be digital signals output from the A / D conversion circuit.

[0016] Alternatively, in the above embodiment, the readout circuit may have a reference signal generation circuit, which may be electrically connected to the second input terminal of the comparator circuit.

[0017] Alternatively, in the above embodiment, the readout circuit may have an A / D conversion circuit, the A / D conversion circuit having a first transistor, a second transistor, a third transistor, a first capacitive element, and a comparator circuit, wherein one of the sources or drains of the first transistor is electrically connected to a first wire, one of the sources or drains of the second transistor is electrically connected to a second wire, the other of the sources or drains of the first transistor and the other of the sources or drains of the second transistor are electrically connected to one of the sources or drains of the third transistor, the other of the sources or drains of the third transistor is electrically connected to one electrode of the first capacitive element, and the other electrode of the first capacitive element is electrically connected to the first input terminal of the comparator circuit.

[0018] Alternatively, in the above embodiment, the readout circuit may have a reference signal generation circuit, and the A / D conversion circuit may have a fourth transistor and a second capacitive element, wherein the reference signal generation circuit is electrically connected to either the source or the drain of the fourth transistor, the other of the source or drain of the fourth transistor is electrically connected to one electrode of the second capacitive element, and the other electrode of the second capacitive element is electrically connected to the second input terminal of the comparator circuit.

[0019] Alternatively, in the above embodiment, the A / D conversion circuit includes a fifth transistor and a sixth transistor, wherein one of the source or drain of the fifth transistor is electrically connected to one electrode of the first capacitive element, one of the source or drain of the sixth transistor is electrically connected to one electrode of the second capacitive element, and the other of the source or drain of the fifth transistor and the other of the source or drain of the sixth transistor are electrically connected to a power line.

[0020] Alternatively, in the above embodiment, the second transistor may have a metal oxide in the channel formation region.

[0021] Alternatively, one aspect of the present invention comprises a matrix of pixels, an IC chip, a gate driver circuit, and a row driver circuit, wherein each pixel has a first pixel circuit having a display element and a second pixel circuit having a light-receiving element, and one IC chip is provided with a control circuit, a data driver circuit, and a readout circuit, the control circuit having the function of supplying a clock signal to the gate driver circuit, the row driver circuit, the data driver circuit, and the readout circuit, the gate driver circuit having the function of selecting the first pixel circuit to which image data is supplied by supplying a first scan signal to the first pixel circuit, and the row driver circuit, The display device has the function of selecting a second pixel circuit to read out imaging data by supplying a second scanning signal to the second pixel circuit, the data driver circuit has the function of supplying image data to the first pixel circuit selected by the gate driver circuit, the readout circuit has the function of reading out imaging data from the second pixel circuit selected by the row driver circuit, the gate driver circuit has the function of outputting a first scanning signal during the period when the row driver circuit is not outputting a second scanning signal, and the row driver circuit has the function of outputting a second scanning signal during the period when the gate driver circuit is not outputting a first scanning signal.

[0022] Alternatively, in the above embodiment, the first pixel circuit includes a display element and a drive transistor, the readout circuit includes an A / D conversion circuit, the A / D conversion circuit includes a first transistor, a second transistor and a comparator circuit, one electrode of the display element is electrically connected to one of the source or drain of the drive transistor, one of the source or drain of the first transistor is electrically connected to the first pixel circuit, one of the source or drain of the second transistor is electrically connected to the second pixel circuit, the other of the source or drain of the first transistor and the other of the source or drain of the second transistor are electrically connected to the first input terminal of the comparator circuit, the A / D conversion circuit has the function of outputting a signal corresponding to the current flowing between the drain and source of the drive transistor, and the A / D conversion circuit may have the function of outputting an imaging signal corresponding to the imaging data.

[0023] Alternatively, in the above embodiment, the readout circuit may have a reference signal generation circuit, which may be electrically connected to the second input terminal of the comparator circuit.

[0024] Alternatively, in the above embodiment, the first pixel circuit includes a display element and a drive transistor, the readout circuit includes an A / D conversion circuit, the A / D conversion circuit includes a first transistor, a second transistor, a third transistor, a first capacitive element, and a comparator circuit, one electrode of the display element is electrically connected to either the source or the drain of the drive transistor, one source or the drain of the first transistor is electrically connected to the first pixel circuit, one source or the drain of the second transistor is electrically connected to the second pixel circuit, and the first The other of the source or drain of the transistor and the other of the source or drain of the second transistor are electrically connected to one of the source or drain of the third transistor, the other of the source or drain of the third transistor is electrically connected to one electrode of the first capacitive element, the other electrode of the first capacitive element is electrically connected to the first input terminal of the comparator circuit, the A / D conversion circuit has the function of outputting a signal corresponding to the current flowing between the drain and source of the drive transistor, and the A / D conversion circuit may also have the function of outputting an imaging signal corresponding to the imaging data.

[0025] Alternatively, in the above embodiment, the readout circuit may have a reference signal generation circuit, and the A / D conversion circuit may have a fourth transistor and a second capacitive element, wherein the reference signal generation circuit is electrically connected to either the source or the drain of the fourth transistor, the other of the source or drain of the fourth transistor is electrically connected to one electrode of the second capacitive element, and the other electrode of the second capacitive element is electrically connected to the second input terminal of the comparator circuit.

[0026] Alternatively, in the above embodiment, the A / D conversion circuit includes a fifth transistor and a sixth transistor, wherein one of the source or drain of the fifth transistor is electrically connected to one electrode of the first capacitive element, one of the source or drain of the sixth transistor is electrically connected to one electrode of the second capacitive element, and the other of the source or drain of the fifth transistor and the other of the source or drain of the sixth transistor are electrically connected to a power line.

[0027] Alternatively, in the above embodiment, the second transistor may have a metal oxide in the channel formation region. [Effects of the Invention]

[0028] According to one aspect of the present invention, a display device having the function of a sensor can be provided. Alternatively, a low-cost display device can be provided. Alternatively, a display device capable of displaying high-quality images can be provided. Alternatively, a display device with easily controllable operation can be provided. Alternatively, a display device capable of displaying high-brightness images can be provided. Alternatively, a low-power display device can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device can be provided. Alternatively, a novel semiconductor device can be provided.

[0029] Alternatively, a method for driving a display device having sensor functionality can be provided. Alternatively, a low-cost method for driving a display device can be provided. Alternatively, a method for driving a display device capable of displaying high-quality images can be provided. Alternatively, a method for driving a display device that can be easily controlled can be provided. Alternatively, a method for driving a display device capable of displaying high-brightness images can be provided. Alternatively, a method for driving a display device with low power consumption can be provided. Alternatively, a highly reliable method for driving a display device can be provided. Alternatively, a novel method for driving a display device can be provided. Alternatively, a novel method for driving a semiconductor device can be provided.

[0030] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawing]

[0031] [Figure 1] Figures 1A and 1B are schematic diagrams showing examples of the configuration of a display device. [Figure 2] Figures 2A and 2B are block diagrams showing examples of display device configurations. [Figure 3] Figures 3A and 3D to 3F are schematic diagrams showing examples of pixel configurations. Figures 3B and 3C are cross-sectional views showing examples of display device configurations. [Figure 4] Figure 4 is a block diagram showing an example of a display device configuration. [Figure 5] Figure 5 is a timing chart showing an example of a method for driving a display device. [Figure 6] Figure 6 is a block diagram showing an example of a display device configuration. [Figure 7] Figure 7 is a block diagram showing an example of a display device configuration. [Figure 8] Figure 8 is a circuit diagram showing an example of a pixel configuration. [Figure 9] Figure 9 is a circuit diagram showing an example of a pixel configuration. [Figure 10] Figure 10 is a circuit diagram showing an example of a pixel configuration. [Figure 11] Figure 11A is a circuit diagram showing an example of a pixel configuration. Figure 11B is a timing chart showing an example of a pixel driving method. [Figure 12] Figures 12A and 12B are circuit diagrams showing example configurations of display devices. [Figure 13] Figure 13 is a timing chart showing an example of a method for driving a display device. [Figure 14] Figures 14A and 14B are circuit diagrams showing example configurations of display devices. [Figure 15] Figure 15 is a timing chart showing an example of a method for driving a display device. [Figure 16] Figure 16 is a circuit diagram showing an example of a method for driving a display device. [Figure 17] Figures 17A and 17B are circuit diagrams showing an example of a method for driving a display device. [Figure 18]Figures 18A and 18B are circuit diagrams showing an example of a method for driving a display device. [Figure 19] Figure 19 is a timing chart showing an example of a method for driving a display device. [Figure 20] Figures 20A and 20B are circuit diagrams showing an example of a method for driving a display device. [Figure 21] Figure 21 is a timing chart showing an example of a method for driving a display device. [Figure 22] Figures 22A and 22B are circuit diagrams showing an example of a method for driving a display device. [Figure 23] Figures 23A to 23C are cross-sectional views showing examples of the configuration of a display device. [Figure 24] Figures 24A to 24C are cross-sectional views showing examples of the configuration of a display device. [Figure 25] Figures 25A to 25C are cross-sectional views showing examples of the configuration of a display device. [Figure 26] Figures 26A to 26C are cross-sectional views showing examples of the configuration of a display device. [Figure 27] Figure 27 is a cross-sectional view showing an example of the configuration of a display device. [Figure 28] Figures 28A and 28B are cross-sectional views showing examples of the configuration of a display device. [Figure 29] Figures 29A and 29B are cross-sectional views showing examples of the configuration of a display device. [Figure 30] Figure 30 is a cross-sectional view showing an example of the configuration of a display device. [Figure 31] Figure 31 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 32] Figure 32 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 33] Figures 33A to 33C are cross-sectional views showing examples of transistor configurations. [Figure 34] Figure 34A is a top view showing an example of a transistor configuration. Figures 34B and 34C are cross-sectional views showing an example of a transistor configuration. [Figure 35]Figure 35A is a top view showing an example of a transistor configuration. Figures 35B and 35C are cross-sectional views showing an example of a transistor configuration. [Figure 36] Figure 36A illustrates the classification of IGZO crystal structures. Figure 36B illustrates the XRD spectrum of a CAAC-IGZO film. Figure 36C illustrates the micro-electron diffraction pattern of a CAAC-IGZO film. [Figure 37] Figure 37A is a perspective view showing an example of an electronic device. Figure 37B is a cross-sectional view showing an example of an electronic device. [Figure 38] Figures 38A to 38D show examples of electronic devices. [Figure 39] Figures 39A to 39F show examples of electronic devices. [Modes for carrying out the invention]

[0032] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be interpreted as being limited to the contents of the following embodiments. In the configuration of the invention described below, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and the repetition of their descriptions will be omitted.

[0033] Furthermore, the following embodiments can be combined as appropriate. Also, if multiple configuration examples are shown within a single embodiment, these configuration examples can be combined as appropriate.

[0034] Furthermore, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings.

[0035] Furthermore, in this specification, the terms "electrode" and "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are formed as a single unit.

[0036] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (e.g., ground potential or source potential). Therefore, voltage and potential are often interchangeable. In this specification, unless otherwise specified, voltage and potential are considered interchangeable.

[0037] Furthermore, ordinal numbers such as "first," "second," etc., in this specification are added to avoid confusion of constituent elements and do not indicate any order or rank, such as process order or layering order. Also, even if an ordinal number is not attached to a term in this specification, an ordinal number may be attached in the claims to avoid confusion of constituent elements. Also, even if an ordinal number is attached to a term in this specification, a different ordinal number may be attached in the claims. Also, even if an ordinal number is attached to a term in this specification, the ordinal number may be omitted in the claims.

[0038] Furthermore, in this specification, the "conducting state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically short-circuited. Conversely, the "non-conducting state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically disconnected. For example, a transistor in the conducting state can be driven in the linear region.

[0039] Furthermore, in this specification, "on-current" may refer to the current flowing between the source and drain when the transistor is conducting. Also, "off-current" may refer to the current flowing between the source and drain when the transistor is not conducting.

[0040] (Embodiment 1) This embodiment describes a display device according to one aspect of the present invention.

[0041] One aspect of the present invention relates to a display device in which pixels, each having a light-emitting element and a light-receiving element, are arranged in a matrix. By providing not only light-emitting elements but also light-receiving elements in each pixel, the display device can not only display images but also have functions such as a touch sensor. On the other hand, when pixels are provided with both light-emitting elements and light-receiving elements, the display device needs to be provided not only with a data driver circuit that has the function of supplying image data representing the image displayed using the light-emitting elements to the pixels, but also with a circuit (readout circuit) that has the function of reading out the image data acquired using the light-receiving elements. In one aspect of the present invention, the data driver circuit and the readout circuit are provided on the same IC chip. This makes it possible to make the display device less expensive than when the data driver circuit and the readout circuit are provided on different IC chips.

[0042] Furthermore, when a light-emitting element is used as a display element for displaying an image, the display unit can display an image by controlling the luminescence brightness by controlling the current flowing through the light-emitting element. However, if the threshold voltage of a drive transistor, which is electrically connected to the light-emitting element and has the function of controlling the current flowing through the light-emitting element according to the image data written to the pixel, varies from pixel to pixel, display unevenness may occur. Therefore, it is preferable that a display device having a light-emitting element has a function to read out the magnitude of the current flowing between the drain and source of the drive transistor as monitor current data. By correcting the threshold voltage of the drive transistor, etc., based on the current value represented by the monitor current data, display unevenness can be reduced. One aspect of the present invention reads out monitor current data using the same circuit as the circuit that has the function of reading out imaging data. In other words, imaging data and monitor current data are read out using the same readout circuit. As a result, the supply of image data to pixels, the reading out of imaging data, and the reading out of monitor current data can be performed using the same IC chip. Therefore, the display device can be made less expensive than when the supply of image data to pixels, the reading out of imaging data, and the reading out of monitor current data are performed using different IC chips.

[0043] <Example of display device configuration> Figure 1A is a schematic diagram showing an example configuration of a display device 10, which is a display device according to one aspect of the present invention. The display device 10 has a display unit 11, a gate driver circuit 13, a row driver circuit 19, an IC 20, and an FPC (Flexible Printed Circuits) 25 on a substrate 18. The row driver circuit may also be called a gate driver circuit. For example, in this specification, the gate driver circuit 13 may be referred to as the first gate driver circuit, and the row driver circuit 19 may be referred to as the second gate driver circuit.

[0044] The display unit 11 has pixels 12 arranged in a matrix. The IC 20 can be mounted on the substrate 18 as an IC chip. The IC 20 is electrically connected to circuits located outside the substrate 18 via the FPC 25.

[0045] IC20 may be mounted on the display device 10 using a mounting method such as COF (Chip On Film) or TCP (Tape Carrier Package). Figure 1B shows an example in which IC20 is placed on FPC25. By placing IC20 on FPC25, the area of ​​the substrate 18 can be reduced, and thus the display device 10 can be miniaturized.

[0046] The gate driver circuit 13 or the row driver circuit 19 may be implemented as an IC. In this case, an FPC electrically connected to the gate driver circuit 13 or an FPC electrically connected to the row driver circuit 19 may be provided on the substrate 18. Alternatively, the gate driver circuit 13 or the row driver circuit 19 may be provided on the display device 10 using a COF method, TCP method, or the like.

[0047] Figures 2A and 2B are schematic diagrams showing an example configuration of the display device 10, and are modified versions of the configuration shown in Figure 1A. The display device 10 in the configurations shown in Figures 2A and 2B differs from the display device 10 in the configuration shown in Figure 1A in that it has a laminated structure of layer 140 and layer 150.

[0048] A substrate 18 is provided in layer 140, and an insulating film 151, which functions as an interlayer insulating film, is provided in layer 150. In the display device 10 with the configuration shown in Figure 2A, an IC 20 and an FPC 25 are provided on the substrate 18, and a display unit 11, a gate driver circuit 13, and a row driver circuit 19 are provided on the insulating film 151. In the display device 10 with the configuration shown in Figure 2B, a gate driver circuit 13, a row driver circuit 19, an IC 20, and an FPC 25 are provided on the substrate 18, and a display unit 11 is provided on the insulating film 151.

[0049] By configuring the display device 10 as shown in Figure 2A or Figure 2B, the display unit 11 can be provided to have an area that overlaps with the IC 20. This allows the area of ​​the display unit 11 to be increased, making the display device 10 a large-screen display device. Furthermore, the display device 10 can be made with a narrow bezel.

[0050] Furthermore, by configuring the display device 10 as shown in Figure 2A or Figure 2B, the area occupied by IC 20 can be increased. This allows for a greater number of transistors and other components to be installed on IC 20. As will be described in detail later, IC 20 has the function of controlling the driving of pixels 12 installed on the display unit 11, for example. If the number of pixels 12 that IC 20 controls to drive is large, the configuration of the circuit installed on IC 20 becomes more complex, and therefore the number of transistors and other components installed on IC 20 increases. In summary, by configuring the display device 10 as shown in Figure 2A or Figure 2B, the number of pixels 12 that IC 20 can control to drive can be increased. Therefore, the number of pixels 12 installed on the display unit 11 can be increased. This allows for a higher pixel density of the display device 10. In addition, the display device 10 can be made into a large-screen display device.

[0051] Figure 3A is a schematic diagram showing an example configuration of pixel 12. The pixel 12 in the configuration shown in Figure 3A has a pixel circuit 14R that emits red light 16R, a pixel circuit 14G that emits green light 16G, a pixel circuit 14B that emits blue light 16B, and a pixel circuit 15 that detects light 17. Pixel circuits 14R, 14G, and 14B are each provided with light-emitting elements, and an image can be displayed on the display unit 11 using the pixel circuit 14. A light-receiving element is also provided in the pixel circuit 15.

[0052] In this specification, for example, pixel circuits 14R, 14G, and 14B are collectively referred to as pixel circuit 14. Also, for example, optical circuits 16R, 16G, and 16B are collectively referred to as optical circuit 16.

[0053] Figures 3B and 3C are schematic diagrams showing an example of the cross-sectional configuration of the display device 10. As shown in Figures 3B and 3C, pixel circuits 14 and 15 are provided between substrate 18 and substrate 121.

[0054] Because the display device 10 has not only a pixel circuit 14 equipped with a light-emitting element, but also a pixel circuit 15 equipped with a light-receiving element, the display device 10 can function as an image sensor or a touch sensor. For example, by detecting light irradiated onto the light-receiving element, the display device 10 can acquire imaging data. Also, as shown in Figure 3B, for example, it can detect an object such as a finger that is in contact with the display device 10. For example, when a finger 122 in contact with the display device 10 reflects light 16 emitted by a light-emitting element in the pixel circuit 14, the light-receiving element in the pixel circuit 15 detects the reflected light as light 17. This makes it possible to detect that a finger 122 has come into contact with the display device 10.

[0055] The display device 10 may have a function to detect objects that are close to it but not in contact with it. This allows the display device 10 to function as a near-touch sensor. Furthermore, as shown in Figure 3C, the display device 10 can detect the eyes 123 of the user. By detecting the eyes 123, the display device 10 can detect the user's facial expression, eye movements, pupil diameter, etc.

[0056] Furthermore, the display device 10 can acquire data such as fingerprints, palm prints, or iris scans. Therefore, the display device 10 can be configured as a display device with a biometric authentication function. In this case, the light-receiving element provided in the pixel circuit 15 can be said to function as a biometric authentication sensor, and the display device 10 can be said to have a built-in biometric authentication sensor. By having the display device 10 have a built-in biometric authentication sensor, the number of components in the electronic device on which the display device 10 is installed can be reduced compared to the case where a separate biometric authentication sensor is provided. Therefore, the electronic device can be made smaller and lighter.

[0057] As described above, the display device 10 can acquire data such as the user's facial expressions, eye movements, or changes in pupil diameter using light-emitting and light-receiving elements. By analyzing this data, information about the user's physical and mental state can be obtained. By changing the output content of either the display or sound, or both, based on this information, it becomes possible to enable users of VR (Virtual Reality), AR (Augmented Reality), or MR (Mixed Reality) devices to use the device safely.

[0058] As described above, when an object reflects the light 16 emitted by the light-emitting element of the display device 10, the light-receiving element can detect the reflected light as light 17. Therefore, imaging and other operations can be performed even in dark places.

[0059] Figure 3A shows an example configuration of a pixel 12 in which pixel circuits 14R, 14G, 14B, and 15 are arranged in a 2x2 matrix, but the present invention is not limited to this. As shown in Figure 3D, pixel circuits 14R, 14G, 14B, and 15 may be arranged in a single horizontal row.

[0060] Furthermore, as shown in Figure 3E, pixel 12 may have pixel circuits 14R, 14G, 14B, and 15, as well as pixel circuit 14W which has the function of emitting white light. When pixel 12 has the configuration shown in Figure 3E, pixel circuits 14R, 14G, 14B, and 14W can be collectively referred to as pixel circuit 14.

[0061] Furthermore, as shown in Figure 3F, in addition to the pixel circuits 14R, 14G, 14B, and 15, the pixel 12 may also have a pixel circuit 14IR that emits infrared light. In this case, it is preferable that the pixel circuit 15 has the function of detecting infrared light. The pixel circuit 15 may also have the function of detecting both visible light and infrared light. By providing the pixel 12 with a pixel circuit 14IR that emits infrared light and the pixel circuit 15 that detects infrared light, the display device 10 can detect objects such as fingers 122 and eyes 123 with high accuracy. Note that both the pixel circuit 14W and the pixel circuit 14IR may be provided in the pixel 12.

[0062] Furthermore, the pixel circuits 14R, 14G, and 14B shown in Figures 3A, 3D to 3F, the pixel circuit 14W shown in Figure 3E, and the pixel circuit 14IR shown in Figure 3F can all be considered pixel circuit 14.

[0063] Figure 4 is a block diagram showing an example configuration of the display device 10. As shown in Figure 4, the IC 20 is provided with an interface circuit 21, a control circuit 22, a memory circuit 26, a data driver circuit 23, and a readout circuit 24. The control circuit 22 also includes a timing signal generation circuit 101 and a level shift circuit 102.

[0064] In Figure 4, it is shown that three pixel circuits 14 are provided for each pixel 12. For example, if the pixel 12 has the configuration shown in Figure 3A or Figure 3D, the three pixel circuits 14 can be pixel circuit 14R, pixel circuit 14G, and pixel circuit 14B, respectively. Furthermore, if the pixel 12 has the configuration shown in Figure 3E or Figure 3F, it can be said that four pixel circuits 14 are provided for each pixel 12.

[0065] In this specification, when the same symbol is used for multiple elements, and especially when it is necessary to distinguish them, the symbol may be accompanied by an identifying symbol such as "[1]", "[m]", "[1,1]", or "[m,n]". For example, pixel 12 in the 1st row and 1st column is described as pixel 12[1,1], and pixel 12 in the mth row and nth column is described as pixel 12[m,n]. Furthermore, the pixel circuits 14 and 15 of pixel 12[1,1] are described as pixel circuit 14[1,1] and pixel circuit 15[1,1], respectively, and the pixel circuits 14 and 15 of pixel 12[m,n] are described as pixel circuit 14[m,n] and pixel circuit 15[m,n], respectively.

[0066] The gate driver circuit 13 is electrically connected to the pixel circuit 14 via wiring 31. The gate driver circuit 13 is also electrically connected to the pixel circuit 14 via wiring 36. The row driver circuit 19 is electrically connected to the pixel circuit 15 via wiring 32. The data driver circuit 23 is electrically connected to the pixel circuit 14 via wiring 33. The readout circuit 24 is electrically connected to the pixel circuit 14 via wiring 34 and to the pixel circuit 15 via wiring 35.

[0067] Figure 4 shows a configuration in which pixels 12 in the same row are electrically connected to the same wiring 31, the same wiring 36, and the same wiring 32, and pixels 12 in the same column are electrically connected to the same wiring 33, the same wiring 34, and the same wiring 35. In this specification, for example, the wirings 31, 36, and 32 electrically connected to the pixels 12 in the first row are described as wiring 31[1], wiring 36[1], and wiring 32[1], respectively, and the wirings 31, 36, and 32 electrically connected to the pixels 12 in the mth row are described as wiring 31[m], wiring 36[m], and wiring 32[m], respectively. Furthermore, for example, the wires 33, 34, and 35 electrically connected to the pixel 12 in the first row are described as wire 33[1], wire 34[1], and wire 35[1], respectively, and the wires 33, 34, and 35 electrically connected to the pixel 12 in the nth row are described as wire 33[n], wire 34[n], and wire 35[n], respectively.

[0068] The gate driver circuit 13 has the function of selecting the pixel 12 on which image data is written. Specifically, it can select the pixel 12 on which image data is written by outputting a signal to the wiring 31. Here, the gate driver circuit 13 outputs the above signal from wiring 31[1] to wiring 31[m] in order, thereby writing image data sequentially from the first row of pixels 12 to the mth row of pixels 12. Therefore, the signal that the gate driver circuit 13 supplies to the pixels 12 via wiring 31 can be said to be a scanning signal, and wiring 31 can be said to be a scanning line.

[0069] One electrode of the light-emitting element in the pixel circuit 14 is electrically connected to either the source or the drain of a drive transistor. The drive transistor has the function of controlling the current flowing through the light-emitting element according to the image data written to the pixel 12. By controlling the current flowing through the light-emitting element, the luminescence brightness of the light-emitting element can be controlled. However, if the threshold voltage of the drive transistor varies from pixel circuit 14 to pixel, display unevenness may occur. The display device 10 has the function of reading the magnitude of the current flowing between the drain and source of the drive transistor provided in the pixel circuit 14 as monitor current data. By correcting the threshold voltage of the drive transistor based on the current value represented by the monitor current data, display unevenness can be reduced. Therefore, a high-quality image can be displayed on the display unit 11.

[0070] The gate driver circuit 13 has a function to select the pixel from which to read the monitor current data. Specifically, by outputting a signal to the wiring 36, it can select the pixel 12 from which to read the monitor current data.

[0071] The row driver circuit 19 has the function of selecting a pixel 12 from which to read the image data acquired by the pixel circuit 15 having a light-receiving element. Specifically, by outputting a signal to the wiring 32, it can select a pixel 12 from which to read the image data. Here, the row driver circuit 19 outputs the above signal from wiring 32[1] to wiring 32[m] in order, thereby reading the image data sequentially from the first row of pixels 12 to the mth row of pixels 12. Therefore, the signal that the row driver circuit 19 supplies to the pixels 12 via wiring 32 can be said to be a scanning signal, and wiring 32 can be said to be a scanning line.

[0072] As described above, the signal supplied by the gate driver circuit 13 to the pixel circuit 14 via the wiring 31, and the signal supplied by the row driver circuit 19 to the pixel circuit 15 via the wiring 32, can both be called scan signals. Therefore, in this specification, for example, the signal supplied by the gate driver circuit 13 to the pixel circuit 14 via the wiring 31 may be referred to as the first scan signal, and the signal supplied by the row driver circuit 19 to the pixel circuit 15 via the wiring 32 may be referred to as the second scan signal. Also, the wiring 31 may be referred to as the first scan line, and the wiring 32 may be referred to as the second scan line.

[0073] The interface circuit 21 has the function of receiving a clock signal CLK1 and a digital image signal GS_D input from a circuit (not shown) electrically connected to the FPC 25. Here, the digital image signal GS_D is a digital signal representing image data to be written to the pixel 12. The interface circuit 21 also has the function of supplying the received clock signal CLK1 to the timing signal generation circuit 101 of the control circuit 22, and supplying the received digital image signal GS_D to the memory circuit 26. For example, if the signal received by the interface circuit 21 is a serial signal, it can be converted to a parallel signal and supplied to the control circuit 22 or the memory circuit 26, etc.

[0074] The control circuit 22 has the function of generating a start pulse signal and a clock signal and supplying them to the gate driver circuit 13, row driver circuit 19, data driver circuit 23, read circuit 24, and memory circuit 26. This allows the control circuit 22 to control the driving of the gate driver circuit 13, row driver circuit 19, data driver circuit 23, read circuit 24, and memory circuit 26. It is preferable to control the driving of the gate driver circuit 13, row driver circuit 19, data driver circuit 23, read circuit 24, and memory circuit 26 with a single control circuit 22 provided on IC 20, as this allows for a simple control method to correlate the driving of these circuits.

[0075] The timing signal generation circuit 101 of the control circuit 22 has the function of generating a start pulse signal SP_D and a clock signal CLK1_D and supplying them to the data driver circuit 23. The timing signal generation circuit 101 also has the function of generating a start pulse signal SP_R and a clock signal CLK1_R and supplying them to the readout circuit 24. The timing signal generation circuit 101 also has the function of generating a start pulse signal SP_M and a clock signal CLK1_M and supplying them to the memory circuit 26. Furthermore, the timing signal generation circuit 101 has the function of generating a start pulse signal GDSP and a clock signal GDCLK1, as well as a start pulse signal RDSP and a clock signal RDCLK1, and supplying them to the level shift circuit 102. Note that the clock signals CLK1_D, CLK1_R, CLK1_M, GDCLK1, and RDCLK1 can be generated by dividing the clock signal CLK1, etc. Here, dividing the clock signal CLK1 means changing the frequency of the clock signal CLK1 by a factor of 1 / N (where N is an integer greater than or equal to 1).

[0076] The level shift circuit 102 of the control circuit 22 has the function of generating a start pulse signal GDSP_LS by changing the potential level of the start pulse signal GDSP and supplying it to the gate driver circuit 13. The level shift circuit 102 also has the function of generating a clock signal GDCLK1_LS by changing the potential level of the clock signal GDCLK1 and supplying it to the gate driver circuit 13. Furthermore, the level shift circuit 102 has the function of generating a start pulse signal RDSP_LS by changing the potential level of the start pulse signal RDSP and supplying it to the row driver circuit 19. In addition, the level shift circuit 102 has the function of generating a clock signal RDCLK1_LS by changing the potential level of the clock signal RDCLK1 and supplying it to the row driver circuit 19.

[0077] The gate driver circuit 13 can be controlled by the start pulse signal GDSP_LS and the clock signal GDCLK1_LS. For example, when the start pulse signal GDSP_LS is input to the gate driver circuit 13, a first scan signal is sequentially output to wiring 31[1] to wiring 31[m] in response to the rising or falling edge of the clock signal GDCLK1_LS. Similarly, the row driver circuit 19 can be controlled by the start pulse signal RDSP_LS and the clock signal RDCLK1_LS. For example, when the start pulse signal RDSP_LS is input to the row driver circuit 19, a second scan signal is sequentially output to wiring 32[1] to wiring 32[m] in response to the rising or falling edge of the clock signal RDCLK1_LS.

[0078] The memory circuit 26 has the function of temporarily storing the digital image signal GS_D and supplying it to the data driver circuit 23 at a predetermined timing. The timing of supplying the digital image signal GS_D stored by the memory circuit 26 to the data driver circuit 23 can be controlled by the start pulse signal SP_M and the clock signal CLK1_M. The memory circuit 26 can be said to have the function of a frame memory. The memory circuit 26 can be configured using memory elements such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory).

[0079] The data driver circuit 23 has the function of supplying image data represented by the digital image signal GS_D to the pixel 12 via the wiring 33. Specifically, the data driver circuit 23 has the function of supplying image data represented by the digital image signal GS_D to the pixel 12 selected by the gate driver circuit 13 outputting a first scan signal to the wiring 31. Since the image data represented by the digital image signal GS_D is supplied to the pixel 12 via the wiring 33, the wiring 33 can be said to be a data line.

[0080] The data driver circuit 23 can be controlled by a start pulse signal SP_D and a clock signal CLK1_D. For example, when the start pulse signal SP_D is input to the data driver circuit 23, the digital image signal GS_D is sequentially output to wiring 33[1] to wiring 33[n] in response to the rising or falling edge of the clock signal CLK1_D.

[0081] The readout circuit 24 has the function of reading out monitor current data. Specifically, the readout circuit 24 has the function of reading out the monitor current data of the pixel circuit 14 selected by the gate driver circuit 13 outputting a signal to the wiring 36. The readout circuit 24 also has the function of reading out imaging data. Specifically, the readout circuit 24 has the function of reading out the imaging data written to the pixel 12 selected by the row driver circuit 19 outputting a second scanning signal to the wiring 32. Here, the readout circuit 24 has the function of outputting the readout data as a data signal DS_OUT and supplying it to the interface circuit 21. Therefore, the data signal DS_OUT can be a signal representing monitor current data or a signal representing imaging data.

[0082] The readout circuit 24 can be controlled by a start pulse signal SP_R and a clock signal CLK1_R. For example, when the start pulse signal SP_R is input to the readout circuit 24, the monitor current data input to the readout circuit 24 via wiring 34[1] to wiring 34[n] is output sequentially as data signals DS_OUT in accordance with the rising or falling edge of the clock signal CLK1_R. Alternatively, when the start pulse signal SP_R is input to the readout circuit 24, the imaging data input to the readout circuit 24 via wiring 35[1] to wiring 35[n] is output sequentially as data signals DS_OUT in accordance with the rising or falling edge of the clock signal CLK1_R.

[0083] Furthermore, since monitor current flows through wiring 34, wiring 34 can be considered a monitor line. Also, since the imaging data written to the pixel circuit 15 is output to wiring 35, wiring 35 can be considered a data line.

[0084] In this specification, the data signal DS_OUT corresponding to the monitor current data may be referred to as the monitor signal or the first data signal, and the data signal DS_OUT corresponding to the imaging data may be referred to as the imaging signal or the second data signal.

[0085] As shown in Figure 4, in one aspect of the present invention, both the data driver circuit 23 and the readout circuit 24 are provided on IC 20. That is, the data driver circuit 23 and the readout circuit 24 are provided on the same IC chip. In another aspect of the present invention, both the imaging data and the monitor current data are read out using the readout circuit 24. As a result, the supply of image data to the pixels 12, the reading out of imaging data, and the reading out of monitor current data can be performed using the same IC chip. Therefore, the display device 10 can be made less expensive than when the supply of image data to the pixels 12, the reading out of imaging data, and the reading out of monitor current data are performed using different IC chips.

[0086] <An example of a method for driving gate driver circuits and row driver circuits> Figure 5 is a timing chart showing an example of how to drive the gate driver circuit 13 and the row driver circuit 19. Specifically, Figure 5 is a timing chart showing the change over time of the potential of the wiring 31 electrically connected to the gate driver circuit 13 and the potential of the wiring 32 electrically connected to the row driver circuit 19. In the timing chart shown in Figure 5, high potential is indicated by "H" and low potential is indicated by "L". The same applies to other timing charts. For the sake of simplicity, the effects of various resistances such as wiring resistance, parasitic capacitance of transistors and wiring, and the threshold voltage of transistors are not considered. The same applies to other timing charts.

[0087] Here, the potential of wiring 31 to which the first scanning signal is output will be high. Also, the potential of wiring 32 to which the second scanning signal is output will be high. In addition, in other wirings, the potential of that wiring may also be high when a signal is output to that wiring.

[0088] During period T1[1], the gate driver circuit 13 sequentially outputs the first scan signal to, for example, wiring 31[1] to wiring 31[3]. On the other hand, the row driver circuit 19 does not output the second scan signal to wiring 32.

[0089] During period T2[1], the row driver circuit 19 sequentially outputs second scan signals to, for example, wiring 32[1] to wiring 32[3]. On the other hand, the gate driver circuit 13 does not output the first scan signal to wiring 31.

[0090] During period T1[2], the gate driver circuit 13 sequentially outputs the first scan signal to, for example, wiring 31[4] to wiring 31[6]. On the other hand, the row driver circuit 19 does not output the second scan signal to wiring 32.

[0091] During period T2[2], the row driver circuit 19 sequentially outputs second scan signals to, for example, wiring 32[4] to wiring 32[6]. On the other hand, the gate driver circuit 13 does not output the first scan signal to wiring 31.

[0092] As described above, the gate driver circuit 13 alternately outputs a first scan signal to the wiring 31, and the row driver circuit 19 alternately outputs a second scan signal to the wiring 32.

[0093] During period T1[n / 3], the gate driver circuit 13 sequentially outputs the first scan signal to, for example, wiring 31[n-2] to wiring 31[n]. On the other hand, the row driver circuit 19 does not output the second scan signal to wiring 32.

[0094] During period T2[n / 3], the row driver circuit 19 sequentially outputs a second scan signal to, for example, wiring 32[n-2] to wiring 32[n]. On the other hand, the gate driver circuit 13 does not output the first scan signal to wiring 31.

[0095] As described above, during period T1, the gate driver circuit 13 generates a first scan signal and outputs it to wiring 31, but the row driver circuit 19 does not generate a second scan signal. Therefore, period T1 can be described as a scan period for the gate driver circuit 13 and a pause period for the row driver circuit 19. On the other hand, during period T2, the row driver circuit 19 generates a second scan signal and outputs it to wiring 32, but the gate driver circuit 13 does not generate a first scan signal. Therefore, period T2 can be described as a pause period for the gate driver circuit 13 and a scan period for the row driver circuit 19.

[0096] As described above, in one aspect of the present invention, when one of the gate driver circuit 13 or the row driver circuit 19 is in the scanning period, the other of the gate driver circuit 13 or the row driver circuit 19 is in the idle period. This makes it possible to suppress interference between the driving of the pixel circuit 14 supplied with the first scanning signal by the gate driver circuit 13 and the driving of the pixel circuit 15 supplied with the second scanning signal by the row driver circuit 19. Therefore, it is possible to reduce the noise contained in the data output by the pixel circuit 14 and the data output by the pixel circuit 15. In particular, since the noise contained in the imaging data output by the pixel circuit 15 can be reduced, the display device 10 can detect objects such as fingers with high accuracy.

[0097] Furthermore, in the driving method shown in Figure 5, periods T1 and T2 are repeated multiple times within one frame period. That is, for example, it is not the case that a first scan signal is output sequentially to all of the wirings 31[1] to 31[m] in period T1[1], and then a second scan signal is output sequentially to all of the wirings 32[1] to 32[m] in period T2[1]. By repeating periods T1 and T2 multiple times in this way, it is possible to suppress the occurrence of flicker in the image displayed on the display unit 11 using the pixel circuit 14. Therefore, a high-quality image can be displayed on the display unit 11. Note that periods T1 and T2 may be provided once each within one frame period. That is, for example, a first scan signal may be output sequentially to all of the wirings 31[1] to 31[m] in period T1[1], and then a second scan signal may be output sequentially to all of the wirings 32[1] to 32[m] in period T2[1].

[0098] In the driving method shown in Figure 5, the period that is the scanning period for the gate driver circuit 13 becomes the pause period for the row driver circuit 19, and the period that is the pause period for the gate driver circuit 13 becomes the scanning period for the row driver circuit 19. Therefore, the driving of the gate driver circuit 13 and the driving of the row driver circuit 19 are not independent but are related to each other. For this reason, it is preferable to control the driving of the gate driver circuit 13 and the driving of the row driver circuit 19 with the same circuit, as this simplifies the control of the driving of the gate driver circuit 13 and the row driver circuit 19. Figure 4 shows a configuration in which the driving of the gate driver circuit 13 and the driving of the row driver circuit 19 are both controlled using the control circuit 22.

[0099] In Figure 5, the gate driver circuit 13 outputs a first scan signal to three wires 31 during period T1, and then the row driver circuit 19 outputs a second scan signal to three wires 32 during period T2. However, the present invention is not limited to this. In period T1, the gate driver circuit 13 may output a first scan signal to one or two wires 31, and then in period T2, the row driver circuit 19 may output a second scan signal to one or two wires 32. Alternatively, in period T1, the gate driver circuit 13 may output a first scan signal to four or more wires 31, and then in period T2, the row driver circuit 19 may output a second scan signal to four or more wires 32.

[0100] <Example of data driver circuit configuration> Figure 6 is a block diagram showing an example configuration of the data driver circuit 23. The data driver circuit 23 includes a shift register circuit 111, a latch circuit 112, a level shift circuit 113, a D / A (Digital to Analog) conversion circuit 114, and an amplifier circuit 115. Here, the number of latch circuits 112, level shift circuits 113, D / A conversion circuits 114, and amplifier circuits 115 can be provided in a number corresponding to, for example, the number of rows of pixels 12 provided on the display unit 11. For example, a configuration can be made in which n latch circuits 112, level shift circuits 113, D / A conversion circuits 114, and amplifier circuits 115 are each provided.

[0101] The shift register circuit 111 can be supplied with a start pulse signal SP_D and a clock signal CLK1_D. The latch circuit 112 can be supplied with a digital image signal GS_D.

[0102] The shift register circuit 111 has the function of generating a signal to control the drive of the latch circuit 112. The latch circuit 112 has the function of holding or outputting the digital image signal GS_D. For example, when a start pulse signal SP_D is input to the shift register circuit 111, the held digital image signal GS_D can be sequentially output from the latch circuits 112[1] to 112[n] in response to the rising or falling edge of the clock signal CLK1_D.

[0103] The level shift circuit 113 has the function of changing the potential level of the digital image signal GS_D output from the latch circuit 112. The D / A conversion circuit 114 has the function of converting the digital image signal output from the level shift circuit 113 into an analog image signal. The amplifier circuit has the function of amplifying the analog image signal output by the D / A conversion circuit 114 and outputting it to the wiring 33 as an analog image signal GS_A. By providing the amplifier circuit 115, the image data represented by the analog image signal GS_A can be stably supplied to the pixel 12. As the amplifier circuit 115, a voltage follower circuit having an operational amplifier or the like can be applied. When using a circuit with a differential input circuit as the amplifier circuit, it is preferable that the offset potential of the differential input circuit be as close to 0V as possible.

[0104] <Example of readout circuit configuration> Figure 7 is a block diagram showing an example configuration of the readout circuit 24. The readout circuit 24 includes a reference signal generation circuit 41, an A / D (Analog to Digital) conversion circuit 42, a shift register circuit 43, and a clock signal generation circuit 44. Here, the number of A / D conversion circuits 42 can be, for example, numbered to correspond to the number of rows of pixels 12 provided on the display unit 11. In other words, the readout circuit 24 can be provided with, for example, A / D conversion circuits 42[1] to A / D conversion circuits 42[n].

[0105] The reference signal generation circuit 41 has the function of generating a reference signal REF and supplying it to the A / D conversion circuit 42. Here, the reference signal REF can be, for example, a ramp signal, which is a signal whose potential changes continuously. The A / D conversion circuit 42 has the function of converting the analog monitor signal MS_A, which represents the monitor current data acquired by the pixel circuit 14, or the analog imaging signal IS_A, which represents the imaging data acquired by the pixel circuit 15, into a digital signal and outputting it as a data signal DS_OUT.

[0106] The shift register circuit 43 has the function of generating signals to control the driving of the A / D conversion circuit 42. For example, when a start pulse signal SP_R is input to the shift register circuit 43, the data signal DS_OUT can be sequentially output from the A / D conversion circuits 42[1] to 42[n] in response to the rising or falling edge of the clock signal CLK1_R.

[0107] The clock signal generation circuit 44 has the function of generating a clock signal CLK2 and supplying it to the A / D conversion circuit 42. Based on the reference signal REF and the clock signal CLK2, the A / D conversion circuit 42 can convert the analog monitor signal MS_A or the analog imaging signal IS_A into a digital signal and output it as a data signal DS_OUT.

[0108] <Example of pixel configuration> Figure 8 is a circuit diagram showing an example configuration of pixel 12. Figure 8 also shows the electrical connection relationship between pixel 12 and the A / D conversion circuit 42. In the example configuration shown in Figure 8, pixel 12 has pixel circuits 14R, 14G, 14B, and 15.

[0109] In Figure 8, all transistors are shown as n-channel transistors, but some or all of the transistors may be p-channel transistors by appropriately reversing the relative potentials. The same applies to circuit diagrams other than Figure 8.

[0110] Each pixel circuit 14 (referred to as pixel circuit 14R, pixel circuit 14G, and pixel circuit 14B in Figure 8) includes a light-emitting element 60, a transistor 61, a transistor 62, a transistor 63, and a capacitive element 64, respectively.

[0111] It is preferable to use an EL element such as an OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode) as the light-emitting element 60. Examples of light-emitting materials for EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials). In addition, LEDs such as microLEDs (Light Emitting Diodes) can also be used as the light-emitting element.

[0112] Here, when a color filter method is applied to the display device 10, the light-emitting elements 60 of the pixel circuit 14R, the light-emitting elements 60 of the pixel circuit 14G, and the light-emitting elements 60 of the pixel circuit 14B can all be light-emitting elements that emit white light. On the other hand, when a color separation method is applied to the display device 10, the light-emitting elements 60 of the pixel circuit 14R can be light-emitting elements that emit red light, the light-emitting elements 60 of the pixel circuit 14G can be light-emitting elements that emit green light, and the light-emitting elements 60 of the pixel circuit 14B can be light-emitting elements that emit blue light.

[0113] One electrode of the light-emitting element 60 is electrically connected to either the source or the drain of transistor 62. One of the source or the drain of transistor 62 is electrically connected to either the source or the drain of transistor 63. One of the source or the drain of transistor 63 is electrically connected to one electrode of the capacitive element 64. One of the source or the drain of transistor 61 is electrically connected to the gate of transistor 62. The gate of transistor 62 is electrically connected to the other electrode of the capacitive element 64.

[0114] The other electrode of the light-emitting element 60 is electrically connected to the wiring 65. The gate of transistor 61 is electrically connected to the wiring 31. The other source or drain of transistor 61 is electrically connected to the wiring 33. The other source or drain of transistor 62 is electrically connected to the wiring 37. The gate of transistor 63 is electrically connected to the wiring 36. The other source or drain of transistor 63 is electrically connected to the wiring 34. The wiring 34 is electrically connected to the A / D conversion circuit 42.

[0115] As mentioned above, wiring 31 functions as a scan line, wiring 33 functions as a data line, and wiring 34 functions as a monitor line. In addition, wiring 37 and wiring 65 function as power lines. For example, if either the source or drain of transistor 62 is electrically connected to the anode of light-emitting element 60, wiring 37 can be set to a high potential and wiring 65 to a low potential.

[0116] When the gate driver circuit 13 outputs a first scan signal to the wiring 31, the wiring 31 to which the first scan signal was output becomes high potential. As a result, the transistor 61 electrically connected to the wiring 31 becomes conductive, and the image data output by the data driver circuit 23 to the wiring 33 is written to the pixel circuit 14. Specifically, the gate potential of transistor 62 becomes the potential corresponding to the image data. As a result, a current of a magnitude corresponding to the gate potential of transistor 62 flows between the drain and source of transistor 62 and to the light-emitting element 60. Therefore, the light-emitting element 60 emits light with a brightness corresponding to the gate potential of transistor 62, and an image can be displayed on the display unit 11.

[0117] From the above, it can be said that transistor 62 has the function of controlling the current flowing to the light-emitting element 60 according to the image data written to the pixel circuit 14. Therefore, it can be said that transistor 62 has the function of controlling the driving of the light-emitting element 60. Thus, it can be said that transistor 62 is a driving transistor.

[0118] Here, if the threshold voltage of transistor 62 varies from pixel circuit 14 to pixel, display irregularities may occur. Therefore, display irregularities can be reduced by correcting the threshold voltage of transistor 62. The threshold voltage of transistor 62 can be calculated by measuring the current flowing between the drain and source of transistor 62. In the pixel circuit 14 with the configuration shown in Figure 8, by making transistor 63 conduct, an analog monitor signal MS_A representing the current flowing between the drain and source of transistor 62 is output to the A / D conversion circuit 42 via wiring 34.

[0119] The pixel circuit 15 includes a light-receiving element 70, transistors 71, 72, 73, 74, and a capacitive element 75. Note that if the gate capacitance of transistor 73 is sufficiently large, the capacitive element 75 may be omitted.

[0120] For example, a pn-type or pin-type photodiode can be used as the light-receiving element. The light-receiving element functions as a photoelectric conversion element that detects the irradiated light and generates an electric charge. The amount of charge generated is determined based on the amount of light irradiated onto the light-receiving element.

[0121] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light-receiving element. Organic photodiodes can be easily made thinner, lighter, and larger in area, and because they offer a high degree of freedom in shape and design, they can be applied to various display devices.

[0122] In one aspect of the present invention, for example, an organic EL element can be used as the light-emitting element and an organic photodiode can be used as the light-receiving element. Organic photodiodes have many layers that can share the same configuration as organic EL elements. Therefore, a light-receiving element can be incorporated into the display device 10 without significantly increasing the manufacturing process. For example, the active layer of the light-receiving element and the light-emitting layer of the light-emitting element can be manufactured separately, while the other layers can have the same configuration for both the light-emitting element and the light-receiving element.

[0123] One electrode of the light-receiving element 70 is electrically connected to either the source or the drain of transistor 71. The other source or drain of transistor 71 is electrically connected to either the source or the drain of transistor 72. One source or drain of transistor 72 is electrically connected to the gate of transistor 73. The gate of transistor 73 is electrically connected to one electrode of the capacitive element 75. One source or drain of transistor 73 is electrically connected to either the source or the drain of transistor 74. The other source or drain of transistor 74 is electrically connected to the wiring 35. The gate of transistor 74 is electrically connected to the wiring 32.

[0124] Furthermore, the wiring 35 is electrically connected to the A / D conversion circuit 42 and the current source 131. The current source 131 can be, for example, a transistor driven in the saturation region. When a transistor is used as the current source 131, it can be said that the transistor is a bias transistor, and the gate potential of the transistor can be said to be the bias potential.

[0125] When transistor 71 becomes conductive, the gate potential of transistor 73 becomes the potential corresponding to the illuminance of the light shining on the photodetector 70. This allows the pixel circuit 15 to acquire imaging data. Subsequently, when the row driver circuit 19 outputs a second scanning signal to wiring 32, wiring 32 to which the second scanning signal has been output becomes high potential. Therefore, transistor 74, which is electrically connected to wiring 32, becomes conductive, and the potential of wiring 35 becomes the potential corresponding to the gate potential of transistor 73. As a result, the imaging data acquired by the pixel circuit 15 is supplied to the A / D conversion circuit 42 via wiring 35 as the analog imaging signal IS_A.

[0126] In the pixel 12 configuration shown in Figure 8, pixel circuits 14R, 14G, 14B, and 15 are arranged in a single row, but the present invention is not limited to this configuration. For example, they may be arranged in two rows and two columns. Figure 9 shows an example of the configuration of pixel 12 when pixel circuit 14R is placed in the first row and first column, pixel circuit 14G is placed in the first row and second column, pixel circuit 14B is placed in the second row and first column, and pixel circuit 15 is placed in the second row and second column.

[0127] Figure 10 shows a modified version of the configuration shown in Figure 8, differing from the configuration in that a CDS circuit 80 is provided. The CDS circuit 80 includes a capacitive element 76, a transistor 77, a transistor 78, and a transistor 79.

[0128] One electrode of the capacitive element 76 is electrically connected to the wiring 35. The other electrode of the capacitive element 76 is electrically connected to either the source or the drain of transistor 77. Either the source or the drain of transistor 77 is electrically connected to the gate of transistor 78. Either the source or the drain of transistor 78 is electrically connected to either the source or the drain of transistor 79. Either the source or the drain of transistor 79 is electrically connected to the wiring 38. The wiring 38 is electrically connected to the A / D conversion circuit 42.

[0129] By providing a CDS circuit 80 between the pixel circuit 15 and the A / D conversion circuit 42, correlated double sampling (CDS) can be performed on the imaging data acquired by the pixel circuit 15. Here, correlated double sampling on the imaging data acquired by the pixel circuit 15 means taking the difference between the potential of the wiring 35 when reading the imaging data written to the pixel circuit 15 and the potential of the wiring 35 when resetting the imaging data written to the pixel circuit 15. By performing correlated double sampling, the analog imaging signal IS_A supplied to the A / D conversion circuit 42 can be made into a signal with reduced noise.

[0130] Figure 11A shows an example of the configuration of the pixel circuit 14, and is a modified version of the configuration of the pixel circuit 14 shown in Figures 8 to 10. The pixel circuit 14 in the configuration shown in Figure 11A includes a light-emitting element 60, transistors 61a, 61b, 62, 63, 66, a capacitive element 64, and a capacitive element 67. The pixel circuit 14 in the configuration shown in Figure 11A is electrically connected to wiring 31a and wiring 31b as wiring 31.

[0131] One electrode of the light-emitting element 60 is electrically connected to either the source or the drain of transistor 62. One of the source or the drain of transistor 62 is electrically connected to either the source or the drain of transistor 63. The gate of transistor 62 is electrically connected to either the source or the drain of transistor 61a. One of the source or the drain of transistor 61a is electrically connected to one electrode of capacitive element 64. The other electrode of capacitive element 64 is electrically connected to either the source or the drain of transistor 61b. One of the source or the drain of transistor 61b is electrically connected to either the source or the drain of transistor 66. One of the source or the drain of transistor 66 is electrically connected to one electrode of capacitive element 67.

[0132] The other electrode of the light-emitting element 60 is electrically connected to the wiring 65. The gate of transistor 61a and the gate of transistor 66 are electrically connected to the wiring 31a. The gate of transistor 61b is electrically connected to the wiring 31b. The other source or drain of transistor 61a and the other source or drain of transistor 61b are electrically connected to the wiring 33. The other source or drain of transistor 62 and the other electrode of capacitive element 67 are electrically connected to the wiring 37. The gate of transistor 63 is electrically connected to the wiring 36. The other source or drain of transistor 63 is electrically connected to the wiring 34. The other source or drain of transistor 66 is electrically connected to the wiring 68.

[0133] Here, node FD11 is defined as the node to which one of the source or drain of transistor 61a, the gate of transistor 62, and one electrode of capacitive element 64 are electrically connected. Also, node FD12 is defined as the node to which one of the source or drain of transistor 61b, the other electrode of capacitive element 64, one of the source or drain of transistor 66, and one electrode of capacitive element 67 are electrically connected.

[0134] Wiring 68 functions as a power line. The potential of wiring 68 is defined as potential V0.

[0135] In the pixel circuit 14 with the configuration shown in Figure 11A, the potential of node FD11 can be maintained by making transistor 61a non-conductive. Furthermore, the potential of node FD12 can be maintained by making transistors 61b and 66 non-conductive. In addition, by making transistor 61a non-conductive and changing the potential of node FD12, the potential of node FD11 can be changed through capacitive coupling via the capacitive element 64.

[0136] Here, it is preferable to use a transistor with a low off-current as transistor 61a, as this allows the potential of node FD11 to be maintained for a long period of time. Similarly, it is preferable to use transistors with low off-currents as transistors 61b and 66, as this allows the potential of node FD12 to be maintained for a long period of time. Examples of transistors with low off-currents include transistors that use a metal oxide in the channel formation region (hereinafter referred to as OS transistors).

[0137] OS transistors preferably have a metal oxide in the channel formation region. Furthermore, the metal oxide applied to the OS transistor is preferably an oxide containing at least one of indium (In) and zinc (Zn).

[0138] Examples of such oxides include In-M-Zn oxide, In-M oxide, Zn-M oxide, and In-Zn oxide (where element M is selected from, for example, aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), vanadium (V), beryllium (Be), hafnium (Hf), tantalum (Ta), and tungsten (W)). Typical examples of In-M-Zn oxide include In-Ga-Zn oxide, In-Sn-Zn oxide, and In-Ga-Sn-Zn oxide.

[0139] OS transistors have an off-current of 1 yA / μm per 1 μm of channel width (y: yocto, 10 -24 ) or more 1 zA / μm (z: zepto, 10 -21 It can be reduced to the following level.

[0140] Furthermore, it is preferable to use CAC (Cloud-Aligned Composite)-OS for the OS transistor. Details of CAC-OS will be described in a later embodiment.

[0141] Furthermore, in addition to transistors 61a, 61b, and 66, OS transistors may also be used for transistors 62 and 63. In other words, OS transistors may be used for all transistors in the pixel circuit 14. This allows all transistors in the pixel circuit 14 to be formed in the same process. Also, in addition to transistors 61a, 61b, 62, 63, and 66, OS transistors may be used for transistors 71 to 74 in the pixel circuit 15. In other words, OS transistors may be used not only for the transistors in the pixel circuit 14, but also for the transistors in the pixel circuit 15.

[0142] Furthermore, transistors using silicon in the channel formation region (hereinafter referred to as Si transistors) may be used as transistors 61a, 61b, and 66. Also, Si transistors may be used for transistor 62 or transistor 63. Furthermore, Si transistors may be used for transistors 71 to 74 of the pixel circuit 15. Examples of silicon include amorphous silicon and crystalline silicon (low-temperature polysilicon, single-crystal silicon, etc.).

[0143] If all the transistors in pixel 12 are of the same type, then all the transistors in pixel 12 can be formed using the same process. This reduces the number of manufacturing steps for the display device 10, and therefore the display device 10 can be made to a lower cost.

[0144] Transistors 61a, 61b, and 66 may be transistors other than OS transistors that have low off-current. For example, transistors using semiconductors with a large bandgap may be used. A semiconductor with a large bandgap may refer to a semiconductor with a bandgap of 2.2 eV or more. Examples include silicon carbide, gallium nitride, and diamond.

[0145] Figure 11B is a timing chart showing an example of a driving method for the pixel circuit 14 configured as shown in Figure 11A. In the driving method shown in Figure 11B, one frame period is divided into periods T101, T102, and T103. Period T101 is the period during which a potential VDa corresponding to data Da is supplied to node FD11, and period T103 is the period during which a potential VDb corresponding to data Db is supplied to node FD12. During periods T101 to T103, the potential of the wiring 36 is set to a low potential, and transistor 63 is made non-conductive. This suppresses the current flowing between the drain and source of the driving transistor 62 from flowing through transistor 63 to the wiring 34, so that the current flowing between the drain and source of transistor 62 can be efficiently supplied to the light-emitting element 60.

[0146] During period T101, the potential of wiring 31a is raised to a high potential, causing transistors 61a and 66 to become conductive. Data Da is also supplied to the pixel circuit 14 via wiring 33. By making transistor 66 conductive, the potential of node FD12 becomes potential V0. This resets the potential of node FD12. Furthermore, by making transistor 61a conductive and supplying data Da to the pixel circuit 14, the potential of node FD11 becomes potential VDa. As a result, data Da is written to the pixel circuit 14.

[0147] During period T102, the potential of wiring 31a is reduced to a low potential, causing transistors 61a and 66 to become non-conductive. This terminates the supply of potential VDa to node FD11 and potential V0 to node FD12.

[0148] During period T103, the potential of wiring 31b is raised to a high potential, causing transistor 61b to conduct. Additionally, data Db is supplied to the pixel circuit 14 via wiring 33. This causes the potential of node FD12 to become potential VDb. Therefore, the potential of node FD12 changes by potential "VDb-V0". As a result, data Db is written to the pixel circuit 14.

[0149] Here, due to capacitive coupling by the capacitive element 64, the potential of node FD11 changes in accordance with the change in the potential of node FD12. Specifically, if the capacitive coupling coefficient of node FD11 is c (where c is a real number between 0 and 1), the potential of node FD11 changes by a potential of "c(VDb-V0)". Here, the potential of node FD11 during period T102 is potential VDa. Therefore, during period T103, the potential of node FD11 becomes potential "VDa+c(VDb-V0)". Note that although Figure 11B shows potential VDb as being greater than potential V0, potential VDb may also be less than potential V0.

[0150] The capacitive coupling coefficient c is roughly determined by the capacitance value of the capacitive element 64 and the capacitance value of the parasitic capacitance of node FD11, such as the gate capacitance of transistor 62. If the capacitance value of the capacitive element 64 is larger than the parasitic capacitance of node FD11, the value of c will increase and approach 1, so the potential of node FD11 in period T103 will be close to the potential "VDa + VDb - V0".

[0151] As shown in Figure 11A, the pixel circuit 14 can combine two types of data. This allows the image displayed on the display unit 11 using the pixel circuit 14 to be corrected internally within the pixel circuit 14. For example, one of the data Da or data Db can be used as image data, and the other of the data Da or data Db can be used as correction data. For example, data Da can be used as correction data and data Db can be used as image data. If data Da is used as correction data and data Db is used as image data, and a transistor with a low off-current, such as an OS transistor, is used as transistor 61a, the correction data can be retained in the pixel circuit 14 for a long period of time. Therefore, it is no longer necessary to write the correction data to the pixel circuit 14 for each frame, and the frequency of writing the correction data to the pixel circuit 14 can be reduced. Consequently, the power consumption of the display device 10 can be reduced.

[0152] Furthermore, both data Da and data Db may be image data. This allows an image created by superimposing the two images to be displayed on the display unit 11. The magnitude of the potential VDa corresponding to data Da and the magnitude of the potential VDb corresponding to data Db are limited by the withstand voltage of the data driver circuit 23, etc. Therefore, by superimposing data Da and data Db, the potential of node FD11 can be set to a potential higher than the maximum potential that the data driver circuit 23 can output. For example, if the capacitive coupling coefficient c of node FD11 is 1, the maximum potential of node FD11 can be set to twice the maximum potential that the data driver circuit 23 can output. Therefore, a potential higher than the maximum potential that the data driver circuit 23 can output can be applied to the gate of the drive transistor transistor 62, allowing a large current to flow through the light-emitting element 60. Consequently, the luminescence brightness of the light-emitting element 60 can be increased, and a high-brightness image can be displayed on the display unit 11. In addition, the dynamic range, which is the difference between the maximum and minimum luminescence brightness of the light-emitting element 60 when displaying an image on the display unit 11, can be expanded. Furthermore, the image corresponding to data Da and the image corresponding to data Db may be the same or different. Also, as mentioned above, if a transistor with a low off-current, such as an OS transistor, is used as transistor 61a, it becomes unnecessary to write data Da to the pixel circuit 14 every frame, and the frequency of writing data Da to the pixel circuit 14 can be reduced to the frequency of writing data Db.

[0153] Furthermore, by increasing the luminescence brightness of the light-emitting element 60, the brightness of the light 16 shown in Figures 3A to 3C can be increased. This increases the brightness of the light 17, which is reflected light from objects such as fingers 122 and eyes 123 and irradiates the pixel circuit 15. Therefore, the object detection sensitivity of the pixel circuit 15 can be increased.

[0154] ​Figure 12A is a circuit diagram showing an example configuration of the A / D conversion circuit 42. Figure 12A also shows the electrical connection relationships between the pixel circuits 14 and 15 and the A / D conversion circuit 42.

[0155] The A / D conversion circuit 42 includes a transistor 51a, a transistor 51b, a capacitive element 52, a comparator circuit 53, and a counter circuit 54. Note that the capacitive element 52 is optional.

[0156] Either the source or drain of transistor 51a is electrically connected to the pixel circuit 14 via wiring 34. The gate of transistor 51a is electrically connected to wiring 55a. Either the source or drain of transistor 51b is electrically connected to the pixel circuit 15 via wiring 35. The gate of transistor 51b is electrically connected to wiring 55b. If a CDS circuit 80 is provided as shown in Figure 10, either the source or drain of transistor 51b is electrically connected to the CDS circuit 80 via wiring 38.

[0157] The source or drain of transistor 51a is electrically connected to the other source or drain of transistor 51b. The source or drain of transistor 51b is electrically connected to one electrode of capacitive element 52. The other electrode of capacitive element 52 is electrically connected to wiring 59. One electrode of capacitive element 52 is electrically connected to the first input terminal of comparator circuit 53. The second input terminal of comparator circuit 53 is electrically connected to reference signal generation circuit 41. The output terminal of comparator circuit 53 is electrically connected to counter circuit 54.

[0158] In this specification, the first input terminal of the comparator circuit refers to either the non-inverting input terminal or the inverting input terminal of the comparator circuit, and the second input terminal of the comparator circuit refers to the other of the non-inverting input terminal or the inverting input terminal of the comparator circuit. In the following description, we will assume that the first input terminal of the comparator circuit 53 is a non-inverting input terminal and the second input terminal of the comparator circuit 53 is an inverting input terminal. However, by appropriately reversing the relative magnitudes of the potentials, the first input terminal may be made an inverting input terminal and the second input terminal a non-inverting input terminal.

[0159] Wiring 59 functions as a power line. The potential of wiring 59 can be, for example, low.

[0160] Transistors 51a and 51b function as switches to select the signal to be converted using A / D conversion. For example, if the potential of wiring 55a is set to a high potential and the potential of wiring 55b is set to a low potential, transistor 51a will be in a conducting state and transistor 51b will be in a non-conducting state. In this case, the A / D conversion circuit 42 can perform A / D conversion on the analog monitor signal MS_A output by the pixel circuit 14 to wiring 34 and output it as a digital data signal DS_OUT. On the other hand, if the potential of wiring 55a is set to a low potential and the potential of wiring 55b is set to a high potential, transistor 51a will be in a non-conducting state and transistor 51b will be in a conducting state. In this case, the A / D conversion circuit 42 can perform A / D conversion on the analog imaging signal IS_A output by the pixel circuit 15 to wiring 35 and output it as a digital data signal DS_OUT.

[0161] By providing transistors 51a and 51b, the analog monitor signal MS_A output from the pixel circuit 14 and the analog imaging signal IS_A output from the pixel circuit 15 can be converted into digital signals using the same A / D conversion circuit.

[0162] The comparison circuit 53 compares the potential of the non-inverting input terminal with the potential of the inverting input terminal and outputs a comparison signal CMP from the output terminal. Specifically, if the potential of the non-inverting input terminal is greater than the potential of the inverting input terminal, the potential of the comparison signal CMP will be high. On the other hand, if the potential of the non-inverting input terminal is less than the potential of the inverting input terminal, the potential of the comparison signal CMP will be low.

[0163] The counter circuit 54 has the function of outputting a digital data signal DS_OUT based on the comparison signal CMP, the signal supplied from the shift register circuit 43, and the clock signal CLK2. For example, the counter circuit 54 has the function of counting the number of rising edges of the clock signal CLK2 when the comparison signal CMP is at a low potential, and stopping the count when the comparison signal CMP is at a high potential. The counter circuit 54 may also have the function of counting the number of falling edges of the clock signal CLK2. Furthermore, the counter circuit 54 may have the function of counting both the number of rising edges and the number of falling edges of the clock signal CLK2 when the comparison signal CMP is at a high potential, and stopping the count when the comparison signal CMP is at a low potential.

[0164] In Figure 12A, transistors 51a and 51b are provided in the A / D conversion circuit 42, but as shown in Figure 12B, transistors 51a and 51b may be provided outside the A / D conversion circuit 42. For example, transistors 51a and 51b may be provided outside the IC 20.

[0165] Figure 13 is a timing chart showing an example of a driving method for the A / D conversion circuit 42 with the configuration shown in Figure 12A or Figure 12B.

[0166] ​During period T, the potential of the reference signal REF is higher than the potential of the analog monitor signal MS_A or the analog imaging signal IS_A. Therefore, the potential of the comparison signal CMP is low.

[0167] During period T, the counter circuit 54 counts the number of rising edges of the clock signal CLK2. Specifically, the counter circuit 54 outputs a data signal DS_OUT with a digital value corresponding to the number of rising edges of the clock signal CLK2. Figure 13 shows the number of rising edges of the clock signal CLK during period T minus 1 as the data signal DS_OUT.

[0168] Furthermore, during period T, the potential of the reference signal REF is continuously decreased. When the potential of the reference signal REF falls below the potential of the analog monitor signal MS_A or the potential of the analog imaging signal IS_A, the potential of the comparison signal CMP becomes high. Period T is considered to end when the potential of the comparison signal CMP becomes high.

[0169] After the end of period T, the counter circuit 54 stops counting the number of rising edges of the clock signal CLK2. Therefore, after the end of period T, the counter circuit 54 continues to output a data signal DS_OUT with a digital value corresponding to the number of times the clock signal CLK2 rose from the start to the end of period T.

[0170] By the above method, the A / D conversion circuit 42 can convert the analog monitor signal MS_A or the analog imaging signal IS_A into a digital signal. Specifically, the A / D conversion circuit 42 can output a data signal DS_OUT that is a digital value corresponding to the potential of the analog monitor signal MS_A or the potential of the analog imaging signal IS_A. When A / D conversion is performed on the analog monitor signal MS_A, the value of the monitor current can be calculated by converting the potential of the analog monitor signal MS_A represented by the data signal DS_OUT into a current. The value of the monitor current can be calculated, for example, by a circuit provided in IC20. For example, the value of the monitor current can be calculated by the interface circuit 21.

[0171] Figure 14A is a circuit diagram showing an example configuration of the A / D conversion circuit 42, and shows a different configuration from Figure 12A. The A / D conversion circuit 42 in the configuration shown in Figure 14A includes transistors 51a, 51b, 81, 82a, 82b, 83a, 83b, 85, 86, capacitive element 52, capacitive element 84a, capacitive element 84b, comparator circuit 53, and counter circuit 54. Note that the capacitive element 52 is optional.

[0172] Either the source or drain of transistor 51a is electrically connected to the pixel circuit 14 via wiring 34. Either the source or drain of transistor 51b is electrically connected to the pixel circuit 15 via wiring 35. Furthermore, if a CDS circuit 80 is provided as shown in Figure 10, either the source or drain of transistor 51b is electrically connected to the CDS circuit 80 via wiring 38.

[0173] ​The other source or drain of transistor 51a is electrically connected to the other source or drain of transistor 51b. The other source or drain of transistor 51b is electrically connected to one electrode of capacitive element 52. One electrode of capacitive element 52 is electrically connected to one source or drain of transistor 81. One source or drain of transistor 81 is electrically connected to one source or drain of transistor 82a. The other source or drain of transistor 82a is electrically connected to one source or drain of transistor 83a. One source or drain of transistor 83a is electrically connected to one electrode of capacitive element 84a. The other electrode of capacitive element 84a, one source or drain of transistor 85, and the first input terminal of comparator circuit 53 are electrically connected to wiring 56.

[0174] One of the sources or drains of transistor 82b is electrically connected to the reference signal generation circuit 41. The other of the sources or drains of transistor 82b is electrically connected to one of the sources or drains of transistor 83b. One of the sources or drains of transistor 83b is electrically connected to one electrode of the capacitive element 84b. The other electrode of the capacitive element 84b, the second input terminal of the comparator circuit 53, and one of the sources or drains of transistor 86 are electrically connected to the wiring 57. The output terminal of the comparator circuit 53 is electrically connected to the counter circuit 54 and the other of the sources or drains of transistor 86.

[0175] The gate of transistor 51a is electrically connected to wiring 55a. The gate of transistor 51b is electrically connected to wiring 55b. The other electrode of capacitive element 52 is electrically connected to wiring 59. The gate of transistor 81 is electrically connected to wiring 91. The other source or drain of transistor 81 is electrically connected to wiring 92. The gates of transistor 82a and transistor 82b are electrically connected to wiring 93. The gates of transistor 83a and transistor 83b are electrically connected to wiring 94. The other source or drain of transistor 83a and transistor 83b are electrically connected to wiring 95. The gates of transistor 85 and transistor 86 are electrically connected to wiring 96. The other source or drain of transistor 85 is electrically connected to wiring 97. In addition to wiring 59, wirings 92, 95, and 97 also function as power lines.

[0176] Node FD1 is defined as the node to which either the source or drain of the pixel circuit 14 and transistor 51a are electrically connected. Here, the parasitic capacitance of node FD1 is denoted as parasitic capacitance PC.

[0177] Furthermore, node FD2a is defined as the node to which the other source or drain of transistor 82a, the other source or drain of transistor 83a, and one electrode of capacitive element 84a are electrically connected. Also, node FD2b is defined as the node to which the other source or drain of transistor 82b, the other source or drain of transistor 83b, and one electrode of capacitive element 84b are electrically connected. In addition, node FD3 is defined as the node to which the reference signal generation circuit 41 and one source or drain of transistor 82b are electrically connected.

[0178] By configuring the A / D conversion circuit 42 as shown in Figure 14A, the monitor current I can be calculated using the following formula, although details will be described later. Here, C FD1 This indicates the capacitance value of node FD1 when transistor 51a is conducting, and ΔVFD1 / Δt indicates the change in potential at node FD1 over time. In the configuration shown in Figure 14A, the capacitance value C FD1 This can be the sum of the capacitance value of the parasitic capacitance PC and the capacitance value of the capacitance element 52. As mentioned above, the value of the monitor current can be calculated by a circuit provided in IC20, for example. For example, the value of the monitor current can be calculated by the interface circuit 21.

[0179]

number

[0180] Furthermore, if the capacity value of the parasitic capacity PC is small, the capacity value C of node FD1 will be small. FD1 ΔV becomes smaller, FD1 / Δt becomes large. In other words, the potential of node FD1 changes significantly in a short time. This can make it difficult to calculate the monitor current I with high accuracy. In this case, by increasing the capacitance value of the capacitive element 52, the capacitance value C of node FD1 when transistor 51a is conducting can be increased. FD1 By increasing this value, the monitor current I can be calculated with high accuracy.

[0181] By configuring the A / D conversion circuit 42 as shown in Figure 14A, the monitor current value can be calculated while taking into account the parasitic capacitance PC of the wiring 34. Therefore, since the monitor current value can be calculated with high accuracy, the threshold voltage of the transistor 62, which functions as a drive transistor for the pixel circuit 14, can be corrected with high accuracy. Consequently, display unevenness can be reduced, and a high-quality image can be displayed on the display unit 11.

[0182] In Figure 14A, transistors 51a and 51b are provided in the A / D conversion circuit 42, but as shown in Figure 14B, transistors 51a and 51b may be provided outside the A / D conversion circuit 42. For example, transistors 51a and 51b may be provided outside the IC 20.

[0183] <Example of Driving Method for A / D Conversion Circuit_2> Hereinafter, an example of a driving method for the A / D conversion circuit 42 will be described.

[0184] Capacitance value C FD1 Example of Calculation Method] FIG. 15 is a timing chart illustrating an example of a method for calculating a capacitance value C of the node FD1 when the transistor 51a is in a conductive state in a case where the A / D conversion circuit 42 has the configuration shown in FIG. 14A or 14B FD1 .

[0185] When the capacitance value C of the node FD1 in a case where the transistor 51a is in a conductive state is calculated by the method shown in FIG. 15 FD1 , a period during which the A / D conversion circuit 42 is driven can be divided into a period T11 to a period T15. Here, in the period T11 to the period T15, the potential of the wiring 55a is set to a high potential to bring the transistor 51a into a conductive state. On the other hand, the potential of the wiring 55b is set to a low potential to bring the transistor 51b into a non-conductive state.

[0186] FIGS. 16 to 18 are circuit diagrams each illustrating an example of a driving method of the A / D conversion circuit 42 and the like in each period shown in FIG. 15. Specifically, FIG. 16 is a circuit diagram illustrating an example of a driving method of the A / D conversion circuit 42 and the like in the period T11, FIG. 17A is in the period T12, FIG. 17B is in the period T13, FIG. 18A is in the period T14, and FIG. 18B is in the period T15. Note that in FIGS. 16 to 18, transistors are shown as switches to indicate the conductive state and non-conductive state of the transistors included in the A / D conversion circuit 42. The same notation may be used in other circuit diagrams illustrating an example of a driving method of the A / D conversion circuit 42 and the like.

[0187] As shown in Figures 16 to 18, during periods T11 to T15, the transistor 63, which is provided in the pixel circuit 14 and electrically connected to the wiring 34, is made non-conductive. In addition, the potentials of wirings 92, 95, and 97, which function as power lines, are set to potentials VPRE, VCOM1, and VCOM2, respectively. Here, potential VPRE is set to be greater than potential VCOM1. As mentioned above, the potential of wiring 59 can be set to a low potential.

[0188] As shown in Figures 15 and 16, during period T11, the potential of wiring 91 is raised to a high potential, causing transistor 81 to conduct. Also, the potential of wiring 93 is lowered to a low potential, causing transistors 82a and 82b to become non-conductive. Furthermore, the potential of wiring 94 is raised to a high potential, causing transistors 83a and 83b to conduct. As a result, the potential of node FD1 becomes potential VPRE, and the potentials of nodes FD2a and FD2b become potential VCOM1. Since the potential of node FD1 is precharged to potential VPRE, period T11 can be described as a precharge period.

[0189] Furthermore, as shown in Figures 15 and 16, during period T11, the potential of wiring 96 is raised to a high potential, causing transistors 85 and 86 to conduct. By causing transistor 85 to conduct, the potential of wiring 56 becomes potential VCOM2. Also, by causing transistor 86 to conduct, the output terminal of comparator circuit 53 and the second input terminal of comparator circuit 53 become conductive. In other words, feedback, such as negative feedback, is applied to comparator circuit 53. As a result, the potential of the comparison signal CMP output from the output terminal of comparator circuit 53 becomes the potential VCOM2 plus the offset potential Voffset. Therefore, the potential of wiring 57, which is electrically connected to the second input terminal of comparator circuit 53, also becomes the potential VCOM2 plus the offset potential Voffset. As a result, a charge corresponding to the offset potential Voffset is accumulated in the capacitive element 84b. Specifically, a charge corresponding to the difference between the potential VCOM1 of node FD2b and the potential of wiring 57 "VCOM2 + Voffset" is accumulated in the capacitive element 84b. Therefore, offset correction can be performed on the comparison circuit 53.

[0190] As shown in Figures 15 and 17A, during period T12[1], the potential of wiring 91 is reduced to a low potential, thereby causing transistor 81 to become non-conductive. This completes the pre-charging of node FD1.

[0191] As shown in Figures 15 and 17B, during period T13[1], the potential of wiring 93 is raised to a high potential, causing transistors 82a and 82b to become conductive. Furthermore, the potential of wiring 94 is lowered to cause transistors 83a and 83b to become non-conductive. As a result, node FD1 and node FD2a become conductive, while node FD2a and wiring 95 become non-conductive. This results in node FD1 and node FD2a being electrically connected, while both nodes FD1 and FD2a become electrically floating. Therefore, when transistor 51a is conductive, charge distribution occurs between the capacitance of node FD1 (parasitic capacitance PC, and capacitance element 52, etc.) and the capacitance of node FD2a (capacitance element 84a, etc.), and the potential Vs[1] of nodes FD1 and FD2a is as shown in the following equation. Here, the capacitance value C FD2a This indicates the capacity value of node FD2a.

[0192]

number

[0193] As mentioned above, the potential VPRE, which is the potential of node FD1 during period T12[1], is greater than the potential VCOM1, which is the potential of node FD2a during period T12[1]. Therefore, the potential of node FD1 decreases during period T13[1].

[0194] As shown in Figures 15 and 17A, during period T12[2], the potential of wiring 93 is set to a low potential, and transistors 82a and 82b are made non-conductive. As a result, nodes FD1 and FD2a become non-conductive. Also, the potential of wiring 94 is set to a high potential, and transistors 83a and 83b become conductive. As a result, the potential of nodes FD2a and FD2b becomes potential VCOM1. Here, since nodes FD1 and FD2a are non-conductive, during period T12[2], the potential Vs[1] of node FD1 during period T13[1] is maintained at node FD1.

[0195] As shown in Figures 15 and 17B, during period T13[2], the potential of wiring 93 is set to a high potential and the potential of wiring 94 is set to a low potential. As a result, similar to period T13[1], charge distribution occurs between the capacitance of node FD1 and the capacitance of node FD2a, and the potentials Vs[2] of nodes FD1 and FD2a are as shown by the following equation.

[0196]

number

[0197] The potential Vs[1] at node FD1 during period T12[2] is greater than the potential VCOM1 at node FD2a during period T12[2]. Therefore, the potential at node FD1 decreases during period T13[2]. Note that, as shown in equation 3, the equation representing potential Vs[2] includes potential Vs[1]. Thus, the equation representing potential Vs can be said to be a recurrence relation.

[0198] In this way, by repeating periods T12 and T13 multiple times, the potential of node FD1 can be significantly reduced. Figure 15 shows the case where the operation of period T12 is performed 5 times and the operation of period T13 is performed 4 times. Alternatively, the operation of period T12 may be performed 2 times and the operation of period T13 may be performed 1 time. Alternatively, the operation of period T12 may be performed 3 times and the operation of period T13 may be performed 2 times. Alternatively, the operation of period T12 may be performed 4 times and the operation of period T13 may be performed 3 times. Furthermore, the operation of period T12 may be performed 6 or more times and the operation of period T13 may be performed 5 or more times.

[0199] The potential VPRE may be less than or equal to the potential VCOM1. If the potential VPRE is less than the potential VCOM1, the potential of node FD1 will rise due to the operation during periods T12 and T13.

[0200] During period T12, the potential of node FD2a is reset to potential VCOM1. Therefore, period T12 can be described as a reset period. Also, during period T13, charge distribution occurs between the capacitance of node FD1 and the capacitance of node FD2a. Therefore, period T13 can be described as a charge distribution period.

[0201] In the case shown in Figure 15, after the end of period T12[5], the process transitions to period T14. As shown in Figures 15 and 18A, during period T14, the potential of wiring 93 is raised to a high potential, causing transistors 82a and 82b to become conductive. In addition, the potential of wiring 94 is lowered to cause transistors 83a and 83b to become non-conductive. Furthermore, the potential of wiring 96 is lowered to cause transistors 85 and 86 to become non-conductive.

[0202] During period T12[5], the potential of node FD2a is potential VCOM1. Then, during period T14, by making transistor 82a conductive and transistor 83a non-conductive, the potential of node FD2a, which is electrically connected to one electrode of capacitive element 84a, becomes potential Vs[4]. In other words, from period T12[5] to period T14, the potential of node FD2a rises by potential "Vs[4]-VCOM1". Also, by making transistor 85 non-conductive, the wiring 56, which is electrically connected to the other electrode of capacitive element 84a, becomes electrically floating. Therefore, assuming the capacitive coupling coefficient of wiring 56 is 1, the potential of wiring 56 also rises by potential "Vs[4]-VCOM1" from period T12[5] to period T14.

[0203] Furthermore, the potential of wiring 56 during period T12[5] is potential VCOM2. Therefore, the potential of wiring 56 during period T14 is potential "Vs[4]-VCOM1+VCOM2". Thus, the potential of the first input terminal of the comparator circuit 53 is the potential corresponding to potential Vs[4].

[0204] Furthermore, by making transistor 82b conductive and transistor 83b non-conductive, the reference signal REF is supplied to node FD2b, which is electrically connected to one electrode of the capacitive element 84b. In addition, by making transistor 86 non-conductive, the wiring 57, which is electrically connected to the other electrode of the capacitive element 84b, becomes electrically floating. As a result, the potential of wiring 57 becomes the potential corresponding to the reference signal REF.

[0205] By making transistor 86 non-conductive, no feedback is applied to the comparator circuit 53. Therefore, during period T14, the potential of the comparison signal CMP output by the comparator circuit 53 will be high if the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, and low if the potential of the non-inverting input terminal is lower than the potential of the inverting input terminal. In Figure 15, the potential of the reference signal REF during period T14, i.e., the potential of node FD3, is higher than the potential of node FD2a. Therefore, the potential of wiring 57 is higher than the potential of wiring 56. Consequently, the potential of the comparison signal CMP will be low.

[0206] During period T14, the same operation as during period T shown in Figure 13 is performed. That is, for example, the potential of the reference signal REF is continuously decreased, and the counter circuit 54 counts the number of rising or falling edges of the clock signal CLK2.

[0207] Period T14 ends and transitions to period T15 when the potential of the comparison signal CMP reaches a high potential.

[0208] During period T15, the same operation as after the end of period T shown in Figure 13 is performed. That is, during period T15, the data signal DS_OUT, which has a digital value corresponding to the number of times the clock signal CLK2 rose or fell from the start to the end of period T14, is continuously output.

[0209] By the above method, the A / D conversion circuit 42 can output a data signal DS_OUT corresponding to, for example, the potential Vs[4]. As mentioned above, the potential Vs can be expressed by a recurrence relation. Also, as shown in equation 2, the potential Vs[1] is given by potential VPRE, potential VCOM1, and capacitance value C. FD1 , and capacity value C FD2a The following can be calculated: The potential Vs[4], potential VPRE, potential VCOM1, and capacitance value C. FD2a Using this, the capacitance value C of node FD1 when transistor 51a is in the conducting state is determined. FD1 It is possible to calculate this.

[0210] Furthermore, if the operation during period T12 is performed k+1 times (where k is an integer greater than or equal to 1), and the operation during period T13 is performed k times, then during period T15, the A / D conversion circuit 42 outputs a data signal DS_OUT corresponding to the potential Vs[k]. The potential Vs[k] is given by the following formula.

[0211]

number

[0212] As shown in equation 4, the equation for the electric potential Vs[k] includes the electric potential Vs[k-1]. Therefore, equation 4 can be said to be a recurrence relation. Solving the recurrence relation shown in equation 4 using equation 2, which shows the electric potential Vs[1], the electric potential Vs[k] is given by the following equation.

[0213]

number

[0214] Therefore, the capacity value C FD1 This is expressed by the following formula.

[0215]

number

[0216] Based on the above, the potential Vs[k], potential VPRE, potential VCOM1, and capacitance value C are determined. FD2a Using this, the capacitance value C of node FD1 when transistor 51a is in the conducting state is determined. FD1 This can be calculated using formula 6.

[0217] By increasing k, that is, by increasing the number of times the operation in period T12 and the operation in period T13 are performed, the potential of node FD1 can be greatly varied from the precharge potential, potential VPRE. This allows the capacitance value C to be increased. FD1 It can be calculated with high accuracy.

[0218] The parasitic capacitance PC included in the capacitance of node FD1 includes capacitance formed outside IC20. Therefore, measuring the capacitance value of node FD1 when transistor 51a is conducting using measuring equipment is more costly than measuring the capacitance value of capacitive elements 84a etc. included in IC20 using measuring equipment. On the other hand, when calculating the capacitance of node FD1 using the method shown in Figures 15 to 18, for example, the capacitance of node FD1 can be calculated without using measuring equipment. Therefore, the display device 10 can be made inexpensive.

[0219] Furthermore, when calculating the capacitance value of node FD1 when transistor 51a is conducting, as shown in Figures 15 to 18, it is preferable to maintain the charge of node FD1 for a long period of time, as this allows for the calculation of the capacitance value of node FD1 with high accuracy. Therefore, it is preferable to use transistors with low off-current for transistors 51b, 81, 82a, 83a, and 63, etc. For example, it is preferable to use OS transistors.

[0220] Furthermore, OS transistors may be applied to other transistors in the A / D conversion circuit 42. Also, OS transistors may be applied to all transistors in IC20. If all transistors in IC20 are OS transistors, all transistors in IC20 can be formed in the same process. Also, OS transistors may be applied to all transistors in IC20 and all transistors in pixel 12. If all transistors in IC20 and all transistors in pixel 12 are OS transistors, all transistors in IC20 and all transistors in pixel 12 can be formed in the same process. Furthermore, if all transistors in the display device 10 are OS transistors, all transistors in the display device 10 can be formed in the same process. As a result, the number of manufacturing steps for the display device 10 can be reduced, and the display device 10 can be made inexpensive.

[0221] Furthermore, some or all of the transistors in the display device 10 may be Si transistors, etc. For example, Si transistors may be applied to the transistors in IC 20. In particular, if transistors having crystalline silicon (typically low-temperature polysilicon, single-crystal silicon, etc.) are used as Si transistors, the on-current of the transistors can be increased. Therefore, the display device 10 can be driven at high speed.

[0222] [Example of a method for calculating the monitoring current] Below, we will describe an example of a method for calculating the monitor current using the capacitance value of node FD1 when transistor 51a is in a conducting state, calculated by the methods shown in Figures 15 to 18. Figure 19 is a timing chart showing an example of a method for performing A / D conversion on the analog monitor signal MS_A.

[0223] When performing A / D conversion on the analog monitor signal MS_A using the method shown in Figure 19, the period during which the A / D conversion circuit 42 is driven can be divided into periods T21 to T25. In periods T21 to T25, the potential of wiring 55a is set to a high potential to make transistor 51a conduct. On the other hand, the potential of wiring 55b is set to a low potential to make transistor 51b non-conducting. Also in periods T21 to T25, similar to periods T11 to T15, the potentials of wiring 92, wiring 95, and wiring 97, which function as power lines, are set to potentials VPRE, VCOM1, and VCOM2, respectively. Here, potential VPRE is set to be smaller than, for example, potential VCOM1.

[0224] Figure 20A is a circuit diagram showing an example of the driving method for the A / D conversion circuit 42, etc., during period T23. Figure 20B is a circuit diagram showing an example of the driving method for the A / D conversion circuit 42, etc., during period T24.

[0225] As shown in Figure 19, during period T21, the potential of wiring 36 is set to a low potential, causing transistor 63 to become non-conductive. Also, the potential of wiring 91 is set to a high potential, causing transistor 81 to become conductive. Furthermore, the potential of wiring 93 is set to a low potential, causing transistors 82a and 82b to become non-conductive. In addition, the potential of wiring 94 is set to a high potential, causing transistors 83a and 83b to become conductive. As a result, the potential of node FD1 becomes potential VPRE, and the potentials of nodes FD2a and FD2b become potential VCOM1. Since the potential of node FD1 is precharged to potential VPRE, period T21 can be said to be a precharge period.

[0226] Furthermore, during period T21, the potential of wiring 96 is raised to a high potential, causing transistors 85 and 86 to conduct. As a result, the potential of the comparison signal CMP becomes the potential VCOM2 plus the offset potential Voffset, enabling offset correction of the comparison circuit 53.

[0227] From the above, it can be said that period T21 is a period in which the same operation as in period T11 is performed.

[0228] As shown in FIG. 19, in period T22, by setting the potential of wiring 91 to a low potential, transistor 81 is turned off. This completes the precharging of node FD1. It can be said that period T22 is a period in which the same operation as in period T12 is performed.

[0229] As shown in FIG. 19 and FIG. 20A, in period T23, by setting the potential of wiring 36 to a high potential, transistor 63 is turned on. Accordingly, the potential of node FD1 increases in correspondence with analog monitor signal MS_A.

[0230] As shown in FIG. 19 and FIG. 20B, in period T24, first, by setting the potential of wiring 36 to a low potential, transistor 63 is turned off. Next, by setting the potential of wiring 93 to a high potential, transistor 82a and transistor 82b are turned on. Further, by setting the potential of wiring 94 to a low potential, transistor 83a and transistor 83b are turned off. Furthermore, by setting the potential of wiring 96 to a low potential, transistor 85 and transistor 86 are turned off.

[0231] By turning transistor 63 off, the potential of node FD1 is held. Let this held potential be potential VMS. With the potential of node FD1 held, by turning transistor 82a on and turning transistor 83a and transistor 85 off, the potential of wiring 56 becomes potential "VMS-VCOM1+VCOM2". Therefore, the potential of the first input terminal of comparison circuit 53 becomes a potential corresponding to potential VMS.

[0232] Furthermore, by making transistor 82b conduct and transistor 83b non-conductive, a reference signal REF is supplied to node FD2b, and the potential of wiring 57 becomes the potential corresponding to the reference signal REF.

[0233] Furthermore, by making transistor 86 non-conductive, the potential of the comparison signal CMP output by the comparator circuit 53 becomes high when the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, and low when the potential of the non-inverting input terminal is lower than the potential of the inverting input terminal. In Figure 19, the potential of the reference signal REF during period T24, i.e., the potential of node FD3, is higher than the potential of node FD2a. Therefore, the potential of wiring 57 becomes higher than the potential of wiring 56. Consequently, the potential of the comparison signal CMP becomes low.

[0234] During period T24, the same operation as during period T shown in Figure 13 is performed. That is, for example, the potential of the reference signal REF is continuously decreased, and the counter circuit 54 counts the number of rising or falling edges of the clock signal CLK2. When the potential of the comparison signal CMP reaches a high potential, period T24 ends and the circuit transitions to period T25.

[0235] Based on the above, it can be concluded that period T24 is a period in which the same operations as period T14 are performed.

[0236] During period T25, the same operation as after the end of period T shown in Figure 13 is performed. That is, during period T25, the data signal DS_OUT, which has a digital value corresponding to the number of times the clock signal CLK2 rose or fell from the start to the end of period T24, is continuously output. From the above, it can be said that period T25 is a period in which the same operation as period T15 is performed.

[0237] As described above, the operation during periods T21 to T25 allows the analog monitor signal MS_A to be converted into a digital signal. Specifically, the A / D conversion circuit 42 can output a data signal DS_OUT, which is a digital value corresponding to the potential VMS of the analog monitor signal MS_A. This allows the potential VMS to be calculated.

[0238] After calculating the potential VMS, the monitor current I is calculated using Equation 1. Here, ΔV FD1 The potential can be set to "VMS-VPRE". Furthermore, Δt can be set to the length of period T23.

[0239] By calculating the capacitance value of node FD1 when transistor 51a is conducting using the method shown in Figures 15 to 18, and then calculating the monitor current value using the method shown in Figure 19, and Figures 20A and 20B, the monitor current value can be calculated taking into account the parasitic capacitance PC of the wiring 34. Therefore, the monitor current value can be calculated with high accuracy, and for example, the threshold voltage of transistor 62, which functions as a drive transistor for the pixel circuit 14, can be corrected with high accuracy. Consequently, for example, display unevenness can be reduced, and a high-quality image can be displayed on the display unit 11.

[0240] [An example of an A / D conversion method for analog imaging signals] Next, an example of a method for performing A / D conversion on the analog imaging signal IS_A will be described. Figure 21 is a timing chart showing an example of a method for performing A / D conversion on the analog imaging signal IS_A. When performing A / D conversion on the analog imaging signal IS_A using the method shown in Figure 21, the period during which the A / D conversion circuit 42 is driven can be divided into periods T21 to T25, similar to the case shown in Figure 19. Here, when performing A / D conversion on the analog imaging signal IS_A, the potential of wiring 55a is set to a low potential during periods T21 to T25, thereby making the transistor 51a non-conductive. On the other hand, the potential of wiring 55b is set to a high potential, thereby making the transistor 51b conductive.

[0241] Figure 22A is a circuit diagram showing an example of how the A / D conversion circuit 42 and the like are driven during period T23 when A / D conversion is performed on the analog imaging signal IS_A. Figure 22B is a circuit diagram showing an example of how the A / D conversion circuit 42 and the like are driven during period T24 when A / D conversion is performed on the analog imaging signal IS_A.

[0242] The following describes the operation of periods T21 to T25 shown in Figure 21. Note that the explanation may be omitted for operations similar to those shown in Figure 19.

[0243] As shown in Figure 21, during period T21, the potential of the wiring 32 is set to a low potential, thereby making the transistor 74, which is provided in the pixel circuit 15 and electrically connected to the wiring 35, non-conductive. During period T21, pre-charging of node FD1 and offset correction of the comparator circuit 53 are performed. Then, during period T22, the pre-charging of node FD1 is terminated.

[0244] As shown in Figures 21 and 22A, during period T23, the potential of wiring 32 is raised to a high potential, causing transistor 74 to conduct. This causes the potential of wiring 35 to become the potential VIS corresponding to the analog imaging signal IS_A. Note that when performing A / D conversion on the analog imaging signal IS_A, it is not necessary to measure the change in the potential of wiring 35 over time. Therefore, it is preferable to continue the operation during period T23 until the potential of wiring 35 reaches a steady state. This allows for highly accurate A / D conversion on the analog imaging signal IS_A.

[0245] As shown in Figures 21 and 22B, during period T24, first, the potential of wiring 32 is set to a low potential, thereby making transistor 74 non-conductive. Next, transistors 82a and 82b are made conductive, and transistors 83a, 83b, 85, and 86 are made non-conductive. By making transistor 82a conductive and transistors 83a and 85 non-conductive, the potential of wiring 56 becomes the potential "VIS-VCOM1+VCOM2". Therefore, the potential of the first input terminal of comparator circuit 53 becomes the potential corresponding to potential VIS. Also, by making transistor 82b conductive and transistor 83b non-conductive, the reference signal REF is supplied to node FD2b, and the potential of wiring 57 becomes the potential corresponding to the reference signal REF.

[0246] Furthermore, by making transistor 86 non-conductive, the potential of the comparison signal CMP output by the comparator circuit 53 becomes high when the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, and low when the potential of the non-inverting input terminal is lower than the potential of the inverting input terminal. In Figure 21, the potential of the reference signal REF during period T24, i.e., the potential of node FD3, is higher than the potential of node FD2a. Therefore, the potential of wiring 57 becomes higher than the potential of wiring 56. Consequently, the potential of the comparison signal CMP becomes low.

[0247] During period T24, the same operation as during period T shown in Figure 13 is performed. Furthermore, during period T25, the same operation as after the end of period T shown in Figure 13 is performed. As a result, the analog imaging signal IS_A can be converted to a digital signal. Specifically, the A / D conversion circuit 42 can output a data signal DS_OUT with a digital value corresponding to the potential of the analog imaging signal IS_A.

[0248] The above is an example of a driving method for the A / D conversion circuit 42, etc., with the configuration shown in Figure 14A or Figure 14B.

[0249] Note that one embodiment of the present invention can be applied even when the pixel 12 does not include the pixel circuit 15. For example, the configuration in which the display portion 11 is provided so as to have a region overlapping with the IC 20 as illustrated in FIG. 2A or FIG. 2B can be applied even when the pixel 12 does not include the pixel circuit 15. Further, the configurations illustrated in FIGS. 12A and 12B and FIGS. 14A and 14B can be applied even when the pixel 12 does not include the pixel circuit 15. Note that in the case where the configurations illustrated in FIGS. 12A and 12B and FIGS. 14A and 14B are applied to a display device that does not include the pixel circuit 15, a configuration without the transistor 51a and the transistor 51b can be employed.

[0250] At least part of the configuration examples illustrated in this embodiment and the drawings corresponding thereto can be combined with other configuration examples or drawings as appropriate.

[0251] At least part of this embodiment can be combined with other embodiments described in this specification as appropriate.

[0252] (Embodiment 2) In this embodiment, an example of a cross-sectional structure of a display device according to one embodiment of the present invention is described.

[0253] FIG. 23A is a cross-sectional view of a display device 10A.

[0254] The display device 10A includes a light-receiving element 70 and a light-emitting element 60.

[0255] The light-receiving element 70 includes a pixel electrode 411, a common layer 412, an active layer 413, a common layer 414, and a common electrode 415.

[0256] The light-emitting element 60 includes a pixel electrode 191, a common layer 412, a light-emitting layer 193, a common layer 414, and a common electrode 415.

[0257] The pixel electrode 411, pixel electrode 191, common layer 412, active layer 413, light-emitting layer 193, common layer 414, and common electrode 415 may each be a single-layer structure or a stacked structure.

[0258] The pixel electrodes 411 and 191 are located on the insulating layer 214. The pixel electrodes 411 and 191 can be formed from the same material and using the same process.

[0259] The common layer 412 is located on the pixel electrode 411 and the pixel electrode 191. The common layer 412 is a layer used in common by the light-receiving element 70 and the light-emitting element 60.

[0260] The active layer 413 overlaps with the pixel electrode 411 via the common layer 412. The light-emitting layer 193 overlaps with the pixel electrode 191 via the common layer 412. The active layer 413 has a first organic compound, and the light-emitting layer 193 has a second organic compound different from the first organic compound.

[0261] The common layer 414 is located on the common layer 412, the active layer 413, and the light-emitting layer 193. The common layer 414 is a layer used in common by the light-receiving element 70 and the light-emitting element 60.

[0262] The common electrode 415 has a portion that overlaps with the pixel electrode 411 via the common layer 412, the active layer 413, and the common layer 414. Furthermore, the common electrode 415 has a portion that overlaps with the pixel electrode 191 via the common layer 412, the light-emitting layer 193, and the common layer 414. The common electrode 415 is a layer used in common by the light-receiving element 70 and the light-emitting element 60.

[0263] In the display device of this embodiment, an organic compound is used for the active layer 413 of the light-receiving element 70. The layers of the light-receiving element 70 other than the active layer 413 can have the same configuration as the light-emitting element 60 (EL element). Therefore, by simply adding a step of forming the active layer 413 to the manufacturing process of the light-emitting element 60, the light-receiving element 70 can be formed in parallel with the formation of the light-emitting element 60. Furthermore, the light-emitting element 60 and the light-receiving element 70 can be formed on the same substrate. Thus, the light-receiving element 70 can be incorporated into the display device without significantly increasing the manufacturing process.

[0264] In the display device 10A, an example is shown where the light-receiving element 70 and the light-emitting element 60 have a common configuration, except that the active layer 413 of the light-receiving element 70 and the light-emitting element 60 are manufactured separately. However, the configuration of the light-receiving element 70 and the light-emitting element 60 is not limited to this. In addition to the active layer 413 and the light-emitting layer 193, the light-receiving element 70 and the light-emitting element 60 may also have layers that are manufactured separately from each other (see display devices 10K, 10L, and 10M described later). It is preferable that the light-receiving element 70 and the light-emitting element 60 have one or more layers that are used in common (common layers). This makes it possible to incorporate the light-receiving element 70 into the display device without significantly increasing the manufacturing process.

[0265] The display device 10A has a light-receiving element 70, a light-emitting element 60, a transistor 341, and a transistor 342, etc., between a pair of substrates (substrate 451 and substrate 452).

[0266] In the light-receiving element 70, the common layer 412, the active layer 413, and the common layer 414, located between the pixel electrode 411 and the common electrode 415, can also be called organic layers (layers containing organic compounds). The pixel electrode 411 preferably has the function of reflecting visible light. The ends of the pixel electrode 411 are covered by partition walls 216. The common electrode 415 has the function of transmitting visible light.

[0267] The light-receiving element 70 has the function of detecting light. Specifically, the light-receiving element 70 is a photoelectric conversion element that receives light 17 incident from outside the display device 10A and converts it into an electrical signal. Light 17 can also be defined as light reflected by an object from the light-emitting element 60. In addition, light 17 may be incident on the light-receiving element 70 via a lens, which will be described later.

[0268] A light-shielding layer BM is provided on the surface of substrate 452 that faces substrate 451. The light-shielding layer BM has openings at positions that overlap with the light-receiving element 70 and at positions that overlap with the light-emitting element 60. By providing the light-shielding layer BM, the range in which the light-receiving element 70 detects light can be controlled.

[0269] As the light-shielding layer BM, a material that blocks light emission from the light-emitting element can be used. Preferably, the light-shielding layer BM absorbs visible light. As the light-shielding layer BM, for example, a black matrix can be formed using a metal material, or a resin material containing a pigment (such as carbon black) or dye. The light-shielding layer BM may also have a laminated structure of a red color filter, a green color filter, and a blue color filter.

[0270] Here, the light-emitting element 60 emits light, which is then reflected by the object to be detected and detected by the light-receiving element 70, allowing the display device 10A to detect the object. However, the light emitted from the light-emitting element 60 may be reflected within the display device 10A and enter the light-receiving element 70 without passing through the object to be detected. The light-shielding layer BM can suppress the effects of such stray light. For example, if the light-shielding layer BM is not provided, the light 423a emitted from the light-emitting element 60 may be reflected by the substrate 452, and the reflected light 423b may enter the light-receiving element 70. By providing the light-shielding layer BM, the entry of reflected light 423b into the light-receiving element 70 can be suppressed. This reduces noise and increases the sensitivity of the sensor using the light-receiving element 70.

[0271] In the light-emitting element 60, the common layer 412, light-emitting layer 193, and common layer 414, located between the pixel electrode 191 and the common electrode 415, can also be called EL layers. The pixel electrode 191 preferably has the function of reflecting visible light. The ends of the pixel electrode 191 are covered by partition walls 216. The pixel electrode 411 and the pixel electrode 191 are electrically insulated from each other by partition walls 216. The common electrode 415 has the function of transmitting visible light.

[0272] The light-emitting element 60 has the function of emitting visible light. Specifically, the light-emitting element 60 is an electroluminescent element that emits light towards the substrate 452 when a voltage is applied between the pixel electrode 191 and the common electrode 415 (see light 16).

[0273] It is preferable that the light-emitting layer 193 is formed so as not to overlap with the light-receiving area of ​​the photodetector 70. This suppresses the absorption of light 17 by the light-emitting layer 193, and increases the amount of light irradiated onto the photodetector 70.

[0274] The pixel electrode 411 is electrically connected to the source or drain of the transistor 341 through an opening provided in the insulating layer 214. The end of the pixel electrode 411 is covered by a partition wall 216.

[0275] The pixel electrode 191 is electrically connected to the source or drain of the transistor 342 through an opening provided in the insulating layer 214. The end of the pixel electrode 191 is covered by a partition wall 216. The transistor 342 has the function of controlling the driving of the light-emitting element 60.

[0276] Transistors 341 and 342 are in contact with each other on the same layer (substrate 451 in Figure 23A).

[0277] Preferably, at least a portion of the circuit electrically connected to the light-receiving element 70 is formed using the same material and process as the circuit electrically connected to the light-emitting element 60. This makes it possible to reduce the thickness of the display device and simplify the manufacturing process compared to forming the two circuits separately.

[0278] It is preferable that the light-receiving element 70 and the light-emitting element 60 are each covered with a protective layer 195. In Figure 23A, the protective layer 195 is provided in contact with the common electrode 415. By providing the protective layer 195, it is possible to suppress the ingress of impurities such as water into the light-receiving element 70 and the light-emitting element 60, thereby improving the reliability of the light-receiving element 70 and the light-emitting element 60. Furthermore, the protective layer 195 and the substrate 452 are bonded together by an adhesive layer 442.

[0279] As shown in Figure 24A, protective layers are not required on the light-receiving element 70 and the light-emitting element 60. In Figure 24A, the common electrode 415 and the substrate 452 are bonded together by an adhesive layer 442.

[0280] [Display device 10B] Figure 23B shows a cross-sectional view of the display device 10B. Note that in the following description of the display device, the same configuration as described earlier may be omitted.

[0281] The display device 10B shown in Figure 23B has a lens 449 in addition to the configuration of the display device 10A.

[0282] The display device of this embodiment may have a lens 449. The lens 449 is provided in a position that overlaps with the light-receiving element 70. In the display device 10B, the lens 449 is provided in contact with the substrate 452. The lens 449 of the display device 10B has a convex surface on the substrate 451 side. Alternatively, the lens 449 may have a convex surface on the substrate 452 side.

[0283] When forming both the light-shielding layer BM and the lens 449 on the same surface of the substrate 452, the order of formation does not matter. Figure 23B shows an example where the lens 449 is formed first, but the light-shielding layer BM may be formed first. In Figure 23B, the end of the lens 449 is covered by the light-shielding layer BM.

[0284] The display device 10B is configured such that light 17 is incident on the photodetector 70 through the lens 449. Having the lens 449 allows for a narrower imaging range of the photodetector 70 compared to the case without the lens 449, thereby suppressing overlap in imaging ranges between adjacent photodetectors 70. This enables the capture of clearer images with less blurring. Furthermore, for the same imaging range of the photodetector 70, having the lens 449 allows for a larger pinhole size (corresponding to the size of the aperture BM overlapping the photodetector 70 in Figure 23B) compared to the case without the lens 449. Therefore, having the lens 449 increases the amount of light incident on the photodetector 70.

[0285] The display devices shown in Figures 24B and 24C are configured in the same way as the display device 10B shown in Figure 23B, with light 17 incident on the light-receiving element 70 via the lens 449.

[0286] In Figure 24B, the lens 449 is provided in contact with the upper surface of the protective layer 195. The lens 449 of the display device shown in Figure 24B has a convex surface on the substrate 452 side.

[0287] The display device shown in Figure 24C has a lens array 446 provided on the display surface side of the substrate 452. The lenses of the lens array 446 are positioned to overlap with the light-receiving element 70. Preferably, a light-shielding layer BM is provided on the surface of the substrate 452 that faces the substrate 451.

[0288] As for the method of forming the lenses used in the display device of this embodiment, lenses such as microlenses may be directly formed on the substrate or on the light-receiving element, or a lens array such as a separately manufactured microlens array may be bonded to the substrate.

[0289] Figure 23C shows a cross-sectional view of the display device 10C.

[0290] The display device 10C shown in Figure 23C differs from the display device 10A in that it does not have substrates 451, 452, and partition wall 216, but has substrates 453, 454, adhesive layer 455, insulating layer 212, and partition wall 217.

[0291] The substrate 453 and the insulating layer 212 are bonded together by an adhesive layer 455. The substrate 454 and the protective layer 195 are bonded together by an adhesive layer 442.

[0292] The display device 10C is manufactured by transferring an insulating layer 212, transistors 341 and 342, a light-receiving element 70, and a light-emitting element 60, etc., formed on a fabricated substrate, onto a substrate 453. It is preferable that both substrates 453 and 454 are flexible. This enhances the flexibility of the display device 10C. For example, it is preferable to use resin for both substrates 453 and 454.

[0293] Substrates 453 and 454 can be made from polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamide-imide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. One or both of substrates 453 and 454 may be made of glass of a thickness sufficient to provide flexibility.

[0294] The substrate of the display device in this embodiment may be a film with high optical isotropy. Examples of films with high optical isotropy include triacetylcellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic resin.

[0295] The partition wall 217 preferably absorbs the light emitted by the light-emitting element. For example, a black matrix can be formed as the partition wall 217 using a resin material containing a pigment or dye. Alternatively, the partition wall 217 can be constructed with a colored insulating layer by using a brown resist material.

[0296] The light 423c emitted by the light-emitting element 60 is reflected by the substrate 452 and the partition wall 217, and the reflected light 423d may enter the photodetector 70. Alternatively, the light 423c may pass through the partition wall 217 and be reflected by the transistor or wiring, and the reflected light may enter the photodetector 70. By absorbing the light 423c with the partition wall 217, the incidence of reflected light 423d into the photodetector 70 can be suppressed. This reduces noise and increases the sensitivity of the sensor using the photodetector 70.

[0297] The partition wall 217 preferably absorbs at least the wavelength of light detected by the photodetector 70. For example, when the photodetector 70 detects green light emitted by the light-emitting element 60, the partition wall 217 preferably absorbs at least the green light. For example, if the partition wall 217 has a red color filter, it can absorb the green light 423c and suppress the incident of reflected light 423d on the photodetector 70.

[0298] Figure 25A shows a cross-sectional view of the display device 10D.

[0299] The display device 10D shown in Figure 25A differs from the display device 10A in that it has a color filter 460. The color filter 460 is provided so as to have an area that overlaps with the light-emitting element 60. The color filter 460 has the function of transmitting light of a specific color (wavelength) and absorbing light of other colors (wavelengths). For example, as shown in Embodiment 1, a color filter 460 that transmits red light can be provided so as to have an area that overlaps with the pixel circuit 14R that emits red light 16R. Also, a color filter 460 that transmits green light can be provided so as to have an area that overlaps with the pixel circuit 14G that emits green light 16G. Furthermore, a color filter 460 that transmits blue light can be provided so as to have an area that overlaps with the pixel circuit 14B that emits blue light 16B.

[0300] In the display device 10D, a light-emitting layer 193 can be, for example, a light-emitting layer that emits white light. Therefore, since it is not necessary to paint the light-emitting layer 193 differently depending on the color of the light emitted by the pixel circuit 14, the pixels 12 can be made higher resolution. In addition, the manufacturing cost of the display device can be reduced, making the display device 10D a low-cost product.

[0301] Figure 25B shows a cross-sectional view of the display device 10E.

[0302] The display device 10E shown in Figure 25B differs from the display device 10A in that it has a lens 461. The lens 461 can be provided in contact with the upper surface of the protective layer 195 such that it has an area that overlaps with the light-emitting element 60. The lens 461 has a convex surface on the substrate 452 side.

[0303] Figure 25C shows a cross-sectional view of the display device 10F.

[0304] The display device 10F shown in Figure 25C differs from the display device 10A in that it has a lens array 462. The lens array 462 can be provided on the display surface side of the substrate 452. The lenses of the lens array 462 are provided so as to have an area that overlaps with the light-emitting element 60.

[0305] By providing a lens such that it overlaps with the light-emitting element 60, as in the display device 10E or display device 10F, the efficiency of extracting the light 16 emitted by the light-emitting layer 193 can be increased. Therefore, a high-brightness image can be displayed on the display unit 11 where the light-emitting element 60 is provided.

[0306] Figure 26A shows a cross-sectional view of the display device 10K, Figure 26B shows a cross-sectional view of the display device 10L, and Figure 26C shows a cross-sectional view of the display device 10M.

[0307] Display device 10K differs from display device 10A in that it does not have a common layer 414, but has buffer layers 184 and 194. Buffer layers 184 and 194 may each be single-layer or multi-layer.

[0308] In the display device 10K, the light-receiving element 70 has a pixel electrode 411, a common layer 412, an active layer 413, a buffer layer 184, and a common electrode 415. Also in the display device 10K, the light-emitting element 60 has a pixel electrode 191, a common layer 412, a light-emitting layer 193, a buffer layer 194, and a common electrode 415.

[0309] Display device 10L differs from display device 10A in that it does not have a common layer 412, but has buffer layers 182 and 192. Each of the buffer layers 182 and 192 may be a single layer or a stacked structure.

[0310] In the display device 10L, the light-receiving element 70 has a pixel electrode 411, a buffer layer 182, an active layer 413, a common layer 414, and a common electrode 415. In addition, in the display device 10L, the light-emitting element 60 has a pixel electrode 191, a buffer layer 192, a light-emitting layer 193, a common layer 414, and a common electrode 415.

[0311] Display device 10M differs from display device 10A in that it does not have a common layer 412 and a common layer 414, but has buffer layers 182, 184, 192, and 194.

[0312] In the display device 10M, the light-receiving element 70 has a pixel electrode 411, a buffer layer 182, an active layer 413, a buffer layer 184, and a common electrode 415. Also in the display device 10M, the light-emitting element 60 has a pixel electrode 191, a buffer layer 192, a light-emitting layer 193, a buffer layer 194, and a common electrode 415.

[0313] In fabricating the light-receiving element 70 and the light-emitting element 60, it is possible not only to fabricate the active layer 413 and the light-emitting layer 193 separately, but also to fabricate other layers separately.

[0314] In the display device 10K, an example is shown in which a buffer layer 184 between the common electrode 415 and the active layer 413 and a buffer layer 194 between the common electrode 415 and the light-emitting layer 193 are fabricated separately. As the buffer layer 194, for example, one or both of an electron injection layer and an electron transport layer can be formed.

[0315] In the display device 10L, an example is shown in which a buffer layer 182 between the pixel electrode 411 and the active layer 413 and a buffer layer 192 between the pixel electrode 191 and the light-emitting layer 193 are fabricated separately. As the buffer layer 192, for example, one or both of a hole injection layer and a hole transport layer can be formed.

[0316] In the display device 10M, an example is shown in which the light-receiving element 70 and the light-emitting element 60 do not have a common layer between a pair of electrodes (pixel electrode 411 or pixel electrode 191 and common electrode 415). The light-receiving element 70 and the light-emitting element 60 in the display device 10M can be manufactured by forming the pixel electrode 411 and the pixel electrode 191 on an insulating layer 214 using the same material and the same process, forming a buffer layer 182, an active layer 413, and a buffer layer 184 on the pixel electrode 411, forming a buffer layer 192, a light-emitting layer 193, and a buffer layer 194 on the pixel electrode 191, and then forming a common electrode 415 so as to cover the pixel electrode 411, buffer layer 182, active layer 413, buffer layer 184, pixel electrode 191, buffer layer 192, light-emitting layer 193, and buffer layer 194. The order in which the layered structures of buffer layer 182, active layer 413, and buffer layer 184 are fabricated, and the layered structures of buffer layer 192, light-emitting layer 193, and buffer layer 194 are fabricated is not particularly limited. For example, buffer layer 192, light-emitting layer 193, and buffer layer 194 may be fabricated after buffer layer 182, active layer 413, and buffer layer 184 have been deposited. Conversely, buffer layer 192, light-emitting layer 193, and buffer layer 194 may be fabricated before buffer layer 182, active layer 413, and buffer layer 184 have been deposited. Alternatively, buffer layer 182, buffer layer 192, active layer 413, light-emitting layer 193, etc., may be fabricated alternately in that order.

[0317] The display device 400A shown in Figure 27 has transistors 201, 205, 206, light-emitting element 60, light-receiving element 70, etc., between substrates 451 and 452.

[0318] The substrate 452 and the insulating layer 214 are bonded together via an adhesive layer 442. For sealing the light-emitting element 60 and the light-receiving element 70, a solid sealing structure or a hollow sealing structure can be applied. In Figure 27, the space 443 surrounded by the substrate 452, the adhesive layer 442, and the insulating layer 214 is filled with an inert gas (such as nitrogen or argon), indicating a hollow sealing structure. The adhesive layer 442 may be provided overlapping the light-emitting element 60. Alternatively, the space 443 surrounded by the substrate 452, the adhesive layer 442, and the insulating layer 214 may be filled with a resin different from that of the adhesive layer 442.

[0319] The light-emitting element 60 has a stacked structure in which the pixel electrode 191, common layer 412, light-emitting layer 193, common layer 414, and common electrode 415 are stacked in that order from the insulating layer 214 side. The pixel electrode 191 is connected to the conductive layer 222b of the transistor 206 through an opening provided in the insulating layer 214. The transistor 206 has the function of controlling the driving of the light-emitting element 60. The end of the pixel electrode 191 is covered by a partition wall 216. The pixel electrode 191 contains a material that reflects visible light, and the common electrode 415 contains a material that transmits visible light.

[0320] The light-receiving element 70 has a stacked structure in which the pixel electrode 411, common layer 412, active layer 413, common layer 414, and common electrode 415 are stacked in that order from the insulating layer 214 side. The pixel electrode 411 is electrically connected to the conductive layer 222b of the transistor 205 through an opening provided in the insulating layer 214. The end of the pixel electrode 411 is covered by a partition wall 216. The pixel electrode 411 contains a material that reflects visible light, and the common electrode 415 contains a material that transmits visible light.

[0321] The light emitted by the light-emitting element 60 is emitted towards the substrate 452. Light is also incident on the light-receiving element 70 through the substrate 452 and the space 443. It is preferable to use a material with high transmittance to visible light for the substrate 452.

[0322] Pixel electrodes 411 and 191 can be manufactured using the same material and process. Common layers 412 and 414, and common electrode 415 are used in both the light-receiving element 70 and the light-emitting element 60. The light-receiving element 70 and the light-emitting element 60 can have the same configuration except for the difference in the configuration of the active layer 413 and the light-emitting layer 193. This allows the light-receiving element 70 to be incorporated into the display device 400A without significantly increasing the manufacturing process.

[0323] A light-shielding layer BM is provided on the surface of substrate 452 facing substrate 451. The light-shielding layer BM has openings at positions overlapping with the light-receiving element 70 and at positions overlapping with the light-emitting element 60. By providing the light-shielding layer BM, the range in which the light-receiving element 70 detects light can be controlled. Furthermore, the presence of the light-shielding layer BM suppresses direct incidence of light from the light-emitting element 60 to the light-receiving element 70 without the need for an intermediary object. Therefore, a sensor with low noise and high sensitivity can be realized.

[0324] Transistors 201, 205, and 206 are all formed on the substrate 451. These transistors can be manufactured using the same materials and the same process.

[0325] On the substrate 451, insulating layers 211, 213, 215, and 214 are provided in this order. A portion of insulating layer 211 functions as a gate insulating layer for each transistor. A portion of insulating layer 213 functions as a gate insulating layer for each transistor. Insulating layer 215 is provided covering the transistors. Insulating layer 214 is provided covering the transistors and functions as a planarization layer. The number of gate insulating layers and insulating layers covering the transistors are not limited and may be a single layer or two or more layers, respectively.

[0326] It is preferable to use a material that does not easily allow impurities such as water and hydrogen to diffuse into at least one layer of the insulating layer covering the transistor. This allows the insulating layer to function as a barrier layer. With such a configuration, the diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the display device.

[0327] It is preferable to use inorganic insulating films for insulating layer 211, insulating layer 213, and insulating layer 215. Examples of inorganic insulating films that can be used include silicon nitride film, silicon oxide nitride film, silicon oxide film, silicon nitride oxide film, aluminum oxide film, and aluminum nitride film. Alternatively, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film may also be used. Furthermore, two or more of the above insulating films may be laminated together.

[0328] Here, organic insulating films often have lower barrier properties than inorganic insulating films. Therefore, it is preferable that the organic insulating film has an opening near the edge of the display device 400A. This prevents impurities from entering through the organic insulating film from the edge of the display device 400A. Alternatively, the organic insulating film may be formed so that its edge is inward from the edge of the display device 400A, so that the organic insulating film is not exposed at the edge of the display device 400A.

[0329] An organic insulating film is preferred for the insulating layer 214, which functions as a planarizing layer. Examples of materials that can be used as the organic insulating film include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimidoamide resins, siloxane resins, benzocyclobutene resins, phenolic resins, and precursors of these resins.

[0330] In the region 228 shown in Figure 27, an opening is formed in the insulating layer 214. This prevents impurities from entering the display unit 11 from the outside through the insulating layer 214, even when an organic insulating film is used for the insulating layer 214. Therefore, the reliability of the display device 400A can be improved.

[0331] Transistors 201, 205, and 206 each have a conductive layer 221 that functions as a gate, an insulating layer 211 that functions as a gate insulating layer, conductive layers 222a and 222b that function as source and drain, a semiconductor layer 231, an insulating layer 213 that functions as a gate insulating layer, and a conductive layer 223 that functions as a gate. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film. The insulating layer 211 is located between the conductive layer 221 and the semiconductor layer 231. The insulating layer 213 is located between the conductive layer 223 and the semiconductor layer 231.

[0332] The transistor structure of the display device of this embodiment is not particularly limited. For example, planar transistors, staggered transistors, inverse staggered transistors, etc., can be used. Furthermore, either a top-gate or bottom-gate transistor structure may be used. Alternatively, gates may be provided above and below the semiconductor layer in which the channel is formed.

[0333] Transistors 201, 205, and 206 are configured in which a semiconductor layer on which a channel is formed is sandwiched between two gates. The transistors may be driven by connecting the two gates and supplying them with the same signal. Alternatively, the threshold voltage of the transistors may be controlled by applying a potential to control the threshold voltage to one of the two gates and a potential to drive the other gate.

[0334] The crystallinity of the semiconductor material used in the transistor is not particularly limited; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystalline properties other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with crystalline regions in part) may be used. Using a single-crystal semiconductor or a semiconductor with crystalline properties other than single crystals is preferable because it can suppress the degradation of transistor characteristics.

[0335] The semiconductor layer of the transistor preferably contains a metal oxide (also called an oxide semiconductor). Alternatively, the semiconductor layer of the transistor may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon (low-temperature polysilicon, single-crystal silicon, etc.).

[0336] The semiconductor layer preferably comprises, for example, indium, M (where M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, it is preferable that M is one or more selected from aluminum, gallium, yttrium, and tin.

[0337] In particular, it is preferable to use an oxide (also written as IGZO) containing indium (In), gallium (Ga), and zinc (Zn) as the semiconductor layer.

[0338] When the semiconductor layer is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the sputtering target used to deposit the In-M-Zn oxide film is equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such a sputtering target include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, and In:M:Zn=5:2:5.

[0339] As a sputtering target, it is preferable to use a target containing a polycrystalline oxide because it facilitates the formation of a crystalline semiconductor layer. The atomic ratio of the deposited semiconductor layer includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target. For example, if the composition of the sputtering target used for the semiconductor layer is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the deposited semiconductor layer may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0340] Furthermore, when the atomic ratio is stated as In:Ga:Zn=4:2:3 or nearby, it includes cases where, with an atomic ratio of In being 4, the atomic ratio of Ga is between 1 and 3, and the atomic ratio of Zn is between 2 and 4. Also, when the atomic ratio is stated as In:Ga:Zn=5:1:6 or nearby, it includes cases where, with an atomic ratio of In being 5, the atomic ratio of Ga is greater than 0.1 and 2 or less, and the atomic ratio of Zn is between 5 and 7. Furthermore, when the atomic ratio is stated as In:Ga:Zn=1:1:1 or nearby, it includes cases where, with an atomic ratio of In being 1, the atomic ratio of Ga is greater than 0.1 and 2 or less, and the atomic ratio of Zn is greater than 0.1 and 2 or less.

[0341] The transistors in circuit 164 and the transistors in the display unit 11 may have the same structure or different structures. The structures of the multiple transistors in circuit 164 may all be the same or there may be two or more different structures. Similarly, the structures of the multiple transistors in the display unit 11 may all be the same or there may be two or more different structures. Note that circuit 164 can be, for example, the gate driver circuit 13 or the row driver circuit 19 shown in Embodiment 1.

[0342] A connection portion 204 is provided in the region of substrate 451 that does not overlap with substrate 452. At the connection portion 204, the wiring 165 is electrically connected to the FPC 172 via a conductive layer 166 and a connecting layer 242. The upper surface of the connection portion 204 exposes the conductive layer 166, which is obtained by processing the same conductive film as the pixel electrode 191. This allows the connection portion 204 and the FPC 172 to be electrically connected via the connecting layer 242.

[0343] Various optical components can be placed on the outside of the substrate 452. Examples of optical components include polarizing plates, phase difference plates, light diffusion layers (diffusion films, etc.), anti-reflective layers, and light-gathering films. In addition, an antistatic film to suppress the adhesion of dust, a water-repellent film to make it difficult for dirt to adhere, a hard coat film to suppress the occurrence of scratches during use, and an impact-absorbing layer may be placed on the outside of the substrate 452.

[0344] Substrates 451 and 452 can be made of glass, quartz, ceramic, sapphire, resin, etc., respectively. Using flexible materials for substrates 451 and 452 can increase the flexibility of the display device.

[0345] Various types of curing adhesives can be used as the adhesive layer, including UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins may also be used. Adhesive sheets may also be used.

[0346] As the connecting layer 242, an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), etc., can be used.

[0347] The light-emitting element 60 can be of the top-emission type, bottom-emission type, dual-emission type, etc. A conductive film that transmits visible light is used for the electrode on the side that extracts light. It is preferable to use a conductive film that reflects visible light for the electrode on the side that does not extract light.

[0348] The light-emitting element 60 has at least an emissive layer 193. The light-emitting element 60 may further have layers other than the emissive layer 193 that contain a material with high hole injection properties, a material with high hole transport properties, a hole blocking material, a material with high electron transport properties, a material with high electron injection properties, or a bipolar material (a material with high electron transport and hole transport properties). For example, the common layer 412 preferably has one or both of a hole injection layer and a hole transport layer. For example, the common layer 414 preferably has one or both of an electron transport layer and an electron injection layer.

[0349] The common layer 412, the light-emitting layer 193, and the common layer 414 may use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the common layer 412, the light-emitting layer 193, and the common layer 414 can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0350] The light-emitting layer 193 may have an inorganic compound such as quantum dots as a light-emitting material.

[0351] The active layer 413 of the photodetector 70 contains a semiconductor. Examples of such semiconductors include inorganic semiconductors such as silicon, and organic semiconductors containing organic compounds. In this embodiment, an example is shown in which an organic semiconductor is used as the semiconductor of the active layer. Using an organic semiconductor is preferable because it allows the light-emitting layer 193 of the light-emitting element 60 and the active layer 413 of the photodetector 70 to be formed using the same method (for example, vacuum deposition), and the manufacturing equipment can be shared.

[0352] The n-type semiconductor material of the active layer 413 is fullerene (for example, C 60 , C 70Examples of electron-accepting organic semiconductor materials include those listed above or their derivatives. Furthermore, examples of p-type semiconductor materials for the active layer 413 include electron-donating organic semiconductor materials such as copper(II) phthalocyanine (CuPc) and tetraphenyldibenzoperiflanthene (DBP).

[0353] For example, the active layer 413 is preferably formed by co-depositing an n-type semiconductor and a p-type semiconductor.

[0354] Materials that can be used for conductive layers such as the gate, source, and drain of transistors, as well as various wirings and electrodes that constitute display devices, include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or alloys mainly composed of these materials. Films containing these materials can be used as single layers or in a multilayer structure.

[0355] Furthermore, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, gallium-containing zinc oxide, or graphene can be used as the light-transmitting conductive material. Alternatively, metallic materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, or alloy materials containing such metallic materials, can be used. Alternatively, nitrides of such metallic materials (e.g., titanium nitride) may be used. When using metallic materials, alloy materials (or their nitrides), it is preferable to make them thin enough to be light-transmitting. In addition, a laminated film of the above materials can be used as a conductive layer. For example, using a laminated film of a silver-magnesium alloy and indium tin oxide is preferable because it can enhance conductivity. These can also be used as conductive layers for various wirings and electrodes that constitute a display device, or as conductive layers in display elements (conductive layers that function as pixel electrodes or common electrodes).

[0356] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide, and aluminum oxide.

[0357] Figure 28A shows a cross-sectional view of the display device 400B.

[0358] Display device 400B differs from display device 400A mainly in that it has a lens 449 and a protective layer 195.

[0359] By providing a protective layer 195 that covers the light-receiving element 70 and the light-emitting element 60, it is possible to suppress the ingress of impurities such as water into the light-receiving element 70 and the light-emitting element 60, thereby improving the reliability of the light-receiving element 70 and the light-emitting element 60.

[0360] In the region 228 near the edge of the display device 400B, it is preferable that the insulating layer 215 and the protective layer 195 are in contact with each other through an opening in the insulating layer 214. In particular, it is preferable that the inorganic insulating film of the insulating layer 215 and the inorganic insulating film of the protective layer 195 are in contact with each other. This makes it possible to suppress the entry of impurities into the display unit 11 from the outside through the organic insulating film. Therefore, the reliability of the display device 400B can be improved.

[0361] Figure 28B shows an example where the protective layer 195 has a three-layer structure. In Figure 28B, the protective layer 195 has an inorganic insulating layer 195a on the common electrode 415, an organic insulating layer 195b on the inorganic insulating layer 195a, and an inorganic insulating layer 195c on the organic insulating layer 195b.

[0362] The edges of the inorganic insulating layer 195a and the inorganic insulating layer 195c extend outward beyond the edge of the organic insulating layer 195b and are in contact with each other. Furthermore, the inorganic insulating layer 195a is in contact with the insulating layer 215 (inorganic insulating layer) through an opening in the insulating layer 214 (organic insulating layer). As a result, the light-receiving element 70 and the light-emitting element 60 can be surrounded by the insulating layer 215 and the protective layer 195, thereby increasing the reliability of the light-receiving element 70 and the light-emitting element 60.

[0363] Thus, the protective layer 195 may have a laminated structure of an organic insulating film and an inorganic insulating film. In this case, it is preferable that the edge of the inorganic insulating film extends outward more than the edge of the organic insulating film.

[0364] A lens 449 is provided on the substrate 451 side of the substrate 452. The lens 449 has a convex surface on the substrate 451 side. Preferably, the light-receiving area of ​​the light-receiving element 70 overlaps with the lens 449 but does not overlap with the light-emitting layer 193. This makes it possible to improve the sensitivity and accuracy of the sensor using the light-receiving element 70.

[0365] The lens 449 preferably has a refractive index of 1.3 to 2.5. The lens 449 can be formed using inorganic or organic materials. For example, a material containing resin can be used for the lens 449. Alternatively, a material containing oxides or sulfides can be used for the lens 449.

[0366] Specifically, resins containing chlorine, bromine, or iodine, resins containing heavy metal atoms, resins containing aromatic rings, resins containing sulfur, etc., can be used for lens 449. Alternatively, materials containing a resin and nanoparticles of a material with a higher refractive index than the resin can be used for lens 449. Titanium oxide or zirconium oxide, etc., can be used as nanoparticles.

[0367] Furthermore, cerium oxide, hafnium oxide, lanthanum oxide, magnesium oxide, niobium oxide, tantalum oxide, titanium oxide, yttrium oxide, zinc oxide, oxides containing indium and tin, or oxides containing indium, gallium and zinc, etc., can be used in lens 449. Alternatively, zinc sulfide, etc., can be used in lens 449.

[0368] In addition, in the display device 400B, the protective layer 195 and the substrate 452 are bonded together by an adhesive layer 442. The adhesive layer 442 is provided in overlapping place with the light-receiving element 70 and the light-emitting element 60, respectively, and a solid encapsulation structure is applied to the display device 400B.

[0369] Figure 29A shows a cross-sectional view of the display device 400C.

[0370] The transistor structure of display device 400C differs from that of display device 400B.

[0371] The display device 400C has transistors 208, 209, and 210 on a substrate 451.

[0372] Transistors 208, 209, and 210 each have a conductive layer 221 that functions as a gate, an insulating layer 211 that functions as a gate insulating layer, a semiconductor layer having a channel forming region 231i and a pair of low-resistance regions 231n, a conductive layer 222a connected to one of the pair of low-resistance regions 231n, a conductive layer 222b connected to the other of the pair of low-resistance regions 231n, an insulating layer 225 that functions as a gate insulating layer, a conductive layer 223 that functions as a gate, and an insulating layer 215 covering the conductive layer 223. The insulating layer 211 is located between the conductive layer 221 and the channel forming region 231i. The insulating layer 225 is located between the conductive layer 223 and the channel forming region 231i.

[0373] The conductive layer 222a and the conductive layer 222b are connected to the low-resistance region 231n via openings provided in the insulating layer 225 and the insulating layer 215, respectively. Of the conductive layer 222a and the conductive layer 222b, one functions as a source and the other functions as a drain.

[0374] The pixel electrode 191 of the light-emitting element 60 is electrically connected to one of the pair of low-resistance regions 231n of the transistor 208 via the conductive layer 222b.

[0375] The pixel electrode 411 of the photodetector 70 is electrically connected to the other of the pair of low-resistance regions 231n of the transistor 209 via the conductive layer 222b.

[0376] Figure 29A shows an example where the insulating layer 225 covers the top and sides of the semiconductor layer. On the other hand, in Figure 29B, the insulating layer 225 overlaps with the channel formation region 231i of the semiconductor layer 231, but does not overlap with the low-resistance region 231n. For example, the structure shown in Figure 29B can be fabricated by processing the insulating layer 225 using the conductive layer 223 as a mask. In Figure 29B, an insulating layer 215 is provided covering the insulating layer 225 and the conductive layer 223, and the conductive layers 222a and 222b are connected to the low-resistance region 231n, respectively, through openings in the insulating layer 215. Furthermore, an insulating layer 218 covering the transistor may also be provided.

[0377] Figure 30 shows a cross-sectional view of the display device 400D.

[0378] The display device 400D differs from the display device 400C mainly in that it does not have substrates 451 and 452, but has substrates 453, 454, adhesive layer 455, and insulating layer 212, and also has a lens 449.

[0379] The substrate 453 and the insulating layer 212 are bonded together by an adhesive layer 455. The substrate 454 and the protective layer 195 are bonded together by an adhesive layer 442.

[0380] The display device 400D is manufactured by transferring an insulating layer 212, transistors 208, 209, 210, a light-receiving element 70, and a light-emitting element 60, etc., formed on a fabricated substrate, onto a substrate 453. It is preferable that both substrates 453 and 454 are flexible. This can increase the flexibility of the display device 400D.

[0381] The insulating layer 212 can be an inorganic insulating film that can be used for insulating layers 211, 213, and 215.

[0382] Furthermore, the display device 400C shows an example without the lens 449, while the display device 400D shows an example with the lens 449. The lens 449 can be provided as appropriate depending on the application of the sensor.

[0383] As described above, the display device of this embodiment has a light-receiving element and a light-emitting element in the display unit, and the display unit has both the function of displaying an image and the function of detecting light. This makes it possible to miniaturize and lighten the electronic device compared to cases where a sensor is provided outside the display unit or outside the display device. Furthermore, by combining it with a sensor provided outside the display unit or outside the display device, it is possible to realize an electronic device with more functions.

[0384] The photodetector can have at least one layer other than the active layer that is the same configuration as the light-emitting element (EL element). Furthermore, the photodetector can have all layers other than the active layer that are the same configuration as the light-emitting element (EL element). For example, by simply adding a step to deposit the active layer to the manufacturing process of the light-emitting element, the light-emitting element and the photodetector can be formed on the same substrate. In addition, the pixel electrodes and common electrodes of the photodetector and the light-emitting element can be formed using the same materials and the same process, respectively. Moreover, by manufacturing the circuit electrically connected to the photodetector and the circuit electrically connected to the light-emitting element using the same materials and the same process, the manufacturing process of the display device can be simplified. In this way, a highly convenient display device with a built-in photodetector can be manufactured without complex processes.

[0385] Furthermore, the display device of this embodiment has a colored layer between the light-receiving element and the light-emitting element. This colored layer may also serve as a partition that electrically insulates the light-receiving element and the light-emitting element. Since the colored layer can absorb stray light within the display device, the sensitivity of the sensor using the light-receiving element can be increased.

[0386] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be implemented by appropriately combining at least a part of them with other configuration examples or drawings, etc.

[0387] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0388] (Embodiment 3) This embodiment describes an example of a semiconductor device configuration applicable to the IC20 described in Embodiment 1. As an example, a configuration in which transistors with different electrical characteristics are stacked is described. This configuration increases the design flexibility of the semiconductor device. Furthermore, stacking transistors with different electrical characteristics increases the integration density of the semiconductor device.

[0389] A portion of the cross-sectional structure of a semiconductor device is shown in Figure 31. The semiconductor device shown in Figure 31 includes a transistor 550, a transistor 500, and a capacitor 600. Figure 33A is a cross-sectional view of transistor 500 in the channel length direction, Figure 33B is a cross-sectional view of transistor 500 in the channel width direction, and Figure 33C is a cross-sectional view of transistor 550 in the channel width direction.

[0390] Transistor 500 is an OS transistor. Transistor 500 has an extremely low off-current. Therefore, it is possible to retain the data voltage or charge written to the memory node via transistor 500 for a long period of time. In other words, the frequency of refresh operations of the memory node can be reduced, or refresh operations can be eliminated, thereby reducing the power consumption of the semiconductor device.

[0391] In Figure 31, transistor 500 is located above transistor 550, and capacitor 600 is located above both transistor 550 and transistor 500.

[0392] The transistor 550 is provided on a substrate 311 and has a conductor 316, an insulator 315, a semiconductor region 313 consisting of a part of the substrate 311, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b.

[0393] As shown in Figure 33C, the transistor 550 has its semiconductor region 313's top surface and side surface in the channel width direction covered by a conductor 316 via an insulator 315. By making the transistor 550 a Fin type in this way, the effective channel width can be increased, thereby improving the on-characteristics of the transistor 550. In addition, the contribution of the gate electrode's electric field can be increased, thus improving the off-characteristics of the transistor 550.

[0394] Note that transistor 550 can be either a p-channel transistor or an n-channel transistor.

[0395] In the low-resistance regions 314a and 314b, which form the channel region of the semiconductor region 313, the region near it, the source region, or the drain region, it is preferable that a semiconductor such as a silicon-based semiconductor is included, and it is preferable that single-crystal silicon is included. Alternatively, it may be formed from a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing is also possible. Alternatively, the transistor 550 may be made into a HEMT by using GaAs and GaAlAs, etc.

[0396] The low-resistance region 314a and the low-resistance region 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron.

[0397] The conductor 316, which functions as the gate electrode, can be a conductive material such as a semiconductor material such as silicon, a metallic material, an alloy material, or a metal oxide material containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0398] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use metallic materials such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0399] The transistor 550 may be formed using an SOI (Silicon on Insulator) substrate or the like.

[0400] Furthermore, as SOI substrates, SIMOX (Separation by Implanted Oxygen) substrates may be used, which are formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface while eliminating defects that have formed in the surface layer. Other SOI substrates may be used that are formed using methods such as the smart cut method, which utilizes the growth of minute voids formed by hydrogen ion implantation through heat treatment to cleave the semiconductor substrate, or the ELTRAN method (registered trademark: Epitaxial Layer Transfer). Transistors formed using a single-crystal substrate have a single-crystal semiconductor in the channel formation region.

[0401] Note that the transistor 550 shown in Figure 31 is just one example, and the configuration is not limited to this; an appropriate transistor can be used depending on the circuit configuration and driving method. For example, if the semiconductor device is a unipolar circuit consisting only of OS transistors (meaning only n-channel transistors, etc., or transistors of the same polarity), then the configuration of transistor 550 can be the same as that of transistor 500, as shown in Figure 32. Details of transistor 500 will be described later.

[0402] The transistor 550 is covered by insulators 320, 322, 324, and 326, which are stacked in that order.

[0403] For insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, etc. may be used.

[0404] In this specification, silicon oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride refers to a material in which the nitrogen content is greater than the oxygen content. Furthermore, in this specification, aluminum oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and aluminum nitride refers to a material in which the nitrogen content is greater than the oxygen content.

[0405] The insulator 322 may also function as a planarizing film that flattens steps caused by transistors 550 or the like located below it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0406] Furthermore, it is preferable to use a film for the insulator 324 that has barrier properties to prevent hydrogen and impurities from diffusing from the substrate 311 or the transistor 550, etc., to the region where the transistor 500 is provided.

[0407] As an example of a film having barrier properties against hydrogen, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the properties of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 550. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0408] The amount of hydrogen desorption can be analyzed, for example, using thermal desorption spectroscopy (TDS). For example, in TDS analysis, the amount of hydrogen desorption from insulator 324, when the film surface temperature is in the range of 50°C to 500°C, is calculated as 10 × 10¹⁶ hydrogen atoms per unit area of ​​insulator 324. 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm 2 The following is acceptable.

[0409] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, than that of the relative permittivity of the insulator 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0410] Furthermore, insulators 320, 322, 324, and 326 have embedded capacitors 600, or conductors 328 and 330, which are connected to transistors 500. Conductors 328 and 330 function as plugs or wires. Conductors that function as plugs or wires may be grouped together and assigned the same reference numeral. In this specification, the wire and the plug connected to the wire may be an integrated unit. That is, a part of the conductor may function as a wire, and a part of the conductor may function as a plug.

[0411] The plugs and wiring (conductor 328, conductor 330, etc.) can be made from conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0412] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 31, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. Conductors 356 function as a plug or wiring for connecting to the transistor 550. Conductors 356 can be provided using the same material as conductors 328 and 330.

[0413] For example, it is preferable that the insulator 350, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 356 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 350. With this configuration, transistors 550 and 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0414] For example, tantalum nitride may be used as the conductor that has barrier properties against hydrogen. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from the transistor 550 while maintaining conductivity as wiring. In this case, it is preferable that the tantalum nitride layer, which has barrier properties against hydrogen, is in contact with the insulator 350, which also has barrier properties against hydrogen.

[0415] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in Figure 31, insulators 360, 362, and 364 are stacked in order. Furthermore, a conductor 366 is formed on insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductor 366 can be provided using the same material as conductors 328 and 330.

[0416] For example, it is preferable that the insulator 360, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 366 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 360. With this configuration, transistors 550 and 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0417] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in Figure 31, insulators 370, 372, and 374 are stacked in order. Furthermore, a conductor 376 is formed on insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductor 376 can be provided using the same material as the conductors 328 and 330.

[0418] For example, it is preferable that the insulator 370, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 376 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 370. With this configuration, transistors 550 and 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0419] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in Figure 31, insulators 380, 382, ​​and 384 are stacked in order. Furthermore, a conductor 386 is formed on insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductor 386 can be provided using the same material as the conductors 328 and 330.

[0420] For example, it is preferable that the insulator 380, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 386 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 380. With this configuration, transistors 550 and 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0421] In the above, wiring layers including conductor 356, wiring layers including conductor 366, wiring layers including conductor 376, and wiring layers including conductor 386 have been described, but the semiconductor device according to this embodiment is not limited thereto. Three or fewer wiring layers similar to the wiring layer including conductor 356 may be used, or five or more wiring layers similar to the wiring layer including conductor 356 may be used.

[0422] Insulators 510, 512, 514, and 516 are layered sequentially on the insulator 384. It is preferable that one of the insulators 510, 512, 514, and 516 is made of a material that has barrier properties against oxygen and hydrogen.

[0423] For example, it is preferable to use a film that has barrier properties against hydrogen and impurities in the insulator 510 and insulator 514, for example, in the region where the transistor 500 is installed, from the substrate 311 or the region where the transistor 550 is installed. Therefore, the same material as that used for insulator 324 can be used.

[0424] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the properties of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 550.

[0425] Furthermore, as a film having barrier properties against hydrogen, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, or tantalum oxide for insulators 510 and 514.

[0426] In particular, aluminum oxide exhibits a high barrier effect, preventing the penetration of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0427] Furthermore, for example, the same materials as those used for insulator 320 can be used for insulator 512 and insulator 516. Additionally, by applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wiring can be reduced. For example, silicon oxide films or silicon oxynitride films can be used as insulators 512 and insulator 516.

[0428] Furthermore, the insulators 510, 512, 514, and 516 have a conductor 518 and a conductor constituting the transistor 500 (for example, conductor 503) embedded in them. The conductor 518 functions as a capacitor 600, or as a plug or wiring for connecting to the transistor 550. The conductor 518 can be provided using the same material as the conductors 328 and 330.

[0429] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, transistor 550 and transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0430] A transistor 500 is provided above the insulator 516.

[0431] As shown in Figures 33A and 33B, the transistor 500 includes a conductor 503 arranged to be embedded in insulators 514 and 516, an insulator 520 arranged on top of insulators 516 and 503, an insulator 522 arranged on top of insulator 520, an insulator 524 arranged on top of insulator 522, an oxide 530a arranged on top of insulator 524, an oxide 530b arranged on top of oxide 530a, conductors 542a and 542b arranged spaced apart from each other on oxide 530b, an insulator 580 arranged on top of conductors 542a and 542b with an opening formed between conductors 542a and 542b, an insulator 545 arranged on the bottom and side surfaces of the opening, and a conductor 560 arranged on the forming surface of insulator 545.

[0432] Furthermore, as shown in Figures 33A and 33B, it is preferable that an insulator 544 is placed between the oxide 530a, oxide 530b, conductor 542a, and conductor 542b and the insulator 580. Also, as shown in Figures 33A and 33B, it is preferable that the conductor 560 has a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. Furthermore, as shown in Figures 33A and 33B, it is preferable that an insulator 574 is placed on top of the insulator 580, conductor 560, and insulator 545.

[0433] In this specification, oxides 530a and 530b are sometimes collectively referred to as oxide 530.

[0434] In the transistor 500, a configuration is shown in which two layers of oxide 530a and oxide 530b are stacked in the region where the channel is formed and in its vicinity, but the present invention is not limited to this. For example, a single layer of oxide 530b or a stacked configuration of three or more layers may be provided.

[0435] Furthermore, although the transistor 500 is shown with a two-layer stacked structure for the conductor 560, the present invention is not limited to this. For example, the conductor 560 may be a single layer or a stacked structure of three or more layers. Also, the transistor 500 shown in Figures 31, 32, and 33A is just an example and is not limited to that configuration; an appropriate transistor may be used depending on the circuit configuration, driving method, etc.

[0436] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode or drain electrode, respectively. As described above, the conductor 560 is formed to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. In other words, in the transistor 500, the gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing a positional margin, the occupied area of ​​the transistor 500 can be reduced. This enables miniaturization and high integration of semiconductor devices.

[0437] Furthermore, since the conductor 560 is formed self-aligned in the region between the conductors 542a and 542b, the conductor 560 does not have any region that overlaps with the conductors 542a or 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. Therefore, the switching speed of the transistor 500 can be improved, and thus the frequency characteristics of the transistor 500 can be enhanced.

[0438] Conductor 560 may function as the first gate (also called the top gate) electrode. Conductor 503 may function as the second gate (also called the bottom gate) electrode. In this case, the threshold voltage of transistor 500 can be controlled by changing the potential applied to conductor 503 independently of the potential applied to conductor 560, rather than in conjunction with it. In particular, by applying a negative potential to conductor 503, the threshold voltage of transistor 500 can be increased, and the off-current can be reduced. Therefore, applying a negative potential to conductor 503 reduces the drain current when the potential applied to conductor 560 is 0V compared to not applying a negative potential.

[0439] The conductor 503 is positioned so as to overlap with the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 connect, and can cover the channel-forming region formed in the oxide 530.

[0440] In this specification, a transistor configuration in which the channel formation region is electrically surrounded by the electric fields of a pair of gate electrodes (a first gate electrode and a second gate electrode) is referred to as a surrounded channel (s-channel) configuration. Furthermore, the s-channel configuration disclosed in this specification differs from the Fin-type and Planar-type configurations. By adopting an s-channel configuration, it is possible to increase resistance to short-channel effects, or in other words, to create a transistor in which short-channel effects are less likely to occur.

[0441] Furthermore, the conductor 503 has the same configuration as the conductor 518, with conductor 503a formed in contact with the inner walls of the openings of the insulators 514 and 516, and conductor 503b formed further inside. Although the transistor 500 shows a configuration in which conductors 503a and conductor 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or as a stacked configuration of three or more layers.

[0442] Here, it is preferable to use a conductive material for the conductor 503a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (i.e., the above impurities are less permeable). Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the above oxygen is less permeable). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or oxygen.

[0443] For example, the conductor 503a has a function of suppressing oxygen diffusion, which can prevent the conductor 503b from oxidizing and reducing its conductivity.

[0444] Furthermore, if the conductor 503 also functions as wiring, it is preferable that the conductor 503b be made of a highly conductive material mainly composed of tungsten, copper, or aluminum. In this embodiment, the conductor 503 is shown as a laminate of conductor 503a and conductor 503b, but the conductor 503 may also be a single layer.

[0445] Insulators 520, 522, and 524 function as second gate insulating films.

[0446] Here, it is preferable to use an insulator 524 that contains more oxygen than satisfactorily satisfactorily satisfactorily to be in contact with the oxide 530. This oxygen is easily released from the film by heating. In this specification, the oxygen released by heating is sometimes referred to as "excess oxygen." In other words, it is preferable that the insulator 524 has a region containing excess oxygen (also called an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen deficiencies (V) in the oxide 530 can be reduced. O This reduces the oxygen vacancy (also known as the oxygen vacancy) and improves the reliability of the transistor 500. Furthermore, if hydrogen enters the oxygen vacancy in the oxide 530, the defect (hereinafter referred to as V) can be reduced. O Sometimes referred to as H, hydrogen acts as a donor, and can generate electrons, which are carriers. In addition, some hydrogen can combine with oxygen that is bonded to a metal atom, generating electrons, which are carriers. Therefore, transistors using oxide semiconductors with a high hydrogen content tend to exhibit normally-on characteristics. Furthermore, since hydrogen in oxide semiconductors is easily moved by stress such as heat and electric fields, if the oxide semiconductor contains a lot of hydrogen, the reliability of the transistor may deteriorate. In one embodiment of the present invention, V in oxide 530 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic.O To obtain an oxide semiconductor with sufficiently reduced H content, it is important to remove impurities such as water and hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation") and to supply oxygen to the oxide semiconductor to compensate for oxygen deficiencies (also called "oxygenation"). O By using an oxide semiconductor with sufficiently reduced H content in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0447] Specifically, it is preferable to use an oxide material in which some oxygen is desorbed upon heating as an insulator having an excess oxygen region. An oxide in which oxygen is desorbed upon heating is defined as one in which the amount of oxygen desorbed, converted to oxygen atoms, is 1.0 × 10¹⁶ as determined by TDS analysis. 18 atoms / cm 3 Preferably 1.0 × 10 19 atoms / cm 3 More preferably 2.0 × 10 19 atoms / cm 3 The above, or 3.0 × 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0448] Furthermore, the insulator having the excess oxygen region and the oxide 530 may be brought into contact and subjected to one or more of the following treatments: heat treatment, microwave treatment, or RF treatment. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction occurs in which the VoH bond is broken, in other words, "V O The reaction H → Vo + H occurs, allowing for dehydrogenation. Some of the hydrogen generated at this time may combine with oxygen to form H2O, which may be removed from oxide 530 or the insulator near oxide 530. In addition, some of the hydrogen may be gettered by conductor 542a or conductor 542b.

[0449] Furthermore, the above microwave processing is preferably carried out using, for example, a device having a power supply that generates high-density plasma, or a device having a power supply that applies RF to the substrate side. For example, by using an oxygen-containing gas and a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. In addition, the above microwave processing should be carried out at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. In addition, as the gas introduced into the device for microwave processing, for example, oxygen and argon should be used, and the oxygen flow rate ratio (O2 / (O2+Ar)) should be 50% or less, preferably 10% to 30% or less.

[0450] Furthermore, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment while the surface of the oxide 530 is exposed. This heat treatment may be performed at, for example, 100°C to 450°C, more preferably 350°C to 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby preventing oxygen deficiency (V O This can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0451] Furthermore, by performing an oxygenation treatment on oxide 530, oxygen vacancies in oxide 530 can be repaired by the supplied oxygen, in other words, the reaction "Vo + O → null" can be promoted. In addition, the supplied oxygen reacts with the hydrogen remaining in oxide 530, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 530 recombines with the oxygen vacancies and V O This can suppress the formation of H.

[0452] Furthermore, if the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function to suppress the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen does not easily permeate it).

[0453] The insulator 522 has a function of suppressing the diffusion of oxygen and impurities, so the oxygen contained in the oxide 530 does not diffuse toward the insulator 520, which is preferable. Furthermore, it is possible to suppress the reaction of the conductor 503 with the oxygen contained in the insulator 524 and the oxide 530.

[0454] The insulator 522 preferably uses a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0455] In particular, it is preferable to use an insulator containing an oxide of either aluminum or hafnium, or both, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (the above-mentioned oxygen is less permeable). As an insulator containing an oxide of either aluminum or hafnium, or both, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When an insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen from the periphery of the transistor 500 into the oxide 530.

[0456] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated onto the above insulators.

[0457] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Also, by combining a high-k material insulator with silicon oxide or silicon oxynitride, an insulator 520 with a thermally stable and high dielectric constant laminated structure can be obtained.

[0458] In Figures 33A and 33B, the transistor 500 is shown with insulators 520, 522, and 524 as a second gate insulating film consisting of three layers. However, the second gate insulating film may have a single layer, two layers, or a multilayer structure of four or more layers. In that case, it is not limited to a multilayer structure made of the same material, but may also have a multilayer structure made of different materials.

[0459] The transistor 500 uses a metal oxide that functions as an oxide semiconductor in the oxide 530 which includes the channel formation region. For example, as the oxide 530, a metal oxide such as In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, tin, or magnesium, etc.) may be used.

[0460] The metal oxide that functions as an oxide semiconductor may be formed by sputtering or by ALD (Atomic Layer Deposition). The metal oxide that functions as an oxide semiconductor will be described in detail in other embodiments.

[0461] Furthermore, it is preferable to use a metal oxide with a band gap of 2 eV or more, preferably 2.5 eV or more, that functions as a channel-forming region in oxide 530. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0462] By having oxide 530a below oxide 530b, oxide 530 can suppress the diffusion of impurities from components formed below oxide 530a to oxide 530b.

[0463] Furthermore, it is preferable that the oxide 530 has a laminated structure of multiple oxide layers with different atomic ratios of each metal atom. Specifically, it is preferable that in the metal oxide used for oxide 530a, the atomic ratio of element M in the constituent elements is greater than the atomic ratio of element M in the constituent elements of the metal oxide used for oxide 530b. Also, it is preferable that in the metal oxide used for oxide 530a, the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, it is preferable that in the metal oxide used for oxide 530b, the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0464] Furthermore, it is preferable that the energy at the lower end of the conduction band of oxide 530a is higher than the energy at the lower end of the conduction band of oxide 530b. In other words, it is preferable that the electron affinity of oxide 530a is smaller than the electron affinity of oxide 530b.

[0465] Here, at the junction of oxide 530a and oxide 530b, the energy level at the lower end of the conduction band changes smoothly. In other words, the energy level at the lower end of the conduction band at the junction of oxide 530a and oxide 530b can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 530a and oxide 530b.

[0466] Specifically, a mixed layer with a low defect level density can be formed if oxide 530a and oxide 530b have a common element other than oxygen (as the main component). For example, if oxide 530b is In-Ga-Zn oxide, then oxide 530a can be In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc.

[0467] In this case, the primary carrier pathway is oxide 530b. By configuring oxide 530a as described above, the defect level density at the interface between oxide 530a and oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 500 can obtain a high on-current.

[0468] Conductors 542a and 542b, which function as source electrodes and drain electrodes, are provided on the oxide 530b. It is preferable to use metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum as conductors 542a and 542b, or alloys composed of the above metallic elements, or alloys combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. In addition, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0469] Furthermore, although conductors 542a and 542b are shown as single-layer structures in Figure 33A, they may also be laminated in two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Alternatively, a titanium film and an aluminum film may be laminated. In addition, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may also be used.

[0470] Furthermore, there are three-layer configurations such as a titanium film or titanium nitride film, an aluminum film or copper film laminated on top of the titanium film or titanium nitride film, and a titanium film or titanium nitride film formed on top of that; and a molybdenum film or molybdenum nitride film, an aluminum film or copper film laminated on top of the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film formed on top of that. Transparent conductive materials containing indium oxide, tin oxide, or zinc oxide may also be used.

[0471] Furthermore, as shown in Figure 33A, regions 543a and 543b may be formed as low-resistance regions at and near the interface between the oxide 530 and the conductor 542a (conductor 542b). In this case, region 543a functions as either a source region or a drain region, and region 543b functions as either a source region or a drain region. In addition, a channel-forming region is formed in the region sandwiched between regions 543a and 543b.

[0472] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. In addition, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in region 543a (region 543b). In such cases, the carrier density in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0473] The insulator 544 is provided so as to cover the conductors 542a and 542b, thereby suppressing oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and be in contact with the insulator 524.

[0474] As the insulator 544, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, or magnesium can be used. Alternatively, silicon nitride or silicon nitride can also be used as the insulator 544.

[0475] In particular, it is preferable to use an insulator 544 that contains an oxide of either aluminum or hafnium, or both, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is especially preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in a later process. Note that if the conductors 542a and 542b are made of oxidation-resistant materials, or if their conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component. It can be designed appropriately according to the desired transistor characteristics.

[0476] The presence of the insulator 544 suppresses the diffusion of water and other impurities such as hydrogen contained in the insulator 580 into the oxide 530b via the insulator 545. Furthermore, it suppresses the oxidation of the conductor 560 due to excess oxygen present in the insulator 580.

[0477] The insulator 545 functions as the first gate insulating film. The insulator 545 is preferably formed using an insulator that contains an excess of oxygen and releases oxygen upon heating, similar to the insulator 524 described above.

[0478] Specifically, silicon oxide with excess oxygen, silicon oxide-nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide can be used. Silicon oxide and silicon oxide-nitride are particularly preferred because they are stable to heat.

[0479] By providing an insulator containing excess oxygen as insulator 545, oxygen can be effectively supplied from insulator 545 to the channel-forming region of oxide 530b. Furthermore, similar to insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in insulator 545 is reduced. The film thickness of insulator 545 is preferably between 1 nm and 20 nm.

[0480] Furthermore, in order to efficiently supply excess oxygen from the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. It is preferable that the metal oxide suppresses the diffusion of oxygen from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. In other words, the reduction in the amount of excess oxygen supplied to the oxide 530 can be suppressed. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, any material that can be used for the insulator 544 may be used.

[0481] Furthermore, the insulator 545 may be in a multilayer configuration, similar to the second gate insulating film. As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as leakage current. Therefore, by using a multilayer configuration of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a multilayer configuration that is thermally stable and has a high dielectric constant can be achieved.

[0482] The conductor 560, which functions as the first gate electrode, is shown as a two-layer structure in Figures 33A and 33B, but it may also be a single-layer structure or a stacked structure of three or more layers.

[0483] It is preferable to use a conductive material for the conductor 560a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules). By having the function of suppressing the diffusion of oxygen in the conductor 560a, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 545, which reduces the conductivity. As a conductive material that has the function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Furthermore, an oxide semiconductor applicable to oxide 530 can be used as the conductor 560a. In that case, by depositing the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0484] Furthermore, it is preferable that the conductor 560b is made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 560b functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 560b may also be in a laminated configuration, for example, a laminated configuration of titanium or titanium nitride and the above conductive material.

[0485] The insulator 580 is provided on the conductors 542a and 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and porous silicon oxide are particularly preferred because they can easily form an excess oxygen region in a later process.

[0486] The insulator 580 preferably has an excess oxygen region. By providing an insulator 580 that releases oxygen upon heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. It is also preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

[0487] The opening in the insulator 580 is formed superimposed on the region between the conductors 542a and 542b. As a result, the conductor 560 is formed to be embedded in the opening in the insulator 580 and in the region sandwiched between the conductors 542a and 542b.

[0488] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 560 does not decrease. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may take on a shape with a high aspect ratio. In this embodiment, since the conductor 560 is embedded in the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, it can be formed without the conductor 560 collapsing during the manufacturing process.

[0489] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545. By forming the insulator 574 by sputtering, an excess oxygen region can be created on the insulator 545 and the insulator 580. This allows oxygen to be supplied to the oxide 530 from the excess oxygen region.

[0490] For example, as the insulator 574, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0491] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in thin films between 0.5 nm and 3.0 nm in thickness. Therefore, aluminum oxide deposited by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0492] Furthermore, it is preferable to provide an insulator 581 that functions as an interlayer film on top of the insulator 574. Similar to the insulator 524, it is preferable that the insulator 581 has a reduced concentration of impurities such as water or hydrogen in the film.

[0493] Furthermore, conductors 540a and 540b are placed in the openings formed in insulators 581, 574, 580, and 544. Conductors 540a and 540b are provided facing each other with conductor 560 in between. Conductors 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0494] An insulator 582 is provided on the insulator 581. It is preferable that the insulator 582 be made of a material that has barrier properties against oxygen and hydrogen. Therefore, the same material as that used for the insulator 514 can be used for the insulator 582. For example, it is preferable that the insulator 582 be made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0495] In particular, aluminum oxide exhibits a high barrier effect, preventing the penetration of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0496] Furthermore, an insulator 586 is provided on the insulator 582. The insulator 586 can be made of the same material as the insulator 320. By applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used as the insulator 586.

[0497] Furthermore, conductors 546 and 548, etc., are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0498] Conductors 546 and 548 function as plugs or wires for connecting to capacitor 600, transistor 500, or transistor 550. Conductors 546 and 548 can be provided using the same materials as conductors 328 and 330.

[0499] Furthermore, after the formation of the transistor 500, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By enclosing the transistor 500 with the above-mentioned high-barrier insulator, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be encased together with an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, forming an opening that reaches the insulator 522 or insulator 514, and forming the above-mentioned high-barrier insulator in contact with the insulator 522 or insulator 514 is preferable because it can also serve as part of the manufacturing process for the transistor 500. As the insulator with high barrier properties against hydrogen or water, for example, the same material as insulator 522 or insulator 514 may be used.

[0500] Next, a capacitor 600 is provided above the transistor 500. The capacitor 600 has a conductor 610, a conductor 620, and an insulator 630.

[0501] Furthermore, a conductor 612 may be provided on the conductors 546 and 548. The conductor 612 functions as a plug or wiring for connecting to the transistor 500. The conductor 610 functions as an electrode with capacitance 600. Note that the conductors 612 and 610 can be formed simultaneously.

[0502] Conductors 612 and 610 can be made of a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) composed of the above elements. Alternatively, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added may also be used.

[0503] In this embodiment, the conductors 612 and 610 are shown in a single-layer configuration, but the embodiment is not limited to this configuration and may be a laminated configuration of two or more layers. For example, a conductor with high adhesion to both the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0504] A conductor 620 is provided so as to overlap the conductor 610 via an insulator 630. The conductor 620 can be a conductive material such as a metal, alloy, or metal oxide. It is preferable to use a high-melting-point material such as tungsten or molybdenum that provides both heat resistance and conductivity, and tungsten is particularly preferable. When forming the conductor simultaneously with other components, low-resistance metal materials such as Cu (copper) or Al (aluminum) may be used.

[0505] An insulator 640 is provided on the conductor 620 and the insulator 630. The insulator 640 can be provided using the same material as the insulator 320. The insulator 640 may also function as a planarizing film that covers the uneven shape below it.

[0506] By using this configuration, it is possible to achieve miniaturization or high integration in semiconductor devices using transistors having oxide semiconductors.

[0507] Furthermore, the configurations shown in Figures 33A and 33B can be applied to the transistors of the pixel 12 shown in Embodiment 1. As mentioned above, the transistors in the configurations shown in Figures 33A and 33B occupy a small area. Therefore, the pixel 12 can be made higher resolution, and the pixel density of the display device 10 can be increased. For example, by configuring the display device 10 as shown in Figure 2A or Figure 2B, and applying the configurations shown in Figures 33A and 33B to all the transistors of the pixel 12, the pixel density of the display device 10 can be made 1000 ppi or more. Or, it can be made 3000 ppi or more. Or, it can be made 5000 ppi or more.

[0508] Substrates that can be used in a semiconductor device according to one embodiment of the present invention include glass substrates, quartz substrates, sapphire substrates, ceramic substrates, metal substrates (e.g., stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, etc.), semiconductor substrates (e.g., single-crystal semiconductor substrates, polycrystalline semiconductor substrates, or compound semiconductor substrates, etc.), SOI (Silicon on Insulator) substrates, etc. Alternatively, a heat-resistant plastic substrate capable of withstanding the processing temperature of this embodiment may be used. Examples of glass substrates include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, or soda-lime glass. Other materials such as crystallized glass can also be used.

[0509] Alternatively, flexible substrates, laminated films, paper containing fibrous materials, or base films can be used as substrates. Examples of flexible substrates, laminated films, and base films include the following: Plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, synthetic resins such as acrylic resins can be used. Alternatively, polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride can be used. Alternatively, polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor-deposited film, or paper can be used. In particular, by manufacturing transistors using semiconductor substrates, single-crystal substrates, or SOI substrates, it is possible to manufacture transistors with less variation in characteristics, size, or shape, high current capability, and small size. By configuring circuits with such transistors, it is possible to reduce the power consumption of the circuit or increase the integration of the circuit.

[0510] Alternatively, a flexible substrate may be used as the substrate, and transistors, resistors, and / or capacitors may be formed directly on the flexible substrate. Or, a release layer may be provided between the substrate and the transistors, resistors, and / or capacitors. The release layer can be used to separate the semiconductor device from the substrate after it has been partially or completely completed and to transfer it to another substrate. In this case, the transistors, resistors, and / or capacitors can be transferred to substrates with poor heat resistance or flexible substrates. The release layer can be, for example, a laminated inorganic film structure of a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on the substrate, or a silicon film containing hydrogen.

[0511] In other words, a semiconductor device may be formed on one substrate and then transferred to another substrate. Examples of substrates to which the semiconductor device is transferred include, in addition to the substrates on which transistors can be formed as described above, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupro, rayon, recycled polyester), etc.), leather substrates, or rubber substrates. By using these substrates, it is possible to manufacture flexible semiconductor devices, semiconductor devices that are less prone to breakage, heat-resistant devices, lightweight devices, or thinner devices.

[0512] By mounting a semiconductor device on a flexible substrate, it is possible to provide a semiconductor device that is less prone to damage and has a reduced increase in weight.

[0513] <Transistor Variation 1> The transistor 500A shown in Figures 34A, 34B, and 34C is a modified example of the transistor 500 with the configuration shown in Figures 33A and 33B. Figure 34A is a top view of the transistor 500A, Figure 34B is a cross-sectional view of the transistor 500A in the channel length direction, and Figure 34C is a cross-sectional view of the transistor 500A in the channel width direction. Note that in the top view of Figure 34A, some elements have been omitted for clarity. The configurations shown in Figures 34A, 34B, and 34C can also be applied to other transistors in a semiconductor device according to one embodiment of the present invention, such as the transistor 550.

[0514] The transistor 500A with the configuration shown in Figures 34A, 34B, and 34C differs from the transistor 500 with the configuration shown in Figures 33A and 33B in that it has insulators 552, 513, and 404. Furthermore, it differs from the transistor 500 with the configuration shown in Figures 33A and 33B in that insulator 552 is provided in contact with the side surface of conductor 540a, and insulator 552 is provided in contact with the side surface of conductor 540b. Finally, it differs from the transistor 500 with the configuration shown in Figures 33A and 33B in that it does not have an insulator 520.

[0515] In the transistor 500A with the configuration shown in Figures 34A, 34B, and 34C, an insulator 513 is provided on an insulator 512. In addition, an insulator 404 is provided on an insulator 574 and on an insulator 513.

[0516] In the transistor 500A with the configuration shown in Figures 34A, 34B, and 34C, insulators 514, 516, 522, 524, 544, 580, and 574 are patterned, and insulator 404 covers them. In other words, insulator 404 is in contact with the top surface of insulator 574, the side surface of insulator 574, the side surface of insulator 580, the side surface of insulator 544, the side surface of insulator 524, the side surface of insulator 522, the side surface of insulator 516, the side surface of insulator 514, and the top surface of insulator 513, respectively. As a result, oxides 530 and the like are isolated from the outside by insulators 404 and 513.

[0517] It is preferable that the insulators 513 and 404 have a high ability to suppress the diffusion of hydrogen (for example, at least one such as a hydrogen atom or hydrogen molecule) or water molecules. For example, it is preferable to use silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, as the insulators 513 and 404. This suppresses the diffusion of hydrogen and the like into the oxide 530, and thus suppresses the degradation of the characteristics of the transistor 500A. Therefore, the reliability of the semiconductor device according to one embodiment of the present invention can be improved.

[0518] The insulator 552 is provided in contact with the insulators 581, 404, 574, 580, and 544. Preferably, the insulator 552 has the function of suppressing the diffusion of hydrogen or water molecules. For example, it is preferable to use an insulator 552 that has high hydrogen barrier properties, such as silicon nitride, aluminum oxide, or silicon nitride oxide. In particular, silicon nitride is a material with high hydrogen barrier properties and is therefore preferable to use as the insulator 552. By using a material with high hydrogen barrier properties as the insulator 552, it is possible to suppress the diffusion of impurities such as water or hydrogen from the insulator 580, etc., through the conductors 540a and 540b to the oxide 530. In addition, it is possible to suppress the absorption of oxygen contained in the insulator 580 by the conductors 540a and 540b. As a result, the reliability of the semiconductor device according to one embodiment of the present invention can be improved.

[0519] <Transistor Variation 2> An example of the configuration of transistor 500B will be explained using Figures 35A, 35B, and 35C. Figure 35A is a top view of transistor 500B. Figure 35B is a cross-sectional view of the L1-L2 region shown by the dashed line in Figure 35A. Figure 35C is a cross-sectional view of the W1-W2 region shown by the dashed line in Figure 35A. Note that in the top view of Figure 35A, some elements have been omitted for clarity.

[0520] The transistor 500B is a modified version of the transistor 500 and is a replaceable transistor for the transistor 500. Therefore, to avoid repetition, we will mainly explain the differences between the transistor 500B and the transistor 500.

[0521] The conductor 560, which functions as the first gate electrode, has a conductor 560a and a conductor 560b on the conductor 560a. It is preferable that the conductor 560a is made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0522] The conductor 560a has the function of suppressing oxygen diffusion, thereby improving the material selectivity of the conductor 560b. In other words, the presence of conductor 560a suppresses the oxidation of conductor 560b and prevents a decrease in conductivity.

[0523] Furthermore, it is preferable to provide an insulator 544 so as to cover the top and side surfaces of the conductor 560 and the side surfaces of the insulator 545. The insulator 544 should be made of an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, other materials that can be used include, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride or silicon nitride, etc.

[0524] By providing the insulator 544, oxidation of the conductor 560 can be suppressed. Furthermore, the presence of the insulator 544 can suppress the diffusion of water, hydrogen, and other impurities present in the insulator 580 to the transistor 500B.

[0525] Transistor 500B tends to have higher parasitic capacitance than transistor 500 because the conductor 560 overlaps with parts of conductors 542a and 542b. Therefore, it tends to have a lower operating frequency compared to transistor 500. However, it has higher productivity compared to transistor 500 because it does not require the process of creating openings in insulators 580, etc., to embed conductors 560 and insulators 545, etc.

[0526] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments and examples.

[0527] (Embodiment 4) This embodiment describes an oxide semiconductor, which is a type of metal oxide.

[0528] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0529] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 36A. Figure 36A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0530] As shown in Figure 36A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous semiconductors. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that single crystal, polycrystal, and completely amorphous semiconductors are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal semiconductors.

[0531] The structure within the thick frame shown in Figure 36A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0532] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 36B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 36B will simply be referred to as the XRD spectrum. In Figure 36B, the vertical axis represents intensity, and the horizontal axis represents 2θ. The composition of the CAAC-IGZO film shown in Figure 36B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 36B is 500 nm.

[0533] As shown in Figure 36B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 36B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0534] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 36C. Figure 36C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 36C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0535] As shown in Figure 36C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0536] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 36A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), amorphous oxide semiconductors, etc.

[0537] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0538] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0539] Each of the above-mentioned crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of that crystalline region will be less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0540] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0541] When structural analysis of a CAAC-OS film is performed using, for example, an XRD instrument, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the peak indicating c-axis orientation (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0542] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0543] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0544] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more effectively than In oxide.

[0545] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0546] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0547] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0548] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0549] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing the metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0550] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0551] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0552] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0553] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0554] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0555] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on ), high field-effect mobility (μ), and good switching operation can be achieved.

[0556] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0557] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0558] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0559] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm-3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0560] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0561] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0562] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0563] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0564] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels within the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are compared by 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 17atoms / cm 3 The following applies:

[0565] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0566] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0567] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons, which act as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0568] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0569] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments and examples.

[0570] (Embodiment 5) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 37, 38, and 39.

[0571] The electronic device of this embodiment has a display device according to one aspect of the present invention. For example, the display device according to one aspect of the present invention can be applied to the display unit of an electronic device. Since the display device according to one aspect of the present invention has a function to detect light, it can perform biometric authentication on the display unit, or detect touch or near-touch. This can enhance the functionality and convenience of the electronic device.

[0572] Examples of electronic devices include television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0573] The electronic device of this embodiment may have sensors (including those with functions to measure force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0574] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0575] The electronic device 6500 shown in Figure 37A is a portable information terminal that can be used as a smartphone.

[0576] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508, etc. The display unit 6502 has a touch panel function.

[0577] A display device according to one embodiment of the present invention can be applied to the display unit 6502. This makes it possible to reduce the cost of the electronic device 6500.

[0578] Figure 37B is a schematic cross-sectional view of the housing 6501, including the end on the microphone 6506 side.

[0579] A light-transmitting protective member 6510 is provided on the display side of the housing 6501, and the display panel 6511, optical member 6512, touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged in the space enclosed by the housing 6501 and the protective member 6510.

[0580] The protective member 6510 is fixed to the display panel 6511, the optical member 6512, and the touch sensor panel 6513 by an adhesive layer (not shown).

[0581] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and the FPC 6515 is connected to this folded portion. IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals provided on the printed circuit board 6517.

[0582] A flexible display according to one embodiment of the present invention can be applied to the display panel 6511. This makes it possible to realize an extremely lightweight electronic device. Furthermore, because the display panel 6511 is extremely thin, it is possible to incorporate a large-capacity battery 6518 while keeping the thickness of the electronic device low. In addition, by folding back a part of the display panel 6511 and placing the connection part with the FPC 6515 on the back of the pixel area, it is possible to realize an electronic device with a narrow bezel.

[0583] Figure 38A shows an example of a television system. The television system 7100 has a display unit 7000 incorporated into a housing 7101. Here, the housing 7101 is shown supported by a stand 7103.

[0584] A display device according to one embodiment of the present invention can be applied to the display unit 7000. This makes it possible to make the television device 7100 inexpensive.

[0585] The television device 7100 shown in Figure 38A can be operated using the operation switches on the housing 7101 or a separate remote control unit 7111. Alternatively, the display unit 7000 may be equipped with a touch sensor, and the television device 7100 can be operated by touching the display unit 7000 with a finger or the like. The remote control unit 7111 may have a display unit that displays information output from the remote control unit 7111. Channels and volume can be controlled and the image displayed on the display unit 7000 can be controlled using the operation keys or touch panel on the remote control unit 7111.

[0586] The television system 7100 is configured to include a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0587] Figure 38B shows an example of a notebook personal computer. The notebook personal computer 7200 has a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7000 is incorporated into the casing 7211.

[0588] A display device according to one embodiment of the present invention can be applied to the display unit 7000. This makes it possible to make the notebook personal computer 7200 inexpensive.

[0589] Figures 38C and 38D show examples of digital signage.

[0590] The digital signage 7300 shown in Figure 38C comprises a housing 7301, a display unit 7000, and a speaker 7303, etc. Furthermore, it may include LED lamps, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0591] Figure 38D shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7000 that is provided along the curved surface of the column 7401.

[0592] In Figures 38C and 38D, a display device according to one embodiment of the present invention can be applied to the display unit 7000. This makes it possible to make the digital signage 7300 and digital signage 7400 inexpensive.

[0593] The larger the display area 7000, the more information can be provided at once. Furthermore, a larger display area 7000 is more eye-catching, which can, for example, enhance the effectiveness of advertising.

[0594] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000, but also allows users to operate it intuitively. Furthermore, when used for purposes such as providing route information or traffic information, intuitive operation can enhance usability.

[0595] Furthermore, as shown in Figures 38C and 38D, it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 or information terminal 7411 such as a smartphone owned by the user. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or information terminal 7411. Also, the display on the display unit 7000 can be switched by operating the information terminal 7311 or information terminal 7411.

[0596] Furthermore, the digital signage 7300 or digital signage 7400 can be used to run games using the screen of the information terminal 7311 or information terminal 7411 as the control device (controller). This allows a large number of users to participate in and enjoy the game simultaneously.

[0597] The electronic equipment shown in Figures 39A to 39F includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, sensors 9007 (including functions for measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0598] The electronic devices shown in Figures 39A to 39F have various functions. For example, they may have functions to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. However, the functions of electronic devices are not limited to these and can have various functions. Electronic devices may have multiple display units. Furthermore, electronic devices may be equipped with a camera, etc., and have functions to capture still images and videos and save them to a recording medium (external or built into the camera), a function to display the captured images on a display unit, etc.

[0599] Details of the electronic equipment shown in Figures 39A to 39F will be explained below.

[0600] Figure 39A is a perspective view showing a personal digital assistant (PDA) 9101. The PDA 9101 can be used, for example, as a smartphone. The PDA 9101 may also be equipped with a speaker 9003, connection terminals 9006, sensors 9007, etc. The PDA 9101 can also display text and image information on multiple surfaces. Figure 39A shows an example where three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the subject of emails and SNS messages, sender name, date and time, time, battery level, antenna signal strength, etc. Alternatively, icons 9050, etc., may be displayed in the position where information 9051 is displayed.

[0601] In Figure 39A, a display device according to one embodiment of the present invention can be applied to the display unit 9001. This makes it possible to make the portable information terminal 9101 inexpensive.

[0602] Figure 39B is a perspective view showing the personal digital assistant (PDA) 9102. The PDA 9102 has the function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053, which is displayed in a position that can be observed from above the PDA 9102, while the PDA 9102 is stored in the breast pocket of their clothing. The user can check the display without taking the PDA 9102 out of their pocket and decide, for example, whether or not to answer a call.

[0603] In Figure 39B, a display device according to one embodiment of the present invention can be applied to the display unit 9001. This makes it possible to make the portable information terminal 9102 inexpensive.

[0604] Figure 39C is a perspective view showing a wristwatch-type personal information terminal 9200. The personal information terminal 9200 can be used, for example, as a smartwatch (registered trademark). The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 can also make hands-free calls by communicating with, for example, a wireless communication headset. Furthermore, the personal information terminal 9200 can transmit data to other information terminals and be charged via a connection terminal 9006. Charging may be performed by wireless power supply.

[0605] In Figure 39C, a display device according to one embodiment of the present invention can be applied to the display unit 9001. This makes it possible to make the portable information terminal 9200 inexpensive.

[0606] Figures 39D, 39E, and 39F are perspective views showing a foldable personal information terminal 9201. Figure 39D shows the personal information terminal 9201 in an unfolded state, Figure 39F shows it in a folded state, and Figure 39E shows a state in between the transition from one of Figures 39D or 39F to the other. The personal information terminal 9201 offers excellent portability in its folded state and excellent readability of the display due to its seamless, wide display area in its unfolded state. The display unit 9001 of the personal information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 0.1 mm to 150 mm.

[0607] In Figures 39A to 39F, a display device according to one embodiment of the present invention can be applied to the display unit 9001. This makes it possible to make the portable information terminal 9201 inexpensive.

[0608] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be implemented by appropriately combining at least a part of them with other configuration examples or drawings, etc.

[0609] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. [Explanation of symbols]

[0610] 10: Display device, 10A: Display device, 10B: Display device, 10C: Display device, 10D: Display device, 10E: Display device, 10F: Display device, 10K: Display device, 10L: Display device, 10M: Display device, 11: Display unit, 12: Pixel, 13: Gate driver circuit, 14: Pixel circuit, 14B: Pixel circuit, 14G: Pixel circuit, 14IR: Pixel circuit, 14R: Pixel circuit, 14W: Pixel circuit, 15: Pixel circuit, 16: Optical, 16B: Optical, 16G: Optical, 16R: Optical, 17: Optical, 18: Substrate, 19: Row driver circuit, 20: IC, 21: Interface circuit, 22: Control circuit 23: Data driver circuit, 24: Circuit, 25: FPC, 26: Memory circuit, 31: Wiring, 31a: Wiring, 31b: Wiring, 32: Wiring, 33: Wiring, 34: Wiring, 35: Wiring, 36: Wiring, 37: Wiring, 38: Wiring, 41: Reference signal generation circuit, 42: A / D conversion circuit, 43: Shift register circuit, 44: Clock signal generation circuit, 51a: Transistor, 51b: Transistor, 52: Capacitive element, 53: Comparator circuit, 54: Counter circuit, 55a: Wiring, 55b: Wiring, 56: Wiring, 57: Wiring, 59: Wiring, 60: Light-emitting element, 61: Transistor, 61a : Transistor, 61b: Transistor, 62: Transistor, 63: Transistor, 64: Capacitive element, 65: Wiring, 66: Transistor, 67: Capacitive element, 68: Wiring, 70: Photodetector, 71: Transistor, 72: Transistor, 73: Transistor, 74: Transistor, 75: Capacitive element, 76: Capacitive element, 77: Transistor, 78: Transistor, 79: Transistor, 80: CDS circuit, 81: Transistor, 82a: Transistor, 82b: Transistor, 83a: Transistor, 83b: Transistor, 84a: Capacitive element, 84b: Capacitor Element, 85: Transistor, 86: Transistor, 91: Wiring, 92: Wiring, 93: Wiring, 94: Wiring, 95: Wiring, 96: Wiring, 97: Wiring, 101: Timing signal generation circuit, 102: Level shift circuit, 111: Shift register circuit, 112: Latch circuit, 113: Level shift circuit, 114: D / A conversion circuit, 115: Amplifier circuit, 121: Substrate, 122: Finger, 123: Eye, 131: Current source, 140: Layer, 150: Layer, 151: Insulating film, 164: Circuit, 165: Wiring, 166: Conductive layer, 172: FPC, 182: Buffer layer, 184: Buffer layer,191: Pixel electrode, 192: Buffer layer, 193: Light-emitting layer, 194: Buffer layer, 195: Protective layer, 195a: Inorganic insulating layer, 195b: Organic insulating layer, 195c: Inorganic insulating layer, 201: Transistor, 204: Connector, 205: Transistor, 206: Transistor, 208: Transistor, 209: Transistor, 210: Transistor, 211: Insulating layer, 212: Insulating layer, 213: Insulating layer, 214: Insulating layer, 215: Insulating layer, 216: Partition, 217: Partition, 218: Insulating layer, 221: Conductive layer, 222a: Conductive layer, 222b: Conductive layer, 223: Conductive layer, 22 5: Insulating layer, 228: Region, 231: Semiconductor layer, 231i: Channel formation region, 231n: Low resistance region, 242: Connecting layer, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 341: Transistor, 342: Transistor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 370: Insulator Body, 372: insulator, 374: insulator, 376: conductor, 380: insulator, 382: insulator, 384: insulator, 386: conductor, 400A: display device, 400B: display device, 400C: display device, 400D: display device, 404: insulator, 411: pixel electrode, 412: common layer, 413: active layer, 414: common layer, 415: common electrode, 423a: light, 423b: reflected light, 423c: light, 423d: reflected light, 442: adhesive layer, 443: space, 446: lens array, 449: lens, 451: substrate, 452: substrate, 453: substrate, 454: substrate, 455: adhesive layer, 460: Color filter, 461: Lens, 462: Lens array, 500: Transistor, 500A: Transistor, 500B: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 510: Insulator, 512: Insulator, 513: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 520: Insulator, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 540a: Conductor, 540b: Conductor, 542a: Conductor, 542b: Conductor, 543a: Region, 543b: Region, 544: Insulator,545: Insulator, 546: Conductor, 548: Conductor, 550: Transistor, 552: Insulator, 560: Conductor, 560a: Conductor, 560b: Conductor, 574: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 586: Insulator, 600: Capacitor, 610: Conductor, 612: Conductor, 620: Conductor, 630: Insulator, 640: Insulator, 6500: Electronic equipment, 6501: Enclosure 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protective component, 6511: Display panel, 6512: Optical component, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7000: Display unit, 7100: Television equipment 7101: Enclosure, 7103: Stand, 7111: Remote control, 7200: Notebook personal computer, 7211: Enclosure, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Enclosure, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 9000: housing, 9001: display unit, 9003: speaker, 9005: operation keys, 9006: connection terminal, 9007: sensor, 9008: microphone, 9050: icon, 9051: information, 9052: information, 9053: information, 9054: information, 9055: hinge, 9101: portable information terminal, 9102: portable information terminal, 9200: portable information terminal, 9201: portable information terminal,

Claims

[Claim 1] It has a display unit, The display unit has a plurality of pixels, Each of the plurality of pixels has a first pixel circuit and a second pixel circuit, The first pixel circuit comprises a first transistor and a photodetector, The aforementioned second pixel circuit is a display device having a second transistor and a light-emitting element, It comprises a first insulating layer, a second insulating layer, a first pixel electrode, a second pixel electrode, a first common layer, an active layer, a light-emitting layer, a second common layer, a common electrode, a third insulating layer, a fourth insulating layer, and a fifth insulating layer. The first insulating layer is a first inorganic insulating layer and has a region located above the first transistor and a region located above the second transistor. The second insulating layer has a region located above the first insulating layer, The first pixel electrode has a region located above the second insulating layer and functions as one of a pair of electrodes of the photodetector. The second pixel electrode has a region located above the second insulating layer and functions as one of a pair of electrodes of the light-emitting element. The first common layer has a region located above the first pixel electrode and a region located above the second pixel electrode, and functions as either or both a hole injection layer and a hole transport layer. The active layer has a region that overlaps with the first pixel electrode via the first common layer, The light-emitting layer has a region that overlaps with the second pixel electrode via the first common layer, The second common layer has a region located above the active layer and a region located above the light-emitting layer, and functions as either or both of an electron transport layer and an electron injection layer. The common electrode has a region that overlaps with the active layer via the second common layer and a region that overlaps with the light-emitting layer via the second common layer, and functions as the other of a pair of electrodes of the photodetector and functions as the other of a pair of electrodes of the light-emitting element. The third insulating layer is a second inorganic insulating layer and has a region located above the common electrode. The fourth insulating layer is an organic insulating layer and has a region located above the third insulating layer. The fifth insulating layer is a third inorganic insulating layer and has a region located above the fourth insulating layer. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer are arranged across the display portion. The first common layer has a first region in contact with the second common layer between the active layer and the light-emitting layer, and a second region in contact with the second common layer at the end of the display portion. Outside the second region, the third insulating layer has a region in contact with the fifth insulating layer. A display device wherein, outside the second region, the first insulating layer has a region in contact with the third insulating layer.

Images