Semiconductor devices and semiconductor circuits

Abstract

To provide a semiconductor device in which destruction due to current concentration is suppressed.SOLUTION: A semiconductor device of an embodiment comprises: a semiconductor layer having a first surface and a second surface opposing the first surface, the semiconductor layer including a first trench provided on a first surface side and a second trench provided on the first surface side; a first gate electrode provided in the first trench; a second gate electrode provided in the second trench; a fourth gate electrode provided on a second surface side; a fifth gate electrode provided on the second surface side; a first electrode in contact with the first surface; a second electrode in contact with the second surface; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; a fourth electrode pad electrically connected to the fourth gate electrode; and a fifth electrode pad electrically connected to the fifth gate electrode.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and semiconductor circuits. Background Art

[0002] As an example of a power semiconductor device, there is an Insulated Gate Bipolar Transistor (IGBT) with a trench gate structure. In an IGBT with a trench gate structure, for example, a p-type collector region, an n-type drift region, and a p-type base region are provided on a collector electrode. A gate electrode is provided in a trench penetrating the p-type base region and reaching the n-type drift region, with a gate insulating film interposed therebetween. Furthermore, an n-type emitter region connected to an emitter electrode is provided in a region adjacent to the trench on the surface of the p-type base region.

[0003] In the above IGBT, when a positive voltage higher than the threshold voltage is applied to the gate electrode, a channel is formed in the p-type base region. Electrons are injected from the n-type emitter region into the n-type drift region, and holes are injected from the p-type collector region into the n-type drift region. As a result, an on-current using electrons and holes as carriers flows between the collector electrode and the emitter electrode.

[0004] A termination region is provided around the cell region provided with the trench gate structure. The termination region includes, for example, an electric field relaxation structure such as a guard ring. Provision of the termination region reduces the electric field intensity at the end of the cell region, and suppresses a decrease in breakdown voltage when the IGBT is in an off state.

[0005] At the end of the cell region, when the IGBT is in an on state, carriers spread to the termination region where no cells are present. During a turn-off operation when the IGBT transitions from the on state to the off state, the carriers that have spread to the termination region are concentrated and discharged to the end of the cell region. Therefore, current concentration occurs at the end of the cell region. Accordingly, there is a risk that the IGBT may be destroyed due to current concentration. Prior Art Documents [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2020-53466 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] The problem that this invention aims to solve is to provide a semiconductor device and semiconductor circuit in which turn-off losses are reduced and breakdown due to current concentration is suppressed. [Means for solving the problem]

[0008] The semiconductor device of the embodiment comprises a semiconductor layer having a first surface and a second surface facing the first surface, the semiconductor layer including a first trench provided on the side of the first surface and a second trench provided on the side of the first surface, a first gate electrode provided in the first trench, a second gate electrode provided in the second trench, a fourth gate electrode provided on the side of the second surface, a fifth gate electrode provided on the side of the second surface, a first electrode in contact with the first surface, a second electrode in contact with the second surface, a first electrode pad electrically connected to the first gate electrode, a second electrode pad electrically connected to the second gate electrode, a fourth electrode pad electrically connected to the fourth gate electrode, and a fifth electrode pad electrically connected to the fifth gate electrode. Before the transistor controlled by the first gate voltage applied to the first gate electrode is turned off, the transistor controlled by the second gate voltage applied to the second gate electrode is turned off; before the transistor controlled by the first gate voltage applied to the first gate electrode is turned off, the transistor controlled by the fourth gate voltage applied to the fourth gate electrode is turned on; and before the transistor controlled by the fourth gate voltage applied to the fourth gate electrode is turned on, the transistor controlled by the fifth gate voltage applied to the fifth gate electrode is turned on. . [Brief explanation of the drawing]

[0009] [Figure 1] A schematic diagram of the semiconductor circuit of the first embodiment. [Figure 2] A schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 3] A schematic plan view of the semiconductor device according to the first embodiment. [Figure 4] Timing chart of a semiconductor device according to the first embodiment. [Figure 5] A schematic plan view of the semiconductor device according to the second embodiment. [Figure 6] A schematic cross-sectional view of a part of the semiconductor device of the third embodiment. [Figure 7] Timing chart of a semiconductor device according to the third embodiment. [Modes for carrying out the invention]

[0010] Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and components that have already been described will be omitted from the description as appropriate.

[0011] In this specification, the distribution and absolute value of impurity concentrations in semiconductor regions can be measured, for example, using secondary ion mass spectrometry (SIMS). Furthermore, the relative magnitudes of impurity concentrations in two semiconductor regions can be determined, for example, using scanning capacitance microscopy (SCM). Additionally, the distribution and absolute value of impurity concentrations can be measured, for example, using spreading resistance analysis (SRA). SCM and SRA provide the relative magnitudes and absolute values ​​of carrier concentrations in the semiconductor regions. By assuming an activation rate for impurities, the relative magnitudes, distribution, and absolute values ​​of impurity concentrations between two semiconductor regions can be determined from the measurement results of SCM and SRA.

[0012] (First embodiment) The semiconductor device of the first embodiment comprises a semiconductor layer having a first surface and a second surface facing the first surface, the semiconductor layer including a first trench provided on the side of the first surface, a second trench provided on the side of the first surface, and a third trench provided on the side of the first surface; a first gate electrode provided in the first trench; a second gate electrode provided in the second trench; a third gate electrode provided in the third trench; a fourth gate electrode provided on the side of the second surface; a fifth gate electrode provided on the side of the second surface; a first electrode in contact with the first surface; a second electrode in contact with the second surface; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; a third electrode pad electrically connected to the third gate electrode; a fourth electrode pad electrically connected to the fourth gate electrode; and a fifth electrode pad electrically connected to the fifth gate electrode.

[0013] Furthermore, the semiconductor circuit of the first embodiment includes the semiconductor device and a control circuit that controls the voltage applied to the first electrode pad, the second electrode pad, the third electrode pad, the fourth electrode pad, and the fifth electrode pad.

[0014] The semiconductor device of the first embodiment is an IGBT100 with a double-sided gate structure, having gate electrodes on both the front and back sides of the semiconductor layer. The IGBT100 also includes three independently controlled gate electrodes on the front side of the semiconductor layer, and two independently controlled gate electrodes on the back side of the semiconductor layer. The gate electrodes on the front side of the semiconductor layer have a trench gate structure provided within a trench. The following description will use the case where the first conductivity type is n-type and the second conductivity type is p-type as an example.

[0015] Figure 1 is a schematic diagram of a semiconductor circuit according to the first embodiment. The semiconductor circuit according to the first embodiment is a semiconductor module 1000.

[0016] The semiconductor module 1000 comprises an IGBT 100 and a control circuit 150.

[0017] Figure 1 shows a layout of an IGBT 100. The IGBT 100 comprises a cell region 100a, a termination region 100b, a first front surface gate electrode pad 101 (first electrode pad), a second front surface gate electrode pad 102 (second electrode pad), a third front surface gate electrode pad 103 (third electrode pad), a first back surface gate electrode pad 104 (fourth electrode pad), and a second back surface gate electrode pad 105 (fifth electrode pad).

[0018] The termination region 100b surrounds the cell region 100a. The first front surface gate electrode pad 101, the second front surface gate electrode pad 102, and the third front surface gate electrode pad 103 are located on the front surface side of the IGBT 100. The first back surface gate electrode pad 104 and the second back surface gate electrode pad 105 are located on the back surface side of the IGBT 100.

[0019] Figure 2 is a schematic cross-sectional view of a part of the semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view taken along line AA' of Figure 1.

[0020] The IGBT 100 according to the first embodiment comprises a semiconductor layer 10, an emitter electrode 12 (first electrode), a collector electrode 14 (second electrode), a first front surface gate insulating film 21, a second front surface gate insulating film 22, a third front surface gate insulating film 23, a first back surface gate insulating film 24, a second back surface gate insulating film 25, a main gate electrode 31 (first gate electrode), a control gate electrode 32 (second gate electrode), a pre-gate electrode 33 (third gate electrode), a back surface cell gate electrode 34 (fourth gate electrode), a back surface termination gate electrode 35 (fifth gate electrode), a front surface interlayer insulating layer 40, and a back surface interlayer insulating layer 42.

[0021] The semiconductor layer 10 includes a main gate trench 51 (first trench), a control gate trench 52 (second trench), a pre-gate trench 53 (third trench), an n-type cell drain region 60 (sixth semiconductor region), an n-type termination drain region 62 (seventh semiconductor region), a p-type cell collector region 64 (fourth semiconductor region), a p-type termination collector region 65 (fifth semiconductor region), an n-type buffer region 66, an n-type drift region 68 (first semiconductor region), a p-type base region 70 (second semiconductor region), an n-type emitter region 72 (third semiconductor region), a p-type contact region 74, a p-type boundary region 76 (eighth semiconductor region), and a p-type guard ring region 78.

[0022] The semiconductor layer 10 has a first surface P1 and a second surface P2 that is opposite to the first surface P1. The first surface P1 is the front surface of the semiconductor layer 10, and the second surface P2 is the back surface of the semiconductor layer 10.

[0023] In this specification, a direction parallel to the first surface P1 is referred to as the first direction. A direction parallel to the first surface P1 and perpendicular to the first direction is referred to as the second direction.

[0024] The semiconductor layer 10 includes a cell portion 10a and a termination portion 10b. The cell portion 10a is included in the cell region 100a of the semiconductor layer 10. The termination portion 10b is included in the termination region 100b of the semiconductor layer 10. The termination portion 10b surrounds the cell portion 10a.

[0025] The semiconductor layer 10 is, for example, single-crystal silicon. The thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0026] The emitter electrode 12 is provided on the side of the first surface P1 of the semiconductor layer 10. At least a portion of the emitter electrode 12 is in contact with the first surface P1 of the semiconductor layer 10. The emitter electrode 12 is, for example, a metal. An emitter voltage (Ve) is applied to the emitter electrode 12. The emitter voltage is, for example, 0V.

[0027] The collector electrode 14 is provided on the side of the second surface P2 of the semiconductor layer 10. At least a portion of the collector electrode 14 is in contact with the second surface P2 of the semiconductor layer 10. The collector electrode 14 is, for example, made of metal.

[0028] A collector voltage (Vc) is applied to the collector electrode 14. The collector voltage is, for example, between 200V and 6500V.

[0029] The main gate trench 51 is provided in the cell region 100a. The main gate trench 51 is provided on the first surface P1 side of the cell portion 10a. The main gate trench 51 is a groove provided in the cell portion 10a. The main gate trench 51 extends in a first direction. The main gate trench 51 is repeatedly provided in a second direction.

[0030] The control gate trench 52 is provided in the cell region 100a. The control gate trench 52 is provided on the first surface P1 side of the cell portion 10a. The control gate trench 52 is a groove provided in the cell portion 10a. The control gate trench 52 extends in a first direction. The control gate trench 52 is repeatedly provided in a second direction.

[0031] The pregate trench 53 is provided in the cell region 100a. The pregate trench 53 is provided on the first surface P1 side of the cell portion 10a. The pregate trench 53 is a groove provided in the cell portion 10a. The pregate trench 53 extends in a first direction. The pregate trench 53 is repeatedly provided in a second direction.

[0032] The main gate electrode 31 is provided in the cell region 100a. The main gate electrode 31 is provided on the side of the first surface P1 of the cell portion 10a. At least a portion of the main gate electrode 31 is provided in the main gate trench 51. The first surface gate electrode pad 101 is electrically connected to the main gate electrode 31 using wiring (not shown).

[0033] The main gate electrode 31 is, for example, polycrystalline silicon containing n-type or p-type impurities. A first gate voltage (Vg1) is applied to the main gate electrode 31. The first gate voltage (Vg1) is a voltage referenced to the emitter voltage (Ve).

[0034] Hereinafter, the transistor controlled by the first gate voltage (Vg1) applied to the main gate electrode 31 will be referred to as the main gate transistor.

[0035] The first surface gate insulating film 21 is provided between the main gate electrode 31 and the cell portion 10a. At least a portion of the first surface gate insulating film 21 is provided inside the main gate trench 51. The first surface gate insulating film 21 is, for example, a silicon oxide film.

[0036] The control gate electrode 32 is provided in the cell region 100a. The control gate electrode 32 is provided on the side of the first surface P1 of the cell portion 10a. At least a portion of the control gate electrode 32 is provided in the control gate trench 52. The second surface gate electrode pad 102 is electrically connected to the control gate electrode 32 using wiring (not shown).

[0037] The control gate electrode 32 is, for example, polycrystalline silicon containing n-type or p-type impurities. A second gate voltage (Vg2) is applied to the control gate electrode 32. The second gate voltage (Vg2) is a voltage referenced to the emitter voltage (Ve).

[0038] Hereinafter, the transistor controlled by the second gate voltage (Vg2) applied to the control gate electrode 32 will be referred to as the control gate transistor.

[0039] The second surface gate insulating film 22 is provided between the control gate electrode 32 and the cell portion 10a. At least a portion of the second surface gate insulating film 22 is provided in the control gate trench 52. The second surface gate insulating film 22 is, for example, a silicon oxide film.

[0040] The pregate electrode 33 is provided in the cell region 100a. The pregate electrode 33 is provided on the side of the first surface P1 of the cell portion 10a. At least a portion of the pregate electrode 33 is provided in the pregate trench 53. The third surface gate electrode pad 103 is electrically connected to the pregate electrode 33 using wiring (not shown).

[0041] The pre-gate electrode 33 is, for example, polycrystalline silicon containing n-type or p-type impurities. A third gate voltage (Vg3) is applied to the pre-gate electrode 33. The third gate voltage (Vg3) is a voltage referenced to the emitter voltage (Ve).

[0042] Hereinafter, a transistor controlled by a third gate voltage (Vg3) applied to the pregate electrode 33 will be referred to as a pregate transistor.

[0043] The third surface gate insulating film 23 is provided between the pregate electrode 33 and the cell portion 10a. At least a portion of the third surface gate insulating film 23 is provided in the pregate trench 53. The third surface gate insulating film 23 is, for example, a silicon oxide film.

[0044] The back cell gate electrode 34 is provided in the cell region 100a. The back cell gate electrode 34 is provided on the side of the second surface P2 of the cell portion 10a. The first back gate electrode pad 104 is electrically connected to the back cell gate electrode 34 using wiring (not shown).

[0045] The back cell gate electrode 34 is, for example, polycrystalline silicon containing n-type or p-type impurities. A fourth gate voltage (Vg4) is applied to the back cell gate electrode 34. The fourth gate voltage (Vg4) is a voltage referenced to the collector voltage (Vc).

[0046] Hereinafter, the transistor controlled by the fourth gate voltage (Vg4) applied to the back cell gate electrode 34 will be referred to as a back cell transistor.

[0047] The first back-side gate insulating film 24 is provided between the back-side cell gate electrode 34 and the cell portion 10a. The first back-side gate insulating film 24 is, for example, a silicon oxide film.

[0048] The back-side termination gate electrode 35 is provided in the termination region 100b. The back-side termination gate electrode 35 is provided on the second surface P2 side of the termination portion 10b. The second back-side gate electrode pad 105 is electrically connected to the back-side termination gate electrode 35 using wiring (not shown).

[0049] The back-side-terminated gate electrode 35 is, for example, polycrystalline silicon containing n-type or p-type impurities. A fifth gate voltage (Vg5) is applied to the back-side-terminated gate electrode 35. The fifth gate voltage (Vg5) is a voltage referenced to the collector voltage (Vc).

[0050] Hereinafter, a transistor controlled by a fifth gate voltage (Vg5) applied to the back-terminal gate electrode 35 will be referred to as a back-terminal transistor.

[0051] The second back-side gate insulating film 25 is provided between the back-side terminal gate electrode 35 and the terminal portion 10b. The second back-side gate insulating film 25 is, for example, a silicon oxide film.

[0052] Figure 3 is a schematic plan view of the semiconductor device according to the first embodiment. Figure 3(a) is a plan view of the front side of the IGBT 100, that is, the first surface P1 side of the semiconductor layer 10. Figure 3(b) is a plan view of the back side of the IGBT 100, that is, the second surface P2 side of the semiconductor layer 10.

[0053] Figure 3(a) schematically shows the arrangement of the main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33. Figure 3(b) schematically shows the arrangement of the back cell gate electrode 34 and the back terminal gate electrode 35.

[0054] As shown in Figure 3(a), the main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33 are provided in the cell region 100a. The main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33 extend in a first direction.

[0055] As shown in Figure 3(b), the back cell gate electrode 34 is provided in the cell region 100a. The back terminal gate electrode 35 is provided in the terminal region 100b. The back cell gate electrode 34 and the back terminal gate electrode 35 extend in the first direction.

[0056] The surface interlayer insulating layer 40 is provided on the side of the first surface P1 of the semiconductor layer 10. The surface interlayer insulating layer 40 is provided between a part of the semiconductor layer 10 and the emitter electrode 12. The surface interlayer insulating layer 40 electrically isolates the part of the semiconductor layer 10 from the emitter electrode 12. The surface interlayer insulating layer 40 electrically isolates the main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33 from the emitter electrode 12.

[0057] The interlayer insulating layer 40 is, for example, silicon oxide.

[0058] The back interlayer insulating layer 42 is provided on the second surface P2 side of the semiconductor layer 10. The back interlayer insulating layer 42 is provided between a part of the semiconductor layer 10 and the collector electrode 14. The back interlayer insulating layer 42 electrically isolates a part of the semiconductor layer 10 from the collector electrode 14. The back interlayer insulating layer 42 electrically isolates the back cell gate electrode 34 and the back termination gate electrode 35 from the collector electrode 14.

[0059] The back surface interlayer insulating layer 42 is, for example, silicon oxide.

[0060] The p-shaped cell collector region 64 is provided in the cell portion 10a. The cell collector region 64 is provided in a part between the drift region 68 and the second surface P2. A part of the cell collector region 64 is in contact with the second surface P2.

[0061] A portion of the cell collector region 64 faces the back cell gate electrode 34, with the first back gate insulating film 24 in between. The cell collector region 64 extends in the first direction on the second surface P2. A channel of the back cell transistor, controlled by the back cell gate electrode 34, is formed in the cell collector region 64 facing the back cell gate electrode 34.

[0062] The cell collector region 64 is electrically connected to the collector electrode 14. A portion of the cell collector region 64 is in contact with the collector electrode 14.

[0063] The p-type terminal collector region 65 is provided at the terminal portion 10b. The terminal collector region 65 is provided in a part between the drift region 68 and the second surface P2. A part of the terminal collector region 65 is in contact with the second surface P2.

[0064] A portion of the termination collector region 65 faces the back-side termination gate electrode 35, with the second back-side gate insulating film 25 in between. The termination collector region 65 extends in the first direction on the second surface P2. A channel of a back-side terminated transistor, controlled by the back-side termination gate electrode 35, is formed in the termination collector region 65 facing the back-side termination gate electrode 35.

[0065] The terminating collector region 65 is electrically connected to the collector electrode 14. A portion of the terminating collector region 65 is in contact with the collector electrode 14.

[0066] The n-shaped cell drain region 60 is provided in the cell portion 10a. The cell drain region 60 is provided in a part between the cell collector region 64 and the second surface P2. A part of the cell collector region 64 faces the back cell gate electrode 34 with the first back gate insulating film 24 in between.

[0067] A portion of the cell drain region 60 is in contact with the collector electrode 14. The cell drain region 60 extends in a first direction. The cell drain region 60 functions as the drain of the back-side cell transistor.

[0068] The concentration of n-type impurities in the cell drain region 60 is higher than the concentration of n-type impurities in the drift region 68.

[0069] The n-type termination drain region 62 is provided at the termination portion 10b. The termination drain region 62 is provided in a part between the termination collector region 65 and the second surface P2. A part of the termination drain region 62 faces the back-surface termination gate electrode 35 with the second back-surface gate insulating film 25 in between.

[0070] A portion of the terminating drain region 62 is in contact with the collector electrode 14. The terminating drain region 62 extends in a first direction. The terminating drain region 62 functions as the drain of a back-surface terminated transistor.

[0071] The n-type impurity concentration in the terminal drain region 62 is higher than the n-type impurity concentration in the drift region 68.

[0072] An n-shaped drift region 68 is provided between the cell collector region 64 and the first surface P1. A drift region 68 is provided between the terminal collector region 65 and the first surface P1. A drift region 68 is provided between the cell collector region 64 and the base region 70.

[0073] The drift region 68 is the path for the on-current when the IGBT 100 is ON. The drift region 68 is depleted when the IGBT 100 is OFF, and has the function of maintaining the voltage withstand capability of the IGBT 100.

[0074] The n-type buffer region 66 is provided between the drift region 68 and the cell collector region 64. The buffer region 66 is provided between the drift region 68 and the termination collector region 65.

[0075] A portion of the buffer region 66 is in contact with the second surface P2. A portion of the buffer region 66 faces the back cell gate electrode 34 with the first back gate insulating film 24 in between. A portion of the buffer region 66 faces the back terminal gate electrode 35 with the second back gate insulating film 25 in between.

[0076] The concentration of n-type impurities in buffer region 66 is higher than the concentration of n-type impurities in drift region 68.

[0077] The buffer region 66 has lower resistance than the drift region 68. By providing the buffer region 66, when the back cell transistor is turned on, the discharge of electrons from the drift region 68 to the collector electrode 14 via the back cell transistor is promoted. By providing the buffer region 66, when the back termination transistor is turned on, the discharge of electrons from the drift region 68 to the collector electrode 14 via the back termination transistor is promoted.

[0078] Furthermore, the buffer region 66 also has the function of suppressing the expansion of the depletion layer when the IGBT 100 is off. It is also possible to configure the system without the buffer region 66.

[0079] The p-shaped base region 70 is provided in the cell region 100a. The base region 70 is provided in the cell portion 10a. The base region 70 is provided between the drift region 68 and the first surface P1.

[0080] A portion of the base region 70 faces the main gate electrode 31, with the first surface gate insulating film 21 in between. In the base region 70 facing the main gate electrode 31, a channel of the main gate transistor, controlled by the main gate electrode 31, is formed.

[0081] A portion of the base region 70 faces the control gate electrode 32, with the second surface gate insulating film 22 in between. In the base region 70 facing the control gate electrode 32, a channel for the control gate transistor, controlled by the control gate electrode 32, is formed.

[0082] A portion of the base region 70 faces the pregate electrode 33, with the third surface gate insulating film 23 in between. In the base region 70 facing the pregate electrode 33, a channel of the pregate transistor, controlled by the pregate electrode 33, is formed.

[0083] The n-type emitter region 72 is provided in the cell region 100a. The emitter region 72 is provided in the cell portion 10a. The emitter region 72 is provided between the base region 70 and the first surface P1. The emitter region 72 extends in a first direction on the first surface P1.

[0084] A portion of the emitter region 72 faces the main gate electrode 31 with the first surface gate insulating film 21 in between. A portion of the emitter region 72 is in contact with the main gate trench 51. A portion of the emitter region 72 is in contact with the first surface gate insulating film 21.

[0085] A portion of the emitter region 72 faces the control gate electrode 32 with the second surface gate insulating film 22 in between. A portion of the emitter region 72 is in contact with the control gate trench 52. A portion of the emitter region 72 is in contact with the second surface gate insulating film 22.

[0086] A portion of the emitter region 72 faces the pregate electrode 33 with the third surface gate insulating film 23 in between. A portion of the emitter region 72 is in contact with the pregate trench 53. A portion of the emitter region 72 is in contact with the third surface gate insulating film 23.

[0087] The emitter region 72 is electrically connected to the emitter electrode 12. A portion of the emitter region 72 is in contact with the emitter electrode 12.

[0088] The n-type impurity concentration in the emitter region 72 is higher than that in the drift region 68. The emitter region 72 serves as an electron source when the IGBT 100 is in the ON state.

[0089] The p-shaped contact region 74 is provided in the cell region 100a. The contact region 74 is provided in the cell portion 10a. The contact region 74 is provided between the base region 70 and the first surface P1. The contact region 74 extends in a first direction on the first surface P1.

[0090] The contact area 74 is electrically connected to the emitter electrode 12. The contact area 74 is in contact with the emitter electrode 12.

[0091] The p-type impurity concentration in the contact region 74 is higher than that in the base region 70.

[0092] The p-shaped boundary region 76 is provided in the terminal region 100b. The boundary region 76 is provided in the terminal portion 10b. The boundary region 76 is provided between the drift region 68 and the first surface P1. The boundary region 76 surrounds the cell portion 10a.

[0093] A p-shaped guard ring region 78 is provided in the terminal region 100b. A guard ring region 78 is provided in the terminal portion 10b. A guard ring region 78 is provided between the drift region 68 and the first surface P1. A guard ring region 78 surrounds the cell portion 10a. For example, multiple guard ring regions 78 may be provided.

[0094] By providing the boundary region 76 and the guard ring region 78, the electric field strength at the end of the cell region 100a is reduced, and the decrease in withstand voltage when the IGBT 100 is in the off state is suppressed.

[0095] The control circuit 150 controls the IGBT 100. The control circuit 150 is, for example, a gate driver circuit. The gate driver circuit independently controls the magnitude and timing of the voltage applied to the first surface gate electrode pad 101, the second surface gate electrode pad 102, the third surface gate electrode pad 103, the first back surface gate electrode pad 104, and the second back surface gate electrode pad 105.

[0096] The control circuit 150 independently controls the first gate voltage (Vg1) applied to the main gate electrode 31, the second gate voltage (Vg2) applied to the control gate electrode 32, the third gate voltage (Vg3) applied to the pre-gate electrode 33, the fourth gate voltage (Vg4) applied to the back cell gate electrode 34, and the fifth gate voltage (Vg5) applied to the back terminal gate electrode 35.

[0097] Next, we will explain the operation of the IGBT100.

[0098] Figure 4 is a timing chart of the semiconductor device according to the first embodiment. Figure 4 shows the timing of the changes in the first gate voltage (Vg1), second gate voltage (Vg2), third gate voltage (Vg3), fourth gate voltage (Vg4), and fifth gate voltage (Vg5).

[0099] The first gate voltage (Vg1) is the gate voltage applied to the main gate transistor, which is controlled by the main gate electrode 31. The second gate voltage (Vg2) is the gate voltage applied to the control gate transistor, which is controlled by the control gate electrode 32. The third gate voltage (Vg3) is the gate voltage applied to the pre-gate transistor, which is controlled by the pre-gate electrode 33. The fourth gate voltage (Vg4) is the gate voltage applied to the back-side cell transistor, which is controlled by the back-side cell gate electrode 34. The fifth gate voltage (Vg5) is the gate voltage applied to the back-side terminated transistor, which is controlled by the back-side termination gate electrode 35.

[0100] When the IGBT100 is off, an emitter voltage (Ve) is applied to the emitter electrode 12. For example, at time t0, an emitter voltage (Ve) is applied to the emitter electrode 12. The emitter voltage (Ve) is, for example, 0V.

[0101] When the IGBT100 is in the off state, a collector voltage (Vc) is applied to the collector electrode 14. The collector voltage (Vc) is, for example, between 200V and 6500V. The collector-emitter voltage (Vce) applied between the collector electrode 14 and the emitter electrode 12 is, for example, between 200V and 6500V.

[0102] The first gate voltage (Vg1), the second gate voltage (Vg2), and the third gate voltage (Vg3) are voltages referenced to the emitter voltage (Ve). The fourth gate voltage (Vg4) and the fifth gate voltage (Vg5) are voltages referenced to the collector voltage (Vc).

[0103] First, we will explain the timing of the change in the first gate voltage (Vg1) applied to the main gate transistor.

[0104] For example, at time t0, the first turn-off voltage (Voff1) is applied as the first gate voltage (Vg1). The first turn-off voltage (Voff1) is a voltage below the threshold voltage at which the main gate transistor does not turn on.

[0105] The first turn-off voltage (Voff1) is, for example, 0V or a negative voltage. Figure 4 shows an example where the first turn-off voltage (Voff1) is -15V.

[0106] At time t1, the first turn-on voltage (Von1) is applied as the first gate voltage (Vg1). The first turn-on voltage (Von1) is a positive voltage that exceeds the threshold voltage of the main gate transistor. Figure 4 shows an example where the first turn-on voltage (Von1) is 15V.

[0107] When the first turn-on voltage (Von1) is applied to the main gate transistor, IGBT100 turns on. IGBT100 is turned on at time t1.

[0108] By applying a first turn-on voltage (Von1) to the main gate transistor, an n-type inversion layer is formed near the interface between the p-type base region 70 and the first surface gate insulating film 21. The formation of the n-type inversion layer causes electrons from the n-type emitter region 72 to be injected through the n-type inversion layer into the n-type drift region 68. These electrons inject into the n-type drift region 68 forward-bias the pn junctions formed between the n-type buffer region 66 and the p-type cell collector region 64, and between the n-type buffer region 66 and the p-type termination collector region 65. The electrons reach the collector electrode 14 and trigger hole injection from the p-type cell collector region 64 and the p-type termination collector region 65. Consequently, the IGBT 100 is turned on.

[0109] At time t4, the first turn-off voltage (Voff1) is applied as the first gate voltage (Vg1). The application of the first turn-off voltage (Voff1) to the main gate transistor turns IGBT100 off. Between time t1 and time t4, IGBT100 is in the on state.

[0110] Next, we will explain the timing of the change in the second gate voltage (Vg2) applied to the control gate transistor.

[0111] For example, at time t0, a second turn-off voltage (Voff2) is applied as the second gate voltage (Vg2). The second turn-off voltage (Voff2) is a voltage below the threshold voltage at which the control gate transistor does not turn on.

[0112] The second turn-off voltage (Voff2) is, for example, a negative voltage. Figure 4 illustrates the case where the second turn-off voltage (Voff2) is -15V.

[0113] At time t1, a second turn-on voltage (Von2) is applied as the second gate voltage (Vg2). The second turn-on voltage (Von2) is a positive voltage exceeding the threshold voltage of the control gate transistor. Figure 4 illustrates the case where the second turn-on voltage (Von2) is 15V.

[0114] By applying a second turn-on voltage (Von2) to the control gate transistor, an n-type inversion layer is formed near the interface between the p-type base region 70 and the second surface gate insulating film 22. With the formation of the n-type inversion layer, electrons are injected from the n-type emitter region 72 through the n-type inversion layer into the n-type drift region 68.

[0115] At time t3, prior to time t4, a second turn-off voltage (Voff2) is applied as the second gate voltage (Vg2). The application of the second turn-off voltage (Voff2) to the control gate transistor blocks the injection of electrons into the drift region 68 via the control gate transistor. Furthermore, by making the second gate voltage (Vg2) a negative voltage, a p-type storage layer is formed in the p-type base region 70 near the control gate trench 52. The formation of the p-type storage layer promotes the discharge of holes to the emitter electrode 12. Consequently, the carriers in the drift region 68 are reduced.

[0116] Next, we will explain the timing of the change in the third gate voltage (Vg3) applied to the pregate transistor.

[0117] For example, at time t0, a third turn-off voltage (Voff3) is applied as the third gate voltage (Vg3). The third turn-off voltage (Voff3) is a voltage below the threshold voltage at which the pre-gate transistor does not turn on.

[0118] The third turn-off voltage (Voff3) is, for example, 0V or a negative voltage. Figure 4 illustrates the case where the third turn-off voltage (Voff3) is 0V.

[0119] At time t1, a third turn-on voltage (Von3) is applied as the third gate voltage (Vg3). The third turn-on voltage (Von3) is a positive voltage exceeding the threshold voltage of the pre-gate transistor. Figure 4 illustrates the case where the third turn-on voltage (Von3) is 15V.

[0120] By applying a third turn-on voltage (Von3) to the pregate transistor, the pregate transistor turns on. By applying a third turn-on voltage (Von3) to the pregate transistor, an n-type inversion layer is formed near the interface between the p-type base region 70 and the third surface gate insulating film 23. With the formation of the n-type inversion layer, electrons are injected from the n-type emitter region 72 through the n-type inversion layer into the n-type drift region 68.

[0121] At time t2, prior to time t3, a third turn-off voltage (Voff3) is applied as a third gate voltage (Vg3). The application of the third turn-off voltage (Voff3) to the pregate transistor causes it to turn off. This off state blocks the injection of electrons into the drift region 68 via the pregate transistor. Therefore, the number of electrons injected into the drift region 68 decreases.

[0122] For example, a negative voltage may be applied as the third gate voltage (Vg3) at time t3. By applying a negative voltage as the third gate voltage (Vg3), a p-type storage layer is formed in the p-type base region 70 near the pre-gate trench 53. The formation of the p-type storage layer promotes the discharge of holes to the emitter electrode 12. Consequently, the carriers in the drift region 68 are reduced.

[0123] Next, we will explain the timing of the change in the fourth gate voltage (Vg4) applied to the back-side cell transistor.

[0124] For example, at time t0, the fourth turn-off voltage (Voff4) is applied as the fourth gate voltage (Vg4). The fourth turn-off voltage (Voff4) is a voltage below the threshold voltage at which the back-side cell transistor does not turn on.

[0125] The fourth turn-off voltage (Voff4) is, for example, 0V or a negative voltage. Figure 4 shows an example where the fourth turn-off voltage (Voff4) is 0V.

[0126] At time ty, the fourth turn-on voltage (Von4) is applied as the fourth gate voltage (Vg4). The fourth turn-on voltage (Von4) is a positive voltage that exceeds the threshold voltage of the back-side cell transistor. Figure 4 shows an example where the fourth turn-on voltage (Von4) is 15V.

[0127] By applying a fourth turn-on voltage (Von4) to the back-side cell transistor, an n-type inversion layer is formed near the interface between the p-type cell collector region 64 and the first back-side gate insulating film 24.

[0128] When an n-type inversion layer is formed near the interface between the p-type cell collector region 64 and the first back-side gate insulating film 24, a path is formed through which electrons are discharged from the n-type buffer region 66 of the cell portion 10a through the n-type inversion layer and the n-type cell drain region 60 to the collector electrode 14. In other words, a short circuit occurs between the n-type buffer region 66 of the cell portion 10a and the collector electrode 14, a so-called anode short.

[0129] The occurrence of an anode short prevents electrons from reaching the collector electrode 14 from the n-type buffer region 66 of the cell portion 10a through the p-type cell collector region 64. As a result, the injection of holes from the p-type cell collector region 64 into the drift region 68 of the cell portion 10a is suppressed.

[0130] Subsequently, at time t5, a fourth turn-off voltage (Voff4) is applied as the fourth gate voltage (Vg4) to turn off the back-side cell transistor.

[0131] Next, we will explain the timing of the change in the fifth gate voltage (Vg5) applied to the back-surface terminated transistor.

[0132] For example, at time t0, a fifth turn-off voltage (Voff5) is applied as the fifth gate voltage (Vg5). The fifth turn-off voltage (Voff5) is a voltage below the threshold voltage at which the back-surface terminated transistor does not turn on.

[0133] The fifth turn-off voltage (Voff5) is, for example, 0V or a negative voltage. Figure 4 illustrates the case where the fifth turn-off voltage (Voff5) is 0V.

[0134] At time tx, preceding time ty, a fifth turn-on voltage (Von5) is applied as a fifth gate voltage (Vg5). The fifth turn-on voltage (Von5) is a positive voltage exceeding the threshold voltage of the back-surface terminated transistor. Figure 4 illustrates the case where the fifth turn-on voltage (Von5) is 15V.

[0135] By applying a fifth turn-on voltage (Von5) to the back-surface terminated transistor, an n-type inversion layer is formed near the interface between the p-type terminated collector region 65 and the second back-surface gate insulating film 25.

[0136] The formation of an n-type inversion layer near the interface between the p-type terminal collector region 65 and the second back-side gate insulating film 25 creates a path for electrons to be discharged from the n-type buffer region 66 of the terminal portion 10b through the n-type inversion layer and the n-type terminal drain region 62 to the collector electrode 14. In other words, a short circuit occurs between the buffer region 66 of the n-type terminal portion 10b and the collector electrode 14, a so-called anode short.

[0137] The occurrence of an anode short prevents electrons from reaching the collector electrode 14 from the n-type buffer region 66 of the termination 10b through the p-type termination collector region 65. As a result, the injection of holes from the p-type termination collector region 65 into the drift region 68 of the termination 10b is suppressed.

[0138] Note that time tx can be before or after time t3. Also, time tx can be before or after time t4.

[0139] Subsequently, at time t5, a fifth turn-off voltage (Voff5) is applied as the fifth gate voltage (Vg5) to turn off the back-terminal transistor.

[0140] The control circuit 150 controls the magnitude and timing of the first gate voltage (Vg1) applied to the first surface gate electrode pad 101, the second gate voltage (Vg2) applied to the second surface gate electrode pad 102, the third gate voltage (Vg3) applied to the third surface gate electrode pad 103, the fourth gate voltage (Vg4) applied to the first back surface gate electrode pad 104, and the fifth gate voltage (Vg5) applied to the second back surface gate electrode pad 105 to realize the operation of the IGBT 100.

[0141] For example, the control circuit 150 applies a first turn-on voltage (Von1) to the first front gate electrode pad 101 at time t1, a second turn-on voltage (Von2) to the second front gate electrode pad 102 at time t1, and a third turn-on voltage (Von3) to the third front gate electrode pad 103 at time t1. Then, at time t2, a predetermined time after time t1, a third turn-off voltage (Voff3) is applied to the third front gate electrode pad 103. Then, at time tx, a predetermined time after time t2, a fifth turn-on voltage (Von5) is applied to the second back gate electrode pad 105. Then, at time ty, a predetermined time after time tx, a fourth turn-on voltage (Von4) is applied to the first back gate electrode pad 104.

[0142] For example, the control circuit 150 applies a third turn-on voltage (Von3) to the third surface gate electrode pad 103 at time t1, and then applies a first turn-off voltage (Voff1) to the first surface gate electrode pad 101 at time t4, after a predetermined time has elapsed. Then, at time tx, prior to time t4, it applies a fifth turn-on voltage (Von5) to the second back surface gate electrode pad 105.

[0143] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0144] The IGBT 100 of the first embodiment includes a control gate transistor on the surface side of the semiconductor layer 10 that can be controlled independently of the main gate transistor. By applying a negative voltage to the gate electrode of the control gate transistor at time t3, before time t4 when the IGBT 100 turns off, and turning it off, the discharge of holes to the emitter electrode 12 is promoted. Therefore, compared to the case without a control gate transistor, the amount of carriers that need to be discharged during the turn-off operation of the IGBT 100 can be reduced. Thus, the turn-off loss of the IGBT 100 can be reduced.

[0145] For example, by applying a negative voltage to the gate electrode of the pre-gate transistor at time t3, the amount of carriers that need to be discharged during turn-off operation can be further reduced. Therefore, the turn-off loss of IGBT100 can be further reduced.

[0146] Furthermore, the IGBT 100 of the first embodiment includes a pretransistor on the surface side of the semiconductor layer 10 that can be controlled independently of the main gate transistor and the control gate transistor. By turning on the pretransistor at time t1 when the IGBT 100 turns on, the amount of electrons injected into the drift region 68 increases compared to when the pretransistor is not provided. Therefore, the turn-on time of the IGBT 100 is shortened compared to when the pretransistor is not provided. Thus, the turn-on loss of the IGBT 100 can be reduced.

[0147] Then, at time t2, which is before time t4 when IGBT100 turns off, the pretransistor is turned off. By turning off the pretransistor, the saturation current of IGBT100 is reduced. Therefore, for example, if a load short circuit occurs and a large current flows through IGBT100, the destruction of IGBT100 can be suppressed.

[0148] Furthermore, the IGBT 100 of the first embodiment is equipped with a back-side cell transistor on the back side of the semiconductor layer 10. By turning on the back-side cell transistor during the turn-off operation of the IGBT 100, the injection of holes into the drift region 68 of the cell portion 10a is suppressed. By suppressing the injection of holes into the drift region 68, the turn-off loss is reduced compared to the case where a back-side cell transistor is not provided. Therefore, the power consumption of the IGBT 100 can be reduced.

[0149] Furthermore, in the first embodiment, the IGBT 100 has a termination region 100b surrounding the cell region 100a. The termination region 100b is provided with a boundary region 76 and a guard ring region 78. By providing the boundary region 76 and the guard ring region 78, the electric field strength at the end of the cell region 100a is reduced, and the decrease in withstand voltage when the IGBT 100 is in the off state is suppressed.

[0150] When IGBT100 is ON, an ON current flows between the emitter electrode 12 and the collector electrode 14 of the termination region 100b. Therefore, when IGBT100 is ON, carriers accumulate in the drift region 68 of the termination portion 10b. In other words, when IGBT100 is ON, carriers spread to the termination region 100b where no transistors are present on the surface.

[0151] During the turn-off operation of the IGBT 100, it is necessary to discharge the carriers accumulated in the drift region 68 of the termination portion 10b. However, there is no carrier discharge path on the surface side of the termination region 100b. Therefore, the carriers are discharged concentrated at the edge of the cell region 100a. Consequently, current concentration occurs at the edge of the cell region 100a. Therefore, there is a risk of IGBT 100 being destroyed due to current concentration.

[0152] The IGBT 100 of the first embodiment includes a back-side termination transistor on the back side of the semiconductor layer 10 in the termination region 100b, which can be controlled independently of the back-side cell transistor. The back-side termination transistor is turned on at time tx, which is before time ty, when the back-side cell transistor is turned on. Turning on the back-side termination transistor suppresses the injection of holes into the n-type drift region 68 of the termination portion 10b.

[0153] By turning on the back-side termination transistor before the back-side cell transistor, the carriers accumulated in the drift region 68 of the termination portion 10b can be selectively reduced. Therefore, current concentration at the edge of the cell region 100a during the turn-off operation of the IGBT 100 can be suppressed. Thus, the destruction of the IGBT 100 due to current concentration can be suppressed.

[0154] From the viewpoint of suppressing the destruction of the IGBT 100 due to current concentration, it is preferable to turn on the back-side terminated transistor before the turn-off operation of the IGBT 100. In other words, it is preferable to turn on the back-side terminated transistor before the time t4 when the IGBT 100 turns off. In other words, it is preferable that time tx is before time t4. In other words, it is preferable to apply a fifth turn-on voltage (Von5) to the second back-side gate electrode pad 105 before applying a first turn-off voltage (Voff1) to the first front-side gate electrode pad 101.

[0155] As described above, according to the first embodiment, a semiconductor device and semiconductor circuit can be realized in which turn-off losses are reduced and breakdown due to current concentration is suppressed.

[0156] (Second embodiment) The semiconductor device and semiconductor circuit of the second embodiment differ from the semiconductor device and semiconductor circuit of the first embodiment in that the first gate electrode extends in a first direction parallel to the first plane, the fourth gate electrode extends in a second direction parallel to the first plane and perpendicular to the first direction, and the fifth gate electrode extends in a direction perpendicular to the fourth gate electrode. Some descriptions that overlap with the first embodiment may be omitted below.

[0157] The semiconductor device of the second embodiment is an IGBT200 with a double-sided gate structure, similar to the first embodiment, having gate electrodes on both the front and back sides of the semiconductor layer. Furthermore, the IGBT200 includes three independently controlled gate electrodes on the front side of the semiconductor layer, and two independently controlled gate electrodes on the back side of the semiconductor layer.

[0158] Figure 5 is a schematic plan view of a semiconductor device according to the second embodiment. Figure 5(a) is a plan view of the front side of the IGBT200, that is, the first surface P1 side of the semiconductor layer 10. Figure 5(b) is a plan view of the back side of the IGBT200, that is, the second surface P2 side of the semiconductor layer 10.

[0159] Figure 5(a) schematically shows the arrangement of the main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33. Figure 5(b) schematically shows the arrangement of the back cell gate electrode 34 and the back terminal gate electrode 35.

[0160] The IGBT200 has a cell region 100a, a terminal region 100b, a first surface gate electrode pad 101 (first electrode pad), a second surface gate electrode pad 102 (second electrode pad), a third surface gate electrode pad 103 (third electrode pad), a first back surface gate electrode pad 104 (fourth electrode pad), and a second back surface gate electrode pad 105 (fifth electrode pad).

[0161] The termination region 100b surrounds the cell region 100a. The first surface gate electrode pad 101, the second surface gate electrode pad 102, and the third surface gate electrode pad 103 are located on the surface side of the IGBT 200. The first back surface gate electrode pad 104 and the second back surface gate electrode pad 105 are located on the back side of the IGBT 200.

[0162] As shown in Figure 5(a), the main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33 are provided in the cell region 100a. The cell region 100a extends in a first direction.

[0163] As shown in Figure 5(b), the back cell gate electrode 34 is provided in the cell region 100a. The back cell gate electrode 34 extends in a second direction perpendicular to the first direction.

[0164] Furthermore, the back-side terminal gate electrode 35 is provided in the terminal region 100b. The back-side terminal gate electrode 35 extends in a first direction perpendicular to the second direction. The back-side terminal gate electrode 35 extends in a direction perpendicular to the back-side cell gate electrode 34.

[0165] The back cell gate electrode 34 extends in a direction perpendicular to the main gate electrode 31, control gate electrode 32, and pre-gate electrode 33, which equalizes the flow of the on-current in the IGBT 200. Therefore, localized on-current concentration is less likely to occur. Consequently, failure of the IGBT 200 due to current concentration is suppressed.

[0166] As described above, according to the second embodiment, a semiconductor device and semiconductor circuit can be realized in which turn-off losses are reduced and breakdown due to current concentration is suppressed.

[0167] (Third embodiment) The semiconductor device and semiconductor circuit of the third embodiment differ from the semiconductor device and semiconductor circuit of the first embodiment in that the third semiconductor region and the second trench are spaced apart. Some descriptions that overlap with the first embodiment may be omitted below.

[0168] The semiconductor device of the third embodiment is an IGBT300 with a double-sided gate structure, similar to the first embodiment, having gate electrodes on both the front and back sides of the semiconductor layer. Furthermore, the IGBT300 includes three independently controlled gate electrodes on the front side of the semiconductor layer, and two independently controlled gate electrodes on the back side of the semiconductor layer.

[0169] Figure 6 is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment. Figure 6 corresponds to Figure 2 of the first embodiment.

[0170] The IGBT300 of the third embodiment comprises a semiconductor layer 10, an emitter electrode 12 (first electrode), a collector electrode 14 (second electrode), a first surface gate insulating film 21, a second surface gate insulating film 22, a third surface gate insulating film 23, a first back surface gate insulating film 24, a second back surface gate insulating film 25, a main gate electrode 31 (first gate electrode), a control gate electrode 32 (second gate electrode), a pre-gate electrode 33 (third gate electrode), a back surface cell gate electrode 34 (fourth gate electrode), a back surface termination gate electrode 35 (fifth gate electrode), a surface interlayer insulating layer 40, and a back surface interlayer insulating layer 42.

[0171] The semiconductor layer 10 includes a main gate trench 51 (first trench), a control gate trench 52 (second trench), a pre-gate trench 53 (third trench), an n-type cell drain region 60 (sixth semiconductor region), an n-type termination drain region 62 (seventh semiconductor region), a p-type cell collector region 64 (fourth semiconductor region), a p-type termination collector region 65 (fifth semiconductor region), an n-type buffer region 66, an n-type drift region 68 (first semiconductor region), a p-type base region 70 (second semiconductor region), an n-type emitter region 72 (third semiconductor region), a p-type contact region 74, a p-type boundary region 76, and a p-type guard ring region 78.

[0172] The emitter region 72 is spaced apart from the control gate trench 52. The emitter region 72 does not come into contact with the control gate trench 52.

[0173] The emitter region 72 is separated from the second surface gate insulating film 22. The emitter region 72 does not come into contact with the second surface gate insulating film 22.

[0174] Figure 7 is a timing chart of the semiconductor device according to the third embodiment. Figure 7 shows the timing of the changes in the first gate voltage (Vg1), second gate voltage (Vg2), third gate voltage (Vg3), fourth gate voltage (Vg4), and fifth gate voltage (Vg5).

[0175] Figure 7 differs from the timing chart shown in Figure 4 of the first embodiment only in the timing of the change in the second gate voltage (Vg2) applied to the control gate electrode 32. Therefore, only the timing of the second gate voltage (Vg2) will be explained.

[0176] Note that even if the second gate voltage (Vg2) applied to the control gate electrode 32 is changed, transistor operation does not occur because the emitter region 72 does not come into contact with the control gate trench 52. However, for the sake of consistency with the description of the first embodiment, the terms second turn-on voltage (Von2) and second turn-off voltage (Voff2) will be used below for convenience.

[0177] For example, at time t0, a second turn-on voltage (Von2) is applied as the second gate voltage (Vg2). The second turn-on voltage (Von2) is a voltage higher than the voltage at which a p-type storage layer is formed in the p-type base region 70 near the control gate trench 52.

[0178] The second turn-on voltage (Von2) is, for example, 0V or a positive voltage. Figure 7 illustrates the case where the second turn-on voltage (Von2) is 0V.

[0179] At time t3, prior to time t4, a second turn-off voltage (Voff2) is applied as the second gate voltage (Vg2). The second turn-off voltage (Voff2) is a voltage below the voltage at which a p-type storage layer is formed in the p-type base region 70 near the control gate trench 52. The second turn-off voltage (Voff2) is a negative voltage. Figure 7 illustrates the case where the second turn-off voltage (Voff2) is -15V.

[0180] When a second turn-off voltage (Voff2) is applied to the control gate transistor, a p-type storage layer is formed in the p-type base region 70 near the control gate trench 52. The formation of the p-type storage layer promotes the discharge of holes to the emitter electrode 12. Consequently, the carriers in the drift region 68 are reduced.

[0181] Subsequently, at time t5, a second turn-on voltage (Von2) is applied as the second gate voltage (Vg2) to extinguish the p-type storage layer.

[0182] In the third embodiment, the IGBT300 does not exhibit transistor operation even when the second gate voltage (Vg2) applied to the control gate electrode 32 is changed. Therefore, the operation of the IGBT300 is more stable compared to the IGBT100.

[0183] Furthermore, the absence of an emitter region 72 in contact with the control gate trench 52 promotes the discharge of holes to the emitter electrode 12 compared to the case where an emitter region 72 is present. Therefore, turn-off losses are further reduced compared to the IGBT 100.

[0184] As described above, according to the third embodiment, semiconductor devices and semiconductor circuits can be realized in which turn-off losses are reduced and breakdown due to current concentration is suppressed.

[0185] In the first to third embodiments, the case where the semiconductor layer is single-crystal silicon was described as an example, but the semiconductor layer is not limited to single-crystal silicon. For example, it may be other single-crystal semiconductors such as single-crystal silicon carbide.

[0186] In the first to third embodiments, the case in which the main gate electrode 31, control gate electrode 32, pre-gate electrode 33, back cell gate electrode 34, and back end gate electrode 35 are all striped in shape was described as an example. However, the shapes of the main gate electrode 31, control gate electrode 32, pre-gate electrode 33, back cell gate electrode 34, and back end gate electrode 35 are not limited to stripe shapes. For example, any or all of the main gate electrode 31, control gate electrode 32, pre-gate electrode 33, back cell gate electrode 34, and back end gate electrode 35 may be polygonal or other shapes other than stripe shapes.

[0187] In the first to third embodiments, the case in which three types of gate electrodes, a main gate electrode 31, a control gate electrode 32, and a pre-gate electrode 33, are provided on the surface side of the semiconductor layer 10 was described as an example. However, in addition to the above three types of gate electrodes, a dummy gate electrode may also be provided. A dummy gate electrode is, for example, a gate electrode in a trench whose potential is fixed to the potential of the emitter electrode 12.

[0188] In the first to third embodiments, the case where the back-side cell transistor and the back-side termination transistor are planar gate type transistors was described as an example, but either one or both of the back-side cell transistor and the back-side termination transistor may be trench gate type transistors.

[0189] In the first to third embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type was described as an example, but it is also possible to have the first conductivity type be p-type and the second conductivity type be n-type.

[0190] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0191] 10 Semiconductor Layers 10a Cell section 10b Termination section 12. Emitter electrode (first electrode) 14. Collector electrode (second electrode) 31 Main gate electrode (first gate electrode) 32 Control gate electrode (second gate electrode) 33. Pre-gate electrode (third gate electrode) 34. Backside cell gate electrode (fourth gate electrode) 35. Backside terminal gate electrode (5th gate electrode) 51 Main Gate Trench (First Trench) 52 Control Gate Trench (Second Trench) 53 Pregate Trench (Third Trench) 60. Cell drain region (6th semiconductor region) 62 Termination drain region (7th semiconductor region) 64. Cell Collector Region (Fourth Semiconductor Region) 65 Termination collector region (5th semiconductor region) 68. Drift region (first semiconductor region) 70 Base region (second semiconductor region) 72. Emitter region (third semiconductor region) 100 IGBTs (Integrated Head Turn Signals) 101 First surface gate electrode pad (first electrode pad) 102 Second surface gate electrode pad (second electrode pad) 103 Third surface gate electrode pad (third electrode pad) 104 First back gate electrode pad (fourth electrode pad) 105 Second back-side gate electrode pad (fifth electrode pad) 150 Control circuits 200 IGBTs (Integrated Head Turn Signals) 300 IGBTs (Integrated Head Turn Signals) 1000 semiconductor modules (semiconductor circuits) P1 First side P2 Second side

Claims

1. A semiconductor layer having a first surface and a second surface facing the first surface, A first trench provided on the side of the first surface, A second trench provided on the side of the first surface, A semiconductor layer including, A first gate electrode provided in the first trench, A second gate electrode provided in the second trench, A fourth gate electrode provided on the side of the second surface, A fifth gate electrode provided on the side of the second surface, A first electrode in contact with the first surface, The second electrode in contact with the second surface, A first electrode pad electrically connected to the first gate electrode, A second electrode pad electrically connected to the second gate electrode, A fourth electrode pad electrically connected to the fourth gate electrode, The device comprises a fifth electrode pad electrically connected to the fifth gate electrode, Before the transistor controlled by the first gate voltage applied to the first gate electrode is turned off, the transistor controlled by the second gate voltage applied to the second gate electrode is turned off. Before the transistor controlled by the first gate voltage applied to the first gate electrode is turned off, the transistor controlled by the fourth gate voltage applied to the fourth gate electrode is turned on. A semiconductor device that turns on a transistor controlled by a fifth gate voltage applied to a fifth gate electrode at a time prior to turning on a transistor controlled by a fourth gate voltage applied to a fourth gate electrode.

2. The semiconductor layer has a cell portion and an end portion surrounding the cell portion. The first trench and the second trench are provided on the side of the first surface of the cell portion. The fourth gate electrode is provided on the side of the second surface of the cell portion, The semiconductor device according to claim 1, wherein the fifth gate electrode is provided on the side of the second surface of the terminal portion.

3. The semiconductor layer has a cell portion and an end portion surrounding the cell portion, The aforementioned semiconductor layer is A first semiconductor region of the first conductivity type, In the cell portion, a second semiconductor region of a second conductivity type is provided between the first semiconductor region and the first surface, and faces the first gate electrode. A third semiconductor region of a first conductivity type is provided between the second semiconductor region and the first surface of the cell portion, and is in contact with the first electrode and the first trench, A fourth semiconductor region of a second conductivity type is provided between the first semiconductor region and the second surface, facing the fourth gate electrode and in contact with the second electrode, A fifth semiconductor region of second conductivity is provided between the first semiconductor region and the second surface, facing the fifth gate electrode and in contact with the second electrode, A sixth semiconductor region of a first conductivity type is provided between the fourth semiconductor region and the second surface and is in contact with the second electrode, A seventh semiconductor region of a first conductivity type is provided between the fifth semiconductor region and the second surface and is in contact with the second electrode, The semiconductor device according to claim 1, comprising: an eighth semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface of the termination portion.

4. The first trench is provided in the cell portion, The fourth gate electrode is provided on the side of the second surface of the cell portion, The semiconductor device according to claim 3, wherein the fifth gate electrode is provided on the side of the second surface of the terminal portion.

5. The first electrode pad and the second electrode pad are provided on the side of the first surface of the semiconductor layer. The semiconductor device according to any one of claims 1 to 4, wherein the fourth electrode pad and the fifth electrode pad are provided on the side of the second surface of the semiconductor layer.

6. A semiconductor layer having a first surface and a second surface facing the first surface, A first trench provided on the side of the first surface, A second trench provided on the side of the first surface, A semiconductor layer including, A first gate electrode provided in the first trench, A second gate electrode provided in the second trench, A fourth gate electrode provided on the side of the second surface, A fifth gate electrode provided on the side of the second surface, A first electrode in contact with the first surface, The second electrode in contact with the second surface, A first electrode pad electrically connected to the first gate electrode, A second electrode pad electrically connected to the second gate electrode, A fourth electrode pad electrically connected to the fourth gate electrode, A semiconductor device comprising a fifth electrode pad electrically connected to the fifth gate electrode, The system comprises a control circuit for controlling the voltage applied to the first electrode pad, the second electrode pad, the fourth electrode pad, and the fifth electrode pad, The aforementioned control circuit is A first turn-on voltage is applied to the first electrode pad, and after the first turn-on voltage is applied to the first electrode pad, a first turn-off voltage is applied to the first electrode pad. A second turn-on voltage is applied to the second electrode pad, and after the second turn-on voltage has been applied to the second electrode pad, a second turn-off voltage is applied to the second electrode pad before the first turn-off voltage is applied to the first electrode pad. After applying the first turn-on voltage to the first electrode pad, and then applying the second turn-on voltage to the second electrode pad, and before applying the first turn-off voltage to the first electrode pad, a third turn-on voltage is applied to the fourth electrode pad. A semiconductor circuit in which, after applying the first turn-on voltage to the first electrode pad, then applying the second turn-on voltage to the second electrode pad, and before applying the third turn-on voltage to the fourth electrode pad, a fourth turn-on voltage is applied to the fifth electrode pad.

7. A third gate electrode is provided in a third trench provided on the side of the first surface of the semiconductor layer, A third electrode pad electrically connected to the third gate electrode, A semiconductor device according to any one of claims 1 to 4, further comprising:

8. The semiconductor device according to any one of claims 1 to 4, wherein the fourth gate electrode and the fifth gate electrode are of the planar gate type.

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