Semiconductor memory devices and semiconductor devices

Abstract

The present invention provides a semiconductor memory device and a semiconductor device that can suppress an increase in the number of TSVs used for transmitting power or electrical signals, and suppress the deterioration of the power or electrical signal transmission characteristics. [Solution] The semiconductor memory device 10 comprises a plurality of stacked memory chips 100a, 100b, 100c, and 100d. Each of the plurality of memory chips 100a to 100d comprises nodes N1 and N2 for transmitting power or electrical signals between each memory chip 100a to 100d, and nodes N1 and N2 include one or more TSVs 101 for transmitting power or electrical signals to nodes N1 and N2 of other memory chips 100a to 100d, and the number of TSVs 101 in nodes N1 and N2 of each memory chip 100a to 100d is configured to decrease from one end to the other in the stacking direction of each memory chip 100a to 100d.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a semiconductor device. Background Art

[0002] A conventional semiconductor memory device is known which includes a plurality of stacked memory chips and is configured such that power or a power signal is transmitted between the respective memory chips via one or more Through Silicon Vias (TSVs) provided in each memory chip (for example, see Patent Document 1).

[0003] In the technology described in Patent Document 1, the same number of TSVs are provided for each of a plurality of memory dies (memory chips), and each TSV of each memory die is provided at the same position when viewed from the stacking direction of the memory dies. Prior Art Documents Patent Documents

[0004] Patent Document 1 Japanese Unexamined Patent Application Publication No. 2018-55740 Summary of the Invention Problems to be Solved by the Invention

[0005] In such a semiconductor memory device, increasing the number of TSVs provided in each memory chip makes it possible to suppress deterioration of power or electric signal transmission characteristics of each memory chip caused by an increase in IR drop, time constant, or the like in any TSV of any memory chip. However, when the number of TSVs in each memory chip increases, the size of the TSV region in each memory chip increases, which may increase the size of each memory chip and raise the manufacturing cost of each memory chip.

[0006] The present invention has been made in view of the above problems, and aims to provide a semiconductor memory device and semiconductor device that can suppress an increase in the number of TSVs used for transmitting power or electrical signals, and suppress the deterioration of the power or electrical signal transmission characteristics. [Means for solving the problem]

[0007] To solve the above problems, the present invention provides a semiconductor memory device comprising a plurality of stacked memory chips, wherein each of the plurality of memory chips comprises a node for transmitting power or electrical signals between the memory chips, the node includes one or more TSVs for transmitting power or electrical signals to the nodes of other memory chips, and the number of TSVs in the node of each memory chip is configured to decrease from one end to the other in the stacking direction of each memory chip.

[0008] According to this invention, since one or more TSVs are provided on each memory chip, it becomes possible to form multiple transmission paths for power or electrical signals between memory chips via any of the TSVs on each memory chip. This makes it possible to suppress the degradation of the power or electrical signal transmission characteristics. Furthermore, according to this invention, since the number of TSVs within the same node of each memory chip is configured to decrease from one end to the other in the stacking direction of each memory chip, it becomes possible to reduce the total number of TSVs within the same node of each memory chip compared to, for example, the case where the same number of TSVs are provided between the same nodes of each memory chip, and to reduce the size of the TSV area for that node on the other end in the stacking direction of each memory chip. This makes it possible to suppress an increase in the number of TSVs used for power or electrical signal transmission, and to suppress an increase in the size and cost of each memory chip.

[0009] The present invention also provides a semiconductor device comprising a plurality of stacked semiconductor chips, wherein each of the plurality of semiconductor chips includes a node for transmitting power or electrical signals between the semiconductor chips, and the node includes one or more TSVs for transmitting power or electrical signals to the nodes of other semiconductor chips, and the number of TSVs in the node of each semiconductor chip is configured to decrease from one end to the other in the stacking direction of each memory chip. [Effects of the Invention]

[0010] The semiconductor memory device and semiconductor device of the present invention can suppress an increase in the number of TSVs used for transmitting power or electrical signals, and can also suppress deterioration of the power or electrical signal transmission characteristics. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows an example configuration of a semiconductor memory device according to one embodiment of the present invention. [Figure 2] This figure shows other examples of semiconductor memory device configurations. [Figure 3] (a) is a diagram showing example configurations of the semiconductor memory device according to the comparative example and the semiconductor memory device according to the present embodiment; (b) is a diagram showing an example of simulation results of IR drop values ​​in the comparative example and the present embodiment; (c) is a diagram showing an example of simulation results of time constants in the comparative example and the present embodiment; and (d) is a diagram showing an example of the number of TSVs in the comparative example and the present embodiment. [Figure 4] This figure shows an example of a plan view of each memory chip. [Figure 5] This figure shows other examples of semiconductor memory device configurations. [Figure 6] This figure shows other examples of semiconductor memory device configurations. [Figure 7] This figure shows an example configuration of a semiconductor device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0012] Figure 1 shows an example configuration of a semiconductor memory device 10 according to one embodiment of the present invention. As shown in Figure 1, the semiconductor memory device 10 comprises a plurality (in this case, four) of memory chips 100a, 100b, 100c, and 100d stacked in the vertical direction, and a control chip 110. Here, the control chip 110 may be a chip for supplying power to each of the memory chips 100a to 100d, or it may be a chip equipped with a control circuit for performing predetermined processing (for example, read / write processing, etc.) on each of the memory chips 100a to 100d.

[0013] In this embodiment, the case where the semiconductor memory device 10 is DRAM (Dynamic Random Access Memory) is described as an example, but the semiconductor memory device 10 may be other semiconductor memory devices (for example, SRAM (Static Random Access Memory), flash memory, etc.).

[0014] Furthermore, in this embodiment, in order to simplify the explanation, a detailed explanation of other circuits in the semiconductor memory device 10 (for example, memory cell array, command decoder, address decoder, clock generator, etc.) will be omitted.

[0015] Each memory chip 100a to 100d may include only a memory element, or it may include a memory element and a control circuit that performs predetermined processing (e.g., read / write processing) on ​​the memory element based on an electrical signal transmitted from the outside (e.g., a command signal, an address signal, a data signal, etc.).

[0016] Furthermore, each memory chip 100a to 100d may be a DRAM chip or another type of memory chip other than DRAM. Alternatively, at least one of the memory chips 100a to 100d may be a DRAM chip, and the other memory chips may be other types of memory chips other than DRAM.

[0017] As shown in FIG. 1, each of the memory chips 100a to 100d includes a first node N1 and a second node N2 for transmitting power or electric signals between the respective memory chips 100a to 100d. Here, the first node N1 of each memory chip 100a to 100d is configured to transmit power or an electric signal to and from the first node N1 of another memory chip 100a to 100d adjacent in the stacking direction of the respective memory chips 100a to 100d. Further, the second node N2 of each memory chip 100a to 100d is configured to transmit power or an electric signal to and from the second node N2 of another memory chip 100a to 100d adjacent in the stacking direction of the respective memory chips 100a to 100d.

[0018] Furthermore, the first node N1 and / or the second node N2 of each memory chip 100a to 100d may be configured to transmit power or electric signals transmitted from outside the corresponding memory chip 100a to 100d to an internal circuit or the like of the corresponding memory chip 100a to 100d, or may be configured to transmit power or electric signals generated by an internal circuit or the like of the corresponding memory chip 100a to 100d to outside the corresponding memory chip 100a to 100d.

[0019] Further, each of the first node N1 and the second node N2 of each memory chip 100a to 100d includes one or more TSVs 101 for transmitting power or electric signals to and from a node (the first node N1 or the second node N2) of another memory chip 100a to 100d. Each TSV 101 is formed so as to extend in the stacking direction of the respective memory chips 100a to 100d. Further, each TSV 101 may have a configuration using a material such as copper, for example. In the present embodiment, as shown in FIG. 1, a case where the same number of TSVs 101 are provided for each of the plurality of memory chips 100a to 100d, and each TSV 101 of each memory chip 100a to 100d is provided at the same position when viewed from the stacking direction of the respective memory chips 100a to 100d will be described as an example.

[0020] Further, although the example shown in FIG. 1 describes, as an example, the case where one or more TSVs 101 are provided on each of the first node N1 and the second node N2 of each of the memory chips 100a to 100d, each of the memory chips 100a to 100d may be provided with other TSVs that are not included in either the first node N1 or the second node N2.

[0021] Each TSV 101 in the first node N1 of each of the memory chips 100a to 100d may be electrically connected, via, for example, a metal wiring, to one or more TSVs 101 in the first node N1 of another memory chip 100a to 100d adjacent in the stacking direction of each of the memory chips 100a to 100d. Furthermore, each TSV 101 in the second node N2 of each of the memory chips 100a to 100d may be electrically connected, via, for example, a metal wiring, to one or more TSVs 101 in the second node N2 of another memory chip 100a to 100d adjacent in the stacking direction of each of the memory chips 100a to 100d.

[0022] Here, the metal wiring that electrically connects the TSV 101 (first TSV 101) of any one of the memory chips 100a to 100d and the TSV 101 (second TSV 101) of another memory chip 100a to 100d adjacent in the stacking direction of the any one of the memory chips may be configured to include, for example, a portion extending from the end of the first TSV 101 in the extending direction of the any one of the memory chips 100a to 100d (the lateral direction in the example of FIG. 1) and a portion extending from the end of the second TSV 101 in the stacking direction of each of the memory chips 100a to 100d (the vertical direction in the example of FIG. 1).

[0023] Furthermore, as shown in Figure 1, one or more TSVs 101 of each of the multiple memory chips 100a to 100d do not need to be electrically connected to one or more TSVs 101 of other memory chips 100a to 100d adjacent to each memory chip 100a to 100d in the stacking direction, provided that they are located at the same position when viewed from the stacking direction of each memory chip 100a to 100d. In addition, connection parts such as pads or lands (not shown) for electrically connecting to metal wiring, etc., may be provided at both ends of each TSV 101 in the extending direction (i.e., the stacking direction of each memory chip 100a to 100d).

[0024] In this embodiment, the number of TSV101s in each node N1 and N2 of each memory chip 100a to 100d is configured to decrease from one end to the other in the stacking direction of each memory chip 100a to 100d. In the example shown in Figure 1, the number of TSV101s in node N1 of each memory chip 100a to 100d is configured to decrease from 5, 4, 3, and 2 in the stacking direction from the lower end (here, memory chip 100a) to the upper end (here, memory chip 100d) of each memory chip 100a to 100d. On the other hand, the number of TSV101s in node N2 of each memory chip 100a to 100d is configured to decrease from 5, 4, 3, and 2 in the stacking direction from the upper end (here, memory chip 100d) to the lower end (here, memory chip 100a) of each memory chip 100a to 100d.

[0025] Furthermore, the number of TSV101s within each node N1, N2 of each memory chip 100a to 100d may be configured to decrease according to the direction of power or electrical signal transmission between each memory chip 100a to 100d. This makes it possible to consolidate the multiple transmission paths of power or electrical signals between each memory chip 100a to 100d via each TSV101 of each memory chip 100a to 100d into a small number each time power or electrical signals are transmitted between each memory chip 100a to 100d.

[0026] Here, we will explain as an example the case where the first node N1 of each memory chip 100a to 100d is a node for transmitting power between each memory chip 100a to 100d, and the second node N2 of each memory chip 100a to 100d is a node for transmitting electrical signals between each memory chip 100a to 100d.

[0027] In the example shown in Figure 1, the power generated by the power generation unit 111 of the control chip 110 is transmitted, for example, via metal wiring to each TSV 101 in the first node N1 at the lower end of each memory chip 100a to 100d in the stacking direction (here, memory chip 100a), and then transmitted towards the upper end of each memory chip 100a to 100d in the stacking direction (here, memory chip 100d) via memory chips 100b and 100c.

[0028] Here, at least one TSV 101 in at least one node N1, N2 of any of the memory chips 100a to 100d may be electrically connected to a generation unit (not shown) that generates power or electrical signals within that memory chip. This makes it possible to transmit power or electrical signals generated within any of the memory chips 100a to 100d to other memory chips.

[0029] In each of the multiple memory chips 100a to 100d, a corresponding driver may be electrically connected to the transmission path of at least one TSV 101 (for example, a metal wiring provided on another memory chip for electrical connection to a TSV 101). Here, Figure 1 shows the case where driver 102 is electrically connected to a TSV 101 located in the first node N1, and driver 103 is electrically connected to a TSV 101 located in the second node N2. In the example in Figure 1, the 3rd, 4th, and 5th TSV 101s from the left of memory chip 100a are each electrically connected to their corresponding driver 102, and the 6th and 7th TSV 101s from the left are each electrically connected to their corresponding driver 103. However, the connection of drivers 102 and 103 of each memory chip 100a to 100d to which TSV 101 is not limited to the example in Figure 1. Furthermore, in the example shown in Figure 1, the number of drivers 102 in memory chip 100a may differ from one memory chip to another, for example, there may be three drivers 102 and two drivers 103. Although the positions of the drivers 102 and 103 in memory chips 100a to 100d largely overlap in the stacking direction, the number and position of the drivers 102 and 103 in each of the memory chips 100a to 100d are not limited to the example shown in Figure 1.

[0030] In the example shown in Figure 1, it is assumed that the operation of the driver 102 electrically connected to the TSV 101 in the first node N1 of each memory chip 100a to 100d is disabled (i.e., the first node N1 of each memory chip 100a to 100d is driven by the generation unit 111 of the control chip 110). Furthermore, the example shown in Figure 1 assumes that an electrical signal generated by a generation unit within any of the memory chips 100a to 100d is supplied to a TSV 101 within the second node N2 via a driver 103 electrically connected to that TSV 101 (i.e., the operation of the driver 103 electrically connected to the TSV 101 within the second node N2 of any of the memory chips 100a to 100d is enabled, and the second node N2 of each memory chip 100a to 100d is driven by the driver 103 of any of the memory chips 100a to 100d). Here, by changing the number of drivers 103 that are enabled for each memory chip 100a to 100d (in the example in Figure 1, the number decreases from 5, 4, 3, and 2 from the upper end (here, memory chip 100d) to the lower end (here, memory chip 100a) in the stacking direction of each memory chip 100a to 100d), it becomes possible to improve the transmission efficiency of electrical signals generated by the generation unit within any of the memory chips 100a to 100d. Note that the operation of drivers 102 and 103 of each memory chip 100a to 100d may be controlled to be enabled or disabled based on a control signal generated by another circuit (e.g., a control chip 110).

[0031] Furthermore, the direction of power transmission between each memory chip 100a to 100d in the first node N1 may be opposite to the direction of electrical signal transmission between each memory chip 100a to 100d in the second node N2. This makes it possible to make the TSV area (i.e., the combined area of ​​the first node N1 and the second node N2) of each memory chip 100a to 100d the same, as shown in Figure 1.

[0032] In the example shown in Figure 1, an electrical signal generated in the generation unit of any of the memory chips 100a to 100d is transmitted towards the lower end of each memory chip 100a to 100d in the stacking direction (here, memory chip 100a) via each TSV 101 in the second node N2 of each memory chip 100a to 100d, and then transmitted from each TSV 101 in the second node N2 at the lower end of each memory chip 100a to 100d in the stacking direction (here, memory chip 100a) to the receiver circuit 112 in the control chip 110 via, for example, metal wiring.

[0033] In other words, the direction of power transmission between each memory chip 100a to 100d in the first node N1 is from the lower end side in the stacking direction (here, memory chip 100a) to the upper end side in the stacking direction (here, memory chip 100d), whereas the direction of electrical signal transmission between each memory chip 100a to 100d in the second node N2 is from the upper end side in the stacking direction (here, memory chip 100d) to the lower end side in the stacking direction (here, memory chip 100a).

[0034] Furthermore, the number of TSV101 reductions in the first node N1 and / or second node N2 of each memory chip 100a to 100d may be the same among the memory chips 100a to 100d (for example, one each in the example in Figure 1). Also, the number of TSV101 reductions in the first node N1 and / or second node N2 of any of the memory chips 100a to 100d may be different from the number of TSV101 reductions in the first node N1 and / or second node N2 of the other memory chips 100a to 100d. For example, while the number of TSV101 reductions in the first node N1 of memory chip 100b is one, the number of TSV101 reductions in the first node N1 of memory chip 100c and / or memory chip 100d may be two or more arbitrary numbers. This makes it possible to arbitrarily set the number of TSV101 reductions in the first node N1 and / or second node N2 of each memory chip 100a to 100d.

[0035] Here, the first node N1 of each memory chip 100a to 100d is a node for transmitting power between each memory chip 100a to 100d, and the second node N2 of each memory chip 100a to 100d is a node for transmitting electrical signals between each memory chip 100a to 100d. However, the present invention is not limited to this case. For example, the first node N may be a node for transmitting electrical signals between each memory chip 100a to 100d, and the second node N2 may be a node for transmitting power between each memory chip 100a to 100d. Furthermore, each of the first node N1 and the second node N2 of each memory chip 100a to 100d may be a node for transmitting power between each memory chip 100a to 100d. This makes it possible to arbitrarily set whether to transmit power or electrical signals using each node N1 and N2.

[0036] Figure 2 shows an example configuration in which the first node N1 of each memory chip 100a to 100d transmits electrical signals. In the example shown in Figure 2, the generation unit 111 of the control chip 110 may be configured to generate electrical signals. Also in Figure 2, the driver 102 may be electrically connected to a generation unit (not shown) that generates electrical signals, and may also be electrically connected to at least one TSV 101 in node N1 of any of the memory chips 100a to 100d. Furthermore, at least one TSV 101 in node N1 of any of the memory chips 100a to 100d may be electrically connected to a receiver 104 for receiving electrical signals.

[0037] Next, with reference to Figure 3, an example of the power or electrical signal transfer characteristics of the semiconductor memory device 10 according to this embodiment will be described. Here, the effects of the semiconductor memory device 10 according to this embodiment will be explained by comparing the simulated values ​​of the power or electrical signal transfer characteristics of the semiconductor memory device 10 according to this embodiment with the simulated values ​​of the power or electrical signal transfer characteristics of the semiconductor memory device 10 according to this embodiment, as shown in Figure 3(a).

[0038] As shown in Figure 3(a), the semiconductor memory device according to the comparative example comprises a plurality (in this case, four) of memory chips 0 to 3 stacked on a control chip. Each memory chip 0 to 3 is provided with the same number (in this case, four) of TSVs, and each TSV of each memory chip 0 to 3 is located at the same position when viewed from the stacking direction of the memory chips. That is, the number of TSVs in the semiconductor memory device according to the comparative example is 16. Furthermore, each memory chip [i] (where i is any integer from 0 to 3) is configured to receive a signal In transmitted from the control chip at its TSV, and then input the received signal In as an internal input signal Int_in[i] to the circuit etc. within the memory chip [i].

[0039] As shown in Figure 3(a), the semiconductor memory device 10 according to this embodiment has the same configuration as the first node N1 in Figure 1, but here it is configured to transmit the signal In transmitted from the control chip 110 between each memory chip 100a to 100d. In the example in Figure 3(a), the number of TSVs used to transmit the signal In in the semiconductor memory device 10 according to this embodiment is 14. When memory chip 100a receives the signal In transmitted from the control chip 110 via the TSV, it is configured to input the received signal In as an internal input signal Int_in[0] to a circuit provided on it. Similarly, when memory chip 100b receives the signal In transmitted from memory chip 100a via the TSV, it is configured to input the received signal In as an internal input signal Int_in[1] to a circuit provided on it. Similarly, when memory chip 100c receives a signal In transmitted from memory chip 100b in the TSV, it is configured to input the received signal In as an internal input signal Int_in[2] to a circuit provided within itself, and when memory chip 100d receives a signal In transmitted from memory chip 100c in the TSV, it is configured to input the received signal In as an internal input signal Int_in[3] to a circuit provided within itself.

[0040] Figure 3(b) shows the simulated IR drop of the internal input signal Int_in[i] when the resistance value (assumed value) of each of the multiple TSVs provided in the semiconductor memory device according to the comparative example and this embodiment is set to 20Ω, the capacitance (assumed value) of each TSV is set to 0.1pF, the voltage of the input signal In (assumed value) is set to 1V, and the load current (assumed value) at the output of the internal input signal Int_in[i] is set to 1mA.

[0041] Here, as shown in Figure 3(b), the ratio of the number of TSVs to the IR drop value in the internal input signal Int_in[3] of the semiconductor memory device according to the comparative example is calculated to be 16 / 50. Also, the ratio of the number of TSVs to the IR drop value in the internal input signal Int_in[3] of the semiconductor memory device 10 according to this embodiment is calculated to be 14 / 52. The ratio of the number of TSVs required to keep the IR drop constant between this embodiment and the comparative example is calculated as 100 × (1 - (ratio of embodiment) / (ratio of comparative example)) = 15.9. In other words, the semiconductor memory device 10 according to this embodiment can reduce the number of TSVs required to keep the IR drop constant by 15.9% compared to the semiconductor memory device according to the comparative example.

[0042] Figure 3(c) shows the simulated transition time when the resistance (assumed value) of each of the multiple TSVs provided in the semiconductor memory devices according to the comparative example and this embodiment is set to 20Ω, the capacitance (assumed value) of each TSV is set to 0.1pF, and the input signal In is applied such that the voltage (assumed value) of the input signal In changes linearly from 0V to 1V over a period of 0.1 nanoseconds. Here, the transition time is assumed to be the time from when the input voltage of the input signal In reaches 50% (i.e., 0.5V) until the voltage of the internal input signal Int_in[3] reaches 50%.

[0043] Here, as shown in Figure 3(c), the transition time in the semiconductor memory device according to the comparative example is 125 picoseconds, while the transition time in the semiconductor memory device 10 according to this embodiment is 104 picoseconds. The ratio of the transition time of this embodiment to that of the comparative example is calculated as 100 × (1 - (time of the embodiment (transition time) / time of the comparative example (transition time))) = 16.8. In other words, the semiconductor memory device 10 according to this embodiment can improve the time constant by 16.8% compared to the semiconductor memory device according to the comparative example.

[0044] Figure 3(d) shows the number of TSVs provided for transmitting the signal In in the semiconductor memory device according to the comparative example and this embodiment, respectively. As described above, the number of TSVs used for transmitting the signal In in the semiconductor memory device according to the comparative example is 16, and the number of TSVs used for transmitting the signal In in the semiconductor memory device according to this embodiment is 14. In this case, the power consumption reduction rate (related to the transmission of signal In) of this embodiment compared to the comparative example is calculated as 100 × (1 - (number of TSVs in the embodiment / number of TSVs in the comparative example)) = 12.5. That is, the semiconductor memory device 10 according to this embodiment can reduce power consumption by 12.5% ​​compared to the semiconductor memory device according to the comparative example.

[0045] As described above, according to the semiconductor memory device 10 of this embodiment, one or more TSVs 101 are provided on each memory chip 100a to 100d, so that multiple transmission paths for power or electrical signals between each memory chip 100a to 100d can be formed via any of the TSVs 101 on each memory chip 100a to 100d. This makes it possible to suppress the degradation of the power or electrical signal transmission characteristics. Furthermore, according to the semiconductor memory device 10 of this embodiment, the number of TSVs 101 within the same node (e.g., node N1) of each memory chip 100a to 100d is configured to decrease from one end to the other in the stacking direction of each memory chip 100a to 100d. Compared to the case where the same number of TSVs 101 are provided between the same nodes (e.g., node N1) of each memory chip 100a to 100d, it becomes possible to reduce the total number of TSVs 101 within the same node (e.g., node N1) of each memory chip 100a to 100d, and to reduce the size of the TSV area for that node (e.g., node N1) on the other end in the stacking direction of each memory chip 100a to 100d. This suppresses an increase in the number of TSVs 101 used for transmitting power or electrical signals, and also suppresses an increase in the size and cost of each memory chip 100a to 100d.

[0046] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit it. Accordingly, each element disclosed in the above embodiments is intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0047] In the embodiments described above, the case in which each memory chip 100a to 100d is provided with two nodes (first node N1 and second node N2) was explained as an example, but the present invention is not limited to this case. The number of nodes provided on each memory chip 100a to 100d may be one, or it may be three or more (four in the example shown in Figure 4), for example. In the example shown in Figure 4, each memory chip 100a to 100d is provided with four nodes A, B, C, and D. Here, the number of TSV101 in each node A and D is configured to decrease from the lower end side (here, memory chip 100a) to the upper end side (here, memory chip 100d) in the stacking direction of each memory chip 100a to 100d. Also, the number of TSV101 in each node B and C is configured to decrease from the upper end side (here, memory chip 100d) to the lower end side (here, memory chip 100a) in the stacking direction of each memory chip 100a to 100d. Note that the arrangement and configuration of nodes A, B, C, and D shown in Figure 4 is just one example, and various other arrangements and configurations are conceivable.

[0048] Furthermore, as shown in Figure 5, the semiconductor memory device 10 may also include a redistribution layer 120 stacked on the memory chip 100d at one end in the stacking direction (here, the upper end in the stacking direction) of the plurality of memory chips 100a to 100d. In the example shown in Figure 5, the redistribution layer 120 is electrically connected to each TSV 101 in the second node N2 at the upper end in the stacking direction (here, memory chip 100d) of each memory chip 100a to 100d, for example, via metal wiring. This makes it possible to reroute the wiring of electrical signals transmitted and received between each memory chip 100a to 100d, thereby optimizing the layout of the electrical connections.

[0049] Furthermore, as shown in Figure 6, the semiconductor memory device 10 may also include a power supply chip 130 stacked on the memory chip 100d at one end of the stacking direction (here, the upper end in the stacking direction) among the plurality of memory chips 100a to 100d, for supplying power to each memory chip 100a to 100d. In the example shown in Figure 6, the power generated by the power generation unit 111 within the power supply chip 130 is transmitted, for example, via metal wiring to each TSV 101 in the second node N2 at the upper end of each memory chip 100a to 100d in the stacking direction (here, memory chip 100d). This makes it possible to supply power to each memory chip 100a to 100d using the power supply chip 130.

[0050] Figure 7 shows an example configuration of a semiconductor device 20 according to one embodiment of the present invention. As shown in Figure 7, the semiconductor device 20 comprises a plurality (in this case, four) of semiconductor chips 200a, 200b, 200c, and 200d stacked in the vertical direction, and a control chip 110. Here, the control chip 110 may be a chip for supplying power to each of the semiconductor chips 200a to 200d, or it may be a chip equipped with a control circuit for performing predetermined processing (e.g., read / write processing) on ​​each of the semiconductor chips 200a to 200d.

[0051] Each semiconductor chip 200a to 200d may be a functional circuit chip that performs a predetermined process, or a processing circuit chip that executes a predetermined program (for example, a CPU core chip). Furthermore, at least one of each semiconductor chip 200a to 200d may be a memory chip (for example, a DRAM chip, etc.) similar to the memory chips 100a to 100d in the semiconductor storage device 10 described above.

[0052] As shown in Figure 7, each semiconductor chip 200a to 200d includes a first node N1 and a second node N2 for transmitting power or electrical signals between each semiconductor chip 200a to 200d. Furthermore, each of the first node N1 and the second node N2 of each semiconductor chip 200a to 200d includes one or more TSV101 for transmitting power or electrical signals to the nodes (first node N1 or second node N2) of the other semiconductor chips 200a to 200d. Note that the configuration of each of the first node N1 and the second node N2, and the configuration of each TSV101 within each node N1, N2, may be the same as the configuration of the semiconductor memory device 10 described above.

[0053] According to the semiconductor device 20 of this embodiment, since one or more TSVs 101 are provided on each semiconductor chip 200a to 200d, it becomes possible to form multiple transmission paths for power or electrical signals between each semiconductor chip 200a to 200d via any of the TSVs 101 on each semiconductor chip 200a to 200d. This makes it possible to suppress the degradation of the power or electrical signal transmission characteristics. Furthermore, according to the semiconductor device 20 of this embodiment, the number of TSV101s in the same node (e.g., node N1) of each semiconductor chip 200a to 200d is configured to decrease from one end to the other in the stacking direction of each semiconductor chip 200a to 200d. Compared to the case where the same number of TSV101s are provided between the same nodes (e.g., node N1) of each semiconductor chip 200a to 200d, it is possible to reduce the total number of TSV101s within the same node (e.g., node N1) of each semiconductor chip 200a to 200d, and to reduce the size of the TSV region for that node (e.g., node N1) on the other end in the stacking direction of each semiconductor chip 200a to 200d. This suppresses an increase in the number of TSV101s used for transmitting power or electrical signals, and also suppresses an increase in the size and cost of each semiconductor chip 200a to 200d. [Explanation of symbols]

[0054] 10…Semiconductor memory 20... Semiconductor equipment 100a, 100b, 100c, 100d…memory chips 101…TSV(Through Silicon Via) 102, 103… Drivers 110…Control chip 120...Rewiring layer 130…Power supply chip 200a, 200b, 200c, 200d… Semiconductor chips N1...First node N2... Second node

Claims

1. A semiconductor memory device comprising multiple stacked memory chips, Each of the plurality of memory chips is provided with a node for transmitting power or electrical signals between the memory chips. The node includes one or more TSVs (Through Silicon Vias) for transmitting power or electrical signals to nodes of other memory chips. The number of TSVs within each memory chip node is configured to decrease from one end to the other in the stacking direction of each memory chip. Semiconductor memory device.

2. The number of TSVs within each memory chip node is configured to decrease according to the direction of power or electrical signal transmission between each memory chip. The semiconductor memory device according to claim 1.

3. Each of the plurality of memory chips comprises a first node which is a node and a second node which is a node, The direction of power or electrical signal transmission between each memory chip in the first node is opposite to the direction of power or electrical signal transmission between each memory chip in the second node. The semiconductor memory device according to claim 2.

4. One of the first node and the second node is a node for transmitting power between each memory chip. The other of the first and second nodes is a node for transmitting electrical signals between each memory chip. The semiconductor memory device according to claim 3.

5. Each of the first and second nodes is a node for transmitting power between each memory chip. The semiconductor memory device according to claim 3.

6. Each of the first and second nodes is a node for transmitting electrical signals between memory chips. The semiconductor memory device according to claim 3.

7. In each of the plurality of memory chips, a corresponding driver is electrically connected to the transmission path of at least one TSV, and the drivers of each memory chip are arranged so that their positions overlap in the stacking direction of each memory chip. The semiconductor memory device according to claim 1.

8. It also features a control chip, The control chip includes a generation unit that generates the power and sequentially transmits the power to the plurality of memory chips on the other end of the stacking direction via one node of the memory chip located on one end of the plurality of memory chips in the stacking direction. The semiconductor memory device according to claim 4.

9. The control chip further includes a receiver circuit that is connected to the other node of the memory chip located at one end in the stacking direction and receives the electrical signal generated by the generation unit of any one of the plurality of memory chips and sequentially transmitted to the plurality of memory chips at one end in the stacking direction via the other node. The semiconductor memory device according to claim 8.

10. At least one TSV in one node of any of the plurality of memory chips is electrically connected to the receiver. The semiconductor memory device according to claim 4.

11. At least one TSV in a node of any of the plurality of memory chips is electrically connected to a generation unit that generates power or electrical signals within any of the memory chips. The semiconductor memory device according to claim 1.

12. The memory chips among the plurality of memory chips have a redistribution layer stacked on one end of the memory chip in the stacking direction. The semiconductor memory device according to claim 1.

13. The memory chips, among the plurality of memory chips, are stacked on one end of the memory chip in the stacking direction and include a power supply chip for supplying power to each memory chip. The semiconductor memory device according to claim 1.

14. At least one of the aforementioned multiple memory chips is a DRAM (Dynamic Random Access Memory) chip. The semiconductor memory device according to claim 1.

15. A semiconductor device comprising multiple stacked semiconductor chips, Each of the plurality of semiconductor chips is provided with a node for transmitting power or electrical signals between the semiconductor chips. The node includes one or more TSVs (Through Silicon Vias) for transmitting power or electrical signals to nodes of other semiconductor chips. The number of TSVs within each semiconductor chip node is configured to decrease from one end to the other in the stacking direction of each semiconductor chip. Semiconductor equipment.

16. At least one of the aforementioned plurality of semiconductor chips is a memory chip. The semiconductor device according to claim 15.

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