Dual-processor device and its control method and processor

Abstract

This application discloses a dual processor device and a control method and processor therefor, the dual processor including a control processor and an arithmetic processor, the method being implemented by the control processor, and characterized in that, upon detecting an arc occurrence, the method includes sending a pre-turn-off output preshake hand to the arithmetic processor, causing the arithmetic processor to stop a related arithmetic operation based on the pre-turn-off output preshake hand; receiving an operation stop notification sent by the arithmetic processor, the operation stop notification being issued after the arithmetic processor has completed an operation on the received data after receiving the pre-turn-off output preshake hand; and executing a turn-off operation. This solves the problem of data accuracy between the control processor and the arithmetic processor, which is caused by a lack of synchronization between the control processor and the arithmetic processor in the prior art.

Description

[Technical Field]

[0001] The present invention relates to the technical field of device control, and specifically relates to a dual-processor device, a control method therefor, and a processor. [Background Art]

[0002] In the control mode of conventional dual-processor devices, processor A is used to control a circuit and detect an arc, and processor B performs PID calculation to provide control circuit operation parameters to processor A. When processor A detects the occurrence of an arc, it immediately disconnects the circuit or stops signal output by executing disable control. However, since the PID calculation cannot be interrupted, when processor A executes disable control, processor B continues to perform PID calculation and feeds back control circuit operation parameters to processor A. For processor A, the calculation parameters fed back by processor B at this time are redundant, unnecessary and erroneous. In addition, the disable control of processor A occurs suddenly, and the operation parameters fed back by processor B may prevent processor A from connecting to subsequent monitoring data, resulting in the entire control data group becoming invalid.

[0003] Therefore, how to design a highly reliable and high-precision dual-processor device and a control method therefor is a technical problem to be solved. [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the problem in the prior art that when PID control is performed between dual processors, the control circuit of the control processor immediately performs interruption, but the calculation processor continues the PID calculation, which affects the data accuracy between the control processor and the calculation processor. Therefore, the present invention provides a dual-processor device, a control method therefor, and a processor. [Means for solving the problem]

[0005] To solve the above technical problems, the embodiments disclosed in the present invention provide at least a dual-processor device, a control method thereof, and a processor.

[0006] According to the first aspect, an embodiment disclosed in the present invention is a dual-processor device control method, wherein the dual processor includes a control processor and an arithmetic processor, and the method is implemented by the control processor. Upon detecting the occurrence of an arc, a pre-turn-off output pre-shakehand is sent to the arithmetic processor, causing the arithmetic processor to stop the associated arithmetic operations based on the pre-turn-off output pre-shakehand; The steps include receiving a calculation stop notification transmitted by the arithmetic processor, the calculation stop notification being issued by the arithmetic processor after it has received the pre-turn-off output pre-shakehand and completed the calculation of the received data, The present invention provides a dual-processor device control method characterized by including the step of performing a turn-off operation.

[0007] Preferably, the above method is If the restart conditions are met, the process includes sending a restarted pre-shakehand to the arithmetic processor, causing the arithmetic processor to recover its readiness for calculation based on the restarted pre-shakehand, The further step includes receiving a recovery confirmation message fed back by the arithmetic processor, recovering the acquisition of equipment operation data, and recovering the transmission of the equipment operation data to the arithmetic processor, wherein the recovery confirmation message is transmitted after the arithmetic processor has completed preparation for calculation.

[0008] Preferably, before sending a restarted pre-shakehand to the arithmetic processor, The process further includes determining whether the arithmetic processor is in a sleep state, Sending a restarted pre-shakehand to the arithmetic processor means sending a restarted pre-shakehand to the arithmetic processor if the arithmetic processor is in a sleep state.

[0009] Preferably, before sending a restarted pre-shakehand to the arithmetic processor, If the arithmetic processor is not in sleep mode, the further step includes directly acquiring the device operation data and transmitting the device operation data to the arithmetic processor.

[0010] Preferably, the restart condition includes whether the turn-off time satisfies a preset turn-off time length, and / or whether restart instruction information is received.

[0011] Preferably, The process further includes a step of entering a sleep state after performing a turn-off operation.

[0012] Preferably, before entering a sleep state, the method further includes the step of freezing the equipment operation data for the arc generation period.

[0013] According to a second aspect, an embodiment disclosed in the present invention is a control processor for a dual-processor device, A pre-turn-off instruction module, which detects arc generation and sends a pre-turn-off output pre-shakehand to the arithmetic processor so that the arithmetic processor stops the associated arithmetic operation based on the pre-turn-off output pre-shakehand, A pre-turn-off execution module for receiving a calculation stop notification transmitted by the arithmetic processor, wherein the calculation stop notification is issued by the arithmetic processor after it has received the pre-turn-off output pre-shakehand and completed the calculation of the received data; The present invention provides a control processor for a dual-processor device, characterized by including a turn-off module for performing a turn-off operation.

[0014] According to a third aspect, an embodiment disclosed in the present invention is a dual-processor device control method, wherein the dual processor includes a control processor and an arithmetic processor, and the method is implemented by the arithmetic processor. The steps include receiving a pre-turn-off output pre-shakehand transmitted by the control processor, The steps include: completing the calculations on the received data and then stopping the associated calculation operations; The present invention provides a dual-processor device control method, which includes the step of sending a calculation stop notification to the control processor, so that the control processor performs a turn-off operation after receiving the calculation stop notification.

[0015] Preferably, The steps include receiving a pre-shake hand transmitted and restarted by the control processor, The steps include completing the preparation for recovery of operations based on the restarted pre-shakehand, The steps include sending a recovery confirmation message to the control processor so that the control processor recovers the acquisition of equipment operation data based on the recovery confirmation message, The further step includes receiving the device operation data transmitted by the control processor.

[0016] Preferably, after sending a notification to the control processor that the calculation has stopped, the method further includes the step of entering a sleep state.

[0017] Preferably, before entering the sleep state, the method further includes freezing the equipment operation data for the arc generation period.

[0018] According to the fourth aspect, an embodiment disclosed in the present invention provides an arithmetic processor for dual-processor equipment, a pre-turn-off instruction receiving module configured to receive a pre-turn-off output pre-shake hand transmitted by a control processor; an arithmetic stop control module configured to stop a related arithmetic operation after completing the arithmetic of the received data; and an arithmetic stop notification module configured to transmit an arithmetic stop notification to the control processor so that the control processor performs a turn-off operation after receiving the arithmetic stop notification, which is characterized in that the arithmetic processor is for dual-processor equipment.

[0019] According to the fifth aspect, an embodiment disclosed in the present invention provides a dual-processor equipment, which is characterized in that it comprises the control processor for dual-processor equipment according to the second aspect and the arithmetic processor for dual-processor equipment according to the fourth aspect.

[0020] According to the sixth aspect, an embodiment disclosed in the present invention provides a dual-processor equipment control method, wherein the dual-processor equipment comprises a control processor, an arithmetic processor and a shared memory, a turn-off instruction identifier is set in the shared memory, and the method is implemented by the control processor, performing a turn-off operation when arc generation is detected; and setting the turn-off instruction identifier in the shared memory to a turn-off state, so that the arithmetic processor skips acquiring first equipment operation data based on the state of the turn-off instruction identifier, wherein the first equipment operation data is equipment operation data acquired by the control processor during an arc generation period, which is characterized in that the method is a dual-processor equipment control method.

[0021] Preferably, before detecting arc generation, the method comprises: acquiring second equipment operation data; The further step includes transmitting the second device operation data to the arithmetic processor via the shared memory.

[0022] Preferably, the step of transmitting the second device operation data to the arithmetic processor via the shared memory is: The process includes the step of storing the second device operation data in the shared memory so that the arithmetic processor can acquire the second device operation data from the shared memory.

[0023] Preferably, after performing a turn-off operation, the method further includes the step of entering a sleep state.

[0024] Preferably, the above method is If the restart conditions are met, the steps to restart are as follows: The steps include setting the turn-off instruction identifier in the shared memory to a normal state, A step to recover the acquisition of the second device operation data, The further step includes the arithmetic processor retrieving the second device operation data from the shared memory based on the state of the turn-off instruction identifier by recovering the transmission of the second device operation data to the arithmetic processor via the shared memory.

[0025] Preferably, the restart conditions are: This includes whether the turn-off time meets a predetermined length of turn-off time, and / or whether restart instruction information is received.

[0026] Preferably, before entering a sleep state, the method further includes the step of freezing the equipment operation data for the arc generation period.

[0027] According to the seventh aspect, an embodiment disclosed in the present invention is a dual-processor device, the dual-processor device comprising a control processor, an arithmetic processor and a shared memory, the shared memory being set with a turn-off instruction identifier, and the control processor, When an arc is detected, a turn-off instruction module is activated to perform a turn-off operation. The present invention provides a dual-processor device comprising: a turn-off state setting module for the arithmetic processor to skip acquiring first device operation data based on the state of the turn-off instruction identifier by setting the turn-off instruction identifier in the shared memory to a turn-off state, wherein the first device operation data is device operation data acquired by the control processor during the arc generation period; and a turn-off state setting module for the arithmetic processor to skip acquiring first device operation data based on the state of the turn-off instruction identifier.

[0028] According to the eighth aspect, an embodiment disclosed in the present invention is a dual-processor device control method, wherein the dual-processor device includes a control processor, an arithmetic processor and a shared memory, the shared memory is set with a turn-off instruction identifier, and the method is implemented by the arithmetic processor. The steps include: obtaining the state of the turn-off instruction identifier in the shared memory; The present invention provides a dual-processor equipment control method, which includes the step of skipping the acquisition of first equipment operation data based on the state of the turn-off instruction identifier when the turn-off instruction identifier is in a turn-off state, wherein the first equipment operation data is equipment operation data acquired by the control processor during the arc generation period.

[0029] Preferably, If the turn-off instruction identifier is in a normal state, the step is to obtain the first device operation data from the shared memory, The control parameters are calculated based on the operation data of the first device, The further step includes transmitting the calculated control parameters to the control processor via the shared memory.

[0030] Preferably, the system further includes entering a sleep state if the turn-off indicator identifier is in the turn-off state.

[0031] Preferably, before obtaining the state of the turn-off instruction identifier in the shared memory, the method is: If the restart conditions are met, the process will further include a step to restart, The step of obtaining the state of the turn-off instruction identifier in the shared memory is to recover the acquisition of the state of the turn-off instruction identifier in the shared memory.

[0032] Preferably, before entering a sleep state, the method further includes the step of freezing the equipment operation data for the arc generation period.

[0033] According to the ninth aspect, an embodiment disclosed in the present invention is a dual-processor device comprising a control processor, an arithmetic processor and a shared memory, wherein a turn-off instruction identifier is set in the shared memory, and the arithmetic processor is A turn-off identifier acquisition module for acquiring the state of the turn-off instruction identifier in the shared memory, The present invention provides a dual-processor device comprising a turn-off data processing module for skipping the acquisition of first device operation data based on the state of the turn-off instruction identifier when the turn-off instruction identifier is in a turn-off state, wherein the first device operation data is device operation data acquired by the control processor during the arc generation period.

[0034] According to the tenth aspect, an embodiment disclosed in the present invention provides a dual-processor device comprising a shared memory, a control processor as described in the ninth aspect, and an arithmetic processor as described in the ninth aspect, wherein a turn-off instruction identifier is set in the shared memory.

[0035] According to the eleventh aspect, an embodiment disclosed in the present invention provides a computer device comprising a processor, memory, and a bus, wherein the memory stores machine-readable instructions that the processor can execute, and when the computer device is executed, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the dual-processor device control method described in any one of the first, third, sixth, or eighth aspects is executed.

[0036] According to the twelfth aspect, an embodiment disclosed in the present invention provides a computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the dual-processor device control method described in any one of the first, third, sixth, or eighth aspects is executed.

[0037] (Effects of the invention) The technical method according to the embodiment of the present invention can have the following beneficial effects. In a control process based on a dual processor, when the control processor detects the occurrence of an arc, it can perform a turn-off operation and stop the acquisition of equipment operation data by the processor being calculated, and can also send a turn-off calculation instruction to the calculation processor. The calculation processor can ensure that the control processor acquires accurate control parameters and prevents arc occurrence by deciding whether to interrupt the calculation operation of the relevant control parameters or to stop sending the calculated relevant control parameters to the control processor, based on whether or not the equipment operation data has been acquired or whether or not the turn-off calculation instruction has been acquired. When the control processor turns off the circuit, the data between the dual processors can maintain good accuracy, stop PID calculations in a timely manner, avoid extending the turn-off occasion point, reduce situations where data is discarded, avoid disruptive operation of the entire circuit caused by the other end still running when one end of the circuit is turned off, and unless the entire PID calculation has started, the calculation may be interrupted or the operation parameters for which the calculation has been completed may not be transmitted, applicable to instructions, shake hands or data sharing, and when turning off, the data is frozen to ensure the stability and consistency of data transmission between the control processor and the arithmetic processor, avoid disruptive operation of the entire circuit caused by the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensure data accuracy between the control processor and the arithmetic processor when arcing occurs.

[0038] Exemplary embodiments of the present invention can be better understood by referring to the following drawings. The drawings are provided for further understanding of the embodiments of the present application and together with the embodiments of the present application form part of the specification for describing the present invention and do not constitute limitations of the present invention. In the drawings, the same reference numerals usually represent the same part or step. [Brief explanation of the drawing]

[0039] [Figure 1] This is a flowchart of a dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 2] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 3] This is a schematic diagram of the interaction and timing between the control processor and the arithmetic processor according to an embodiment disclosed in the present invention. [Figure 4] This is a schematic diagram of the interaction and timing between the control processor and the arithmetic processor according to an embodiment disclosed in the present invention. [Figure 5] This is a schematic diagram of the interaction and timing between the control processor and the arithmetic processor according to an embodiment disclosed in the present invention. [Figure 6] This is a schematic diagram of the interaction and timing between the control processor and the arithmetic processor according to an embodiment disclosed in the present invention. [Figure 7] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 8] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 9] This is a schematic diagram of the structure of a control processor for a dual-processor device according to an embodiment disclosed in the present invention. [Figure 10] This is a schematic diagram of the structure of an arithmetic processor for a dual-processor device according to an embodiment disclosed in the present invention. [Figure 11] This is a schematic diagram of the structure of a dual-processor device according to an embodiment disclosed in the present invention. [Figure 12] This is a flowchart of a dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 13] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 14] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 15] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 16] This is a schematic diagram of the structure of a control processor in a dual-processor device according to an embodiment disclosed in the present invention. [Figure 17] This is a schematic diagram of the structure of the arithmetic processor in another dual-processor device according to an embodiment disclosed in the present invention. [Figure 18] This is a schematic diagram of a dual-processor device structure according to an embodiment disclosed in the present invention. [Figure 19] This is a timing relationship diagram of a dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 20] This is a timing relationship diagram of a dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 21] This is a timing relationship diagram of a dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 22] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 23] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Modes for carrying out the invention]

[0040] Illustrative embodiments of the Disclosure will be described in more detail below with reference to the drawings. While the drawings illustrate exemplary embodiments of the Disclosure, it should be understood that the Disclosure is not limited to the embodiments described herein and can be implemented in various forms. Conversely, these embodiments are provided to allow for a better understanding of the Disclosure and to fully convey its scope to those skilled in the art.

[0041] In the description of this invention, unless otherwise specifically defined and limited, the terms "attachment," "connection," and "linking" should be understood in a broad sense. For example, a connection may be fixed, detachable, integral, mechanical, electrical, direct, indirect via an intermediate medium, or an internal connection between two elements. Those skilled in the art will be able to specifically understand the concrete meaning of these terms in this invention depending on the specific circumstances.

[0042] Furthermore, the technical features of the different embodiments of the present invention described below can be combined with each other as long as there is no collision between them.

[0043] (Example 1) As shown in Figure 1, this is a flowchart of a dual-processor device control method according to an embodiment disclosed in the present invention, wherein the dual processor includes a control processor and an arithmetic processor, and the method is implemented by the control processor and includes the following:

[0044] S11: Upon detecting arc generation, the arithmetic processor sends a pre-turn-off output pre-shakehand to the arithmetic processor, which then stops the associated arithmetic operations based on the pre-turn-off output pre-shakehand.

[0045] S12: The system receives a halt notification sent by the arithmetic processor. This halt notification is issued by the arithmetic processor after it has received the pre-turnoff output pre-shakehand and completed the calculation of the received data.

[0046] S13: Perform the turn-off operation.

[0047] To make it easier to understand, in the technical proposal according to this embodiment, when the control processor detects an arc during the control process of a dual-processor device, it sends a pre-turnoff output pre-shakehand to the arithmetic processor. Based on the pre-turnoff output pre-shakehand, the arithmetic processor completes the calculation of the received data and stops the associated calculation operations. After the control processor receives the calculation stop notification sent by the arithmetic processor, it performs a turn-off operation. The shakehand ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the arithmetic processor on the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0048] (Example 2) As an improvement to Example 1, Figure 2 shows a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention, wherein the dual processor includes a control processor and an arithmetic processor, and the method is implemented by the control processor and includes the following:

[0049] S21: If the restart conditions are met, the control processor determines whether the arithmetic processor is in a sleep state. If the arithmetic processor is in a sleep state, it executes S22. If the arithmetic processor is not in a sleep state, it executes S24.

[0050] S22: The control processor sends a restarted pre-shakehand to the arithmetic processor, which then recovers its readiness for arithmetic based on the restarted pre-shakehand.

[0051] S23: The control processor receives a recovery confirmation message fed back by the arithmetic processor and resumes execution of S24. The recovery confirmation message is sent after the arithmetic processor has completed preparation for calculation.

[0052] S24: The control processor acquires device operation data and transmits the device operation data to the arithmetic processor.

[0053] S25: Upon detecting arc generation, the control processor sends a pre-turn-off output pre-shakehand to the arithmetic processor, which then stops the associated arithmetic operation based on the pre-turn-off output pre-shakehand.

[0054] S26: The control processor receives a halt-of-calculation notification sent by the arithmetic processor, which is issued after the arithmetic processor has received a pre-turn-off output pre-shakehand and has completed the calculation of the received data.

[0055] S27: The control processor performs the turn-off operation.

[0056] S28: The control processor freezes the equipment operation data for the arc generation period.

[0057] S29: The control processor enters sleep mode.

[0058] In some selective embodiments, the restart conditions include whether the turn-off time satisfies a predetermined turn-off time length and / or whether restart instruction information is received.

[0059] Furthermore, data can be frozen, and CPUB can enter a limited sleep state either alone or with CPUA and CPUB simultaneously.

[0060] It should be noted that the embodiments described herein are merely illustrative examples of specific embodiments under the concept of the present invention, and the order of execution of the steps in each embodiment is not limited to the embodiments described herein. In carrying out a specific process, a person skilled in the art can adjust the order of execution of each step based on the actual situation. For example, S21 and S27 do not necessarily have a causal relationship or sequence, and the restart operation in S21 may be described after the turn-off operation in S27.

[0061] To facilitate the reader's understanding, the interaction process and timing relationships of the dual-processor device control method in the embodiment of the present invention will be described in detail below, with reference to Figures 3, 4, 5, and 6, with CPUA as the control processor and CPUB as the arithmetic processor. At the first timing, CPUA transmits the data necessary for PID calculation to CPUB, CPUB acquires the data and performs PID calculation, CPUA detects the arc and sends a pre-shakehand of pre-turn-off output, CPUB completes the PID calculation, acquires accurate data and returns it to CPUA, CPUB feeds back the stopped timing PID calculation preparation to CPUA in response to the shakehand, CPUA acquires the feedback from CPUB and executes the turn-off output, and CPUA discards the PID data fed back at this timing.

[0062] At the Nth timing, if N is an integer > 1, there are two cases: 1) CUPB sleeps, and 2) CUPB does not sleep. 1) If CUPB does not sleep, CPUA restarts the control circuit and outputs power, CPUA transmits the data necessary for PID calculation to CPUB, and CPUB receives the data and performs PID calculation.

[0063] 2. If CPUB goes to sleep, CPUA outputs a restarted pre-shakehand signal, CPUB provides feedback that CPUA is ready, CPUA transmits the data necessary for PID calculation to CPUB, and CPUB receives the data and performs PID calculation.

[0064] To make it easier to understand, in the technical proposal according to this embodiment, when the control processor detects an arc during the control process of a dual-processor device, it sends a pre-turnoff output pre-shakehand to the arithmetic processor. Based on the pre-turnoff output pre-shakehand, the arithmetic processor completes the calculation of the received data and stops the associated calculation operations. After the control processor receives the calculation stop notification sent by the arithmetic processor, it performs a turn-off operation. The shakehand ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the arithmetic processor on the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0065] (Example 3) As shown in Figure 7, an embodiment of the present invention further provides a dual-processor device control method, wherein the dual processor includes a control processor and an arithmetic processor, and the method is implemented by the arithmetic processor and includes the following:

[0066] S31: Receive the pre-turn-off output pre-shakehand sent by the control processor.

[0067] S32: After completing the calculations on the received data, the associated calculation operations are stopped.

[0068] S33: By sending a calculation stop notification to the control processor, the control processor performs a turn-off operation after receiving the calculation stop notification.

[0069] To make it easier to understand, in the technical proposal according to this embodiment, when the control processor detects an arc during the control process of a dual-processor device, it sends a pre-turnoff output pre-shakehand to the arithmetic processor. Based on the pre-turnoff output pre-shakehand, the arithmetic processor completes the calculation of the received data and stops the associated calculation operations. After the control processor receives the calculation stop notification sent by the arithmetic processor, it performs a turn-off operation. The shakehand ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the arithmetic processor on the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0070] (Example 4) As an improvement to Example 3, as shown in Figure 8, the embodiment of the present invention further provides a dual-processor device control method, wherein the dual processor includes a control processor and an arithmetic processor, and the method is implemented by the arithmetic processor and includes the following:

[0071] S41: The arithmetic processor receives the pre-turn-off output pre-shakehand transmitted by the control processor.

[0072] S42: After completing the calculations on the received data, the arithmetic processor stops the associated calculation operations.

[0073] S43: The processing unit freezes the equipment operation data for the arc generation period.

[0074] S44: The arithmetic processor sends a calculation stop notification to the control processor, and the control processor performs a turn-off operation after receiving the calculation stop notification.

[0075] S45: The processing unit enters sleep mode.

[0076] S46: The arithmetic processor receives the pre-shakehand sent and restarted by the control processor.

[0077] S47: The arithmetic processor completes preparation for arithmetic recovery based on the restarted pre-shakehand.

[0078] S48: The arithmetic processor sends a recovery confirmation message to the control processor, which then recovers the acquisition of equipment operation data based on the recovery confirmation message.

[0079] S49: The arithmetic processor receives the device operation data transmitted by the control processor.

[0080] To make it easier to understand, in the technical proposal according to this embodiment, when the control processor detects an arc during the control process of a dual-processor device, it sends a pre-turnoff output pre-shakehand to the arithmetic processor. Based on the pre-turnoff output pre-shakehand, the arithmetic processor completes the calculation of the received data and stops the associated calculation operations. After the control processor receives the calculation stop notification sent by the arithmetic processor, it performs a turn-off operation. The shakehand ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the arithmetic processor on the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0081] (Example 5) As shown in Figure 9, an embodiment of the present invention further provides a control processor for a dual-processor device, which includes a pre-turn-off instruction module 51 for the arithmetic processor to stop the associated arithmetic operation based on the pre-turn-off output pre-shakehand when it detects arc generation, by sending a pre-turn-off output pre-shakehand to the arithmetic processor; a pre-turn-off execution module 52 for receiving an arithmetic stop notification sent by the arithmetic processor, the arithmetic stop notification being issued by the arithmetic processor after it has received the pre-turn-off output pre-shakehand and completed the calculation of the received data; and a turn-off module 53 for performing a turn-off operation.

[0082] In some selective embodiments, as shown in the dashed portion of the drawing, the control processor further includes a restart shakehand module 54 for the arithmetic processor to recover ready for arithmetic based on a restarted pre-shakehand, by sending a restarted pre-shakehand to the arithmetic processor when restart conditions are met, and a recovery confirmation module 55 for recovering the acquisition of equipment operation data, recovering the transmission of equipment operation data to the arithmetic processor, and, if the arithmetic processor is not in sleep mode, directly acquiring equipment operation data and transmitting equipment operation data to the arithmetic processor, wherein the recovery confirmation message is sent after the arithmetic processor has completed ready for arithmetic.

[0083] In some selective embodiments, as shown by the dashed lines in the drawings, the control processor further includes a first data freeze module 56 for freezing equipment operation data during the arc generation period, a first sleep start module 57 for the control processor to enter a sleep state after performing a turn-off operation, and a sleep determination module 58 for determining whether the arithmetic processor is in a sleep state.

[0084] The restart shakehand module 54 sending a restarted pre-shakehand to the arithmetic processor means that if the arithmetic processor is in a sleep state, the restart shakehand module 54 sends a restarted pre-shakehand to the arithmetic processor.

[0085] In some selective embodiments, the restart conditions include whether the turn-off time satisfies a predetermined turn-off time length and / or whether restart instruction information is received.

[0086] To make it easier to understand, in the technical proposal according to this embodiment, when the control processor detects an arc during the control process of a dual-processor device, it sends a pre-turnoff output pre-shakehand to the arithmetic processor. Based on the pre-turnoff output pre-shakehand, the arithmetic processor completes the calculation of the received data and stops the associated calculation operations. After the control processor receives the calculation stop notification sent by the arithmetic processor, it performs a turn-off operation. The shakehand ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the arithmetic processor on the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0087] (Example 6) As shown in Figure 10, an embodiment of the present invention further provides an arithmetic processor for a dual-processor device, which includes a pre-turn-off instruction receiving module 61 for receiving a pre-turn-off output pre-shakehand transmitted by a control processor; an arithmetic stop control module 62 for stopping the associated arithmetic operation after completing calculations on the received data; and an arithmetic stop notification module 63 for performing a turn-off operation after the control processor receives an arithmetic stop notification by sending an arithmetic stop notification to the control processor.

[0088] In some selective embodiments, as shown in the dashed lines in the drawings, the arithmetic processor includes a second data freeze module 64 for freezing equipment operation data during the arc generation period, a second sleep start module 65 for the arithmetic processor to enter a sleep state, a shakehand receive module 66 for receiving a pre-shakehand transmitted and restarted by the control processor, an arithmetic recovery module 67 for completing preparation for arithmetic recovery based on the restarted pre-shakehand, and a recovery message send module 68 for sending a recovery confirmation message to the control processor so that the control processor recovers the acquisition of equipment operation data and recovers the transmission of operation data to the equipment based on the recovery confirmation message. The system further includes an equipment data receiving module 69 for receiving equipment operation data transmitted by a control processor.

[0089] To make it easier to understand, in the technical proposal according to this embodiment, when the control processor detects an arc during the control process of a dual-processor device, it sends a pre-turnoff output pre-shakehand to the arithmetic processor. Based on the pre-turnoff output pre-shakehand, the arithmetic processor completes the calculation of the received data and stops the associated calculation operations. After the control processor receives the calculation stop notification sent by the arithmetic processor, it performs a turn-off operation. The shakehand ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the arithmetic processor on the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0090] (Example 7) As shown in Figure 11, the embodiment of the present invention further provides a dual-processor device which includes a control processor for the dual-processor device of Embodiment 5 and an arithmetic processor for the dual-processor device of Embodiment 6.

[0091] To make it easier to understand, in the technical proposal according to this embodiment, when the control processor detects an arc during the control process of a dual-processor device, it sends a pre-turnoff output pre-shakehand to the arithmetic processor. Based on the pre-turnoff output pre-shakehand, the arithmetic processor completes the calculation of the received data and stops the associated calculation operations. After the control processor receives the calculation stop notification sent by the arithmetic processor, it performs a turn-off operation. The shakehand ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the arithmetic processor on the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0092] (Example 8) As shown in Figure 12, this is a flowchart of a dual-processor device control method according to an embodiment disclosed in the present invention, the dual-processor device includes a control processor, an arithmetic processor and a shared memory, the shared memory is set with a turn-off instruction identifier, the method is implemented by the control processor and includes the following:

[0093] S81: When arc generation is detected, the turn-off operation is performed.

[0094] S82: By setting the turn-off instruction identifier in the shared memory to the turn-off state, the arithmetic processor skips acquiring the first equipment operation data based on the state of the turn-off instruction identifier, and the first equipment operation data is equipment operation data acquired by the control processor during the arc generation period.

[0095] To make it easier to understand, in the technical proposal according to this embodiment, in the PID control process based on dual processors, when the control processor detects an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to the turn-off state. Based on the state of the turn-off instruction identifier, the arithmetic processor skips acquiring equipment operation data acquired by the control processor during the arc period. By utilizing a data sharing mode in the shared memory, where the other CPU can still read even if one CPU writes and area protection occurs, both CPUs can acquire the changing data and operating status of the other CPU from the high-speed memory unit in the first hour, regardless of what work they are performing. This ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0096] (Example 9) As an improvement to Example 8, Figure 13 shows a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention, wherein the dual-processor device includes a control processor, an arithmetic processor and a shared memory, the shared memory being set with a turn-off instruction identifier, the method being implemented by the control processor and including the following:

[0097] S91: The control processor acquires the operation data of the second device.

[0098] S92: The control processor transmits second device operation data to the arithmetic processor via shared memory.

[0099] S93: When arc generation is detected, the control processor performs a turn-off operation.

[0100] S94: The control processor sets the turn-off instruction identifier in the shared memory to the turn-off state, and the arithmetic processor skips acquiring the first equipment operation data based on the state of the turn-off instruction identifier. The first equipment operation data is equipment operation data acquired by the control processor during the arc generation period.

[0101] S95: The control processor freezes the equipment operation data for the arc generation period.

[0102] S96: The control processor enters sleep mode.

[0103] S97: If the restart conditions are met, the control processor will restart.

[0104] S98: The control processor sets the turn-off instruction identifier in the shared memory to a normal state and restores the execution of S91.

[0105] In some selective embodiments, the control processor stores the second device operation data in shared memory, and the arithmetic processor can retrieve the second device operation data from the shared memory.

[0106] In some selective embodiments, the restart conditions include whether the turn-off time satisfies a predetermined turn-off time length and / or whether restart instruction information is received.

[0107] It should be noted that the embodiments described herein are merely illustrative examples of specific embodiments under the concept of the present invention, and the order of execution of the steps in each embodiment is not limited to the embodiments described herein. In carrying out a specific process, a person skilled in the art can adjust the order of execution of each step based on the actual situation. For example, S91 and S97 do not necessarily have a causal relationship or sequence, and the restart operation in S97 may be described after the acquisition of the second device operation data in S91.

[0108] To make it easier to understand, in the technical proposal according to this embodiment, in the PID control process based on dual processors, when the control processor detects an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to the turn-off state. Based on the state of the turn-off instruction identifier, the arithmetic processor skips acquiring equipment operation data acquired by the control processor during the arc period. By utilizing a data sharing mode in the shared memory, where the other CPU can still read even if one CPU writes and area protection occurs, both CPUs can acquire the changing data and operating status of the other CPU from the high-speed memory unit in the first hour, regardless of what work they are performing. This ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0109] (Example 10) As shown in Figure 14, an embodiment of the present invention further provides a dual-processor device control method, the dual-processor device comprising a control processor, an arithmetic processor and a shared memory, the shared memory being set with a turn-off instruction identifier, the method being implemented by the arithmetic processor and including the following:

[0110] S101: Retrieve the status of the turn-off instruction identifier in shared memory.

[0111] S102: If the turn-off instruction identifier is in the turn-off state, the acquisition of the first equipment operation data is skipped based on the state of the turn-off instruction identifier, and the first equipment operation data is equipment operation data acquired by the control processor during the arc generation period.

[0112] To make it easier to understand, in the technical proposal according to this embodiment, in the PID control process based on dual processors, when the control processor detects an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to the turn-off state. Based on the state of the turn-off instruction identifier, the arithmetic processor skips acquiring equipment operation data acquired by the control processor during the arc period. By utilizing a data sharing mode in the shared memory, where the other CPU can still read even if one CPU writes and area protection occurs, both CPUs can acquire data on the other CPU's changes or operating status from the high-speed memory unit in the first hour, regardless of what work they are performing. This ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0113] (Example 11) As an improvement to Example 10, as shown in Figure 15, the embodiment of the present invention further provides a dual-processor device control method, wherein the dual-processor device includes a control processor, an arithmetic processor and a shared memory, the shared memory being set with a turn-off instruction identifier, the method being implemented by the arithmetic processor and including the following:

[0114] S111: If the restart conditions are met, the arithmetic processor restarts and resumes execution of S42.

[0115] S112: The arithmetic processor obtains the state of the turn-off instruction identifier in the shared memory.

[0116] S113: If the turn-off instruction identifier is in a normal state, the arithmetic processor obtains the operation data of the first device from the shared memory.

[0117] S114: The arithmetic processor performs control parameter calculations based on the operation data of the first device.

[0118] S115: The arithmetic processor transmits the calculated control parameters to the control processor via shared memory.

[0119] S116: If the turn-off instruction identifier is in the turn-off state, the arithmetic processor skips acquiring the first equipment operation data based on the state of the turn-off instruction identifier, and the first equipment operation data is equipment operation data acquired by the control processor during the arc generation period.

[0120] S117: The processing unit freezes the equipment operation data for the arc generation period.

[0121] S118: If the turn-off instruction identifier is in the turn-off state, the arithmetic processor enters sleep mode and waits for the restart condition to be triggered.

[0122] To make it easier to understand, in the technical proposal according to this embodiment, in the PID control process based on dual processors, when the control processor detects an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to the turn-off state. Based on the state of the turn-off instruction identifier, the arithmetic processor skips acquiring equipment operation data acquired by the control processor during the arc period. By utilizing a data sharing mode in the shared memory, where the other CPU can still read even if one CPU writes and area protection occurs, both CPUs can acquire the changing data and operating status of the other CPU from the high-speed memory unit in the first hour, regardless of what work they are performing. This ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0123] (Example 12) Embodiments of the present invention further provide a dual-processor device comprising a control processor, an arithmetic processor, and a shared memory, the shared memory being set with a turn-off instruction identifier, and as shown in Figure 16, the control processor, upon detecting arc generation, includes a turn-off instruction module 121 for performing a turn-off operation. A turn-off state setting module 122 is provided for the arithmetic processor to skip acquiring first equipment operation data based on the state of the turn-off instruction identifier by setting the turn-off instruction identifier in shared memory to the turn-off state setting module 122, wherein the first equipment operation data is equipment operation data acquired by the control processor during the arc generation period.

[0124] In some selective embodiments, as shown in the dashed lines in the drawings, the device includes an operation data acquisition module 123 for acquiring operation data of a second device, An operation data transmission module 124 transmits second device operation data to the arithmetic processor via shared memory, recovers the acquisition, and transmits the second device operation data to the arithmetic processor via shared memory, thereby enabling the arithmetic processor to acquire second device operation data from shared memory based on the state of the turn-off instruction identifier. A first data freezing module 125 for freezing equipment operation data during the arc generation period, A first sleep module 126 for entering sleep mode, If the restart conditions are met, the first restart module 127 for restarting, The system may further include a shared identifier setting module 128 for setting the turn-off instruction identifier in the shared memory to a normal state.

[0125] In some selective embodiments, the restart conditions include whether the turn-off time satisfies a predetermined turn-off time length and / or whether restart instruction information is received.

[0126] To make it easier to understand, in the technical proposal according to this embodiment, in the PID control process based on dual processors, when the control processor detects an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to the turn-off state. Based on the state of the turn-off instruction identifier, the arithmetic processor skips acquiring equipment operation data acquired by the control processor during the arc period. By utilizing a data sharing mode in the shared memory, where the other CPU can still read even if one CPU writes and area protection occurs, both CPUs can acquire the changing data and operating status of the other CPU from the high-speed memory unit in the first hour, regardless of what work they are performing. This ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0127] (Example 13) Embodiments of the present invention further provide a dual-processor device comprising a control processor, an arithmetic processor and a shared memory, wherein a turn-off instruction identifier is set in the shared memory, and as shown in Figure 17, the arithmetic processor includes a turn-off identifier acquisition module 131 for acquiring the state of the turn-off instruction identifier in the shared memory, A turn-off data processing module 132 for skipping the acquisition of first equipment operation data based on the state of the turn-off instruction identifier when the turn-off instruction identifier is in the turn-off state, wherein the first equipment operation data is equipment operation data acquired by the control processor during the arc generation period.

[0128] In some selective embodiments, as shown in the dashed lines in the drawings, the device includes an operation data extraction module 133 for acquiring first device operation data from shared memory when the turn-off instruction identifier is in a normal state, and for recovering the acquisition of the state of the turn-off instruction identifier in shared memory after a restart. A control parameter calculation module 134 for calculating control parameters based on the operation data of the first device, A control parameter transmission module 135 for transmitting calculated control parameters to the control processor via shared memory, If the turn-off instruction identifier is in the turn-off state, the second sleep module 1313 enters the sleep state, If the restart conditions are met, the second restart module 137 for restarting is activated, The system further includes a second data freezing module 138 for freezing equipment operation data during the arc generation period.

[0129] To make it easier to understand, in the technical proposal according to this embodiment, in the PID control process based on dual processors, when the control processor detects an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to the turn-off state. Based on the state of the turn-off instruction identifier, the arithmetic processor skips acquiring equipment operation data acquired by the control processor during the arc period. By utilizing a data sharing mode in the shared memory, where the other CPU can still read even if one CPU writes and area protection occurs, both CPUs can acquire the changing data and operating status of the other CPU from the high-speed memory unit in the first hour, regardless of what work they are performing. This ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0130] (Example 14) As shown in Figure 18, the embodiment of the present invention further provides a dual-processor device which includes a shared memory 141, a control processor 142 and an arithmetic processor 143 in the dual-processor device, and a turn-off instruction identifier is set in the shared memory 141.

[0131] To facilitate the reader's understanding, the following explanation of dual-processor devices will be detailed, including the timing diagrams in Figures 19, 20, and 21. CPUA represents the control processor, CPUB the arithmetic processor, RAM the shared memory, and FLAG the turn-off instruction identifier. In normal mode, PID control of a dual-processor device includes the following process: CPUA did not detect an arc and did not rewrite the CPUA activation flag in RAM. CPUA transmits the data necessary for PID calculation and writes it to RAM. CPUB reads the CPUA activation FLAG in RAM and determines that it is ENABLE. CPUB reads RAM, retrieves data, and performs PID calculations. The CPUB writes the circuit control parameters generated by the calculations to RAM. CPUA reads from RAM to obtain parameters and controls circuit operation and power output.

[0132] PID control of a dual-processor device in shared memory mode includes the following steps: At the first timing, CPUA detects an arc and rewrites the CPUA activation FLAG in RAM to DISABLE. CPUA performs the turn-off output. CPUB reads the CPUA activation flag in RAM and determines that it is disabled. CPUB does not read RAM and does not perform PID calculations at the current timing.

[0133] Furthermore, data can be frozen, and CPUB or dual CPUs can enter a limited sleep state.

[0134] At the Nth timing, if N is an integer > 1, CPUA restarts the control circuit and outputs power. CPUA rewrites the CPUA operation FLAG in RAM, CPUA transmits the data necessary for PID calculation and writes it to RAM. CPUB reads the CPUA activation FLAG in RAM and determines that it is ENABLE. CPUB reads RAM, retrieves data, and performs PID calculations. The CPUB writes the circuit control parameters generated by the calculations into RAM.

[0135] To make it easier to understand, in the technical proposal according to this embodiment, in the PID control process based on dual processors, when the control processor detects an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to the turn-off state. Based on the state of the turn-off instruction identifier, the arithmetic processor skips acquiring equipment operation data acquired by the control processor during the arc period. By utilizing a data sharing mode in the shared memory, where the other CPU can still read even if one CPU writes and area protection occurs, both CPUs can acquire the changing data and operating status of the other CPU from the high-speed memory unit in the first hour, regardless of what work they are performing. This ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0136] (Example 15) The dual-processor device according to the embodiments disclosed in the present invention has the same schematic diagram of its structure as Figure 11, and the device is, When an arc occurs, a control processor 151 (not shown) performs a specified operation, the specified operation including at least one of operation 1, which stops the acquisition of equipment operation data by the calculation processor 152 (not shown), and operation 2, which sends a turn-off calculation instruction to the calculation processor 152. A processing unit 152 ensures that the control processor 11 obtains accurate control parameters by determining an operation policy based on the results generated by a specified operation, wherein the results generated by the specified operation include whether or not equipment operation data has been obtained and whether or not a turn-off calculation instruction has been obtained, and the operation policy is Method 1 for interrupting the calculation operation of related control parameters, The system includes an arithmetic processor 152 that includes at least one of the following methods: 1) stopping the transmission of the relevant control parameters, once the calculation is complete, to the control processor 151.

[0137] To make it easier to understand, in the technical proposal according to this embodiment, when the control processor detects arc generation during the control process of a dual-processor device, it can stop the acquisition of device operation data by the processor being computed and can also send a turn-off computation instruction to the computation processor. The computation processor, based on whether or not it has acquired the device operation data, or based on whether or not it has received a turn-off computation instruction, decides whether or not to interrupt the computation operation of the relevant control parameters, or whether or not to stop sending the calculated relevant control parameters to the control processor, thereby ensuring that the control processor acquires accurate control parameters and prevents arc generation. When the control processor turns off the circuit, the data between the dual processors can maintain good accuracy, stop PID calculations in a timely manner, avoid extending the turn-off occasion point, reduce situations where data is discarded, avoid disruptive operation of the entire circuit caused by the other end still running when one end of the circuit is turned off, and unless the entire PID calculation has started, the calculation may be interrupted or the operation parameters for which the calculation has been completed may not be transmitted, applicable to instructions, shake hands or data sharing, and when turning off, the data is frozen to ensure the stability and consistency of data transmission between the control processor and the arithmetic processor, avoid disruptive operation of the entire circuit caused by the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensure data accuracy between the control processor and the arithmetic processor when arcing occurs.

[0138] (Example 16) An improvement to Example 15 is that the schematic diagram is the same as that of Figure 18, and another dual-processor device according to the embodiments disclosed in the present invention is A control processor that detects the occurrence of an arc and executes a specified operation, wherein the specified operation is: Operation 1 stops the acquisition of device operation data by the processor performing the calculations, A control processor that includes at least one of the following: operation 2, which sends a turn-off operation instruction to the arithmetic processor; A processing unit that ensures the control processor 21 obtains accurate control parameters by determining an operation policy based on the results generated by a specified operation, wherein the results generated by the specified operation include whether or not equipment operation data has been obtained and whether or not a turn-off calculation instruction has been obtained, and the operation policy is Method 1 for interrupting the calculation operation of related control parameters, The system includes an arithmetic processor that includes at least one of the following methods: 1) stopping the transmission of the relevant control parameters, once the calculation is complete, to the control processor.

[0139] In some selective embodiments, the control processor stops the acquisition of device operation data by the processor being computed and simultaneously performs a turn-off operation.

[0140] It should be explained that the method by which the arithmetic control module acquires device operation data may be either the control processor spontaneously transmitting the device operation data to the arithmetic processor, or the arithmetic processor reading the device operation data from the control processor. In the embodiments of the present invention, the control processor stopping the acquisition of device operation data by the processor being computed may be understood as the control processor stopping spontaneously transmitting the device operation data to the arithmetic processor, or as the arithmetic processor stopping spontaneously reading the device operation data from the arithmetic processor.

[0141] In some selective embodiments, the apparatus further includes a shared memory in which a turn-off instruction identifier is set, the state of the turn-off instruction identifier includes a turn-off state and a normal state, and the control processor sending a turn-off arithmetic instruction to an arithmetic processor includes the control processor performing a turn-off operation and setting the state of the turn-off instruction identifier to the turn-off state; and an arithmetic processor that retrieves the state of the turn-off instruction identifier from the shared memory and considers the turn-off state to be a turn-off arithmetic instruction.

[0142] In some selective embodiments, the control processor retrieves device operation data from the processor being computed via shared memory, and the computed processor retrieves device operation data from shared memory and transmits control parameters to the control processor via shared memory.

[0143] In some selective embodiments, the control processor sends a turn-off operation instruction to the arithmetic processor. The control processor sends a pre-turn-off output pre-shakehand to the arithmetic processor, The arithmetic processor receives a pre-turn-off output pre-shakehand, stops the associated arithmetic operation based on the pre-turn-off output pre-shakehand, completes the calculation of the received data, and then sends a notification to the control processor that the calculation has stopped. The control processor performs a turn-off operation after receiving a notification from the arithmetic processor that the calculation has stopped.

[0144] In some selective embodiments, when the control processor detects an arc, it queries for any unsent control parameters and stops transmitting any currently unsent control parameters.

[0145] In some selective embodiments, if the arithmetic processor has not received the device operation data transmitted by the control processor, all current control parameter calculations are stopped.

[0146] In some selective embodiments, the control parameter calculation includes, in sequence, a PID calculation stage and a digital-to-analog conversion stage, and the arithmetic processor determining the operation policy based on the results of the specified operation includes, after the arithmetic processor receives a turn-off calculation instruction sent by the control processor, determining the current progress of the control parameter calculation, and, if the relevant equipment operation data has been acquired and analog-to-digital conversion has started but PID calculation has not started, not performing PID calculation and subsequent digital-to-analog conversion, and if the relevant equipment operation data has been acquired and PID calculation has started but digital-to-analog calculation has not started, now completing the PID calculation.

[0147] In some selective embodiments, if the arithmetic processor has not received the device operation data transmitted by the control processor, or if the turn-off instruction identifier obtained by the arithmetic processor from shared memory indicates a turn-off state, the arithmetic processor enters a limited sleep state.

[0148] In some selective embodiments, after the arithmetic processor has stopped the relevant arithmetic operation based on a pre-turn-off output pre-shakehand, the arithmetic processor enters a limited sleep state.

[0149] In some selective embodiments, the shared memory includes a shared memory in which a turn-off instruction identifier is set, the state of the turn-off instruction identifier includes a turn-off state and a normal state, the control processor enters a limited sleep state after performing a turn-off operation, the control processor restarts if restart conditions are met, sets the turn-off instruction identifier in the shared memory to the normal state, and recovers to transmit the reacquired device operation data to the arithmetic processor via the shared memory, and the arithmetic processor recovers to acquire the state of the turn-off instruction identifier in the shared memory.

[0150] In some selective embodiments, the control processor enters a limited sleep state after performing a turn-off operation. If the restart conditions are met, the control processor sends a restarted pre-shakehand to the arithmetic processor, receives a recovery confirmation message fed back by the arithmetic processor, recovers the acquisition of equipment operation data, recovers the acquisition of equipment operation data by the processor being calculated, the arithmetic processor receives the restarted pre-shakehand sent by the control processor, completes preparation for calculation recovery based on the restarted pre-shakehand, and sends a recovery confirmation message to the control processor.

[0151] In some selective embodiments, the arithmetic processor freezes the acquired equipment operation data for the arcing period before entering a limited sleep state, and the control processor also freezes the equipment operation data for the arcing period before entering a limited sleep state.

[0152] To make it easier to understand, in the technical proposal according to this embodiment, when the control processor detects arc generation during the control process of a dual-processor device, it can stop the acquisition of device operation data by the processor being computed, and can also send a turn-off computation instruction to the computation processor. The computation processor then decides whether or not to interrupt the computation operation of the relevant control parameters, or whether or not to stop sending the calculated relevant control parameters to the control processor, based on whether or not it has acquired the device operation data, or whether or not it has received the turn-off computation instruction, thereby ensuring that the control processor acquires accurate control parameters and prevents arc generation. When the control processor turns off the circuit, the data between the dual processors can maintain good accuracy, stop PID calculations in a timely manner, avoid extending the turn-off occasion point, reduce situations where data is discarded, avoid disruptive operation of the entire circuit caused by the other end still running when one end of the circuit is turned off, and unless the entire PID calculation has started, the calculation may be interrupted or the operation parameters for which the calculation has been completed may not be transmitted, applicable to instructions, shake hands or data sharing, and when turning off, the data is frozen to ensure the stability and consistency of data transmission between the control processor and the arithmetic processor, avoid disruptive operation of the entire circuit caused by the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensure data accuracy between the control processor and the arithmetic processor when arcing occurs.

[0153] (Example 17) As shown in Figure 22, an embodiment of the present invention further provides a dual-processor device control method, the method being used in a dual-processor device, the dual processor including a control processor and an arithmetic processor, the method being used in the control processor, and including the following:

[0154] S171: When an arc is detected, the control processor performs a specified operation, which includes at least one of operation 1, which stops the acquisition of equipment operation data by the calculation processor, and operation 2, which sends a turn-off calculation instruction to the calculation processor.

[0155] S172: The arithmetic processor ensures that the control processor obtains accurate control parameters by determining an operation policy based on the results of a specified operation, the results of a specified operation include whether or not equipment operation data has been obtained and whether or not a turn-off operation instruction has been obtained, and the operation policy includes at least one of method 1, which interrupts the calculation operation of the relevant control parameters, and method 2, which stops transmitting the calculated relevant control parameters to the control processor.

[0156] In some selective embodiments, when the control processor detects an arc, it queries for any unsent control parameters and stops transmitting any currently unsent control parameters.

[0157] In some selective embodiments, the aforementioned designated operation further includes the control processor stopping the acquisition of device operation data by the processor being computed, while simultaneously performing a turn-off operation.

[0158] In some selective embodiments, the dual-processor device further includes a shared memory in which a turn-off instruction identifier is set, the state of the turn-off instruction identifier includes a turn-off state and a normal state, and in such embodiments, the control processor sending a turn-off arithmetic instruction to the arithmetic processor includes the control processor performing a turn-off operation and setting the state of the turn-off instruction identifier to the turn-off state, the arithmetic processor retrieving the state of the turn-off instruction identifier from the shared memory and considering the turn-off state as a turn-off arithmetic instruction.

[0159] In some selective embodiments, the control processor transmits device operation data to the arithmetic processor via shared memory.

[0160] In some selective embodiments, the control processor sending a turn-off operation instruction to the arithmetic processor means that the control processor sends a pre-turn-off output pre-shakehand to the arithmetic processor, and after receiving the operation stop notification sent by the arithmetic processor, it performs the turn-off operation and determines the operation policy based on whether or not the arithmetic processor has acquired equipment operation data.

[0161] In some selective embodiments, the control processor, after performing a turn-off operation, enters a limited sleep state, restarts if the restart conditions are met, sets the turn-off instruction identifier in shared memory to a normal state, and recovers the ability to send the device operation data to be reacquired to the arithmetic processor via shared memory; or, if the restart conditions are met, sends a restarted pre-shakehand to the arithmetic processor, recovers the acquisition of device operation data after receiving a recovery confirmation message fed back by the arithmetic processor, and recovers the acquisition of device operation data by the processor being computed.

[0162] To make it easier to understand, in the technical proposal according to this embodiment, when the control processor detects arc generation during the control process of a dual-processor device, it can stop the acquisition of device operation data by the processor being computed, and can also send a turn-off computation instruction to the computation processor. The computation processor then decides whether or not to interrupt the computation operation of the relevant control parameters, or whether or not to stop sending the calculated relevant control parameters to the control processor, based on whether or not it has acquired the device operation data, or whether or not it has received the turn-off computation instruction, thereby ensuring that the control processor acquires accurate control parameters and prevents arc generation. When the control processor turns off the circuit, the data between the dual processors can maintain good accuracy, stop PID calculations in a timely manner, avoid extending the turn-off occasion point, reduce situations where data is discarded, avoid disruptive operation of the entire circuit caused by the other end still running when one end of the circuit is turned off, and unless the entire PID calculation has started, the calculation may be interrupted or the operation parameters for which the calculation has been completed may not be transmitted, applicable to instructions, shake hands or data sharing, and when turning off, the data is frozen to ensure the stability and consistency of data transmission between the control processor and the arithmetic processor, avoid disruptive operation of the entire circuit caused by the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensure data accuracy between the control processor and the arithmetic processor when arcing occurs.

[0163] (Example 18) As shown in Figure 23, an embodiment of the present invention further provides a dual-processor device control method, the method being used in a dual-processor device, the dual processor including a control processor and an arithmetic processor, the method being used in the arithmetic processor, and including the following:

[0164] S181: The arithmetic processor obtains the result that occurs after the control processor performs a specified operation, the specified operation includes at least one of operation 1, which stops the processor from obtaining device operation data, and operation 2, which sends a turn-off operation instruction to the arithmetic processor, and the result that occurs as a result of the specified operation includes whether or not the device operation data was obtained and whether or not the turn-off operation instruction was obtained.

[0165] S182: The arithmetic processor ensures that the control processor obtains accurate control parameters by determining an operation policy based on the results of a specified operation, and the operation policy includes at least one of two methods: method 1, which interrupts the calculation operation of the relevant control parameters, and method 2, which stops sending the relevant control parameters, once the calculation is complete, to the control processor.

[0166] In some selective embodiments, the dual-processor device further includes a shared memory in which a turn-off instruction identifier is set, the state of the turn-off instruction identifier includes a turn-off state and a normal state, in which the control processor sets the state of the turn-off instruction identifier to the turn-off state after performing a turn-off operation, and the arithmetic processor retrieves the state of the turn-off instruction identifier from the shared memory and considers the turn-off state to be a turn-off arithmetic instruction.

[0167] In some selective embodiments, the arithmetic processor retrieves device operation data from shared memory and transmits control parameters to the control processor via shared memory.

[0168] In some selective embodiments, when the control processor sends a pre-turnoff output pre-shakehand to the arithmetic processor, the arithmetic processor receives the pre-turnoff output pre-shakehand, stops the associated arithmetic operation based on the pre-turnoff output pre-shakehand, completes the calculations on the received data, and then sends an operation stop notification to the control processor. The control processor then performs a turnoff operation after receiving the operation stop notification sent by the arithmetic processor.

[0169] In some selective embodiments, if the arithmetic processor has not acquired the device operation data from the control processor, it stops all current control parameter calculations.

[0170] In some selective embodiments, the control parameter calculation includes, in sequence, a PID calculation stage and a digital-to-analog conversion stage, and the arithmetic processor determining the operation policy based on the results of the specified operation includes, after the arithmetic processor receives a turn-off calculation instruction sent by the control processor, determining the current progress of the control parameter calculation, and, if the relevant equipment operation data has been acquired and analog-to-digital conversion has started but PID calculation has not started, not performing PID calculation and subsequent digital-to-analog conversion, and if the relevant equipment operation data has been acquired and PID calculation has started but digital-to-analog calculation has not started, now completing the PID calculation.

[0171] In some selective embodiments, if the arithmetic processor has not acquired device operation data from the control processor, or if the turn-off instruction identifier acquired by the arithmetic processor from shared memory indicates a turn-off state, the arithmetic processor enters a limited sleep state.

[0172] In some selective embodiments, after the arithmetic processor has stopped the relevant arithmetic operation based on a pre-turn-off output pre-shakehand, the arithmetic processor enters a limited sleep state.

[0173] In some selective embodiments, the control processor recovers to set the turn-off instruction identifier in shared memory to a normal state and to send the reacquired device operation data to the arithmetic processor via shared memory, the arithmetic processor recovers to acquire the state of the turn-off instruction identifier in shared memory, or, after acquiring the pre-shakehand sent and restarted by the control processor, the arithmetic processor completes preparation for arithmetic recovery based on the restarted pre-shakehand and sends a recovery confirmation message to the control processor.

[0174] In some selective embodiments, the computing processor freezes the acquired equipment operation data for the arc generation period before entering a limited sleep state.

[0175] To make it easier to understand, in the technical proposal according to this embodiment, when the control processor detects arc generation during the control process of a dual-processor device, it can stop the acquisition of device operation data by the processor being computed, and can also send a turn-off computation instruction to the computation processor. The computation processor then decides whether or not to interrupt the computation operation of the relevant control parameters, or whether or not to stop sending the calculated relevant control parameters to the control processor, based on whether or not it has acquired the device operation data, or whether or not it has received the turn-off computation instruction, thereby ensuring that the control processor acquires accurate control parameters and prevents arc generation. When the control processor turns off the circuit, the data between the dual processors can maintain good accuracy, stop PID calculations in a timely manner, avoid extending the turn-off occasion point, reduce situations where data is discarded, avoid disruptive operation of the entire circuit caused by the other end still running when one end of the circuit is turned off, and unless the entire PID calculation has started, the calculation may be interrupted or the operation parameters for which the calculation has been completed may not be transmitted, applicable to instructions, shake hands or data sharing, and when turning off, the data is frozen to ensure the stability and consistency of data transmission between the control processor and the arithmetic processor, avoid disruptive operation of the entire circuit caused by the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensure data accuracy between the control processor and the arithmetic processor when arcing occurs.

[0176] (Example 19) To facilitate the reader's understanding, the dual-processor device and its control method according to the present invention will be described below with specific examples.

[0177] In this embodiment, CPUA is a control processor and CPUB is an arithmetic processor. The two CPUs operate independently, each controlling the control circuit and PID calculation circuit connected to them. Between the dual CPUs, instructions (COMMAND / ORDER), shake hands, flags, or data sharing methods are used to cause CPUB to perform a PID interrupt operation. The entire PID calculation block is divided into three stages: the analog-to-digital conversion stage, the PID calculation stage, and the digital-to-analog conversion stage, i.e., DC-PID-DAC.

[0178] The overall PID control flow is as follows:

[0179] At the first timing, CPUA transmits the data necessary for PID calculation to CPUB. CPUB acquires data and performs PID calculations. The CPUA detects the arc and sends a turn-off instruction or rewrite flag. The CPUB receives an instruction or flag and, depending on the current state of operation, determines at what stage to interrupt the calculation. If it is between ADC and PID, the calculation after PID is stopped. If the PID period is before the DAC, the calculation is completed, but the calculation data is not output.

[0180] Or, When the CPUA decides to turn off, it will not transmit any data or information. At the time CPUB acquired the data, it had not yet acquired CPUA's data or information. Alternatively, if updated data or information has not been retrieved from the shared RAM, all PID calculations are directly interrupted.

[0181] At the Nth timing, N is an integer > 1. CPUA restarts the control circuit and outputs power. CPUA transmits the data necessary for PID calculation to CPUB. CPUB acquires data and performs PID calculations.

[0182] Or, CPUA restarts the control circuit and outputs power. CPUA rewrites the CPUA operation FLAG in RAM, CPUA transmits the data necessary for PID calculation and writes it to RAM. CPUB reads the CPUA activation FLAG in RAM and determines that it is ENABLE. CPUB reads RAM, retrieves data, and performs PID calculations. The CPUB writes the circuit control parameters generated by the calculations into RAM.

[0183] To make it easier to understand, in the technical proposal according to this embodiment, when the control processor detects arc generation during the control process of a dual-processor device, it can stop the acquisition of device operation data by the processor being computed, and can also send a turn-off computation instruction to the computation processor. The computation processor then decides whether or not to interrupt the computation operation of the relevant control parameters, or whether or not to stop sending the calculated relevant control parameters to the control processor, based on whether or not it has acquired the device operation data, or whether or not it has received the turn-off computation instruction, thereby ensuring that the control processor acquires accurate control parameters and prevents arc generation. When the control processor turns off the circuit, the data between the dual processors can maintain good accuracy, stop PID calculations in a timely manner, avoid extending the turn-off occasion point, reduce situations where data is discarded, avoid disruptive operation of the entire circuit caused by the other end still running when one end of the circuit is turned off, and unless the entire PID calculation has started, the calculation may be interrupted or the operation parameters for which the calculation has been completed may not be transmitted, applicable to instructions, shake hands or data sharing, and when turning off, the data is frozen to ensure the stability and consistency of data transmission between the control processor and the arithmetic processor, avoid disruptive operation of the entire circuit caused by the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensure data accuracy between the control processor and the arithmetic processor when arcing occurs.

[0184] (Example 20) Based on the same technical concept, the present embodiment further provides a computer device comprising memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the dual-processor device control method described in any one of the above items is realized.

[0185] Here, memory includes at least one readable storage medium, including flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, memory may be an internal storage unit of the OTT video traffic monitoring system, such as a hard disk. In other embodiments, memory may be an external storage device of the OTT video traffic monitoring system, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Memory Card.

[0186] Furthermore, the memory may include internal and external storage units of the OTT video traffic monitoring system. The memory can be used not only to store various data such as application software installed on the OTT video service monitoring system and the code of the OTT video service monitoring program, but also to temporarily store output data or output data.

[0187] In some embodiments, the processor may be a central processing unit, controller, microcontroller, microprocessor, or other data processing chip that executes program code or processing data stored in memory, for example, an OTT video traffic monitoring program.

[0188] To make it easier to understand, in the technical proposal according to this embodiment, in the PID control process based on dual processors, when the control processor detects an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to the turn-off state. Based on the state of the turn-off instruction identifier, the arithmetic processor skips acquiring equipment operation data acquired by the control processor during the arc period. By utilizing a data sharing mode in the shared memory, where the other CPU can still read even if one CPU writes and area protection occurs, both CPUs can acquire the changing data and operating status of the other CPU from the high-speed memory unit in the first hour, regardless of what work they are performing. This ensures the stability and consistency of data transmission between the control processor and the arithmetic processor, avoids disruptive operation of the entire circuit due to the other end's arithmetic processor still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures data accuracy between the control processor and the arithmetic processor when an arc occurs.

[0189] Embodiments disclosed in the present invention further provide a computer-readable storage medium in which a computer program is stored, and when the computer program is executed by a processor, the steps of the dual-processor device control method described in the above-described embodiment are performed. The storage medium may be a volatile or non-volatile computer-readable storage medium. The computer program product of the dual-processor device control method according to the embodiments disclosed in the present invention includes a computer-readable storage medium that stores program code, and the instructions contained in the program code may be used to perform the steps of the dual-processor device control method described in the above-described embodiment, for which specific examples should be found in the above-described embodiment, and will not be described further here.

[0190] Embodiments disclosed in the present invention further provide computer programs that, when executed by a processor, realize any of the methods of the embodiments described above. The computer program product is specifically realized in hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically realized as a computer storage medium, and in another optional embodiment, the computer program product is specifically realized as a software product, such as a software development kit (SDK).

[0191] To ensure understanding, identical or similar parts in each of the above embodiments can refer to one another, and content not described in detail in some embodiments can refer to identical or similar content in other embodiments.

[0192] In this description of the present invention, terms such as "first," "second," etc., are used solely for explanatory purposes and should not be understood as indicating or implying relative importance. Furthermore, unless otherwise specified, "multiple" in this description means at least two.

[0193] A flowchart or any description of a process or method otherwise described herein may be understood as representing a module, segment, or portion containing one or more executable instruction codes for implementing a particular logical function or step in a process, and the scope of preferred embodiments of the present invention includes other implementations, which may not be in the order shown or discussed, and which include performing functions essentially concurrently or in reverse order depending on the relevant functions, as should be understood by those skilled in the art to which embodiments of the present invention belong.

[0194] It should be understood that each part of the present invention may be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, a plurality of steps or methods may be implemented by software or firmware stored in memory and executed by an appropriate instruction execution system. For example, if implemented in hardware, as in other embodiments, it can be implemented by any or a combination of technologies known in the art, such as discrete logic circuits having logic gate circuits for implementing logic functions for data signals, application-specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), and field-programmable gate arrays (FPGAs).

[0195] Those skilled in the art will understand that all or part of the steps included in the above embodiment can be completed by instructing the relevant hardware by a program, which may be stored on a computer-readable storage medium, and when the program is executed, it includes one or a combination of the steps of the embodiment of the method.

[0196] In each embodiment of the present invention, each functional unit may be integrated into a single processor, each unit may exist physically independently, or two or more units may be integrated into a single module. The integrated module may be implemented in hardware form or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may be stored in a computer-readable storage medium.

[0197] The above-mentioned storage medium may be read-only memory, magnetic disk, optical disk, or the like.

[0198] In this specification, any description referring to terms such as “one embodiment,” “several embodiments,” “example,” “specific example,” or “several examples” means that the specific features, structures, materials, or properties described with reference to such embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or properties described may be combined in an appropriate manner in any one or more embodiments or examples.

[0199] Although embodiments of the present invention have been described above, it should be understood that the above embodiments are illustrative and do not limit the present invention, and those skilled in the art can modify, alter, substitute, and transform the above embodiments within the scope of the present invention.

Claims

1. A dual-processor device control method, The dual processor mentioned above includes a control processor and an arithmetic processor. The above method is implemented by the control processor, Upon detecting the occurrence of an arc, a pre-turn-off output pre-shakehand is sent to the arithmetic processor, causing the arithmetic processor to stop the associated arithmetic operations based on the pre-turn-off output pre-shakehand; The steps include receiving a calculation stop notification transmitted by the arithmetic processor, the calculation stop notification being issued by the arithmetic processor after it has received the pre-turn-off output pre-shakehand and completed the calculation of the received data, A dual-processor device control method characterized by comprising the step of performing a turn-off operation.

2. The aforementioned method, If the restart conditions are met, the process includes sending a restarted pre-shakehand to the arithmetic processor, causing the arithmetic processor to recover its readiness for calculation based on the restarted pre-shakehand, The dual-processor device control method according to claim 1, further comprising the steps of: receiving a recovery confirmation message fed back by the arithmetic processor, recovering the acquisition of device operation data, and recovering the transmission of the device operation data to the arithmetic processor, wherein the recovery confirmation message is transmitted after the arithmetic processor has completed preparation for calculation.

3. Before sending the restarted pre-shakehand to the aforementioned processing unit, The process further includes determining whether the arithmetic processor is in a sleep state, The dual-processor device control method according to claim 2, characterized in that sending a restarted pre-shakehand to the arithmetic processor means sending a restarted pre-shakehand to the arithmetic processor when the arithmetic processor is in a sleep state.

4. Before sending the restarted pre-shakehand to the aforementioned processing unit, The dual-processor device control method according to claim 3, further comprising the step of directly acquiring the device operation data and transmitting the device operation data to the arithmetic processor if the arithmetic processor is not in a sleep state.

5. The aforementioned restart conditions are: Whether the turn-off time meets the predetermined turn-off time length, The dual-processor device control method according to claim 2, characterized in that it includes and / or whether or not to receive restart instruction information.

6. The dual-processor device control method according to claim 5, further comprising the step of entering a sleep state after performing a turn-off operation.

7. Before entering sleep mode, The dual-processor equipment control method according to claim 6, further comprising the step of freezing equipment operation data during the arc generation period.

8. A control processor for a dual-processor device, A pre-turn-off instruction module, which detects arc generation and sends a pre-turn-off output pre-shakehand to the arithmetic processor so that the arithmetic processor stops the associated arithmetic operation based on the pre-turn-off output pre-shakehand, A pre-turn-off execution module for receiving a calculation stop notification transmitted by the arithmetic processor, wherein the calculation stop notification is issued by the arithmetic processor after it has received the pre-turn-off output pre-shakehand and completed the calculation of the received data; A control processor for a dual-processor device, comprising a turn-off module for performing a turn-off operation.

9. A dual-processor device control method, The dual processor mentioned above includes a control processor and an arithmetic processor. The above method is implemented by a computing processor, The steps include receiving a pre-turn-off output pre-shakehand transmitted by the control processor, The steps include: completing the calculations on the received data and then stopping the associated calculation operations; A dual-processor device control method characterized by comprising the step of sending a calculation stop notification to the control processor, thereby enabling the control processor to perform a turn-off operation after receiving the calculation stop notification.

10. The steps include receiving a pre-shake hand transmitted and restarted by the control processor, The steps include completing the preparation for recovery of operations based on the restarted pre-shakehand, The steps include sending a recovery confirmation message to the control processor, which in turn causes the control processor to recover the acquisition of equipment operation data based on the recovery confirmation message, The dual-processor device control method according to claim 9, further comprising the step of receiving the device operation data transmitted by the control processor.

11. The dual-processor device control method according to claim 9, characterized in that, after sending a calculation stop notification to the control processor, the method further includes entering a sleep state.

12. Before entering sleep mode, The aforementioned method, The dual-processor equipment control method according to claim 11, further comprising the step of freezing equipment operation data during the arc generation period.

13. A computing processor for a dual-processor device, A pre-turn-off instruction receiving module for receiving a pre-turn-off output pre-shakehand transmitted by the control processor, After completing the calculations on the received data, a calculation stop control module is provided to stop the associated calculation operations. A computing processor for a dual-processor device, comprising: a computing stop notification module for sending a computing stop notification to the control processor, thereby enabling the control processor to perform a turn-off operation after receiving the computing stop notification.

14. Dual-processor device, A dual-processor device comprising a control processor for a dual-processor device according to claim 8 and an arithmetic processor for a dual-processor device according to claim 13.

15. A computer device comprising a processor, memory, and a bus, wherein the memory stores machine-readable instructions that the processor can execute, and when the computer device is executed, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the dual-processor device control method described in any one of claims 1 to 7 or 9 to 12 is executed.

16. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the dual-processor device control method described in any one of claims 1 to 7 or 9 to 12 is executed.

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