Method and apparatus for operating a memory device, and memory device

Abstract

A method for operating a memory device having at least one memory unit, e.g., a memory cell, wherein the at least one memory unit has a bistable flip-flop, the method comprising the steps of providing a first current that depends on a state of the bistable flip-flop, which can be characterized, e.g., by a potential of a first circuit node of the bistable flip-flop, and optionally evaluating at least the first current.

Description

[Technical Field]

[0001] The present disclosure relates to a method for operating a memory device. The present disclosure further relates to an apparatus for operating a memory device. The present disclosure further relates to a memory device. [Summary of the Invention]

[0002] An exemplary embodiment relates to a method for operating a memory device comprising at least one memory unit, for example a memory cell, wherein the at least one memory unit comprises a bistable flip-flop, the method comprising: providing a first current dependent on a state of the bistable flip-flop, which can be characterized for example by a potential of a first circuit node of the bistable flip-flop; and optionally, evaluating at least the first current.

[0003] Furthermore, combining, for example adding, the first current with at least one further first current of a further, for example similar memory unit is contemplated. In a further exemplary embodiment, information about the memory content of at least one memory unit can thereby be obtained, for example. In a further exemplary embodiment, the principle according to the above embodiments can be applied to, for example, a plurality of memory units that may exist in a memory device, for example, information about the memory content of the plurality of memory units of the memory device is obtained, for example simultaneously, which, in a further exemplary embodiment, can be used, for example, to perform an arithmetic operation based on the obtained information.

[0004] In a further exemplary embodiment, the at least one memory unit is designed as or forms a static RAM (random access memory) memory cell.

[0005] In a further exemplary embodiment, the bistable flip-flop has, for example, multiple field-effect transistors of the MOSFET type. In a further exemplary embodiment, the step of providing a first current includes at least one of the following elements: a) providing a first current from an external power source with respect to, for example, a bistable flip-flop; and b) providing, e.g., deriving a first current from, for example, a first circuit node of the bistable flip-flop.

[0006] In a further exemplary embodiment, the method includes the step of using, for example, at least one provided transistor designed as a MOSFET type field-effect transistor for the steps provided.

[0007] In a further exemplary embodiment, the method comprises the steps of: connecting a first terminal of the load path of at least one supplying transistor to, for example, an external power supply; connecting a control terminal, for example, a gate electrode, of at least one supplying transistor to one or a first circuit node of a bistable flip-flop; and optionally, providing a first current to a second terminal of the load path of at least one supplying transistor.

[0008] In a further exemplary embodiment, the step of connecting the first terminal of the load path of at least one supplying transistor to, for example, an external power supply is performed via a resistor. Thus, in a further exemplary embodiment, the supplying transistor can operate in a voltage follower configuration.

[0009] In a further exemplary embodiment, the method includes the steps of: connecting a first terminal of the load path of at least one supplying transistor to one or a first circuit node of a bistable flip-flop; connecting a control terminal, e.g., gate electrode, of at least one supplying transistor to, for example, an external power supply; and optionally, providing a first current to a second terminal of the load path of at least one supplying transistor by providing a corresponding potential, for example, an external power supply.

[0010] In a further exemplary embodiment, the step of connecting the first terminal of the load path of at least one providing transistor to the first circuit node of the bistable flip-flop is performed via a resistor.

[0011] In a further exemplary embodiment, at least one memory unit has controllable access transistors via a first control line for two second control lines associated with at least one memory unit, e.g., a bit line and a controllable connection of a bistable flip-flop, and the step of providing a first current is intended to be performed by a current-providing device different from the two access transistors. In other words, in a further exemplary embodiment, the first current is not provided by the access transistors.

[0012] However, in further exemplary embodiments, the first current may be provided by at least one of the access transistors. In a further exemplary embodiment, the method includes the step of outputting a first current to a first output line.

[0013] Further exemplary embodiments relate to apparatus for carrying out the method according to the above embodiments. In a further exemplary embodiment, the device includes a current-providing device, which is intended to be designed to provide a first current based on the state of a bistable flip-flop, for example, based on the potential of a first circuit node of the bistable flip-flop.

[0014] In a further exemplary embodiment, for example, at least one supplying transistor, designed as, for example, a MOSFET type field-effect transistor, is provided for supplying a first current, and the supplying transistor is intended to be designed, for example, to a) supply a first current from an external power supply with respect to, for example, a bistable flip-flop, and / or b) supply a first current from, for example, a bistable flip-flop, or to derive.

[0015] Further exemplary embodiments relate to a memory device having at least one memory unit, for example, a memory cell, wherein the at least one memory unit has a bistable flip-flop and at least one device according to the above embodiments.

[0016] In further exemplary embodiments, the memory device is intended to have control lines for controlling the current supply devices of at least one, for example, more than one, or all of the memory units.

[0017] In further exemplary embodiments, at least one, for example, controllable resistor is provided, and it is intended that at least one, for example, multiple, or all of the memory unit's current-supplying devices can be controlled by a control line via the resistor.

[0018] Further exemplary embodiments relate to computing devices, such as vector-matrix multipliers, having at least one apparatus and / or at least one memory device according to the embodiments described above.

[0019] Further exemplary embodiments relate to the use of the above-described methods and / or apparatus and / or memory devices and / or computing devices for at least one of the following: a) processing of currents associated with bistable flip-flops; b) determining the sum of first currents associated with each bistable flip-flop in each memory unit; c) providing a computing device relating to, for example, artificial intelligence algorithms for performing, for example, inference in an artificial neural network; and d) extension of, for example, a conventional memory cell.

[0020] Further features, possible applications, and advantages of the present invention will become apparent from the following description of exemplary embodiments of the invention shown in each of the drawings. All features described or illustrated herein, individually or in any combination, constitute the subject matter of the present invention, regardless of their summary or relationship in the claims, and regardless of their formulation or representation herein or in the drawings. [Brief explanation of the drawing]

[0021] [Figure 1] This is a simplified schematic circuit diagram based on an exemplary embodiment. [Figure 2] This is a simplified schematic flowchart based on an exemplary embodiment. [Figure 3] This is a simplified schematic flowchart illustrating a further exemplary embodiment. [Figure 4] This is a simplified schematic circuit diagram of a further exemplary embodiment. [Figure 5] This is a simplified schematic flowchart illustrating a further exemplary embodiment. [Figure 6] This is a simplified schematic circuit diagram of a further exemplary embodiment. [Figure 7] This is a simplified schematic flowchart illustrating a further exemplary embodiment. [Figure 8]It is a simplified schematic circuit diagram according to a further exemplary embodiment. [Figure 9] It is a simplified schematic circuit diagram according to a further exemplary embodiment. [Figure 10] It is a simplified schematic block diagram according to a further exemplary embodiment. [Figure 11] It is a diagram schematically illustrating a mode of use according to a further exemplary embodiment. Detailed Description of the Invention

[0022] The exemplary embodiment (Figs. 1 and 2) is directed to a method for operating a memory device 100 comprising at least one memory unit 110, e.g., a memory cell, wherein the at least one memory unit 110 has a bistable flip-flop KS, and the method comprises: providing step 200 (Fig. 2) a first current I1 that depends on a state of the bistable flip-flop KS, which can be characterized for example by a potential at a first circuit node N1 (Fig. 1) of the bistable flip-flop KS; and optionally, evaluating at least the first current I1 in step 202.

[0023] In a further exemplary embodiment, this enables obtaining information related to memory contents of at least one memory unit 110, for example. In a further exemplary embodiment, the principle according to the above embodiments can be applied to, for example, a plurality of memory units that may already exist in a memory device (see, e.g., Fig. 8), and for example, information related to memory contents of a plurality of memory units of the memory device is obtained simultaneously, which in a further exemplary embodiment can be used, for example, to perform an arithmetic operation based on the obtained information.

[0024] In a further exemplary embodiment (Fig. 1), the at least one memory unit 110 is configured as a static RAM (random access memory) memory cell, or forms a static RAM memory cell.

[0025] In a further exemplary embodiment (Figure 1), the bistable flip-flop KS has, for example, a plurality of field-effect transistors T1, T2, T3, T4 of the MOSFET type, which are connected in the manner shown in Figure 1, for example. Reference numeral BP1 represents, for example, a first reference potential, e.g., the ground potential. Reference numeral BP2 represents, for example, a second reference potential different from the ground potential BP1, e.g., the operating voltage potential.

[0026] Element N1, for example, represents a first circuit node of the bistable flip-flop KS, where the memory contents of the memory unit 110 exist in the form of a potential, characterized by, for example, one of two possible states, e.g., "1" or "0". In a further exemplary embodiment, the opposite state may exist, for example, in the form of a potential at a second circuit node N2.

[0027] In a further exemplary embodiment (Figure 1), at least one memory unit 110 has, for example, two access transistors T5, T6 of MOSFET type. Optional access transistors T5, T6 are controllable, for example, via a first control line (which may be called a "word line") SL1 for selective connection of a bistable flip-flop KS with two secondary control lines (which may be called "bit lines") SL2a, SL2b associated with, for example, at least one memory unit 110.

[0028] For example, in the case of writing to and / or reading from the memory unit 100 using a conventional method, the optional access transistors T5 and T6 are both activated via the first control line SL1, i.e., a gate-source voltage is applied to them, which is, for example, relatively large above the threshold voltage of the access transistors T5 and T6.

[0029] Therefore, during readout, according to a further exemplary embodiment, the potential at at least one of the circuit nodes N1, N2 can be determined via at least one bit line SL2a (or, for example, via both bit lines SL2a, SL2b) and can be detected, for example, by voltage measurement.

[0030] During writing, according to a further exemplary embodiment, the corresponding value is pre-assigned via at least one bit line SL2a (or, for example, via both bit lines SL2a and SL2b) and can be applied to the bit line, for example, in the form of their respective potentials.

[0031] In further exemplary embodiments, reading data from and / or writing data to the memory unit 110 can be performed, for example, by a first control line SL1 under appropriate control of access transistors T5, T6, while providing a first current I1 200 (Figure 2) can be performed, for example, by a device 300 different from access transistors T5, T6.

[0032] In a further exemplary embodiment, the apparatus 300 for carrying out an aspect of the method according to the exemplary embodiment is designed, for example, to perform the exemplary sequence shown in Figure 2. In a further exemplary embodiment (Figure 1), the apparatus 300 has a current-providing device 302 which is intended to provide a first current I1 based on the state of a bistable flip-flop KS, for example, based on the potential of a first circuit node N1 of the bistable flip-flop KS.

[0033] In a further exemplary embodiment (Figure 2), step 200 of providing a first current I1 includes at least one of the following elements: a) providing a first current I1 from an external power supply V-ext (Figure 1) with respect to a bistable flip-flop KS, for example; b) providing a first current I1 from a bistable flip-flop KS, for example from a first circuit node N1 of the bistable flip-flop KS, for example, deriving it, for example, 200b.

[0034] In a further exemplary embodiment (Figure 3), the method has step 210 which, for the step to be provided, uses at least one provided transistor 304-1 designed, for example, as a MOSFET type field-effect transistor (see also exemplary configuration 100a, for example, Figure 4).

[0035] In further exemplary embodiments (Figures 3 and 4), the method includes the steps of: 212 connecting a first terminal 304a of the load path of at least one supply transistor 304-1 to, for example, an external power supply V-ext (Figure 1) via, for example, a third control line SL3 (Figure 4); 214 connecting a control terminal of at least one supply transistor 304-1, for example, a gate electrode 304b, to one or a first circuit node N1 of a bistable flip-flop KS; and optionally, 216 providing a first current I1 to a second terminal 304c of the load path of at least one supply transistor 304-1.

[0036] In a further exemplary embodiment (Figure 4), step 212, which connects the first terminal 304a of the load path of at least one supply transistor 304-1 to, for example, an external power supply V-ext, is performed via a resistor 306. Thus, in a further exemplary embodiment, the supply transistor 304-1 can operate in a voltage follower configuration.

[0037] In further exemplary embodiments (Figures 5 and 6), the method has step 220 using, for example, at least one providing transistor 304-2 designed as, for example, a MOSFET type field-effect transistor (see also exemplary configuration 100a, for example, Figure 6).

[0038] In further exemplary embodiments (Figures 5 and 6), the method includes the steps of: connecting a first terminal 304a (Figure 6) of the load path of at least one supplying transistor 304-2 to one or a first circuit node N1 of a bistable flip-flop KS; connecting a control terminal, e.g., gate electrode 304b, of at least one supplying transistor 304-2 to, e.g., an external power supply V-ext (Figure 1) via, e.g., a third control line SL3; and optionally, the step of providing a first current I1 to a second terminal 304c of the load path of at least one supplying transistor 304-2, e.g., by providing a corresponding potential, e.g., an external power supply V-ext, via, e.g., a third control line SL3.

[0039] In further exemplary embodiments (Figures 5 and 6), step 222, which connects the first terminal 304a of the load path of at least one providing transistor 304-2 to the first circuit node N1 of the bistable flip-flop KS, is performed via a resistor 308.

[0040] In further exemplary embodiments (Figures 4 and 6), memory devices 100a and 100b are designed to provide control signals to drive transistors 304-1 and 304-2 provided by a third control line SL3 when, for example, a first current I1 is provided.

[0041] In further exemplary embodiments (Figures 4, 6), memory devices 100a, 100b are designed to synchronize the operation of providing transistors 304-1, 304-2 with at least one further operating mode of the memory unit 110, such as conventional read and / or write, under the corresponding control of, for example, at least one of the control lines SL1, SL2a, SL2b.

[0042] In further exemplary embodiments (Figures 1, 4, and 6), memory devices 100, 100a, and 100b are designed to perform temperature compensation with respect to an external power supply V-ext or to a control signal (e.g., a reference voltage) that can be provided via a third control line SL3.

[0043] In a further exemplary embodiment (Figure 4), for example, the flip-flop KS is designed to provide an appropriate gate-source voltage to a first circuit node N1 for providing a first current I1, based on a control signal for terminal 304a of the providing transistor 304-1, which can be supplied, for example, via a third control line SL3.

[0044] In contrast, in configuration 100b shown in Figure 6, the gate-source voltage for the supply transistor 304-2 can be supplied, for example, from an external power supply V-ext (Figure 1) via a third control line SL3.

[0045] In further exemplary embodiments (Figures 4 and 6), the memory devices 100a and 100b have a first output line AL1 and are capable of outputting a first current I1 to and / or via the first output line AL1, for example, at least temporarily.

[0046] In further exemplary embodiments (Figures 4 and 6), the memory devices 100a and 100b may have at least one further memory unit 110', the memory unit 110' may, in further exemplary embodiments, have the same or at least the same configuration as, for example, the configuration 110 shown in Figure 1.

[0047] In further exemplary embodiments (Figures 4, 6), a first current I1 that can be provided by at least one memory unit 110 via, for example, a first output line AL1 is combinatorial with, for example, an additional first current I1' that can be provided by at least one further memory unit 110'.

[0048] Therefore, in a further exemplary embodiment (Figure 7), the method has at least one of the following elements: a) step 230 of outputting a first current I1 to one or a first output line AL1; b) step 232 of combining, for example, a first current I1 with at least one further first current I1' of further, for example, identical, similar, or different memory units 110'.

[0049] In a further exemplary embodiment, the exemplary sequence shown in Figure 7 allows the first currents I1, I1' of different memory units 110, 110' of memory devices 100, 100a, 100b to be added together, so that, for example, in-memory computing, i.e., a form of computation within a memory device, where the first currents I1, I1' of different memory units 110, 110' each depend, for example, on the memory contents of the associated flip-flops KS of memory units 110, 110'.

[0050] In a further exemplary embodiment (Figure 1), at least one memory unit 110 has two second control lines SL2a, SL2b associated with at least one memory unit, e.g., a bit line and the aforementioned access transistors T5, T6 for controllable connections of a bistable flip-flop KS, and the provision of a first current I1 200 (Figure 2) is intended to be done by a current-providing device 302 distinct from the two access transistors T5, T6. In other words, in a further exemplary embodiment, the first current I1 is provided not by the access transistors T5, T6, but by a current-providing device 302 including, for example, at least one providing transistor 304-1 (Figure 4), 304-2 (Figure 6).

[0051] However, in further exemplary embodiments, the first current I1 may also be provided by at least one of the access transistors T5, T6. Thus, in some embodiments, the current supply device 302, for example, may be omitted (not shown). In further exemplary embodiments, at least one of the access transistors T5, T6 may be controlled to provide the first current I1 200, thereby making the load path of at least one access transistor T5, T6 at least partially conductive compared to, for example, a high-resistance state of the load path of at least one access transistor T5, T6, and less conductive compared to, for example, a low-resistance state of the load path of at least one access transistor T5, T6. In further exemplary embodiments, this can be achieved, for example, by applying a control voltage below the threshold voltage of at least one access transistor T5, T6 to at least one control terminal (e.g., gate electrode) of the two access transistors T5, T6, for example, via a first control line SL1, outside the time range in which, for example, conventional read or write operations are performed using at least one access transistor T5, T6.

[0052] A further exemplary embodiment (Figure 1) relates to a memory device 100 having at least one memory unit 110, for example, a memory cell, wherein the at least one memory unit 110 has a bistable flip-flop KS and at least one device 300 according to the above embodiment.

[0053] In a further exemplary embodiment (Figure 1), the memory device 100 is intended to have control lines, for example, a third control line SL3, for controlling the current supply devices 302 of at least one, for example, multiple, or all of the memory units.

[0054] In other words, in a further exemplary embodiment (Figure 8) in which the memory device 100c has multiple (for example, four) memory units 110-1, 110-2, 110-3, 110-4, a common, for example, third control line SL3 can be provided to power multiple, for example, all of the memory units 110-1, 110-2, 110-3, 110-4 of the memory device 100c, for example, all of the supply transistors 304-1.

[0055] For example, the memory units 110-1, 110-2, 110-3, and 110-4 of the memory device 100c shown in Figure 8 each have the configuration shown in Figure 4, and the gate electrode 304b of the provided transistor 304-1 is connected to the first circuit node N1 of the respective bistable flip-flop KS.

[0056] For example, the memory units 110-1, 110-2, 110-3, and 110-4 of the memory device 100c can be organized in a matrix, i.e., in rows and columns, such that memory units 110-1 and 110-2 from Figure 8 form a first column, and memory units 110-3 and 110-4 from Figure 8 form a second column. The memory units 110-1 and 110-2 in the first column output their respective first currents I1-1 and I1-2 to a common first output line AL1, for example, and the memory units 110-3 and 110-4 in the second column output their respective first currents I1-3 and I1-4 to a common second output line AL2, for example.

[0057] In Figure 8, element SL1-1 represents a first word line, through which access transistors T5, T6 of the first row, which have memory units 110-1, 110-3, can be controlled, for example, for conventional reading and / or writing.

[0058] In Figure 8, element SL1-2 represents a second word line, and through the second word line, it is possible to control the access transistors T5, T6 of the second row, which have, for example, memory units 110-2, 110-4, for conventional reading and / or writing.

[0059] In Figure 8, elements SL2a and SL2b represent a first bit line, which can control, for example, memory units 110-1 and 110-2 for conventional reading and / or writing.

[0060] In Figure 8, elements SL2c and SL2d represent a second bit line, which allows control of memory units 110-3 and 110-4, for example, conventional read and / or write operations.

[0061] In a further exemplary embodiment (Figure 8), at least one resistor (here, two resistors) R1, R2 are provided, and it is intended that at least one, for example, a plurality, for example, all of the memory units 110-1, 110-2, 110-3, 110-4, a current supplying device, for example, a supplying transistor 304-1, is controllable by a third control line SL3 via resistors R1, R2. In this case, for example, the supplying transistor 304-1 of memory units 110-1, 110-2 is controllable by the third control line SL3 via resistor R1, and for example, the supplying transistor 304-1 of memory units 110-3, 110-4 is controllable by the third control line SL3 via resistor R2.

[0062] In further exemplary embodiments, resistors R1 and R2 may have the same resistance value. In further exemplary embodiments, resistors R1 and R2 may have different resistance values.

[0063] Figure 9 shows a further configuration 100d of a memory device according to a further exemplary embodiment, similar to configuration 100c according to Figure 8. In contrast to Figure 8, the configuration in Figure 9 has controllable resistors RS1 and RS2 instead of resistors R1 and R2. The controllable resistors RS1 and RS2 according to Figure 9 are here, for example, realized by transistors, such as MOSFETs, and the load paths of these transistors are connected to a third control line SL3, similar to resistors R1 and R2 (Figure 8), however, the gate electrodes of these transistors are here controllable via a common fourth control line SL4, thereby allowing adjustment of the resistance values ​​of the load paths of, for example, MOSFETs RS1 and RS2.

[0064] Figure 10 schematically shows a simplified block diagram of a memory device 100e according to a further exemplary embodiment, the memory device 100e having, here as an example, six memory units 110-1, 110-2, 110-3, 110-4, 110-5, and 110-6, which are similar to or identical to the configuration 110 shown in, for example, Figure 1, Figure 4, or Figure 6.

[0065] Elements 310-1 and 310-2 represent optional decision devices for the memory contents of each memory unit, for example, a sense amplifier. Decision device 310-1 is assigned to the first column of memory units 110-1, 110-2, and 110-3, and decision device 310-2 is assigned to the second column of memory units 110-4, 110-5, and 110-6.

[0066] Elements 312-1 and 312-2 represent optional decision devices for currents to flow through their respective output lines AL1 and AL2, respectively, where these currents correspond, for example, to the sum of the first currents I1-1, I1-2, I1-3, or I1-4, I1-5, I1-6 for the corresponding column of the memory unit. These currents can be supplied, at least temporarily, by the respective memory unit under the control of control lines SL3-1, SL3-2, SL3-3 (for example, each of which is provided, for example, at least per row).

[0067] Similarly, control lines SL1-1, SL1-2, and SL1-3, provided for each row (i.e., common to all memory units in the same row), can be used to activate (for example, for conventional reading or writing) or deactivate optional access transistors T5 and T6, as described above, by referring to control line SL1 as shown in Figure 1.

[0068] The memory contents of each memory unit. Here, decision device 310-1 is assigned to the first column of memory units 110-1, 110-2, and 110-3, and decision device 310-2 is assigned to the second column of memory units 110-4, 110-5, and 110-6.

[0069] Element 314 represents, for example, a central control device for providing at least one control signal at least temporarily to at least one of the control lines SL1-1, SL1-2, SL1-3, SL3-1, SL3-2, SL3-3. For example, the control device 314 may be assigned, for example, a temperature-compensated reference voltage source V1 from which, in a further exemplary embodiment, at least one control signal for at least one of the memory units 110-1, ..., 110-6 can be derived or generated.

[0070] Further exemplary embodiments (Figure 8) relate to a computing device 400, such as a vector matrix multiplier VMM, having at least one apparatus 300 (Figure 1) according to the above embodiments and / or at least one memory device 100, 100a, 100b, 100c, 100d, 100e according to the above embodiments.

[0071] Further exemplary embodiments (Figure 11) relate to methods and / or apparatus 300 and / or use of memory devices 100, 100a, 100b, 100c, 100d, 100e and / or computing device 400 of the above embodiments for at least one aspect of a) processing a current I1 associated with a bistable flip-flop KS 501, b) determining the sum of first currents I1, I1' associated with the bistable flip-flops of each memory unit 502, c) providing a computing device 400 for in-memory computing, for example, for artificial intelligence algorithms, for example, for performing inference of an artificial neural network 503, and d) extension of a conventional memory cell, for example 504.

[0072] In a further exemplary embodiment (Figure 10), the functions of devices 310-1, 312-1, or 310-2, 312-2 can be combined. That is, for example, one composite device can be provided for each column, and the composite device is designed to perform read and write operations on each memory unit, as well as to determine the total current of the first currents I1-1, I1-2, I1-3 for each column.

[0073] In further exemplary embodiments, devices 312-1, 312-2, or the aforementioned composite devices, can be designed, for example, as current-based or current-driven analog-to-digital converter devices.

[0074] In further exemplary embodiments, instead of the analog-to-digital converter devices 312-1, 312-2, for example, one or the sense amplifier or determination devices 310-1, 310-2 described above may be provided.

[0075] In further exemplary embodiments, sense amplifiers or decision devices 310-1, 310-2 may have, for example, memory registers that can store thresholds for detection, the thresholds being, for example, modifiable or preset, thereby the operational behavior of decision devices 310-1, 310-2 may be affected, for example, with respect to reading the contents of the memory unit, and in further exemplary embodiments, for example, embodiments of activation functions of artificial neurons can be realized.

[0076] In a further exemplary embodiment, the activation function controls, for example, when or under what circumstances input data or the value of the input data or its output to, for example, one or more (artificial) neurons is activated, and adds the input data and outputs the sum only when it exceeds a preset threshold that can be characterized by, for example, the activation function.

[0077] In further exemplary embodiments, for example, threshold voltages for decision devices 310-1 and 310-2 can be selected based on the values ​​in a memory register. In a further exemplary embodiment (Figure 4), the provided transistor 304-1 can operate in a voltage follower configuration as already described above, using a digital signal as, for example, a control signal, where the voltage at the source electrode follows, for example, the voltage at the gate electrode.

[0078] In a further exemplary embodiment, the provided transistor 304-1 provides, for example, a voltage drop corresponding to its threshold voltage. The first current I1 regulated here is defined, for example, by the voltage drop across the load path of the provided transistor 304-1.

[0079] In a further exemplary embodiment (Figure 4), the optionally selected resistor 306 can be replaced, for example, with a transistor, such as a MOSFET, which can operate as a controllable resistor and has a relatively small footprint with respect to relatively large resistance values, for example.

[0080] In a further exemplary embodiment (Figure 8), for example, in the context of in-memory computing, "weight 1" of "kernel 1" may be stored in the first row of the matrix configuration 100c, and "weight 2" of "kernel 1" may be stored in the third row of the matrix configuration 100c. For example, when a calculation is performed using "kernel 1", only rows 1 and 3 are activated, and no resistors are shared.

[0081] In further exemplary embodiments (Figures 8 and 9), the first current supply 200 (Figure 2) can be performed, for example, by applying a "HIGH" potential to the third control line SL3.

[0082] In further exemplary embodiments, a memory unit 110 having, for example, six transistors T1, T2, T3, T4, T5, and T6 can be extended or supplemented according to the principles of the present invention.

[0083] In further exemplary embodiments, a memory unit having more than six transistors T1, T2, T3, T4, T5, T6 can also be extended or supplemented by the principles of the present invention.

[0084] In a further exemplary embodiment, for example, one memory device 100, 100a, 100b, 100c, 100d according to at least one of Figures 1, 4, 6, 8, 9 may be assigned to at least one device 310-1, 312-1, 310-2, 312-2, 314 according to Figure 10, for example, for conventional reading and / or writing, and / or for determining and / or evaluating a first current of at least one memory unit.

[0085] Information on aid and support The project for which this application was filed was funded by the joint venture ECSEL (Joint Venture) under Grant Agreement No. 826655. This joint venture is supported by the European Union's Horizon 2020 Research & Innovation Programme, as well as by Belgium, France, Germany, the Netherlands, and Switzerland.

Claims

1. A method for operating a memory device (100; 100a; 100b; 100c; 100d; 100e) having memory cells which are at least one memory unit (110; 110-1, 110-2, 110-3, ...), wherein the at least one memory unit (110; 110-1, 110-2, 110-3, ...) has a bistable flip-flop (KS), the method comprising the steps (200) of providing a first current (I1) which depends on the state of the bistable flip-flop (KS), which can be characterized by the potential of a first circuit node (N1) of the bistable flip-flop (KS); and (232) of adding the first current (I1) with at least one further first current (I1') of further similar memory units (110'), The step (200) of providing the first current (I1) comprises at least one of the following elements: a) providing the first current (I1) from an external power source (V-ext) with respect to the bistable flip-flop (KS) (200a), and b) deriving the first current (I1) from the bistable flip-flop (KS) (200b). For the aforementioned providing step (200), the step (210; 220) includes using at least one providing transistor (304-1; 304-2) designed as a MOSFET type field-effect transistor, A method comprising the steps of: (222) connecting a first terminal (304a) of the load path of the at least one supplying transistor (304-2) to one of the bistable flip-flops (KS) or the first circuit node (N1); (224) connecting a gate electrode (304b), which is a control terminal of the at least one supplying transistor (304-2), to an external power supply (V-ext); and (226) supplying the first current (I1) to a second terminal (304c) of the load path of the at least one supplying transistor (304-2).

2. The method according to claim 1, comprising the steps of: (212) connecting a first terminal (304a) of the load path of the at least one supplying transistor (304-1) to an external power supply (V-ext); (214) connecting a gate electrode (304b), which is a control terminal of the at least one supplying transistor (304-1), to one of the bistable flip-flops (KS) or the first circuit node (N1); and (216) providing the first current (I1) to the second terminal (304c) of the load path of the at least one supplying transistor (304-1).

3. The method according to claim 2, wherein the step (212) of connecting the first terminal (304a) of the load path of the at least one supplying transistor (304-1) to the external power supply (V-ext) is performed via a resistor (306).

4. The method according to claim 1, wherein the step (222) of connecting the first terminal (304a) of the load path of the at least one providing transistor (304-2) to the first circuit node (N1) of the bistable flip-flop (KS) is performed via a resistor (308).

5. The method according to claim 1, wherein the at least one memory unit (110; 110-1, 110-2, 110-3, ...) has bit lines which are two second control lines (SL2a, SL2b) associated with the at least one memory unit (110; 110-1, 110-2, 110-3, ...) and two access transistors (T5, T6) which are controllable via a first control line (SL1), respectively, for a controllable connection of the bistable flip-flop (KS), and the step (200) of providing the first current (I1) is performed by a current-providing device (302) different from the two access transistors (T5, T6).

6. Apparatus (300) for carrying out the method described in at least one of claims 1 to 5.

7. The apparatus (300) according to claim 6, wherein the apparatus (300) has a current supplying device (302), and the current supplying device (302) is designed to supply a first current (I1) based on the potential of the first circuit node (N1) of the bistable flip-flop (KS).

8. The apparatus (300) according to claim 6, wherein at least one providing transistor (304-1; 304-2) designed as a MOSFET type field-effect transistor is provided for the providing (200) of the first current (I1), and the providing transistor (304-1) is designed to a) provide the first current (I1) from an external power supply (V-ext) with respect to the bistable flip-flop (KS), and / or b) derive the first current (I1) from the bistable flip-flop (KS) (200b).

9. A memory device (100; 100a; 100b; 100c; 100d; 100e) having memory cells which are at least one memory unit (110; 110-1, 110-2, 110-3, 110-4), wherein the at least one memory unit (110; 110-1, 110-2, 110-3, 110-4) comprises a bistable flip-flop (KS) and the device (300) described in claim 6.

10. The memory device (100; 100a; 100b; 100c; 100d; 100e) according to claim 9, having a control line (SL3) for controlling a current supply device (302) of at least one of the memory units (110; 110-1, 110-2, 110-3, 110-4).

11. The memory device (100; 100a; 100b) according to claim 10, wherein at least one controllable resistor (R1, R2; RS1, RS2) is provided, and the current supply device (302) of the at least one memory unit (110; 110-1, 110-2, 110-3, 110-4) can be controlled by the control line (SL3) via the resistor (R1, R2; RS1, RS2).

12. A computing device (400) comprising a vector matrix multiplier (VMM), having at least one device (300) as described in claim 6.

13. A computing device (400) comprising a vector matrix multiplier (VMM), having at least one memory device (100; 100a; 100b; 100c; 100d; 100e) as described in claim 9.

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