Reducing leakage power in volatile memory

Abstract

A system and method for reducing the amount of power leaked by volatile memory in memory units of a memory system. In one aspect, the memory system includes a volatile memory including a plurality of memory units. The memory system includes a descriptor queue configured to maintain a sequence of descriptors corresponding to received memory access requests. The descriptor queue includes a memory access pointer indicating a current descriptor being processed and a power management pointer indicating one or more subsequent descriptors for an active state transition. The memory system includes a memory controller configured to process the descriptors based on the memory access pointer and access the memory units of the descriptors in response to the received memory access requests. The memory system includes a power manager configured to selectively transition each memory unit between an active state and a low power state.

Description

[[Technical Field]]

[0001] The present specification relates to computer memory and reducing the amount of power leaked by volatile computer memory. [[Background Art]]

[0002] Volatile memory is a type of computer memory that retains data when power is supplied, but loses the data when power is interrupted. Two exemplary types of volatile memory are Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM requires periodic refreshing to maintain its data, while SRAM requires constant power to maintain its data.

[0003] Transistors in SRAM have multiple sources of leakage power. Since a large amount of SRAM may be present on a system-on-chip (SoC) and other types of integrated circuits, the constant power requirement of SRAM can lead to a large amount of wasted power and associated adverse thermal characteristics. [[Summary of Invention]]

[0004] This specification relates to reducing the amount of power leaked by volatile memory, particularly SRAM and other types of volatile memory where the memory can be accessed in any order. A physical memory unit can be put into a low-power state to reduce the amount of power leaked when the memory unit is not being accessed. However, it takes some time to transition the memory unit from the low-power state to an active state where the memory unit can be accessed. If the memory unit does not transition to the active state until an access request for data stored in the memory unit is received, the transition time adds latency and imposes back pressure on the memory system. The techniques described herein reduce power leakage of volatile memory without such latency and back pressure, even in situations where memory access is random and does not follow any schedule or defined pattern.

[0005] Generally, one innovative aspect of the subject matter described herein can be embodied in a memory system comprising a volatile memory including a plurality of memory units, and a descriptor queue configured to maintain a sequence of descriptors, each corresponding to an received memory access request, for performing a memory access operation in each of the plurality of memory units, wherein the descriptor queue includes a memory access pointer indicating the current descriptor to be processed, and a power management pointer indicating one or more subsequent descriptors for an active state transition, and the memory system further comprises a memory controller configured to process descriptors in the descriptor queue based on the memory access pointer and to access the memory unit of a descriptor to respond to an received memory access request corresponding to a descriptor in the descriptor queue, and a power manager configured to selectively transition each memory unit between an active state and a low-power state, including monitoring the power management pointer to identify one or more subsequent descriptors, and transitioning each of the one or more subsequent descriptors from a low-power state to an active state before the one or more subsequent descriptors are processed by the memory controller. Other embodiments of this aspect include corresponding systems, devices, and computer programs configured to perform actions of a method encoded on a computer storage device.

[0006] These and other embodiments may each optionally include one or more of the following features. In some embodiments, the descriptor queue includes a first-in, first-out queue, where each descriptor is removed from the descriptor queue after the memory controller has performed the memory access operation indicated by the descriptor. The volatile memory may include static random access memory (SRAM). The descriptor queue may include a queue manager, which is configured to update the descriptor queue to include the descriptor of each newly received memory access request, update the memory access pointer after each descriptor has been processed by the memory controller, and update the power management pointer after each descriptor has been processed by the memory controller.

[0007] In some embodiments, one or more subsequent descriptors include a number of descriptors selected based on the amount of time required for the memory unit to transition from a low-power state to an active state. The number of descriptors may be based on the number of memory access operations that the memory controller can complete within the amount of time. The number of descriptors may be based on the number of processor processing unit clock cycles that occur during the amount of time and are communicatively coupled to the volatile memory.

[0008] In some embodiments, the descriptor queue includes one or more additional power management pointers indicating an additional set of subsequent descriptors for an active state transition. The additional set of subsequent descriptors includes a number of additional descriptors selected based on the amount of time required for the transition from the low-power state to the active state of the memory unit corresponding to each additional descriptor. The number of additional descriptors can be based on the number of memory access operations that the memory controller can complete within the time length.

[0009] In some embodiments, the power manager is configured to determine whether each memory unit of the current descriptor is a subsequent descriptor for an active state transition, to keep each memory unit of the current descriptor active after processing the current descriptor whenever each memory unit of the current descriptor is a subsequent descriptor for an active state transition, and to transition each memory unit of the current descriptor from the active state to a low-power state whenever each memory unit of the current descriptor is not a subsequent descriptor for an active state transition.

[0010] In general, another innovative aspect of the subject matter described herein can be embodied in a manner performed by a memory controller configured to manage volatile memory comprising a plurality of memory units. The method comprises accessing a descriptor queue, which comprises a sequence of descriptors, each corresponding to an received memory access request, each descriptor corresponding to a memory access operation to each of the plurality of memory units indicated by the descriptor, and the descriptor queue further comprises a memory access pointer indicating the current descriptor for processing, and a power management pointer indicating one or more subsequent descriptors for active state transitions. The method comprises identifying one or more subsequent descriptors based on the power management pointer, transitioning each subsequent descriptor in a low-power state from the low-power state to an active state, and accessing one or more memory units of each subsequent descriptor when the memory access pointer reaches a subsequent descriptor in the descriptor queue. Other embodiments of this aspect include corresponding systems, devices, and computer programs configured to perform the actions of the method encoded on a computer storage device.

[0011] These and other embodiments may optionally include one or more of the following features. In some embodiments, accessing one or more memory units of each subsequent descriptor includes performing a memory access operation of the subsequent descriptor.

[0012] In some embodiments, the method includes updating the memory access pointer and the power management pointer so that a memory access operation for a descriptor is performed and the descriptor is removed from the descriptor queue, indicating a different descriptor each time.

[0013] In some embodiments, the method includes updating one or more subsequent descriptors for an active state transition by performing a memory access operation on the current descriptor; removing the current descriptor from the descriptor queue in response to performing the memory access operation on the current descriptor; updating the memory access pointer to indicate the next descriptor in the descriptor queue following the current descriptor; and updating the power management pointer in response to performing the memory access operation on the current descriptor.

[0014] In some embodiments, the method includes determining whether each memory unit of the current descriptor is a subsequent descriptor for an active state transition; keeping each memory unit of the current descriptor active after processing the current descriptor whenever it is a subsequent descriptor for an active state transition; and transitioning each memory unit of the current descriptor from an active state to a low-power state whenever it is not a subsequent descriptor for an active state transition.

[0015] In some embodiments, the method includes identifying each descriptor between a memory access pointer and a power management pointer as one or more subsequent descriptors.

[0016] In some embodiments, the method includes controlling a power management pointer to identify a specific number of subsequent descriptors based on the time length required for the memory unit to transition from a low-power state to an active state.

[0017] In some embodiments, the descriptor queue includes a first-in, first-out queue, where each descriptor is removed from the descriptor queue after the memory controller has performed the memory access operation indicated by the descriptor.

[0018] In some embodiments, volatile memory includes static random-access memory (SRAM). A descriptor queue may include a queue manager, which is configured to update the descriptor queue to include descriptors for each newly received memory access request, update the memory access pointer after each descriptor has been processed by the memory controller, and update the power management pointer after each descriptor has been processed by the memory controller.

[0019] In some embodiments, one or more subsequent descriptors include a number of descriptors selected based on the time length required for the memory unit to transition from a low-power state to an active state. The number of descriptors may be based on the number of memory access operations that the memory controller can complete within the time length. The number of descriptors may be based on the number of processing unit clock cycles of the processor communicatively coupled to the volatile memory that occur during the time length.

[0020] In some embodiments, the method includes determining that a particular descriptor corresponding to a particular memory unit is not in the descriptor queue, and transitioning the particular memory unit to a low-power state in response to determining that a particular descriptor corresponding to a particular memory unit is not in the descriptor queue.

[0021] The subject matter described herein can be implemented in particular embodiments to achieve one or more of the following advantages: By managing the low-power state of volatile memory so that the memory unit transitions to an active state before being accessed, leakage power of the memory unit is reduced, which also reduces the amount of heat dissipated by the leakage power. Power management pointers and descriptor queues, which can be implemented as first-in, first-out (FIFO) units, can be used to identify the memory unit that is about to be accessed (e.g., within a specified amount of time) and to transition the memory unit immediately before it is accessed (e.g., within one, two, or another appropriate number of clock cycles). This further reduces leakage power and associated heat by the amount of time the memory unit is in an active state. This also ensures that the memory unit is in an active state at the time the memory controller accesses the memory unit, reducing latency and backpressure. By using power-managed pointers and descriptor queues, transitions can be made in just the right amount of time regardless of the order in which memory requests are received, thus enabling the use of low-power techniques in all situations, not just when the memory access pattern is known or conforms to a predefined pattern.

[0022] Details of one or more embodiments of the subject matter of this specification are described in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. [Brief explanation of the drawing]

[0023] [Figure 1] This illustrates an exemplary memory system in which a memory controller controls access to volatile memory and transitions the memory units of volatile memory between an active state and a low-power state. [Figure 2] An illustrative state of the descriptor queue is shown. [Figure 3]Fig. 1 is a flow diagram of an exemplary process for transitioning a memory unit between an active state and a low power state. [Figure 4] Fig. 3 is a flow diagram of an exemplary process for accessing a memory unit and transitioning the memory unit between an active state and a low power state. DETAILED DESCRIPTION OF THE INVENTION

[0024] Like reference numerals and designations in different drawings indicate like elements.

[0025] Fig. 1 shows an exemplary memory system 100 in which a memory controller 110 controls access to a volatile memory 150 and transitions memory units 152 (e.g., 152-1 to 152-N) of the volatile memory 150 between an active state and a low power state. The memory system 100 may be part of (e.g., integrated into) or coupled to a system-on-chip (SOC) that may be installed on or integrated with any suitable computing device. The techniques described herein are particularly suitable for reducing power leakage of the volatile memory 150 with reduced latency and backpressure, so the memory system 100 may be particularly advantageous when installed in a mobile host device or other device that relies on battery power or other limited power supplies. For example, reducing power leakage in a portable device (e.g., a smartphone, a smartwatch or another wearable computing device, a tablet computer, or a laptop computer) can improve the battery performance and operability of the portable device over an extended period of time without accessing an external power source.

[0026] The memory system 100 includes a memory controller 110, a power manager 120 configured to transition a memory unit 152 between an active state and a low power state to satisfy a memory access request, and a volatile memory 150. Examples of the volatile memory 150 include cache memory and random access memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM). The power management and memory access techniques described herein can be used in volatile memory that requires constant power to retain data, such as SRAM.

[0027] Each memory unit 152 is a physical instance of memory, for example, a smaller partition of a larger memory system or device. A physical memory instance of a memory unit can transition between different power states, such as from an active state to a low power state, and from a low power state to an active state. The power state of a physical memory instance can transition independently of the power states of physical instances of other memory units. For example, the memory unit 152 may be one or more rows of memory cells, one or more columns of memory cells, or a group of memory cells such as one or more memory banks. The memory units 152 may be grouped or clustered based on their characteristics or other factors, including power state, operating parameters, computing applications, latency when transitioning between a low power state and an active state, and read / write speed. In some embodiments, each memory unit 152 is a group of cells that share the same power state (e.g., an active state or a low power state) and transition together between power states. For example, a bank or row of memory cells receives power at the same portion of a power distribution circuit, and thus may always have the same power state. The memory system 100 may include any number "N" of memory units 152.

[0028] Each memory unit 152 may include a group of memory circuits that are powered together and are in the same power state together. A memory device can be partitioned into any number of banks, rows, and rows of banks in any number of ways. For example, a memory device with a capacity of 8 megabytes (MB) can be partitioned into eight individual banks of equal size, for example, 1MB per bank. In this example, each bank can be a memory unit 152. Each memory bank can be a vertical partition of a memory device that can contain a single or multiple physical instances of memory. For example, a 1MB memory bank may contain 1MB of physical instances. In another example, a 1MB memory bank can be partitioned into eight physical instances of memory, such that each physical instance of memory contains 128kB of memory. In this example, each 128kB instance of memory can be a memory unit 152.

[0029] The active state of memory unit 152 is a state in which the memory cells of memory unit 152 can be accessed by the memory controller 110. The power manager 120 can transition memory units to low-power states to reduce power consumption and leakage power of memory unit 152 when it is not being accessed. Exemplary low-power states include write sleep, deep sleep, and power gating. The power manager 120 can transition memory unit 152 between the active state and the low-power state by sending power state instructions to memory unit 152. For example, the power manager 120 can provide one or more power state instructions (e.g., a series of instructions) to one or more memory units 152 to wake up (e.g., transition from a low-power state to an active state) or power down (e.g., transition from an active state to a low-power state). Power state instructions may include input signals to the memory units that enable the transition. Specific instructions may vary based on the type of volatile memory 150 used and the memory management techniques of the memory system 100.

[0030] The power manager 120 includes and / or maintains a status table 122 to store data indicating the current power state of each memory unit 152. The status table 122 includes a cell for each memory unit 152, and the value or label stored in the cell indicates the current power state of the memory unit 152. For example, if the possible states are "active" and "low power," the cell for the memory unit 152 may contain a label indicating "active" or "low power," or a value representing "active" or "low power," such that the value is "1" for active and the value is "0" for low power. Other values ​​may also be used.

[0031] The power manager 120 can maintain the status table 122 based on power state instructions it sends to the memory unit 152 and / or feedback it receives from the volatile memory 150. For example, if the power manager 120 sends a power state instruction to the memory unit 152-3 to transition from an active state to a low-power state, the power manager 120 can use the exemplary labels and values ​​described above to update the cells of the memory unit 152-3 from active to low-power state, i.e., from 0 to 1. In another example, the power manager 120 can wait for feedback indicating that the memory unit 152-3 has successfully transitioned from an active state to a low-power state.

[0032] The memory controller 110 includes a memory access engine 112, a descriptor queue 114, and a queue manager 116. The memory controller 110 can be implemented in hardware and / or software, and the descriptor queue 114 and the queue manager 116 may be additional memory or hardware and / or software of the memory system 100.

[0033] The memory controller 110 is configured to receive memory access requests from agents 105 (e.g., agents 105-1 to 105-N). Agents 105 may be hardware devices or software components (e.g., applications or modules) that provide data for storage in the volatile memory 150 and / or request data stored in the volatile memory 150. Exemplary agents include the operating system (OS) of a computing device, applications running on the computing device, integrated circuits (ICs) communicatively coupled to the memory system 100, processor cores (e.g., central processing unit (CPU), digital signal processor, graphics processing unit (GPU), etc.), and external interfaces.

[0034] A memory access request may be to request data from volatile memory 150 or to store data in volatile memory 150. Each memory access request may include a descriptor and, if the request is to store data, the data to be stored. The descriptor of a memory access request may include data that identifies a memory location, such as a memory address, and a memory operation, such as read / write. The memory location identifies the location in memory where the memory operation is performed. In some embodiments, the memory location may not directly identify a memory unit 152. For example, each memory unit 152 may be a physical instance of memory and correspond to a separate logical memory address assigned to the physical instance. In such an example, the memory controller 110 may be configured to translate the memory location to the corresponding memory unit 152 and / or a specific location (e.g., a group of cells) within the memory unit 152.

[0035] In one example, agent 105 can send a memory access request to memory controller 110 that corresponds to a write request to store data in volatile memory 150. The memory access request includes a descriptor containing the data to be stored and data identifying the memory location where the data is stored and the write operation. Queue manager 116 can store the descriptor in descriptor queue 114.

[0036] In another example, agent 105 may send a memory access request to the memory controller 110 that corresponds to a read request to retrieve data stored in the volatile memory 150. In this example, the memory access request includes a descriptor containing data that identifies the memory location from which the data is retrieved and the read operation. As in the example above, the queue manager 116 may store the descriptors in the descriptor queue 114.

[0037] The descriptor queue 114 is configured to store descriptors received from the agent 105. In some embodiments, the descriptors in the descriptor queue may have a number of bits, such as 24 bits, or a 23-bit value, where all but one bit of the descriptor describes a memory location, while the remaining bits describe an operation, such as read or write. Other number of bits can also be used for each part of the descriptor. The descriptor queue 114 can be implemented as a FIFO queue where descriptors are processed in the order they are received by the memory controller 110. In other words, the descriptor queue 114 can be a FIFO unit. The descriptor queue 114 includes a plurality of queue positions, including an initial position that can store the current descriptor being processed, and a final position that stores the last descriptor currently in the descriptor queue 114 being processed. Each newly received descriptor can be added to the end of the queue, and this queue position becomes the new final queue position.

[0038] The queue manager 116 can be configured to manage descriptors stored in the descriptor queue 114, and pointers to descriptors in the descriptor queue 114. For example, when the queue manager 116 receives a memory access request containing a descriptor, it can be configured to add the descriptor to the descriptor queue 114 (for example, at the tail or last position in the descriptor queue 114). Furthermore, the queue manager 116 can be configured to remove descriptors from the descriptor queue 114 when they are processed by the memory access engine 112, as described below.

[0039] The descriptor queue 114 includes one or more memory access pointers that indicate the next descriptor in the sequence of descriptors being processed. As described below with reference to Figure 2, the descriptor queue 114 may include read access pointers for read operations and write access pointers for write operations. For example, read and write operations may be processed in groups. A read access pointer may indicate the next read operation to be processed, and a write access pointer may indicate the next write operation to be processed. In some embodiments, the descriptor queue includes a single memory access pointer for the next descriptor, regardless of the type of operation.

[0040] The descriptor queue 114 also includes power management pointers that indicate one or more subsequent descriptors that will transition the memory unit to an active state if the memory unit is not already active. When a descriptor is about to be processed, for example, when it is within a specified number of queue positions from its initial position in the descriptor queue 114, the power manager 120 can transition the memory unit 152 corresponding to the descriptor (e.g., the memory unit 152 indicated by the descriptor's memory location) to an active state if the memory unit 152 is currently in a low-power state. The power manager 120 and power management pointers are described in more detail below.

[0041] The memory access engine 112 is configured to process descriptors using memory access pointers and to perform memory operations on the descriptors. Whenever the memory access engine 112 finishes processing a descriptor, it can notify the queue manager 116. In response, the queue manager 116 may remove the processed descriptor from the descriptor queue 114 and update the descriptor queue 114 so that a descriptor that was in the second position is now in the first position, and each other descriptor moves up one position in the descriptor queue 114. By removing processed descriptors from the descriptor queue 114 and updating it with the next descriptor to be processed, the queue manager 116 maintains a FIFO scheme for processing descriptors in the descriptor queue 114.

[0042] The memory access engine 112 can process a descriptor by identifying the descriptor's operation and its memory location. The memory access engine 112 can then perform an operation on the memory unit 152 corresponding to the memory location. For example, if the operation is a read operation, the memory access engine 112 can open the memory unit 152, read the appropriate data from it, and send the data to the agent 105 that sent the memory access request. If the operation is a write operation, the memory access engine 112 can open the memory unit 152 and write data to it. In some embodiments, the memory access engine 112 may be referred to as a direct memory access engine for coupled volatile memory devices.

[0043] The power manager 120 monitors the power management pointer of the descriptor queue 114 and is configured to selectively transition the memory unit 152 between an active state and a low-power state. Using the power management pointer, the power manager 120 can identify subsequent descriptors (e.g., descriptors after the currently processed descriptor) that should cause the memory unit 150 to be in an active state. For each of these subsequent descriptors, the power manager 120 can identify the corresponding memory unit 152 and, if they are not already in an active state, can transition them to an active state. In this way, when a descriptor reaches its first position in the descriptor queue 114, the corresponding memory unit 152 is in an active state, and the memory access engine 112 can immediately access the memory unit 152. This reduces the latency when performing memory operations for memory access requests and, therefore, reduces back pressure on the memory system 110.

[0044] The power manager 120 can also be configured to return the memory unit 152 to a low-power state after it has been accessed for a processed descriptor. For example, the power manager 120 can be configured to monitor a memory access pointer to identify the descriptor being processed. When the memory access pointer transitions to a different descriptor, the power manager 120 can determine that the previous descriptor has been processed. In another example, the memory access engine 112 can be configured to notify the power manager 120 when a descriptor has been fully processed. Such notification may include the descriptor, or at least the memory location of the descriptor.

[0045] Before the memory unit 152 transitions back to a low-power state, the power manager 120 can evaluate the descriptor queue to determine, for example, whether the memory unit 152 will be accessed again immediately within the time required for the memory unit 152 to transition back to an active state if it transitions back to a low-power state. For example, the memory unit may take 3 clock cycles to transition from a low-power state to an active state, and the memory access engine 112 may be able to process one descriptor per clock cycle. In this example, if there are descriptors for the same memory unit 152 in the first three positions of the descriptor queue 114, the power manager 120 can keep the memory unit 152 in an active state, thereby allowing this descriptor to be processed without delay when it reaches the first position of the descriptor queue 114. In some embodiments, the power manager 120 performs this evaluation by determining whether any descriptor between the memory access pointer and the power management pointer is for that memory unit 152.

[0046] A power transition of the memory unit 152 to an active state may include activating the memory unit 152 to an active state (e.g., executing a wake-up routine), which may involve an increase in power consumption. A power transition to a low-power state may include reducing the power of the memory unit to a low-power state, which may involve a reduction in power consumption. In some embodiments, the low-power state may be distinguished between a light sleep state, which reduces power consumption, and a deep sleep state, which further reduces power consumption compared to the light sleep state. As an example, the deep sleep state of the memory unit 152 may result in significant power savings compared to the light sleep state, but may also increase latency, such as additional processing unit clock cycles, additional processing time, and additional memory access operations required to transition to the active state.

[0047] Figure 2 shows an exemplary state of descriptor queue 214. Descriptor queue 214 is an example of descriptor queue 114 as described with reference to Figure 1, and stages A to C show how memory access pointers and power management pointers can be used to process descriptors and transition memory units between active and low-power states.

[0048] Referring to Stage A, the descriptor queue 214 contains descriptors 1 through 13, with descriptor 1 at the first position 221 and descriptor 13 at the last position 222. As described above, each descriptor may include a memory location (e.g., memory address) and an operation (e.g., read or write) corresponding to a memory unit in volatile memory. The read access pointer is a memory access pointer configured to track descriptors for memory access requests that include instructions to read data from memory unit 150. The write access pointer is a memory access pointer configured to track descriptors for memory access requests that include instructions to write data to memory unit 150. The power management pointer is configured, for example, in the illustrated example, to indicate the number of subsequent descriptors following the current descriptor being processed by the read access pointer.

[0049] In this example, the descriptor queue 214 includes both read and write access pointers. The memory access unit 112 can be configured to process descriptors indicated by access pointers higher up in the descriptor queue 214.

[0050] The number of subsequent descriptors read prior to a read access pointer can be based on the amount of time required for the memory unit 152 to transition from a low-power state to an active state. In some embodiments, the amount of time used is the minimum amount of time required for the transition to occur. The amount of time can be based on and / or expressed as the number of clock cycles of the hardware processor performing the memory access operation.

[0051] In some embodiments, the number of subsequent descriptors that transition to the active state and are therefore indicated by the power management pointer can be determined based on the time length of time it takes for the memory unit 152 to transition from the low-power state to the active state, and / or the number of memory access operations that the memory unit can perform per clock cycle. For example, the memory access engine 112 may be able to perform one memory operation per clock cycle. Furthermore, it may take at least 5 clock cycles for the memory unit 152 to transition from the low-power state to the active state. In this example, the power management pointer may indicate a descriptor that is 5 positions below the currently processed descriptor in the descriptor queue 214. For example, as shown in stage A of Figure 2, the power management pointer points to descriptor 6, which is 5 positions below descriptor 1.

[0052] The power manager 120 monitors the power management pointer and can identify all subsequent descriptors between the highest access pointer in the descriptor queue (e.g., the read access pointer at stage A) and the power management pointer. If the memory unit 152 is not yet active, the power manager 120 can transition the memory unit 152 corresponding to each subsequent descriptor to an active state.

[0053] Any number of power management pointers can be used to determine the corresponding group of subsequent descriptors for the transition to the active state. For example, some memory units 152 may have different amounts of time required to transition from a lower power state to the active state. In another example, different transition times may exist depending on the low power state. For example, transitioning from a deep sleep state to an active state may take longer than transitioning from a light sleep state to an active state. The descriptor queue 214 can contain power management pointers for different transition times and / or for each low power state (for example, for different groups of memory units, each having a different transition time). Each power management pointer may indicate a sequence of subsequent descriptors that will cause the memory unit 152 corresponding to the descriptor to transition to the active state.

[0054] For example, a first power management pointer and a first group of subsequent descriptors may correspond to a first set of memory units 152 in volatile memory 150 belonging to one cluster. The first set of memory units 152 may include a first number of clock cycles to transition from a low-power state to an active state. A second power management pointer and a second group of subsequent descriptors may correspond to a second set of memory units 152 in volatile memory 150 belonging to another cluster. The second set of memory units 152 may include a second number of clock cycles to transition from a low-power state to an active state. The first and second power management pointers may have different numbers of subsequent descriptors that they read before the memory access pointer, depending on the difference in transition time.

[0055] The queue manager 116 can manage each power management pointer based on the number of descriptors for each and the descriptors corresponding to the memory unit 152 for its power management pointer. For example, if there is a first set of memory units and the number of descriptors for the first power management pointer is 3, the queue manager 116 can operate the first power management pointer so that it points to a third descriptor (not the currently processed descriptor) in the descriptor queue 214 corresponding to the memory unit 152 in the first set of memory units.

[0056] In some embodiments, all pointers, such as read access pointers, write access pointers, and power management pointers, may be initialized to start from the beginning of the descriptor queue 214, for example, before agent 105 submits a memory access request. Upon receiving a memory access request, the memory access engine 112 may group the memory access requests by operation, such as read or write, so that each pointer for an operation can track a group of operations. For example, a read access pointer may start tracking read memory accesses, and a write access pointer may start tracking write memory accesses.

[0057] Referring again to Stage A, the descriptor queue 214 points to a read access pointer that points to the first descriptor, for example, descriptor 1, while the power management pointer points to descriptor 6. The write access pointer simultaneously points to descriptor 12. In this example, descriptors 1 through 11 correspond to read operations, and descriptors 12 and 13 correspond to write operations.

[0058] The memory access engine 112 can monitor the read access pointer and the write access pointer to obtain the next descriptor for performing a memory operation. For example, the memory access engine 112 can obtain descriptor 1 from the descriptor queue 214 and, based on the read access pointer indicating that descriptor 1 is the next read descriptor and the fact that the read access pointer is higher in the descriptor queue 214 than the write access pointer, can perform a read operation corresponding to descriptor 1.

[0059] The power manager 120 can monitor the power management pointer and identify descriptors that cause the corresponding memory units to transition to an active state. The power manager 120 can identify each descriptor (including both ends) between the top-level memory access pointer and the power management pointer as subsequent descriptors. The power manager 120 can transition the memory unit 152 corresponding to each of these subsequent descriptors to an active state. In this example, the power manager 120 can transition the memory units 152 corresponding to descriptors 2-6 to an active state based on the power management pointer pointing to descriptor 6. The memory units 152 corresponding to subsequent descriptors, for example, descriptors 2-6 in stage A, remain active at least until the memory access engine 112 has finished processing the descriptors, for example, until it has completed the memory operation corresponding to the descriptors.

[0060] For example, the number of subsequent descriptors being scanned by the power management pointer can be particularly advantageous when the number of memory units 152 in the volatile memory 150 exceeds the number of descriptors between the memory access pointer and the power management pointer. For example, a volatile memory device such as SRAM may have 32 memory units, for example, an SRAM bank, along with five subsequent descriptors in the descriptor queue 114 between the memory access pointer and the power management pointer. For example, assuming that all five descriptors being scanned correspond to five memory units 152, up to 27 memory units out of the 32 memory units in the volatile memory can be put into a power-saving state.

[0061] Referring to Stage B, the read access pointer is incremented, for example, by the queue manager 116 after descriptors 1-3 have been processed by the memory access engine 112. The queue manager 116 also increments the power management pointer for each descriptor processed. As shown, here the power management pointer points to descriptor 9, for example, the descriptor five positions after the currently accessed descriptor 4, and maintains the same number of subsequent descriptors in the descriptor queue 214. In Stage B, the power manager 120 transitions descriptors 7-9 to the active state, just as descriptors 4-6 transitioned to the active state in Stage A.

[0062] Referring to Stage C, the read access pointer is incremented after processing descriptors 4-7. Similarly, the power management pointer is incremented to point to descriptors 12. In Stage C, the power manager 120 activates descriptors 10-12, just as descriptors 7-9 were activated in Stage A.

[0063] If the power management pointer points to a descriptor, for example, descriptor 12 in descriptor queue 214, the power manager 120 determines the memory address of the physical instance in volatile memory, for example, the memory unit(s) corresponding to the descriptor(s) that need to transition to the active state. For example, if a scanned descriptor with a descriptor value to be scanned points to a memory unit 152 in volatile memory 150 that is currently active, the power manager 120 ensures that the memory unit 152 remains active until the scanned descriptor is processed by the memory access engine 112.

[0064] Addresses read before the memory access pointer are used to determine which memory units need to be transitioned to the active state. Other memory units, or the current location of the memory access pointer, whose addresses are not determined by the number of subsequent descriptors scanned by the power management pointer, may remain in a low-power state.

[0065] Figure 3 shows a flowchart of an exemplary process 300 for transitioning a memory unit between an active state and a low-power state. Process 300 can be performed by a memory system, for example, the memory system 100 in Figure 1. For simplicity of explanation, process 300 is described as being performed by a component of the memory system 100.

[0066] Descriptors are received based on the power management pointer (302). For example, the power manager 120 can identify one or more descriptors between the descriptor at the first position in the descriptor queue 114 and the descriptor pointed to by the power management pointer (including both ends). The power manager 120 can transition the memory units corresponding to these descriptors to an active state before the descriptors are processed, so that the memory access engine 112 does not have to wait to perform a memory access operation when the descriptors are processed. As described above, each descriptor may contain data indicating the memory location where the memory access operation will be performed.

[0067] The power manager 120 determines whether the memory unit 152 corresponding to the memory address of the descriptor is in an active state (304). As described above, the power manager 120 can maintain a status table 122 for the memory unit 152. The power manager 120 can access the status table 122 to determine whether the memory unit 152 is in an active state. For example, the power manager 120 can access the cell corresponding to the memory unit 152 to obtain a label or value about the current state of the memory unit 152. If the memory unit 152 is in an active state, the power manager 120 can keep the memory unit in an active state (306).

[0068] If the memory unit 152 is not in an active state, the power manager 120 can transition the memory unit 152 to an active state (308). The power manager 120 can then keep the memory unit 152 in an active state until at least a memory access operation of the memory unit is performed.

[0069] A determination is made (310) as to whether the memory unit 152 has been accessed by the memory access engine. For example, the memory access unit 112 may be configured to notify the power manager 120 of each descriptor that has been processed. In another example, the power manager 120 may be configured to monitor the memory access pointer to determine when a descriptor has been processed. If the memory unit 152 has not been accessed, the process 300 can return to operation (306), and the memory unit 152 can remain active until it is accessed.

[0070] To determine whether to return the memory unit 152 to a lower power state, the power manager 120 checks whether any subsequent descriptors that transition to the active state, such as scanned descriptors, contain a memory address pointing to the memory unit 152 (312). For example, the memory access pointer and the power management pointer may indicate the number of subsequent descriptors that the corresponding memory unit 152 should be in an active state. If the descriptor between the memory access pointer and the scan pointer points to the same memory unit 152 that has just undergone a memory access operation, the power manager 120 keeps the memory unit active. This prevents backpressure that might occur if the memory unit 152 transitioned to a low power state, if the memory unit 152 is accessed again in less time than it would take for it to transition from a low power state to an active state.

[0071] If the power manager 120 determines that none of the subsequent descriptors between the memory access pointer and the power management pointer contain a memory location corresponding to the memory unit 152, the power manager 120 can transition the memory unit 120 to a low-power state (314). Otherwise, the process 300 can return to the operation in which the power manager 120 keeps the memory unit 152 active (306), and as a result, the descriptors corresponding to the memory unit 152 can be processed without delay.

[0072] Figure 4 shows a flowchart of an exemplary process 400 for accessing a memory unit and transitioning the memory unit between an active state and a low-power state. Process 400 can be executed by a memory system, for example, a memory system 100, to manage volatile memory 150 to satisfy memory access requests received from one or more agents 105.

[0073] The memory controller 110 accesses a descriptor queue, for example, descriptor queue 114 (402). Descriptor queue 114 contains a sequence of descriptors, memory access pointers, and power management pointers. The queue manager 116 may be configured to update the descriptor queue with descriptors when the memory controller 110 receives a new memory access request. In some implementations, the memory access engine 114 of the memory controller 110 may be configured to process new memory requests. The descriptor queue can be a FIFO queue into which descriptors corresponding to memory access operations from the agent device of agent 105 are entered. The memory access engine 112 may be configured to read the sequence of descriptors from the sequence of descriptors, including memory access pointers that access memory addresses, and the sequence of descriptors based on the operations contained in the descriptors.

[0074] The memory controller 110 identifies one or more subsequent descriptors in the descriptor queue 114 that transition to the active state (404). The power manager 120 can use a power management pointer to determine which subsequent descriptors the corresponding memory unit should transition to the active state before the descriptors are processed by the memory access engine 114. As described above, the number of subsequent descriptors identified may be based, for example, on the amount of time required for the memory unit to transition from a low-power state to an active state in terms of the number of clock cycles.

[0075] In some embodiments, the queue manager 116 maintains a distance with respect to the number of descriptors between the memory access pointer and the power management pointer. The number of descriptors in this distance can be based on the amount of time required for the memory unit 152 to transition from a low-power state to an active state, and / or the number of descriptors that can be processed simultaneously. The amount of time for the transition can be expressed as the number of clock cycles of the processor of the memory system 100, or the processor of a system including the memory system 100 and / or a system communicatively coupled to the memory system 100.

[0076] For example, if the memory system 100 can process one descriptor per clock cycle, and the memory unit 152 requires three clock cycles to transition from a low-power state to an active state, the distance between the memory access pointer and the power management pointer may be three descriptors. In this way, the power management pointer moves to a new descriptor each clock cycle, remaining three descriptors ahead of the memory access pointer, and the new descriptor has three clock cycles to transition to the active state before reaching the head of the descriptor queue 114.

[0077] In this way, each descriptor's memory unit 152 has enough time to transition to the active state before being processed by the memory controller 110, but the memory units 152 are not transitioned too early, so that they remain active longer than they are approved. This reduces the amount of time the memory units 152 are active, thereby reducing the amount of leakage power, and similarly, the latency and backpressure caused by the memory units 152 not being active when reaching the top of the descriptor queue 114.

[0078] The power manager 120 transitions the memory unit corresponding to the identified subsequent descriptor, which is currently in a low-power state, to an active state (406).

[0079] The memory controller 110 accesses one or more memory units for each subsequent descriptor when the memory access pointer points to a subsequent descriptor in the descriptor queue (408). The queue manager 116 is configured to update the memory access pointer and the power management pointer after each descriptor of a subsequent descriptor has been processed by the memory controller 110. In some embodiments, accessing one or more memory units for each subsequent descriptor includes performing memory access operations related to the subsequent descriptor (e.g., reading data from a memory unit, writing data to a memory unit).

[0080] The subject matter and functional embodiments described herein can be implemented in digital electronic circuits, tangibly embodied computer software or firmware, or computer hardware, including the structures disclosed herein and their structural equivalents, or one or more combinations thereof. Embodiments of the subject matter described herein can be implemented as one or more computer programs encoded in a tangible, non-transient program carrier, i.e., one or more modules of computer program instructions, to be executed by a data processing device or to control the operation of a data processing device. Alternatively or additionally, program instructions may be encoded into artificially generated propagating signals, such as mechanically generated electrical signals, optical signals, or electromagnetic signals, which are generated to encode information for transmission to a receiving device suitable for execution by a data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random-access memory device or a serial-access memory device, or one or more combinations thereof.

[0081] The processes and logic flows described herein can be performed by one or more programmable computers executing one or more computer programs to act on input data and produce outputs. The processes and logic flows can also be performed by dedicated logic circuits, such as FPGAs (Field-Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), or GPGPUs (General-Purpose Graphics Processing Units), and these devices can also be implemented as dedicated logic circuits.

[0082] A computer suitable for running computer programs may include, for example, a general-purpose or dedicated microprocessor, or both, or any other type of central processing unit, or may be based on them. Generally, a central processing unit receives instructions and data from read-only memory, random-access memory, or both. The basic components of a computer are a central processing unit for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer may also include one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or may be operably connected to them to receive data from them, transmit data to them, or both. However, a computer is not required to have such devices. Furthermore, a computer may be incorporated into other devices, such as mobile phones, personal digital assistants (PDAs), mobile audio or video players, game consoles, Global Positioning System (GPS) receivers, or portable storage devices (such as Universal Serial Bus (USB) flash drives) (these are just a few examples).

[0083] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks. Processors and memory may be complemented by or incorporated into dedicated logic circuits.

[0084] While this specification includes details of many specific embodiments, these should not be construed as limiting the scope or claimable content of any invention, but rather as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described herein as separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described as a single embodiment may also be implemented in multiple embodiments, individually or in any preferred secondary combination. Furthermore, features may be described above as functioning in a particular combination, and even if initially claimed as such, one or more features from the claimed combination may be removed from the combination, and the claimed combination may cover secondary combinations or variations of secondary combinations.

[0085] Similarly, while operations are shown in a specific order in the drawings, this should not be understood as requiring that such operations be performed in a specific illustrated or sequential order, or that all illustrated operations be performed, in order to achieve the desired result. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the program components and systems described can generally be integrated into a single software product or packaged into multiple software products.

[0086] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions described in the claims may be performed in a different order, and this may still yield desirable results. As an example, the process shown in the accompanying drawings does not necessarily require to be performed in the specific order or sequence shown to obtain the desired results. In certain embodiments, multitasking and parallel processing may be advantageous.

Claims

1. It is a memory system, A volatile memory containing multiple memory units, The memory system further comprises a descriptor queue configured to maintain a sequence of descriptors corresponding to received memory access requests for each of the plurality of memory units to perform memory access operations, the descriptor queue includes a memory access pointer indicating the current descriptor to be processed, and a power management pointer indicating one or more subsequent descriptors for active state transitions, and the memory system further comprises A memory controller configured to process the descriptors in the descriptor queue based on the memory access pointer and to access the memory unit of the descriptor in order to respond to an incoming memory access request corresponding to the descriptor in the descriptor queue, A power manager configured to selectively transition each memory unit between the active state and the low-power state, including monitoring the power management pointer to identify one or more subsequent descriptors, and transitioning each of the one or more subsequent descriptors from the low-power state to the active state for each of the one or more subsequent descriptors before they are processed by the memory controller, A memory system equipped with the following features.

2. The memory system according to claim 1, wherein the descriptor queue includes a first-in, first-out queue, and each descriptor is removed from the descriptor queue after the memory controller has performed a memory access operation indicated by the descriptor.

3. The memory system according to claim 1, wherein the volatile memory includes static random access memory (SRAM).

4. The descriptor queue includes a queue manager, and the queue manager is Update the descriptor queue to include the descriptor for each newly received memory access request, After each descriptor has been processed by the memory controller, the memory access pointer is updated. The memory system according to claim 1, wherein each descriptor is configured to update the power management pointer after it has been processed by the memory controller.

5. The memory system according to claim 1, wherein the one or more subsequent descriptors include a number of descriptors selected based on the amount of time required for the memory unit to transition from the low-power state to the active state.

6. The memory system according to claim 5, wherein the number of descriptors is based on the number of memory access operations that the memory controller can complete within the given time.

7. The memory system according to claim 5, wherein the number of descriptors is based on the number of processing unit clock cycles of a processor communicatively coupled to the volatile memory that occur during the amount of time.

8. The memory system according to claim 1, wherein the descriptor queue includes one or more additional power management pointers indicating an additional set of subsequent descriptors for active state transitions.

9. The memory system according to claim 8, wherein the additional set of subsequent descriptors includes an additional number of descriptors selected based on the time length required for the memory unit corresponding to each additional descriptor to transition from the low-power state to the active state.

10. The memory system according to claim 9, wherein the number of additional descriptors is based on the number of memory access operations that the memory controller can complete within the time length.

11. The aforementioned power manager, Determine whether each of the memory units of the current descriptor is a subsequent descriptor for an active state transition. Whenever the memory units of the current descriptor are subsequent descriptors for an active state transition, after processing the current descriptor, the memory units of the current descriptor remain in the active state. The memory system according to any one of claims 1 to 10, wherein the system is configured to transition each of the memory units of the current descriptor from the active state to the low-power state whenever the respective memory unit of the current descriptor is not a subsequent descriptor for an active state transition.

12. A method performed by a memory controller configured to manage volatile memory comprising multiple memory units, wherein the method is: This includes accessing a descriptor queue, the descriptor queue is: The received memory access request includes a sequence of descriptors, each descriptor corresponding to a memory access operation to each of the plurality of memory units indicated by the descriptor, and the descriptor queue further includes: A memory access pointer indicating the current descriptor for processing, The method further includes a power management pointer indicating one or more subsequent descriptors for an active state transition, and the method further includes Identifying one or more subsequent descriptors based on the power management pointer, Transitioning each subsequent descriptor in the low-power state from the low-power state to the active state, When the memory access pointer reaches the subsequent descriptor in the descriptor queue, it accesses one or more memory units for each subsequent descriptor. Methods that include...

13. The method according to claim 12, wherein accessing one or more memory units of each subsequent descriptor includes performing the memory access operation of the subsequent descriptor.

14. The method according to claim 12, further comprising updating the memory access pointer and the power management pointer to indicate a different descriptor each time the memory access operation for a descriptor is performed and the descriptor is removed from the descriptor queue.

15. Executing the memory access operation of the current descriptor, In response to performing the memory access operation of the current descriptor, the current descriptor is removed from the descriptor queue, Updating the memory access pointer to indicate the next descriptor in the descriptor queue following the current descriptor, Updating the power management pointer in response to performing the memory access operation of the current descriptor updates one or more subsequent descriptors for an active state transition, The method according to claim 12, further comprising:

16. To determine whether each of the memory units of the current descriptor is a subsequent descriptor for an active state transition, Whenever each of the memory units of the current descriptor is a subsequent descriptor for an active state transition, the memory units of the current descriptor are kept in the active state after processing the current descriptor. If each of the memory units of the current descriptor is not a subsequent descriptor for an active state transition, then each of the memory units of the current descriptor is transitioned from the active state to the low-power state. The method according to claim 15, further comprising:

17. The method according to claim 12, further comprising identifying each descriptor between the memory access pointer and the power management pointer as one or more subsequent descriptors.

18. The method according to claim 17, further comprising controlling the power management pointer to identify a specific number of subsequent descriptors based on the time length required for the memory unit to transition from the low-power state to the active state.

19. The method according to claim 12, wherein the descriptor queue includes a first-in, first-out queue, and each descriptor is removed from the descriptor queue after the memory controller has performed the memory access operation indicated by the descriptor.

20. The method according to claim 12, wherein the volatile memory includes static random access memory (SRAM).

21. The descriptor queue includes a queue manager, and the queue manager is Update the descriptor queue to include the descriptor for each newly received memory access request, After each descriptor has been processed by the memory controller, the memory access pointer is updated. The method according to claim 12, wherein each descriptor is configured to update the power management pointer after it has been processed by the memory controller.

22. The method according to claim 12, wherein the one or more subsequent descriptors include a number of descriptors selected based on the time length required for the memory unit to transition from the low-power state to the active state.

23. The method according to claim 22, wherein the number of descriptors is based on the number of memory access operations that the memory controller can complete within the time length.

24. The method according to claim 22, wherein the number of descriptors is based on the number of processing unit clock cycles of a processor communicatively coupled to the volatile memory that occur during the time length.

25. Determining that a specific descriptor corresponding to a specific memory unit is not in the descriptor queue, In response to determining that the specific descriptor corresponding to a particular memory unit is not in the descriptor queue, the specific memory unit is transitioned to the low-power state, The method according to any one of claims 12 to 24, further comprising:

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