Method for creating a strain layer

Abstract

This specification relates to a method for producing a strained metal layer, semiconductor layer, or insulating layer, the method comprising the step of transferring the metal layer, semiconductor layer, or insulating layer (11) from a first support substrate (10) to a second support substrate (20), wherein the thermal expansion coefficients of the first and second support substrates (10, 20) are different, and the transfer step is performed at a high temperature. After removing the first support substrate (10), the resulting structure is cooled to obtain a metal layer, semiconductor layer, or insulating layer (11) that has been subjected to tensile or compressive strain.

Description

[Technical Field]

[0001] This disclosure relates to the fabrication of strain layers in general. Such strain layers are particularly advantageous for structures used in microelectronics, especially for SSOI (Strained Silicon On Insulator) type structures. [Background technology]

[0002] Silicon-on-insulator (SOI) substrates include substrates formed from semiconductor materials covered with thin oxide and silicon layers. These structures are particularly advantageous because they avoid the use of bulk substrates and allow for higher component integration density.

[0003] Forming strain layers within these structures is attracting considerable interest in many applications.

[0004] For example, the fabrication of SSOIs can improve the performance of microprocessors [Huang et al. "Carrier mobility enhancement in strained Si-on-insulator fabricated bywafer bonding," "2001 Symposium on VLSI Technology, 2001. Digest of Technical Papers, 57-58, 2001; Mazurier et al. "High performance and low variability fully-depleted strained-SOIMOSFETs," 2010 IEEE International SOI Conference (SOI), 1-2, 2010].

[0005] By applying strain to a germanium film, gaps are directly formed within the germanium, making it even possible to fabricate optical devices [Gassenq et al. "1.9% Bi-Axial Tensile Strain in Thick Germanium Suspended Membranes Fabricated in Optical Germanium-on-Insulator Substrates for Laser Applications", Applied Physics Letters 107, 19, 2015, 191904]. [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] Generally, an epitaxial growth process is performed to create a strained layer. This type of growth makes it possible to utilize the mismatch in lattice constants. However, dislocations and other crystal defects inevitably occur in the strained layer. Therefore, in the SSOI structure, 10 5 Dislocation / cm 2 It is difficult to obtain less than this.

[0007] Alternatively, these structures can be manufactured by performing thermal bonding to better control the distortion of the SSOI structure [Abadie et al. "Germanium Thin Film Manufacturing Using Covalent Bonding Process", Semiconductor Science and Technology 37, 4, 2022, 045012], or by bonding with curvature, as described in European Patent No. 1570509. These various bonding techniques allow for the addition of distortion to the structure while avoiding the generation of crystal defects.

[0008] However, after thermal bonding, the bonded structure must withstand returning to room temperature despite the difference in thermal expansion coefficients of the bonded materials. However, due to the large thickness of the bonded materials (typically greater than 100 μm), the accumulated elastic energy can reach a considerable value, potentially causing defects or failure in the bonded structure. Therefore, the thermal bonding temperature must be limited, which in turn limits the available strain level.

[0009] A method is needed to manufacture a tensile strain layer or a compressive strain layer, and the resulting strain layer must exhibit a high strain level (particularly greater than 200 MPa, preferably greater than 700 MPa, or even greater than 1 GPa) and have a low incidence of crystal defects or be free of crystal defects. [Means for solving the problem]

[0010] The purpose is a method for manufacturing a strain layer, a) A step of preparing a first basic structure, which includes a first support substrate formed of a first material having a thickness greater than 100 μm, preferably greater than 500 μm, and for example greater than 700 μm, and on the one hand, a first support substrate formed of a first material having a thickness greater than 100 μm, preferably greater than 500 μm, and for example greater than 700 μm, and on the other hand, a second basic structure, which includes a second support substrate having a thickness greater than 100 μm, preferably greater than 500 μm, and for example greater than 700 μm, wherein the thermal expansion coefficient of the first support substrate is different from that of the second support substrate, and the first and second support substrates are selected such that the thermal expansion coefficients of the first and second support substrates cause a desired strain level in the metal layer, semiconductor layer, or insulating layer during step c), b) assembling said first base structure and said second base structure by bonding them at a bonding temperature Tc such that Tc>70° C., to obtain a bonded structure in which a metal layer, a semiconductor layer or an insulating layer is strained at a first strain level, then removing the first support substrate at a temperature Tt such that Tc-50° C.<Tt<Tc+50° C. and Tt>70° C., to transfer the metal layer, semiconductor layer or insulating layer onto the second base structure, wherein during bonding and removal of the first support substrate, the temperature of the bonded structure is maintained at a temperature higher than 70° C. and within a range of not more than 50° C. relative to the bonding temperature, such that the transferred metal layer, semiconductor layer or insulating layer is strained at the first strain level on the second support substrate; c) cooling the resulting assembly to obtain a metal layer, a semiconductor layer or an insulating layer to which tensile strain or compressive strain is applied at a desired strain level The method of the present invention is achieved by a method comprising the above steps.

[0011] When the material of the useful layer is the same as the material of the second support substrate, the desired strain level is equal to the first strain level. When the material of the useful layer and the material of the second support substrate are different, the strain of the useful layer is changed according to the difference in CTE between the two materials.

[0012] The present invention is fundamentally different from the prior art in that all transfer steps are performed at high temperature, that is, not only the step of bonding the base structures but also the step of removing the first support substrate is performed at high temperature. High temperature means a temperature higher than 70° C.

[0013] Furthermore, during the bonding of the two base structures and the removal of the first support substrate, the temperature of the bonded structure is maintained at a temperature Tt such that Tc-50° C.<Tt<Tc+50° C. and Tt>70° C. In other words, the bonded structure is always at a temperature higher than 70° C.

[0014] Because the layer thickness is small (less than 10 μm), high strain occurs in the layer during heating. However, because the first support substrate is very thick, no strain occurs in the first support substrate, or if strain occurs, it is relatively small. Therefore, the accumulated elastic energy is sufficiently low, preventing any damage or defects in the support substrate.

[0015] Furthermore, because the layer thickness is small (less than 10 μm), high strain occurs in the layer during cooling. However, because the second support substrate is very thick, strain does not occur in the second support substrate, or if it does, it is relatively small. Therefore, the accumulated elastic energy is sufficiently low, preventing any damage or defects in the support substrate.

[0016] In this way, an assembly is obtained that includes a second support substrate covered with a metal layer, semiconductor layer, or insulating layer and is substantially free of strain, the internal strain within this metal layer, semiconductor layer, or insulating layer being relatively uniform and greater than the internal strain initially present in the same layer on the first support substrate before heating.

[0017] During step c), the temperature Tt may be the same as the bonding temperature Tc, or it may be close to the bonding temperature Tc. "Close to" means a variation within a range of 50°C or less, or 20°C or less, from the bonding temperature, and preferably no variation exceeding 10°C from the bonding temperature. The temperature is selected according to the layer to which strain is desired, so as not to adversely affect the transfer process.

[0018] The bonding is performed at a high temperature (Tc > 70°C), and the temperature of the bonded structure is maintained within a temperature range that has a final value that does not fluctuate by more than 50°C, 20°C, or preferably 10°C from the bonding temperature.

[0019] The smaller the temperature difference, the greater the potential difference in CTE between the two substrates, resulting in greater distortion.

[0020] The metal layer, semiconductor layer, or insulating layer is a semiconductor layer, and it is advantageous that it is preferably formed of silicon.

[0021] The first basic structure may comprise one or more additional layers disposed above and / or below a metal layer, a semiconductor layer or an insulating layer.

[0022] The second basic structure may comprise one or more additional layers disposed on the second support substrate.

[0023] The provision of these additional layers may facilitate thermal bonding and / or make it possible to protect the metal layer, the semiconductor layer or the insulating layer.

[0024] The additional layer may be selected from, for example, an oxide layer, a nitride layer, and a layer of amorphous semiconductor material.

[0025] It is advantageous that the first basic structure comprises a first support substrate, a metal layer, a semiconductor layer or an insulating layer, and a first layer of amorphous semiconductor material, and / or the second basic structure comprises a second support substrate and a second layer of amorphous semiconductor material. According to this advantageous embodiment, in step b), the first layer of amorphous semiconductor material is bonded to the second layer of amorphous semiconductor material.

[0026] It is advantageous that the first support substrate and the second support substrate are selected from substrates formed of germanium, SiC, sapphire, copper, stainless steel, silicon, SiGe, GaN, silica, InP, AsGa and diamond. The support substrate is selected depending on the layer to be transferred.

[0027] According to a first advantageous embodiment, the first support substrate is formed of sapphire, and the second support substrate is formed of silica.

[0028] According to a second embodiment, the first support substrate is formed of copper, and the second support substrate is formed of silica.

[0029] These first two variants are advantageous for applying tension to a layer, for example a silicon layer.

[0030] According to a third advantageous alternative embodiment, the first support substrate is made of silicon and the second support substrate is made of copper.

[0031] When assembling the first basic structure with the second basic structure, it is advantageous to perform a so-called curved joint to adjust the strain level.

[0032] It is advantageous to repeat steps b) and c) multiple times to increase the strain within the layer. According to this advantageous modification, after step c), d) A step of bonding a metal layer, a semiconductor layer, or an insulating layer to a third support substrate, preferably the same as the first support substrate. e) Step of removing the second support substrate, f) A step of transferring the metal layer, semiconductor layer, or insulating layer onto a fourth support substrate, preferably the same as the second support substrate, by performing step b), g) A step to cool the assembly obtained in step f). It is preferable that it has

[0033] The metal layer, semiconductor layer, or insulating layer is a semiconductor layer, and the method is advantageous to have a subsequent step after step c) or step g) in which the metal layer, semiconductor layer, or insulating layer is transferred onto a semiconductor substrate covered with an oxide layer to form a structure on an insulator (SSOI if the layer of interest is silicon). [Brief explanation of the drawing]

[0034] These and other features and advantages are described in detail in the following specific embodiments, which are given as examples not limiting the invention with reference to the accompanying drawings.

[0035] [Figure 1A] This figure schematically shows one step of a method for manufacturing a strained layer according to a first specific embodiment of the present invention. [Figure 1B] This figure schematically shows one step of a method for manufacturing a strained layer according to a first specific embodiment of the present invention. [Figure 1C] This figure schematically shows one step of a method for manufacturing a strained layer according to a first specific embodiment of the present invention. [Figure 2A] This figure schematically illustrates one step of a method for manufacturing a strained layer according to another specific embodiment of the present invention. [Figure 2B] This figure schematically illustrates one step of a method for manufacturing a strained layer according to another specific embodiment of the present invention. [Figure 2C] This figure schematically illustrates one step of a method for manufacturing a strained layer according to another specific embodiment of the present invention. [Figure 3A] This figure schematically illustrates one step in a method for manufacturing a basic structure including a layer to which strain is applied, according to a specific embodiment of the present invention. [Figure 3B] This figure schematically illustrates one step in a method for manufacturing a basic structure including a layer to which strain is applied, according to a specific embodiment of the present invention. [Figure 3C] This figure schematically illustrates one step in a method for manufacturing a basic structure including a layer to which strain is applied, according to a specific embodiment of the present invention. [Figure 4A] This figure schematically illustrates one step in a method for manufacturing a basic structure including a layer to which strain is applied, according to another specific embodiment of the present invention. [Figure 4B] This figure schematically illustrates one step in a method for manufacturing a basic structure including a layer to which strain is applied, according to another specific embodiment of the present invention. [Figure 4C] This figure schematically illustrates one step in a method for manufacturing a basic structure including a layer to which strain is applied, according to another specific embodiment of the present invention. [Figure 4D] This figure schematically illustrates one step in a method for manufacturing a basic structure including a layer to which strain is applied, according to another specific embodiment of the present invention. [Figure 5] This is a schematic cross-sectional view showing an SSOI structure including a strain layer according to a specific embodiment of the present invention.

[0036] For clarity in the drawing, various elements are not shown at a uniform scale. [Modes for carrying out the invention]

[0037] The same elements are indicated by the same reference numeral in various drawings. In particular, structural and / or functional elements common to various embodiments may have the same reference numeral and may have the same structural, dimensional, and material properties.

[0038] For clarity, only the steps and elements useful for understanding the embodiments described are shown and described in detail.

[0039] In the following descriptions, when referring to phrases that specify a relative position, such as "above" or "below," unless otherwise specified, these phrases refer to the orientation of the drawing.

[0040] Unless otherwise specified, the expressions "approximately," "briefly," "substantially," and "to the extent" represent plus or minus 10%, preferably plus or minus 5%, of the corresponding value.

[0041] A method for manufacturing a strained metal layer, semiconductor layer, or insulating layer will first be described in more detail with reference to Figures 1A-1C and 2A-2C. Depending on the application of the strained layer, the layer may be subjected to tensile strain or compressive strain.

[0042] A method for manufacturing a strained metal layer, semiconductor layer, or insulating layer includes a step of transferring the metal layer, semiconductor layer, or insulating layer 11 from a first support substrate 10 to a second support substrate 20, wherein the first support substrate 10 and the second support substrate 20 have different coefficients of thermal expansion. The joining and transfer step is performed at a high temperature. After removing the first support substrate, the resulting structure is cooled to obtain a metal layer, semiconductor layer, or insulating layer 11 that has been subjected to tensile or compressive strain.

[0043] More specifically, this method is, a) on the one hand, providing a first basic structure S1 comprising a first support substrate 10 covered with a metal layer, a semiconductor layer or an insulating layer 11 having a thickness of less than 10 µm, and on the other hand, providing a second basic structure S2 comprising a second support substrate 20, the coefficient of thermal expansion of the first support substrate 10 being different from the coefficient of thermal expansion of the second support substrate 20 (Figures 1A and 2A); b) - assembling and bonding the first basic structure S1 and the second basic structure S2 at a bonding temperature Tc such that Tc>70°C (Figures 1B and 2B) to obtain a bonded structure, thereafter, - removing the first support substrate 10 at a temperature Tt such that Tt>70°C and Tc-50°C<Tt<Tc+50°C, preferably Tc-20°C<Tt<Tc+20°C, more preferably Tc-10°C<Tt<Tc+10°C (Figures 1C and 2C), transferring the metal layer, semiconductor layer or insulating layer 11 from the first support substrate 10 onto the second support substrate 20 (during the bonding and removing of the first support substrate, the temperature of the bonded structure is always maintained above 70°C and within a range of not more than 50°C, preferably not more than 20°C, more preferably not more than 10°C from the bonding temperature); c) obtaining the metal layer, semiconductor layer or insulating layer 11 to which tensile strain or compressive strain is applied by cooling the assembly obtained in step b) comprising the above steps.

[0044] The strained layer 11 may be a metal layer, a semiconductor layer or an insulating layer. The term "insulating layer" refers to an electrically insulating layer. Preferably, the layer is a semiconductor layer, more preferably a semiconductor layer formed of silicon or SiGe. The semiconductor layer may be an amorphous layer or a crystalline (preferably single-crystalline) layer. The insulating layer may be silica.

[0045] The thickness of the strained layer 11 is less than 10 µm, preferably less than 2 µm. The thickness of the layer may be less than 500 nm or less than 200 nm. The thickness of the layer 11 is preferably greater than 5 nm, more preferably greater than 10 nm. Depending on the thickness of the layer 11, this layer may also be referred to as a film.

[0046] The coefficient of thermal expansion (CTE) of the first support substrate 10 is different from that of the second support substrate 20. The first and second support substrates are selected according to the desired strain (tensile or compressive) and the properties of the layer to which the strain is applied.

[0047] The material of the first support substrate 10 is different from the material of layer 11. Therefore, the thermal expansion coefficient of the first support substrate 10 is different from that of layer 11. Due to the difference in CTE between the material of layer 11 and the material of the first support substrate 10, either compression or tension occurs in layer 11 during the temperature rise before bonding. As a result, the layer is at a first strain level. By selecting an appropriate material for the second support substrate, it is possible to increase or decrease this tension or compression to obtain a desired strain level of layer 11 at the end of the method.

[0048] The thermal expansion coefficients of the support substrates 10 and 20 may be higher or lower than the thermal expansion coefficient of the layer 11 to which strain is applied. Preferably, the thermal expansion coefficient of one of the support substrates 10 and 20 is higher than that of the layer 11 to which strain is applied, and the thermal expansion coefficient of the other support substrate 10 or 20 is lower than that of the layer 11 to which strain is applied.

[0049] The support substrates 10 and 20 are selected from substrates formed of germanium, SiC, sapphire, copper, stainless steel, silicon, SiGe, GaN, silica, InP, AsGa, and diamond.

[0050] For example, in order to apply tension to layer 11 using a silicon layer, the first support substrate 10 and the second support substrate 20 are - A first support substrate 10 made of sapphire and a second support substrate 20 made of silica, - A first support substrate 10 made of copper and a second support substrate 20 made of silica You may choose either of the pairs.

[0051] For example, the CTE of silica is approximately 0.5 ppm and hardly changes with temperature.

[0052] Conversely, the CTE of silicon typically fluctuates between 2 ppm at room temperature (i.e., temperatures in the range of 20°C to 25°C) and 4 ppm around 450°C.

[0053] The CTE of copper typically varies between 16 ppm at room temperature and 20 ppm around 450 °C.

[0054] The CTE of sapphire typically varies between 6.5 ppm at room temperature and 7.5 ppm at around 450 °C.

[0055] Therefore, when the first structure S1 is heated during step b), the copper or sapphire support substrate 10 expands more than the silicon, and as a result, the silicon layer 11 expands. The expanded silicon layer 11 is thermally bonded to the second support substrate 20, which is made of silica and hardly expands. The first support substrate 10 is removed at a high temperature. As the temperature decreases again, the silica support substrate 20 hardly shrinks, and the tension of the easily shrinkable silicon layer 11 increases further.

[0056] If the first support substrate is not removed before cooling, the assembly formed by the assembly of the first and second basic structures will be damaged by internal strain generated by the difference in thermal expansion coefficients between the two support substrates.

[0057] The first structure S1 may be formed from a first support substrate 10 covered with a layer 11 to which strain is applied.

[0058] According to an advantageous alternative embodiment, the first structure S1 further includes a first layer 13 of a material that can facilitate or enable thermal bonding. The first layer 13 may further advantageously protect layer 11 during bonding and transfer. This first layer may be formed of an amorphous semiconductor material, such as amorphous silicon in particular (Figure 1A).

[0059] According to a particular alternative embodiment, the first structure S1 further includes an oxide layer 12 positioned between the strained layer 11 and the amorphous silicon layer 13 (Figure 2A). Generally, it is possible to have one or more multilayer structures above and / or below layer 11.

[0060] The first structure S1 may further include a layer or multilayer structure between the first support substrate 10 and the layer 11 to which strain is applied, which enables delamination during step b), particularly in the case of laser lift-off (LLO). The multilayer structure may be a two-layer structure including a GaN layer and an oxide layer, for example, in the case of the first support substrate 10 formed of sapphire. The multilayer structure may further be a three-layer structure of SiO2 / AlN / SiO2 or SiO2 / TiN / SiO2, for example, in the case of the first support substrate 10 formed of silicon. The multilayer structure may further be a silicon layer or a silicon / oxide two-layer structure when transferred using Smart Cut® processing. The splitting by Smart Cut® processing occurs in this silicon layer, not in layer 11. This silicon layer may be polycrystalline. As a variation, the splitting may occur in layer 11.

[0061] As shown in Figures 3A-3C and 4A-4D, an SOI substrate including a semiconductor substrate 14 covered with an oxide layer 12 and a semiconductor layer 11 is bonded to a first support substrate 10 or, if applicable, a delamination layer or multilayer structure. Then, the semiconductor substrate 14 and optionally the oxide layer 12 are removed to obtain the first structure S1. This allows for obtaining a structure that can be bonded and transferred at high temperatures.

[0062] The second structure S2 may be formed from the first support substrate 20.

[0063] According to an advantageous alternative embodiment, the second structure S2 may be formed of a second support substrate 20 covered with a second layer 21 of a material that can promote or enable thermal bonding. This layer 21 may be formed of an amorphous semiconductor material, such as amorphous silicon in particular (Figure 1A).

[0064] It is preferable that the first layer 13 of the amorphous semiconductor material and the second layer 21 of the amorphous semiconductor material are formed of silicon.

[0065] The first layer 13 of the amorphous semiconductor material and the second layer 21 of the amorphous semiconductor material may be formed, for example, by chemical vapor deposition techniques, particularly reduced-pressure chemical vapor deposition (LPCVD).

[0066] In step b), the layer 11 to which strain is applied is moved from the first basic structure S1 to the second basic structure S2. During the transfer, in the first step, the first basic structure S1 is assembled with the second basic structure S2 at a high temperature, the layer 11 is placed on the second basic structure S2, and then the first support substrate 10 is removed at a high temperature.

[0067] First, the two basic structures S1 and S2 are assembled by thermal bonding. For example, if amorphous semiconductor material layers 13 and 21 are present, the basic structures S1 and S2 are assembled by bringing the surfaces of the amorphous semiconductor material layers 13 and 21 into contact.

[0068] To facilitate bonding, the surfaces to be bonded may be pre-treated with various processes, such as mechanical polishing and / or chemical polishing, chemical treatment, UV / ozone treatment, RIE (reactive ion etching), plasma, or hydrogen annealing.

[0069] The bonding may be performed under ultra-high vacuum (UHV).

[0070] The bonding is preferably SAB (surface-activated bonding). For this purpose, the surfaces of structure S1 and structure S2 are ion-irradiated under ultra-high vacuum before contact.

[0071] In the case of SAB bonding and a second support substrate 20 formed of silica, a second layer 21 of amorphous silicon may be pre-deposited on the second support substrate 20 to promote SAB bonding.

[0072] The layer 11 to be subjected to strain can be covered with an oxide layer, and then with an amorphous silicon layer 13. The oxide layer avoids damaging layer 11 during the SAB process and creating particularly undesirable amorphous regions on the surface. The amorphous silicon layer 13 facilitates the bonding of the SAB.

[0073] Alternatively, the bonding is ADB (activated diffusion bonding). A filler metal may be used to assemble the surfaces to be bonded. The filler metal may be a semiconductor layer such as silicon or germanium.

[0074] According to the embodiment, the bonding may be a so-called curved bonding. The curvature of the amorphous semiconductor material layers 13 and 21 is selected to allow the transfer of the layer 11 (metal layer, semiconductor layer, or insulating layer) to which strain is applied. The bonding is then performed at a high temperature with the curvature applied.

[0075] To perform a curved joint, a difference in tangential strain is introduced between the two surfaces to be assembled before bringing the two amorphous layers 13 and 21 into contact. This difference can be obtained, for example, by curving each of the two basic structures S1 and S2 to be assembled by applying a mechanical force. For example, by using a curvatured electrostatic support (chuck), it is possible to impart curvature to basic structures S1 and S2 when applying electrostatic force. It is advantageous that basic structures S1 and S2 are curved such that the two surfaces to be assembled are complementary. For example, one surface may be concave and the other surface may be convex.

[0076] The amorphous layers 13 and 21 are bonded at a bonding temperature referred to as Tc. The bonding temperature is determined according to the materials to be bonded. Advantageously, the bonding temperature Tc may be maintained for a period ranging from 1 minute to 10 hours after bonding. The bonding temperature Tc is at least 50°C higher than the ambient temperature (TA), that is, at a typical ambient temperature of 20°C, the bonding temperature Tc is higher than 70°C. It is advantageous that Tc>RT+380°C (in other words, when RT=20°C, Tc>400°C), or Tc>RT+880°C (in other words, when RT=20°C, Tc>900°C).

[0077] During bonding, the basic structure S1 and the basic structure S2 may each be held by an electrostatic support (chuck) that can be heated to the same temperature or different temperatures.

[0078] According to a first alternative embodiment, during bonding, the first basic structure S1 and the second basic structure S2 are at the same temperature.

[0079] According to another alternative embodiment, during bonding, the first basic structure S1 and the second basic structure S2 are at different temperatures. In this case, the bonding temperature Tc is considered to be the maximum temperature.

[0080] After bonding, the first support substrate 10 is removed at a high temperature Tt. The temperature Tt may be the same as or close to the bonding temperature Tc. Between transferring and bonding, the bonded structure maintains a temperature close to the bonding temperature Tc.

[0081] The term "close" means not varying by more than 20°C, preferably not varying by more than 10°C. In other words, step c) is performed at a temperature Tt such that Tc-20°C < Tt < Tc+20°C, preferably Tc-10°C < Tt < Tc+10°C.

[0082] Advantageously, the temperature Tt may be maintained for a period ranging from 1 minute to 10 hours.

[0083] Depending on the transfer technology used, a portion of layer 11 may be further removed. This is especially true in the case of Smart Cut™ type processing. However, the thickness removed remains small compared to the thickness of the layer at the time of joining. In particular, less than 90% of the layer thickness is removed, more specifically less than 50% or less than 10%. To avoid changing the thickness of layer 11, Smart Cut™ can be performed on a layer located beneath layer 11.

[0084] To perform a Smart Cut (trademark) type method, a step is taken to implant ionic species such as hydrogen and / or helium, which may bind with boron, to form an embrittlement zone that defines a portion of the layer 11 to be transferred. Since the splitting of the first base structure S1 is performed along the embrittlement zone, it becomes possible to peel off the rest of the base structure S1 and transfer the thin layer 11. The implantation step is performed before performing step b).

[0085] In another embodiment, the first support substrate 10 may be removed by a laser lift-off (LLO) process, such as the Nanocleave® process. In the case of a laser lift-off (LLO) process, a layer or multilayer structure that enables peeling is placed between the first support substrate 10 and the metal layer, semiconductor layer, or insulating layer 11.

[0086] Alternatively, the first support substrate 10 may be removed by processing with a porous material (e.g., porous SiOCH4) or by a process of melting the sacrificial layer and mechanically separating it (slide-off).

[0087] During step c), the assembly obtained after transferring the metal layer, semiconductor layer, or insulating layer 11 is cooled. It is preferable to cool the assembly to room temperature. Room temperature means a temperature within the range of 20 to 25°C.

[0088] At the end of step c), an assembly is obtained comprising a second support substrate 20, optionally amorphous layers 13, 21, one or more additional layers potentially necessary for carrying out the final structure and / or method, and a metal layer, semiconductor layer or insulating layer 11 subjected to tensile or compressive strain.

[0089] To increase the strain within the layer, the method is as follows: d) A step of bonding the metal layer, semiconductor layer, or insulating layer 11 to a third substrate, preferably the same as the first substrate 10. e) Step of removing the second support substrate 20, f) A step to cool the assembly obtained in step e). It may further have the following:

[0090] Step d) is preferably carried out by direct bonding, more preferably by SAB or ADB.

[0091] By step f), the third substrate is thermally bonded, and the third substrate is removed while at a high temperature, making it possible to transfer the metal layer, semiconductor layer, or insulating layer 11.

[0092] At the end of step f), a metal layer, semiconductor layer, or insulating layer 11 is obtained that has a higher strain level than the strain level obtained at the end of step b).

[0093] Therefore, by repeating this procedure several times, it becomes possible to significantly increase the strain within layer 11.

[0094] The number of repetitions is selected according to the desired strain level and thickness of the metal layer, semiconductor layer, or insulating layer 11. In fact, a portion of layer 11 may be removed in each transfer step. It is advantageous that the additional layer is cleverly positioned for transfer.

[0095] This method makes it possible to obtain a layer, for example, made of silicon, that has been subjected to tensile or compressive strain.

[0096] The resulting layer exhibits a strain greater than 200 MPa, preferably greater than 400 MPa, more preferably greater than 700 MPa, and most preferably greater than 1 GPa.

[0097] Such layers are particularly advantageous for microelectronics applications, especially in the high-frequency range, as they increase the mobility of charge carriers.

[0098] Therefore, at the end of step c) or step f), the layer 11 subjected to tensile or compressive strain can be advantageously deposited on the target substrate. For example, in the case of a semiconductor layer 11 formed of silicon, this layer may be deposited on a target substrate including a silicon substrate 30 and an oxide layer 31 to form an SSOI substrate (Figure 5).

[0099] The SSOI structure continuously includes a semiconductor substrate, an oxide layer, and a semiconductor layer subjected to tensile or compressive strain, wherein the semiconductor layer has a strain greater than 200 MPa in absolute value, preferably greater than 400 MPa, more preferably greater than 700 MPa, and most preferably greater than 1 GPa. It is preferable that the semiconductor layer subjected to tensile or compressive strain is free of defects.

[0100] Various embodiments and modifications are described. Those skilled in the art will understand that certain features of these various embodiments and modifications can be combined, and other modifications will be conceivable to those skilled in the art.

[0101] Finally, the actual implementation of the embodiments and modifications described is within the scope of the skills of those skilled in the art based on the functional representations set forth above.

[0102] Exemplary, non-limiting examples of various specific embodiments

[0103] First embodiment: Manufacturing SSOI from sapphire substrates and silica substrates using the Smart Cut™ process. In this first embodiment, the SOI substrate is first bonded to the first sapphire support substrate by direct bonding.

[0104] SOI substrates are commercially available SOI substrates formed from a silicon substrate with a diameter of 200 mm and a thickness of 725 μm, covered with a 500 nm oxide and a thin 1000 nm silicon film.

[0105] The first sapphire substrate is a substrate with a diameter of 200 mm and a thickness of 725 μm.

[0106] Before bonding, nitrogen plasma treatment is performed on the SOI substrate, and then ethylenediamine (10 -4 Add (diluted to M). After bonding, perform thermal annealing at 150 °C (the maximum temperature is approximately 200 °C; exceeding this temperature will break the bond).

[0107] A lapping process is performed on the silicon substrate to reduce the substrate thickness to approximately 50 μm. The remaining portion of the substrate can be removed by chemical etching using HF / HNO3. The concentration is, for example, 1 volume% of HF (50%) in HNO3 (70%). This process can be performed using a machine that processes only one side, such as an SEZ type machine. Subsequently, chemical mechanical polishing (CMP) is performed on the oxide used to stop the chemical etching, reducing the thickness to 100 nm and reducing the roughness to less than RMS 0.3 nm to make it suitable for direct bonding.

[0108] Subsequently, a 30 nm amorphous silicon layer is deposited by reduced-pressure chemical vapor deposition (LPCVD) at 550 °C.

[0109] 8E in a silicon layer with an energy of 76 keV 16 at / cm 2 Inject hydrogen at the specified hydrogen injection rate.

[0110] In parallel, a second support substrate (plate) formed of fused silica with a diameter of 200 mm and a thickness of 725 μm is polished by CMP to obtain a surface suitable for direct bonding. An amorphous silicon layer of the same 30 nm thickness as the amorphous silicon layer of the first structure is deposited on the silica plate. The amorphous silicon layers are bonded to each other by SAB (surface-activated bonding) at 400 °C. Therefore, 10 -8 After being placed under an ultra-high vacuum (UHV or "High Ultra Vacuum") of mbar, the surfaces to be bonded are irradiated with a 200 eV and 150 mA argon ion beam for 60 seconds. Next, the substrate is placed on an electrostatic support (chuck) preheated to 400 °C. After 5 minutes of thermal stabilization, the two surfaces to be bonded are brought into contact. Since both substrates are at 400 °C, the bonding is performed without changing the strain level. The heat treatment is continued for 2 hours to allow the Smart Cut™ process to be performed. After separation by Smart Cut™, the first support containing a portion of the silicon film and the assembly formed by the silicon layer, amorphous silicon layer, and second support substrate are cooled to room temperature (typically 20-25 °C). Approximately 800 nm silicon is transferred from the sapphire substrate to the silica substrate.

[0111] By raising the temperature of the silicon layer bonded to the sapphire to 400°C, it is possible to apply a tension of +262 MPa to the silicon layer.

[0112] After being transferred to the silica substrate, the silica remains at the same temperature (400 °C in this case), so there is no change in the strain of the silicon layer. After cooling to room temperature and separating the substrate, the strain of the silicon layer transferred to the silica increases to +465 MPa.

[0113] The various processes described above may be repeated to increase the strain of the silicon layer.

[0114] To achieve this, a silicon layer of approximately 800 nm is polished by CMP to match the direct bonding surface, and then the silica substrate covered with the silicon layer is cold-bonded to a new sapphire plate. The silicon layer is approximately 700 nm thick. The silica substrate is removed by lapping and chemical etching (hydrofluoric acid). The strain of the silicon layer transferred to the sapphire substrate is still +465 MPa.

[0115] Next, the silicon layer is transferred to another silica substrate at a high temperature, as described above. This yields a layer (with adjusted hydrogen implantation) with a strain of 930 MPa and a thickness of 500 nm. After a new CMP process, the silicon layer is ready for a third iteration, with a thickness of 400 nm. After the final CMP, a 200 nm silicon layer with a strain of 1,395 MPa and a thickness of 100 nm is obtained.

[0116] This 100 nm silicon layer can ultimately be transferred onto a silicon substrate covered with a 20 nm oxide film by lapping and chemical etching. A SSOI containing a layer with a strain of approximately 1.4 GPa is obtained.

[0117] Second embodiment: Manufacturing SSOI from copper substrates and silica substrates using the Smart Cut™ process. In this second embodiment, the SOI substrate is first bonded to the first copper support substrate by direct bonding.

[0118] The SOI substrate is a commercially available SOI substrate formed from a silicon-supported substrate with a diameter of 200 mm and a thickness of 725 μm, covered with a 500 nm oxide and a thin 400 nm silicon film.

[0119] The first copper support substrate is a substrate with a diameter of 200 mm and a thickness of 725 μm.

[0120] A SOI substrate is bonded to a copper substrate by SAB. As described above, a lapping step is performed on the silicon substrate to reduce the thickness of the silicon substrate to approximately 50 μm, and then a chemical etching process using HF / HNO3 (concentration of 1% by volume of 50% HF in 70% HNO3) is performed to remove this portion of the silicon substrate. CMP is performed on the oxide used to stop the chemical etching. Thus, the oxide returns to a surface state compatible with direct bonding and a thickness of 50 nm. A 30 nm amorphous silicon layer is deposited on the oxide by LPCVD at 550° C. Finally, implantation into the silicon layer is performed by, for example, co-implantation of helium and hydrogen at energy and dose of 38 keV / 1.3E16 at / cm 2 and 24 keV / 5.25E16 at / cm 2 , respectively.

[0121] In parallel, a second support substrate (plate) of fused silica with a diameter of 200 mm and a thickness of 725 μm is polished by CMP to obtain a surface compatible with direct bonding. A 30 nm amorphous silicon layer is deposited on said surface.

[0122] The two amorphous silicon layers are bonded by SAB at 400° C. To this end, as described above, the two surfaces to be bonded are placed under an ultra-high vacuum of 10 -8 mbar and activated with an argon ion beam of 200 eV and 150 mA for 60 seconds. Next, the plate is placed on an electrostatic support (chuck) preheated to 400° C. After 5 minutes of thermal stabilization, the two plates are brought into contact. Since both substrates are at 400° C., bonding is performed without changing the strain level. Thermal annealing is continued for 2 hours to perform the Smart Cut® process. In this way, a silicon layer of approximately 200 nm is transferred from the copper substrate to the silica substrate.

[0123] Before bonding, the silicon film bonded to copper is heated to 400 °C, thereby applying a tension of +1,030 MPa to the silicon film. After transfer to silica, since the silica is also at 400 °C, there is no change in strain. After separating the two substrates, the substrates are cooled to room temperature. The strain of the silicon layer transferred to the silica increases to +1.23 GPa. After the final CMP, a strain of 1,395 MPa and a thickness of 100 nm are obtained.

[0124] Subsequently, this 100 nm layer can be transferred onto a silicon substrate covered with a 20 nm oxide film by lapping and chemical etching. Finally, an SSOI structure containing a silicon layer with a strain of approximately 1.4 GPa is obtained. In this embodiment, it is not necessary to repeat the above method to obtain an SSOI with a strain of more than 1.2 GPa.

[0125] Third embodiment: Manufacturing SSOI by performing a process of transferring from sapphire substrates and silica substrates by "laser lift-off" (LLO). First, a commercially available SOI substrate, formed from a thin 100 nm silicon film on a 500 nm oxide layer, is bonded to a silicon substrate with a diameter of 200 mm and a thickness of 725 μm.

[0126] Next, a 100 nm thick GaN layer is deposited on the first sapphire substrate by epitaxy, and a 200 nm oxide layer is continuously deposited on the GaN layer. CMP is performed on this oxide layer to create a direct bond. Nitrogen plasma treatment is then performed, followed by ethanolamine (10 -4 After adding (diluted to M), SOI is directly bonded to a sapphire substrate coated with GaN and oxide, having a diameter of 200 mm and a thickness of 725 μm. After heat treatment at 150 °C (the maximum temperature is approximately 200 °C, above which the bond will break), the silicon substrate is wrapped, leaving only 50 μm, and this remaining thickness is then removed by chemical etching using HF / HNO3 (containing 1 volume% of HF (50%) in HNO3 (70%)) in a machine (e.g., SEZ type). The oxide is further removed.

[0127] The second support substrate is a fused silica plate with a diameter of 200 mm and a thickness of 725 μm. The second support substrate is polished by CMP to obtain a surface suitable for direct bonding. A 30 nm amorphous silicon layer is deposited on its surface by LPCVD at 550 °C.

[0128] To transfer the layer to which the strain is applied, SAB bonding is first performed at 900°C. To perform SAB bonding, two plates are placed 10 -8 The plates are placed under an ultra-high vacuum of mbar. Each surface is activated with an argon ion beam of 200 eV and 150 mA for 60 seconds. The plates are then placed on an electrostatic support (chuck) preheated to 900 °C. After 5 minutes of thermal stabilization, the two plates are brought into contact. Since both substrates are at 900 °C, bonding occurs without altering the strain level. The resulting assembly is then transferred to a chamber capable of laser lift-off (LLO) transfer while maintaining the temperature at 900 °C, separating the GaN from the sapphire.

[0129] In this way, a 100 nm silicon layer is transferred onto silica.

[0130] Before bonding, the silicon layer is bonded to the sapphire at a temperature of 900 °C, so the silicon layer is subjected to a tensile strain of +700 MPa. After transfer to the silica, the silica is also at 900 °C, so there is no change in strain. After separating the substrates, both substrates are cooled to room temperature. The strain of the silicon layer transferred to the silica increases to +1.24 GPa.

[0131] Subsequently, the remaining GaN and silicon oxide are removed by chemical etching using HF.

[0132] Subsequently, the 100 nm layer can be transferred onto a silicon substrate covered with a 20 nm oxide film by lapping and chemical etching. As a result, an SSOI with a silicon layer strained to approximately 1.24 GPa is obtained.

[0133] This application is based on French Patent Application No. 23 / 08447, filed on 3 August 2023, titled "Procede defabrication d' une couche contrainte," whose contents are incorporated herein by reference to the extent permitted by law, and claims priority to French Patent Application No. 23 / 08447.

Claims

1. A method for manufacturing a strain layer, a) A step of preparing a first basic structure, which includes a first support substrate made of the first material and covered with a metal layer, semiconductor layer, or insulating layer having a thickness of less than 10 μm, and on the other hand a second basic structure, wherein the thermal expansion coefficient of the first support substrate is different from that of the second support substrate, and the first and second support substrates are selected such that the thermal expansion coefficients of the first and second support substrates cause a desired strain level in the metal layer, semiconductor layer, or insulating layer during step c), b) By joining the first basic structure and the second basic structure at a joining temperature Tc such that Tc > 70°C, a joined structure is obtained in which the metal layer, semiconductor layer, or insulating layer is subjected to strain at a first strain level, and then, By removing the first support substrate at a temperature Tt such that Tc-50°C < Tt < Tc+50°C, and obtaining an assembly including the second support substrate and the metal layer, semiconductor layer, or insulating layer, The metal layer, semiconductor layer, or insulating layer is transferred onto the second basic structure. The process involves maintaining the temperature of the bonded structure above 70°C and within a range of 50°C or less from the bonding temperature Tc, so that the transferred metal layer, semiconductor layer, or insulating layer is subjected to strain at the first strain level on the second support substrate while the first support substrate is bonded and removed, c) A step of obtaining an assembly comprising the second support substrate and a metal layer, semiconductor layer, or insulating layer to which tensile or compressive strain is applied at the desired strain level by cooling the obtained assembly. It has, If the metal layer, semiconductor layer, or insulating layer is formed of the same material as the material of the second support substrate, the desired strain level is equal to the first strain level. A method wherein, if the metal layer, semiconductor layer, or insulating layer is formed of a material different from the material of the second support substrate, the desired strain level is different from the first strain level.

2. The method according to claim 1, wherein the metal layer, semiconductor layer, or insulating layer is a semiconductor layer.

3. The method according to claim 1 or 2, wherein the first support substrate and the second support substrate are selected from substrates formed of germanium, SiC, sapphire, copper, stainless steel, silicon, SiGe, GaN, silica, InP, AsGa, and diamond.

4. The method according to claim 1 or 2, wherein the first basic structure includes one or more additional layers which may be disposed above and / or below the metal layer, semiconductor layer, or insulating layer, and / or the second basic structure includes one or more additional layers disposed on the second support substrate.

5. The first basic structure includes the first support substrate, the metal layer, semiconductor layer or insulating layer, and a first layer of amorphous semiconductor material, and / or The method according to claim 1 or 2, wherein the second basic structure includes the second support substrate and a second layer of amorphous semiconductor material.

6. The method according to claim 1 or 2, wherein the first support substrate is made of sapphire and the second support substrate is made of silica.

7. The method according to claim 1 or 2, wherein the first support substrate is made of copper and the second support substrate is made of silica.

8. The method according to claim 1 or 2, wherein the first support substrate is made of silicon and the second support substrate is made of copper.

9. The method according to claim 1 or 2, wherein the bonding temperature Tc and the temperature Tt are the same.

10. The method according to claim 5, wherein when assembling the first basic structure with the second basic structure, there is a difference in the tangential strain between the first layer of amorphous semiconductor material and the second layer of amorphous semiconductor material.

11. After step c), d) A step of joining the metal layer, semiconductor layer, or insulating layer to a third support substrate, e) Step of removing the second support substrate, f) A step of transferring the metal layer, semiconductor layer, or insulating layer onto a fourth support substrate by performing step b), g) A step of cooling the assembly obtained in step f). The method according to claim 1 or 2, comprising:

12. The aforementioned metal layer, semiconductor layer, or insulating layer is a semiconductor layer. The method according to claim 1 or 2, further comprising a subsequent step of forming a structure on an insulator by transferring the metal layer, semiconductor layer, or insulating layer onto a semiconductor substrate covered with an oxide layer after step c) or step g).

13. The method according to claim 1 or 2, wherein the first support substrate is removed by dividing the first basic structure along the embrittlement zone formed in the metal layer, semiconductor layer, or insulating layer.

14. The method according to claim 1 or 2, wherein the first support substrate is removed by laser lift-off processing, and the layer or multilayer structure disposed between the first support substrate and the metal layer, semiconductor layer, or insulating layer enables the peeling of the first support substrate.

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