Semiconductor equipment

Abstract

To provide a semiconductor device that can detect output current with a higher degree of accuracy.SOLUTION: A semiconductor device comprises: a first transistor that has a first electrode having predetermined voltage applied, a second electrode having control voltage applied and a third electrode connected to a load; a second transistor that has a first electrode having the predetermined voltage applied, a second electrode having the control voltage applied, and a third electrode outputting second current corresponding to first current flowing in the load; a third transistor that is serially connected to the second transistor and to which the second current is supplied; an output circuit that outputs second voltage amplifying a difference of first voltage of the third electrode of the first transistor and reference voltage, and fourth voltage amplifying a difference of third voltage of the third electrode of the second transistor and the reference voltage; and an operational amplifier that controls the third transistor on the basis of the second and fourth voltages such that the first voltage and the third voltage coincide.SELECTED DRAWING: Figure 2

Description

[[Technical Field]]

[0001] The present invention relates to a semiconductor device. [[Background Art]]

[0002] For example, there is a semiconductor device that operates with power supplied from a battery and supplies or cuts off an output current to a load in accordance with an external signal (see, for example, Patent Document 1). [[Prior Art Documents]] [[Patent Documents]]

[0003] [[Patent Document 1]] Japanese Patent Laid-Open No. 2007-135274 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0004] Incidentally, some of the above-described semiconductor devices include a main transistor for passing an output current and a sense transistor for detecting a sense current corresponding to the output current. Here, the sizes of the respective transistors are designed such that the ratio between the current value of the output current and the current value of the sense current is constant. However, when the voltages applied to the main transistor and the sense transistor are different, this proportional relationship is not satisfied.

[0005] Therefore, a semiconductor device may include a circuit using an operational amplifier that operates to equalize the voltages applied to the main transistor and the sense transistor.

[0006] However, when the operational amplifier has an offset voltage, the voltages applied to the main transistor and the sense transistor will be different. As a result, the proportional relationship between the current value of the output current and the current value of the sense current is no longer satisfied, and depending on the current value of the sense current, the output current may not be accurately detected.

[0007] The present invention has been made in view of the above-mentioned conventional problems, and its objective is to provide a semiconductor device that can detect output current with higher accuracy. [Means for solving the problem]

[0008] An embodiment of the semiconductor device according to the present invention that solves the aforementioned problems comprises: a first transistor having a first electrode to which a predetermined voltage is applied, a second electrode to which a control voltage is applied, and a third electrode connected to a load; a second transistor having the first electrode to which the predetermined voltage is applied, a second electrode to which the control voltage is applied, and a third electrode that outputs a second current corresponding to a first current flowing through the load; a third transistor connected in series with the second transistor and supplied with the second current; an output circuit that outputs a second voltage obtained by amplifying the difference between a first voltage at the third electrode of the first transistor and a reference voltage, and a fourth voltage obtained by amplifying the difference between the third voltage at the third electrode of the second transistor and the reference voltage; and an operational amplifier that controls the third transistor based on the second and fourth voltages so that the first voltage and the third voltage match. [Effects of the Invention]

[0009] According to the present invention, a semiconductor device capable of detecting output current with higher precision can be provided. [Brief explanation of the drawing]

[0010] [Figure 1] This figure shows an example of a motor control device 10. [Figure 2] This is a diagram showing an example of the IPS21 configuration. [Figure 3] This figure shows an example of the configuration of the output circuit 240. [Figure 4] This diagram illustrates the offset voltages present in operational amplifiers 250 and 315. [Figure 5] This figure shows the effects of this embodiment. [Modes for carrying out the invention]

[0011] At least the following matters will be made clear by the description in the present specification and the accompanying drawings.

[0012] =====Present Embodiment===== <<<Outline of Motor Control Device 10>>>[] FIG. 1 is a diagram showing a configuration of a motor control device 10 according to an embodiment of the present invention. The motor control device 10 is a device for controlling a motor 12 provided in an automobile using electric power from a battery 11, and includes an ECU 20 including an IPS (Intelligent Power Switch) 21. The battery 11 is, for example, a lithium-ion battery for automobiles, and outputs a power supply voltage Vcc of 12 V.

[0013] An ECU (Electronic Control Unit) 20 is a device that controls the motor 12, and is configured to include an IPS 21 (described later) and a microcomputer 30.

[0014] The microcomputer 30 controls the IPS 21 based on an instruction (not shown) input from the outside.

[0015] The IPS 21 is a semiconductor device that switches whether to supply the power supply voltage Vcc of the battery 11 to the motor 12 based on an instruction signal Sa output from the microcomputer 30. The motor 12 corresponds to a "load".

[0016] The power supply voltage Vcc of the battery 11 is applied to a terminal A of the IPS 21, and a terminal B is grounded. Further, the instruction signal Sa from the microcomputer 30 is input to a terminal C, and the voltage Vcc is output from a terminal D when an NMOS transistor 210 (described later) inside the IPS 21 is on. In the present embodiment, the voltage of the GND terminal is set as a ground voltage Vgnd (0 V).

[0017] <<<Configuration of IPS 21>>>[] Figure 2 is a diagram illustrating an example configuration of IPS21. IPS21 operates as a switch that supplies or cuts off the output current I1 to the motor 12 based on the instruction signal Sa. Specifically, when an instruction signal Sa of high level (hereinafter referred to as "H" level) is input, IPS21 supplies the output current I1 to the motor 12. On the other hand, when an instruction signal Sa of low level (hereinafter referred to as "L" level) is input, IPS21 cuts off the output current I1 to the motor 12.

[0018] IPS21 is configured to include a control circuit 200, NMOS transistors 210, 220, 230, an output circuit 240, a signal output circuit 241, an operational amplifier 250, a low-pass filter (LPF) 260, a resistor 270, and a detection circuit 280.

[0019] == Control Circuit 200 == When an "H" level instruction signal Sa is input, the control circuit 200 turns on the NMOS transistors 210 and 220, and when an "L" level instruction signal Sa is input, the control circuit 200 turns off the NMOS transistors 210 and 220. The control circuit 200 is configured to include an input interface (I / F) 201 and a charge pump circuit (CP) 202.

[0020] === Input Interface 201 === The input interface 201 outputs a signal obtained by inverting the logic level of the input instruction signal Sa.

[0021] === Charge Pump Circuit 202 === The charge pump circuit 202 outputs a control voltage Vcnt obtained by stepping up the power supply voltage Vcc in response to a signal from the input interface 201. Specifically, when the instruction signal Sa is at "H" level, the charge pump circuit 202 outputs an "H" level control voltage Vcnt obtained by stepping up the power supply voltage Vcc to turn on the NMOS transistors 210 and 220.

[0022] On the other hand, when the instruction signal Sa is at the "L" level, the charge pump circuit 202 stops boosting the power supply voltage Vcc and outputs a control voltage Vcnt at the "L" level in order to turn off the NMOS transistors 210 and 220.

[0023] ==NMOS Transistor 210== The NMOS transistor 210 supplies or cuts off the output current I1 to the motor 12 in response to the instruction signal Sa. Specifically, when a control voltage Vcnt of the "H" level is applied to the gate electrode of the NMOS transistor 210, it turns on and supplies the output current I1 to the motor 12. On the other hand, when a control voltage Vcnt of the "L" level is applied to the gate electrode of the NMOS transistor 210, it turns off and stops supplying the output current I1 to the motor 12.

[0024] Furthermore, the NMOS transistor 210 in this embodiment has a drain electrode to which the power supply voltage Vcc is applied, a gate electrode to which the control voltage Vcnt is applied, and a source electrode connected to the motor 12. The voltage of the source electrode of the NMOS transistor 210 is denoted as voltage V1. The NMOS transistor 210 corresponds to the "first transistor," and the drain electrode, gate electrode, and source electrode of the NMOS transistor 210 correspond to the "first electrode," "second electrode," and "third electrode," respectively, and the voltage Vcc corresponds to the "predetermined voltage." The output current I1 corresponds to the "first current."

[0025] ==NMOS Transistor 220== The NMOS transistor 220 is a sense MOS transistor for the NMOS transistor 210, and a current I2 flows through the NMOS transistor 220 corresponding to the output current I1 flowing through the NMOS transistor 210. The NMOS transistor 220 in this embodiment has a drain electrode to which the power supply voltage Vcc is applied, a gate electrode to which the control voltage Vcnt is applied, and a source electrode that outputs a current I2 corresponding to the current I1 flowing through the motor 12. The voltage of the source electrode of the NMOS transistor 220 is denoted as voltage V3. Voltages V2 and V4 will be described later. The NMOS transistor 220 corresponds to the "second transistor," and the drain electrode, gate electrode, and source electrode of the NMOS transistor 220 correspond to the "first electrode," "second electrode," and "third electrode," respectively. The current I2 corresponds to the "second current."

[0026] ==NMOS Transistor 230== NMOS transistor 230 is an NMOS transistor used to adjust the voltage V3 of the source electrode of NMOS transistor 220. It is connected in series with NMOS transistor 220, and a current I2 is supplied to NMOS transistor 230. A voltage Vlpf, which changes according to voltages V1 and V3, is applied to the gate electrode of NMOS transistor 230. The on-resistance of NMOS transistor 230 changes according to voltage Vlpf, and as a result, voltage V3 also changes. Details of voltage Vlpf will be described later. Also, "NMOS transistor 230" corresponds to the "third transistor".

[0027] ==Outline of Output Circuit 240== The output circuit 240 outputs a voltage V2, which is an amplified version of the difference between voltage V1 and the power supply voltage Vcc, and a voltage V4, which is an amplified version of the difference between voltage V3 and the power supply voltage Vcc. Further details of the output circuit 240 will be described later with reference to Figure 3. Voltage V1 corresponds to the "first voltage," voltage V2 to the "second voltage," voltage V3 to the "third voltage," and voltage V4 to the "fourth voltage." The power supply voltage Vcc corresponds to the "reference voltage." In this embodiment, the power supply voltage Vcc is used as the reference voltage, but a predetermined voltage (for example, the ground voltage Vgnd) may be used as the reference voltage.

[0028] ==Signal output circuit 241== The signal output circuit 241 outputs a signal sel to select the voltage that the output circuit 240 will amplify from among the voltages V1 and V3. Specifically, the signal output circuit 241 outputs a signal sel at a "H" level for a predetermined period, and then outputs a signal sel at a "L" level for the same predetermined period, repeating this cycle.

[0029] ==Details of Output Circuit 240== As shown in Figure 3, the output circuit 240 is configured to include a selection circuit 300, an amplification circuit 310, and a voltage holding circuit 320.

[0030] ===Selection Circuit 300=== The selection circuit 300 selects either voltage V1 or voltage V3 to output to the amplification circuit 310 based on the selection signal sel from the signal output circuit 241. Specifically, the selection circuit 300 selects voltage V1 based on the "L" level signal sel and selects voltage V3 based on the "H" level signal sel. The selection circuit 300 corresponds to the "first selection circuit," the signal sel corresponds to the "control signal," the "L" level corresponds to the "first logic level," and the "H" level corresponds to the "second logic level."

[0031] ===Amplification circuit 310=== The amplification circuit 310 is a differential amplifier that outputs voltages V2 and V4 to match voltage V1 and voltage V3, and amplifies the difference between the voltage output from the selection circuit 300 and the power supply voltage Vcc. Specifically, the amplification circuit 310 amplifies the difference between node N1 to which the power supply voltage Vcc is applied and node N2 to which the voltage output from the selection circuit 300 is applied.

[0032] Furthermore, the amplification circuit 310 outputs a voltage Vdiff that becomes voltage V2 or voltage V4 based on the voltage V1 or voltage V3 selected by the selection circuit 300. The amplification circuit 310 also includes resistors 311 to 314 and an operational amplifier 315. Note that node N1 corresponds to the "first node" and node N2 corresponds to the "second node".

[0033] Resistors 311-314 and operational amplifier 315 constitute a differential amplifier circuit that amplifies the difference between the voltage at node N1 and the voltage at node N2. The non-inverting input of operational amplifier 315 is applied with a voltage Vin+ obtained by dividing the power supply voltage Vcc by resistors 311 and 312. The inverting input of operational amplifier 315 is applied by resistors 313 and 314 with a voltage Vin- corresponding to the output voltage Vdiff of operational amplifier 315 and the voltage at node N2.

[0034] Here, in order to explain the operation of the amplifier circuit 310, if we denote the resistance values ​​of resistors 311 to 314 as Ra to Rd, respectively, and the voltage at node N2 as Vn2, then the voltages Vin+ and Vin- are as follows. Note that here, the operation of the amplifier circuit 310 is explained in the ideal state where the operational amplifier 315 does not have an offset voltage. Vin+=Vcc×Rb / (Ra+Rb) ···(1) Vin-=(Vdiff-Vn2)×(Rc / (Rc+Rd))+Vn2 ···(2)

[0035] Then, assuming Ra=Rc=Re and Rb=Rd=Rf, and given the circuit configuration, Vin+=Vin-, the voltage Vdiff is as follows, and the amplifier circuit 310 operates as a differential amplifier circuit with gain Rf / Re. Vdiff=(Rf / Re)×(Vcc-Vn2) ···(3)

[0036] Based on the above, the amplification circuit 310 outputs a voltage Vdiff that becomes voltage V2 or voltage V4 based on the voltage V1 or voltage V3 selected by the selection circuit 300.

[0037] ===Voltage holding circuit 320=== The voltage holding circuit 320 holds voltages V2 and V4 based on voltages V1 and V3. Specifically, the voltage holding circuit 320 holds the output from the amplifier circuit 310 (i.e., the voltage Vdiff at output node Nout) as voltage V2 based on the "L" level signal sel, and holds the output from the amplifier circuit 310 as voltage V4 based on the "H" level signal sel. The voltage holding circuit 320 is composed of a selection circuit 321 and capacitors 322 and 323. Note that the voltage holding circuit 320 corresponds to a "holding circuit".

[0038] ====Selection circuit 321, capacitors 322, 323==== The selection circuit 321 connects the output of the amplifier circuit 310 to the capacitor 322 based on the "L" level signal sel, and connects the output of the amplifier circuit 310 to the capacitor 323 based on the "H" level signal sel. The voltage V2 held in capacitor 322 is applied to the non-inverting input of the operational amplifier 250, and the voltage V4 held in capacitor 323 is applied to the inverting input of the operational amplifier 250. The selection circuit 321 corresponds to the "second selection circuit," capacitor 322 corresponds to the "first capacitor," and capacitor 323 corresponds to the "second capacitor."

[0039] ==Op-amp 250== The operational amplifier 250 controls the NMOS transistor 230 based on voltages V2 and V4 so that voltages V1 and V3 match. Specifically, as described above, the voltage V2 generated across capacitor 322 based on voltage V1 is applied to the non-inverting input of the operational amplifier 250, and the voltage V4 generated across capacitor 323 based on voltage V3 is applied to the inverting input. The operational amplifier 250 then outputs voltage Vop.

[0040] In this embodiment, the operational amplifier 250 is subjected to voltages V2 and V4, which are amplified versions of voltages V1 and V3. However, if voltages V1 and V3 smaller than V2 and V4 are directly applied to the operational amplifier 250, it will be greatly affected by the offset voltage. As a result, in such a case, the operational amplifier 250 cannot control the NMOS transistor 230 so that voltages V1 and V3 match with high precision.

[0041] On the other hand, in this embodiment, the output circuit 240 amplifies the difference between voltages V1 and V3 and the power supply voltage Vcc, and outputs them as voltages V2 and V4. As a result, voltages V2 and V4, which are larger than voltages V1 and V3, are input to the operational amplifier 250, thus reducing the effect of the offset voltage on the operational amplifier 250. Details regarding the relationship between the gain of the output circuit 240 and the offset voltage will be described later using mathematical formulas with reference to Figures 4 and 5.

[0042] <<<Operation of Operation Amplifier 250>>> Furthermore, the following explains, using mathematical formulas, how the operational amplifier 250 matches voltages V1 and V3 based on voltages V2 and V4. First, assuming that the on-resistance of the NMOS transistor 210 is Rg and the on-resistance of the NMOS transistor 220 is Rh, voltages V1 and V3 are as follows. Note that the operation of IPS21 in the ideal state where the operational amplifier 250 does not have an offset voltage is explained here. V1 = Vcc - Rg × I1 ... (4) V3 = Vcc - Rh × I² ... (5)

[0043] Furthermore, when voltages V1 and V3 and equations (4) and (5) are applied to equation (3), voltages V2 and V4 are obtained as follows. V2=(Rf / Re)×(Vcc-V1)=(Rf / Re)×Rg×I1 (6) V4=(Rf / Re)×(Vcc-V3)=(Rf / Re)×Rh×I2 (7)

[0044] Furthermore, due to the circuit configuration, V2 = V4, so as a result, V1 = V3.

[0045] ==Low-pass filter (LPF) 260== The low-pass filter 260 in Figure 2 is placed between the output of the operational amplifier 250 and the NMOS transistor 230, stabilizing the voltage Vop, which fluctuates according to the signal sel, and outputting it as voltage Vlpf. Specifically, the low-pass filter 260 consists of a resistor 261 connected between the output of the operational amplifier 250 and the gate electrode of the NMOS transistor 230, and a capacitor 262 placed between the gate electrode of the NMOS transistor 230 and ground. Furthermore, the cutoff frequency of the low-pass filter 260 is lower than the frequency corresponding to the period of the signal sel. As a result, a stable voltage Vlpf is applied to the gate electrode of the NMOS transistor 230.

[0046] ==Resistance 270== Resistor 270 is an element for detecting the current I2 and is placed between the NMOS transistor 230 and terminal B. The current I2 that flows through the NMOS transistors 220 and 230 flows through resistor 270. When current I2 flows through resistor 270, a voltage Vr is generated across resistor 270.

[0047] ==Detection Circuit 280== The detection circuit 280 detects that the current I1 is an overcurrent based on the voltage Vr generated across the resistor 270. Specifically, the detection circuit 280 detects that the current I1 is an overcurrent when the current value of the current I2 exceeds a predetermined value and the voltage Vr generated across the resistor 270 exceeds a predetermined voltage corresponding to the predetermined value. The detection circuit 280 corresponds to an "overcurrent detection circuit".

[0048] <<<Effect of offset voltage on op-amps 250 and 315>>> Figure 4 illustrates the offset voltages of operational amplifiers 250 and 315. Here, the offset voltage of operational amplifier 315 is denoted as offset voltage Vofs1 and is assumed to occur on the non-inverting input side of operational amplifier 315, as shown in Figure 4. Similarly, the offset voltage of operational amplifier 250 is denoted as offset voltage Vofs2 and is assumed to occur on the non-inverting input side of operational amplifier 250, as shown in Figure 4.

[0049] In such a case, when the offset voltage Vofs1 is converted to the change in voltage Vcc ΔV, equation (3) above becomes as follows. Vdiff=(Rf / Re)×(Vcc+ΔV-Vn2) ···(8)

[0050] Therefore, the voltages V2 and V4 can be found in the same way as equations (6) and (7), as follows: V2=(Rf / Re)×(Vcc+ΔV-V1) ···(9) V4=(Rf / Re)×(Vcc+ΔV-V3) ···(10)

[0051] Furthermore, considering the offset voltage Vofs2 of the op-amp 250, the relationship between voltages V2 and V4 is as follows. V2 - Vofs2 = V4 ... (11)

[0052] Substituting equations (9) and (10) into equation (11), we obtain equation (12), which shows that the effect of the offset voltage Vofs1 on the amplifier circuit 310 that outputs voltages V2 and V4 is eliminated. This is because voltages V2 and V4 are output by a single amplifier circuit 310, and the offset voltage Vofs1 affects both voltages V2 and V4 in the same way. V3=V1+(Re / Rf)×Vofs2 (12)

[0053] Furthermore, since Re / Rf is the reciprocal of the gain Rf / Re of the amplifier circuit 310, if the gain Rf / Re of the amplifier circuit 310 is sufficiently large, voltages V1 and V3 will be almost identical even if there is an offset voltage Vofs2 in the operational amplifier 250.

[0054] <<<Relationship between current I1 and voltage Vr>>> Figure 5 shows the effect of this embodiment and illustrates the relationship between current I1 and voltage Vr. Substituting equations (4) and (5) into equation (12), and assuming the resistance value of resistor 270 is resistance value Ri, the voltage Vr is expressed as follows. Vr=Ri×I2=Rg×(Ri / Rh)×I1-(Re / Rf)×(Ri / Rh)×Vofs2 (13)

[0055] In equation (13), if we set K0 = Rg × (Ri / Rh) and K1 = (Re / Rf) × (Ri / Rh), then equation (13) becomes equation (14). Here, K1 contains the reciprocal of the gain Rf / Re of the amplifier circuit 310. Therefore, the larger the gain Rf / Re, the closer the graph with offset voltage shown in Figure 5 approaches the graph without offset voltage, allowing for more accurate detection of the output current. Vr=K0×I1-K1×Vofs2 (14)

[0056] ===Other=== Furthermore, in this embodiment, the amplification circuit 310 amplifies the difference between the power supply voltage Vcc and the output of the selection circuit 300. However, it may also amplify the difference between a predetermined voltage other than the power supply voltage Vcc (for example, the ground voltage Vgnd) and the output of the selection circuit 300. Even in this case, the same effects as in this embodiment can be obtained. However, when the amplification circuit 310 amplifies the difference between the power supply voltage Vcc and the output of the selection circuit 300, the bias voltage applied to the NMOS transistors 210 and 220 can be matched more reliably.

[0057] ===Summary=== The motor control device 10 of this embodiment has been described above. The IPS21 comprises NMOS transistors 210, 220, and 230, an output circuit 240, and an operational amplifier 250. The output circuit 240 outputs a voltage V2, which is an amplified difference between voltage V1 and the power supply voltage Vcc, and a voltage V4, which is an amplified difference between voltage V3 and the power supply voltage Vcc. The operational amplifier 250 controls the NMOS transistor 230 based on voltages V2 and V4 so that voltages V1 and V3 match. Since the output circuit 240 operates as a differential amplifier circuit and amplifies the changes in voltages V1 and V3, the effect of the offset voltage Vofs2 of the operational amplifier 250 can be reduced. This makes it possible to provide a semiconductor device that can detect the output current with higher accuracy.

[0058] The output circuit 240 also includes a selection circuit 300, an amplification circuit 310, and a voltage holding circuit 320. The selection circuit 300 selects either voltage V1 or voltage V3 based on the signal sel. The amplification circuit 310 amplifies the difference between the voltage selected by the selection circuit 300 and the power supply voltage Vcc. The voltage holding circuit 320 then holds the voltage from the amplification circuit 310 as voltage V2 or voltage V4 based on the signal sel. Since voltages V2 and V4 are output by a single amplification circuit 310, the effect of the offset voltage Vofs1 of the operational amplifier 315 can be reduced.

[0059] Furthermore, the amplification circuit 310 amplifies the difference between node N1, to which the power supply voltage Vcc is applied, and node N2, to which the voltage output from the selection circuit 300 is applied. Since the power supply voltage Vcc is used as the reference voltage, a circuit to generate the reference voltage is not required.

[0060] Furthermore, the voltage holding circuit 320 includes a selection circuit 321 and capacitors 322 and 323. This allows the voltage output by a single amplifier circuit 310 to be held by capacitors 322 and 323 in a simple circuit.

[0061] Furthermore, the IPS21 is equipped with a low-pass filter 260. The low-pass filter 260 prevents fluctuations in the voltage Vop of the operational amplifier 250, caused by fluctuations in voltages V2 and V4, from being transmitted to the NMOS transistor 230.

[0062] Furthermore, IPS21 is equipped with a resistor 270. Resistor 270 converts the current I2 into a voltage Vr. As a result, IPS21 can detect the current I1 by detecting the voltage Vr.

[0063] Furthermore, the IPS21 includes a detection circuit 280 that detects whether the current I1 is an overcurrent based on the voltage Vr. As a result, the IPS21 can detect that the current I1 is an overcurrent when the current value of the current I2 exceeds a predetermined value and the voltage Vr generated across the resistor 270 exceeds a predetermined voltage corresponding to the predetermined value.

[0064] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. Furthermore, the present invention may be modified or improved without departing from its spirit, and it goes without saying that equivalents thereof are included. [Explanation of Symbols]

[0065] 10 Motor control device 11 batteries 12 motors 30 Microcontrollers 200 Control circuits 201 Input Interface 202 Charge Pump Circuit 210, 220, 230 NMOS transistors 240 Output Circuit 241 Signal Output Circuit 250,315 operational amplifiers 260 Low-pass filters 261, 270, 311~314 resistors 262,322,323 Capacitors 280 Detection Circuit 300,321 Selection Circuit 310 Amplifier Circuit 320 Voltage holding circuit

Claims

1. A first transistor having a first electrode to which a predetermined voltage is applied, a second electrode to which a control voltage is applied, and a third electrode connected to a load, A second transistor having a first electrode to which the predetermined voltage is applied, a second electrode to which the control voltage is applied, and a third electrode that outputs a second current corresponding to the first current flowing through the load, A third transistor connected in series with the second transistor and supplied with the second current, An output circuit that outputs a second voltage obtained by amplifying the difference between the first voltage at the third electrode of the first transistor and the reference voltage, and a fourth voltage obtained by amplifying the difference between the third voltage at the third electrode of the second transistor and the reference voltage, A first operational amplifier controls the third transistor based on the second and fourth voltages so that the first voltage and the third voltage match, Equipped with, The output circuit described above is A first selection circuit that selects the first voltage based on a first logic level control signal and selects the third voltage based on a second logic level control signal, An amplification circuit that amplifies the difference between the voltage output from the first selection circuit and the reference voltage, A holding circuit that holds the output from the amplifier circuit as the second voltage based on the first logic level control signal, and holds the output from the amplifier circuit as the fourth voltage based on the second logic level control signal, Includes, The aforementioned amplification circuit is The second operational amplifier amplifies the difference between the first node to which the predetermined voltage is applied as the reference voltage and the second node to which the voltage output from the first selection circuit is applied. The holding circuit is A first capacitor with one end grounded, A second capacitor with one end grounded, A second selection circuit connects the output of the amplifier circuit to the other end of the first capacitor based on the control signal of the first logic level, and connects the output of the amplifier circuit to the other end of the second capacitor based on the control signal of the second logic level, Semiconductor equipment including

2. A semiconductor device according to claim 1, A low-pass filter is provided between the output of the first operational amplifier and the third transistor. The cutoff frequency of the low-pass filter is lower than the frequency corresponding to the period of the control signal. Semiconductor equipment.

3. A semiconductor device according to claim 1 or 2, The resistor through which the second current flows is provided, Semiconductor equipment.

4. A semiconductor device according to claim 3, The system includes an overcurrent detection circuit that detects whether the first current is an overcurrent based on the voltage generated across the resistor. Semiconductor equipment.

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