Control circuits and switching power supplies

Abstract

To miniaturize a control circuit for a switching element.SOLUTION: Provided is a control circuit for controlling an ON period and an OFF period in a switching cycle of a switching element configured to perform switching control of a principal current flowing through a transformer of a switching power source, and performing control to turn off the switching element when an overcurrent is detected after an elapse of an invalidation period in the switching cycle and to set a period, in which the switching element is turned on in the switching cycle, to a minimum period or more. The control circuit includes a shared timer unit configured to output a first timer signal for defining the invalidation period and a second timer signal for defining the minimum period.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a control circuit and a switching power supply.

Background Art

[0002] Conventionally, there has been known a switching power supply that repeatedly transitions a switching element between an on state and an off state to output a predetermined voltage or current (see, for example, Patent Document 1). Patent Document 1: Japanese Unexamined Patent Application Publication No. 2003-070247

Summary of the Invention

Problem to be Solved by the Invention

[0003] An object of the present invention is to reduce the circuit size of a control circuit for a switching power supply.

Means for Solving the Problem

[0004] In order to solve the above problem, according to a first aspect of the present invention, there is provided a control circuit that controls an on period and an off period in a switching cycle of a switching element that performs switching control on a main current flowing through a transformer of a switching power supply, turns off the switching element when an overcurrent is detected after a blanking period elapses in the switching cycle, and controls a period for which the switching element is kept on in the switching cycle to be equal to or longer than a minimum period. The control circuit may include a common timer section that outputs a first timer signal that defines the blanking period and a second timer signal that defines the minimum period.

[0005] In the above control circuit, the start timings of the blanking period and the minimum period may be common. In any of the above control circuits, the common timer section may time the remainder of the minimum period after timing the blanking period.

[0006] In any of the above control circuits, the common timer unit may have a common capacitor. In any of the above control circuits, the common timer unit may have a charge / discharge control unit that starts charging the common capacitor at the start timing and controls the charging and discharging of the common capacitor. In any of the above control circuits, the common timer unit may have an inactive period output unit that outputs a first timer signal indicating the end timing of the inactive period when the voltage of the common capacitor reaches a first set voltage after the start timing, discharges the common capacitor, and recharges the common capacitor. In any of the above control circuits, the common timer unit may have a minimum period output unit that outputs a second timer signal indicating the end timing of the minimum period when the voltage of the common capacitor reaches a second set voltage after the common capacitor has been discharged.

[0007] In any of the above control circuits, the charge / discharge control unit may change the value of the charging current used to charge the common capacitor before and after the end of the inactive period.

[0008] In any of the above control circuits, the charge / discharge control unit may reduce the charging current after the end of the inactivity period compared to the amount before the end of the inactivity period.

[0009] In any of the control circuits described above, the first set voltage and the second set voltage may be the same voltage.

[0010] In any of the above control circuits, the inactive period output unit may be a flip-flop that receives a first set signal according to the start timing, receives a first reset signal when the voltage of the common capacitor becomes the first set voltage, and outputs the first timer signal. In any of the above control circuits, the minimum period output unit may be a flip-flop that receives a second set signal according to the start timing, receives a second reset signal when the voltage of the common capacitor becomes the second set voltage, and outputs the second timer signal. In any of the above control circuits, the control circuit may include a reset control unit that masks the input of the second reset signal to the minimum period output unit from the start timing until the output of the inactive period output unit transitions according to the first reset signal.

[0011] In any of the above control circuits, there may be multiple switching cycles that are repeated continuously. Any of the above control circuits may have a discrimination circuit that determines whether to perform light-load operation or normal operation based on the magnitude of the output voltage of the switching power supply. In any of the above control circuits, when performing light-load operation, the switching element may be turned off if an overcurrent is detected after the invalid period has elapsed in each switching cycle by using the inactive period and the minimum period, and the period during which the switching element is turned on in each switching cycle may be controlled to be longer than the minimum period. In any of the above control circuits, when performing normal operation, the switching element may be turned off if an overcurrent is detected after the invalid period has elapsed in each switching cycle by using the inactive period instead of the minimum period.

[0012] In any of the above control circuits, the start timing of the ON period, the OFF period, and the minimum period may be the same.

[0013] If the light-load operation is performed within the switching cycle in any of the above control circuits, and the overcurrent is detected after the inactive period has elapsed but before the minimum period, the switching element may be turned off.

[0014] A second embodiment of the present invention provides a switching power supply. The switching power supply may have a transformer. The switching power supply may have a switching element that switches and controls the main current flowing through the transformer. Any of the above switching power supplies may include a control circuit that controls the on and off periods in the switching cycle of the switching element, turns off the switching element when an overcurrent is detected after an inactive period has elapsed in the switching cycle, and controls the period in which the switching element remains on in the switching cycle to be greater than or equal to a minimum period. The control circuit may have a common timer unit that outputs a first timer signal defining the inactive period and a second timer signal defining the minimum period. [Brief explanation of the drawing]

[0015] [Figure 1] This figure shows an example of a switching power supply 200 according to one embodiment of the present invention. [Figure 2] This figure shows an example configuration of the control circuit 100. [Figure 3] This figure shows an example configuration of the common timer unit 300. [Figure 4] This timing chart shows an example of the operation of the control circuit 100 under light load conditions (VstbL=L). [Figure 5] This timing chart shows an example of the operation of the control circuit 100 under normal load conditions (VstbL=H). [Figure 6] This figure shows an example configuration of the oscillation frequency control unit 24 and the oscillator 26. [Figure 7] This figure shows the relationship between the oscillation frequency of oscillator 26 and the Vfb voltage. [Figure 8]This diagram shows the relationship between the voltage at the RT terminal and the Vfb voltage. [Figure 9] This figure shows the waveform of the charging voltage of capacitor C0. [Figure 10] This diagram shows the relationship between the ON width (pulse width) of the control signal OUT and the Vfb voltage. [Modes for carrying out the invention]

[0016] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention to the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same function and configuration are denoted by the same reference numeral to avoid redundant explanations, and elements not directly related to the present invention are omitted from the illustration. In addition, in a single drawing, elements having the same function and configuration may be denoted by a representative reference numeral, while reference numerals may be omitted for others. In this specification, when terms such as "identical" or "equal" are used, it may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0017] Figure 1 shows an example of a switching power supply 200 according to one embodiment of the present invention. The switching power supply 200 is a switching element Q1 By repeatedly controlling the on and off states, a predetermined voltage or current is output. The switching power supply 200 in this example comprises a primary circuit 210, a secondary circuit 220, and a transformer T1. The switching power supply 200 shown in Figure 1 is a so-called forward-type circuit, but is not limited to this.

[0018] The primary-side circuit 210 may include a power supply circuit 205. The power supply circuit 205 supplies power to the primary-side circuit 210. The power supply circuit 205 of the present example may be connected to an external AC power supply (voltage VIN) such as a commercial power supply. The power supply circuit 205 may include a diode bridge DS1 and a capacitor C1 that rectify and smooth the voltage and current from the AC power supply.

[0019] The primary-side circuit 210 includes a control circuit 100, a primary winding n1 of a transformer T1, a reset winding n3 of the transformer T1, a diode D1, and a switching element Q1. In this example, the primary winding n1 is supplied with power from the power supply circuit 205.

[0020] The secondary-side circuit 220 includes a secondary winding n2 of the transformer T1, a diode D2, a diode D3, a secondary coil Ld, and one or more capacitors (a capacitor C2 and a capacitor C3 in FIG. 1). The secondary winding n2 is magnetically coupled to the primary winding n1.

[0021] The switching element Q1 is connected in series with the primary winding n1, and performs switching control on whether to allow a main current to flow through the primary winding n1. The switching element Q1 is, for example, a power MOSFET. The control circuit 100 controls the on and off states of the switching element Q1. The control circuit 100 may output a control signal to be input to the gate terminal of the switching element Q1. The control circuit 100 is, for example, an integrated circuit chip.

[0022] When the switching element Q1 is turned on and an excitation current flows through the primary winding n1, a load current corresponding to the turns ratio flows through the secondary winding n2. The load current flowing through the secondary winding n2 is rectified by the diode D2. In this example, the diode D2 is arranged between the high-voltage terminal of the secondary winding n2 and the secondary coil Ld. The capacitors C2 and C3 are charged by the load current passing through the secondary coil Ld. An output voltage Vout is applied to a load in accordance with the amount of charge accumulated in the capacitors C2 and C3.

[0023] When the switching element Q1 is turned off, the current flowing through the primary winding n1 is interrupted, and an excitation current flows through the reset winding n3. This excitation current flows from diode D1 to the reset winding n3 and is regenerated to the high-voltage side of the power supply circuit 205. If the switching element Q1 remains off, this excitation current gradually decreases. Also, the load current that was flowing through the secondary winding n2 is recirculated through diode D3. In this example, diode D3 is placed between the low-voltage terminal of the secondary winding n2 and the secondary coil Ld.

[0024] After the excitation current flowing through the reset winding n3 becomes zero, the excitation current flows from the low-voltage side to the high-voltage side of the primary winding n1, using the parasitic capacitance of the switching element Q1 as the power source. When the parasitic capacitance discharges, the diode D2 of the secondary circuit 220 is forward-biased and conducts, and the excitation current flows to the secondary winding n2. Subsequently, the switching element Q1 turns ON. The above operation is repeated for each switching cycle of the switching element Q1. Multiple switching cycles exist, as they are repeated continuously. By switching the switching element Q1 in this way, a predetermined voltage and current are supplied to the load.

[0025] The primary circuit 210 may have a power supply circuit 230 that supplies power to the power supply terminal VCC of the control circuit 100. The power supply circuit 230 may generate power based on the current generated by the switching operation of the switching element Q1. In this example, the power supply circuit 230 includes an auxiliary winding n4, a diode D5, a resistor R10, and one or more capacitors (in the example in Figure 1, capacitors C8 and C9). of To possess.

[0026] The auxiliary winding n4 is located between the high-voltage terminal of the power supply circuit 205 and the GND line. A resistor R1 may be placed between the auxiliary winding n4 and the power supply circuit 205. The auxiliary winding n4 is magnetically coupled to the secondary winding n2. That is, a current corresponding to the current of the secondary winding n2 flows through the auxiliary winding n4. Diode D5 is located between the high-voltage terminal of the auxiliary winding n4 and the power supply terminal VCC of the control circuit 100, and rectifies the current flowing through the auxiliary winding n4. Resistor R10 is located between diode D5 and the power supply terminal VCC. Capacitors C8 and C9 are charged by the current that passes through diode D5. The power stored in capacitors C8 and C9 is supplied as the power supply power of the control circuit 100.

[0027] During startup, when the switching operation of the switching element Q1 has not yet begun, capacitors C8 and C9 are charged via resistor R1. When the voltage across capacitors C8 and C9 rises to a predetermined startup voltage, the control circuit 100 starts up and initiates the switching operation of the switching element Q1. of After startup, capacitors C8 and C9 are charged by the current from the auxiliary winding n4. However, if the switching operation of the switching element Q1 stops due to a protection operation or the like, capacitors C8 and C9 are charged via resistor R1. This allows the control circuit 100 to continue operating.

[0028] The control circuit 100 has an OUT terminal that outputs a control signal OUT for controlling the switching element Q1. In this example, the OUT terminal is connected to the gate terminal of the switching element Q1 via a resistor R3. The gate resistance of the switching element Q1 can be adjusted by resistor R3. The gate terminal of the switching element Q1 may also be connected to the GND line via a resistor R5. The reference potential line GND is connected to the GND terminal of the control circuit 100.

[0029] The primary circuit 210 may have a resistor R6, one end of which is connected to the source terminal of the switching element Q1, and the other end of which is connected to the low-voltage terminal of the power supply circuit 205 (i.e., the common line of the primary circuit 210). The other end of resistor R6 is also connected to the reference potential line GND via resistor R9 and capacitor C7. The current flowing through the primary winding n1 and the switching element Q1 flows to the low-voltage side of the power supply circuit 205 via resistor R6.

[0030] The control circuit 100 has a CS terminal that detects the magnitude of the main current (in this example, the drain current Ids) flowing through the switching element Q1. The CS terminal takes the potential of one end of the resistor R6 (the other end mentioned above). The connection part that takes this potential into the CS terminal may have a filter consisting of a resistor R9 connecting the CS terminal and resistor R6, and a capacitor C7, as in the primary circuit 210 of this example. The potential of the other end of resistor R6 (the end connected to the switching element Q1 mentioned above) is input to the GND terminal of the control circuit 100 via the reference potential line GND. In other words, the potential of the source terminal of the switching element Q1 and the potential of the GND terminal of the control circuit 100 are the same. A potential difference corresponding to the magnitude of the drain current Ids is generated between the two ends of resistor R6. Therefore, the potential difference between the GND terminal and the CS terminal indicates the magnitude of the drain current Ids. In this example, the potential of the CS terminal of the control circuit 100 swings to the negative side relative to the potential of the GND terminal, depending on the magnitude of the drain current Ids.

[0031] The control circuit 100 may have an FB terminal to which a signal indicating the magnitude of the output voltage Vout of the secondary circuit 220 is input. The secondary circuit 220 in this example is provided with a voltage detection unit 240 for detecting the magnitude of the output voltage Vout. The voltage detection unit 240 includes a resistor R12, a light-emitting diode PC1A, a resistor R13, and a shunt regulator SR1. The control input of the shunt regulator SR1 may be a voltage obtained by dividing the output voltage Vout by resistors R13 and R14. The shunt regulator SR1 draws current if the voltage applied to the control input is higher than a predetermined reference voltage, and does not draw current if it is lower. In other words, the shunt regulator SR1 operates so that the output voltage Vout is the value shown in the following equation. Vout = Reference voltage / (R14 × (R13 + R14))

[0032] Resistor R12, light-emitting diode PC1A, and shunt regulator SR1 are connected in series between the output terminal that outputs the output voltage Vout and the reference potential. Resistor R13 is connected in parallel with light-emitting diode PC1A. A current corresponding to the output voltage Vout flows through the light-emitting diode PC1A, and it outputs light of an intensity corresponding to the magnitude of that current.

[0033] The primary circuit 210 includes a light-receiving element such as a phototransistor PC1B that receives light output from the light-emitting diode PC1A. The phototransistor PC1B generates a current corresponding to the intensity of the received light. The phototransistor PC1B may be placed between the FB terminal and the GND line of the control circuit 100. As a result, a current corresponding to the output voltage Vout flows through the FB terminal. The primary circuit 210 may also include a capacitor C6 connected in parallel with the phototransistor PC1B. This allows for the removal of high-frequency components from the current flowing through the FB terminal.

[0034] The voltage at the FB terminal changes according to the output voltage Vout. In this example, the voltage at the FB terminal decreases as the output voltage Vout increases. The control circuit 100 controls the on and off periods of the switching element Q1 according to the voltage at the FB terminal. For example, the control circuit 100 shortens the on period of the switching element Q1 in each switching cycle as the output voltage Vout increases.

[0035] The control circuit 100 may have an SS terminal to which capacitor C4 is connected. Capacitor C4 is connected between the SS terminal and the GND line and is charged by the voltage applied from the SS terminal. Capacitor C4 is charged when the switching power supply 200 is started and is used for the soft start of the switching power supply 200. The operation of the soft start will be described later.

[0036] The control circuit 100 may have an RT terminal. The RT terminal may be connected to the GND line via a resistor R8. The RT terminal is controlled to maintain a constant voltage, and the current flowing through the resistor R8 controls the frequency of the oscillation signal described later.

[0037] As described above, the control circuit 100 controls the on-period and off-period of each switching cycle of the switching element Q1. The control circuit 100 may also change the switching frequency (i.e., the length of the switching cycle) of the switching element Q1 according to the load state of the switching power supply 200. The lighter the load on the switching power supply 200, the lower the voltage at the FB terminal. When the voltage at the FB terminal is low, the period during which the switching element Q1 is turned on in each switching cycle becomes shorter. When the on-period of the switching element Q1 is shortened, the on-loss in the switching element Q1 becomes smaller. On the other hand, when the switching frequency is constant, the switching element Q1 switches at regular intervals, so the switching loss remains almost unchanged. In this example, the control circuit 100 reduces the switching frequency of the switching element Q1 and reduces the switching loss in light load conditions by lowering the switching frequency (i.e., lengthening the switching cycle) as the load state of the switching power supply 200 becomes lighter (i.e., the output voltage Vout is higher).

[0038] If the on-period of the switching element Q1 becomes shorter, almost no energy can be transferred to the secondary side even when the switching element Q1 is switched. As a result, the voltage at the FB terminal does not decrease, and the switching frequency does not decrease easily. The control circuit 100 in this example controls the on-period of the switching element Q1 in each switching cycle to be longer than a predetermined minimum period. This allows the switching frequency to be stably reduced when the switching power supply 200 is in a light load state, thereby reducing switching losses. The control circuit 100 uses a timer circuit to set this minimum period. Timekeeping do.

[0039] The control circuit 100 determines whether or not an overcurrent has flowed through the switching element Q1 based on the voltage at the CS terminal. If an overcurrent flows through the switching element Q1, the control circuit 100 controls the switching element Q1 to the OFF state. This protects the switching element Q1. However, immediately after the switching element Q1 is turned on, noise during the turn-on process may cause a false detection of an overcurrent. Therefore, the control circuit 100 invalidates the detection of an overcurrent for a predetermined invalid period after the switching element Q1 is turned on. In other words, the control circuit 100 turns off the switching element Q1 if an overcurrent is detected after the invalid period has elapsed in each switching cycle. This prevents the switching element Q1 from being turned off due to a false detection of an overcurrent. The control circuit 100 uses a timer circuit to determine the invalid period. Timekeeping do.

[0040] The minimum period and invalid period mentioned above are not necessarily the same, so the minimum period Timekeeping A timer circuit and an invalid period Timekeeping It is conceivable to provide a timer circuit and a control circuit 100. However, providing two timer circuits increases the circuit size. In particular, a timer circuit that charges a capacitor with a constant current and measures the period by comparing the charging voltage of the capacitor with a predetermined threshold has an analog circuit for charging the capacitor. Therefore, providing separate timer circuits for the minimum period and the invalid period increases the circuit size. In this example, the control circuit 100 uses a single common timer section to measure the above-mentioned minimum period and invalid period. Timekeeping This allows for a reduction in the circuit size of the timer circuit.

[0041] Figure 2 shows an example of the configuration of the control circuit 100. The control circuit 100 in this example has an internal power supply 11 that generates an internal voltage based on the power supplied from the VCC terminal. The internal power supply 11 is internal This generates the power supply voltage Vdd. internal The power supply voltage Vdd is 5V. Each circuit included in the control circuit 100 operates on the power supply voltage VCC or internal It receives the power supply voltage Vdd.

[0042] The control circuit 100 in this example includes a protection diode 14, a hysteresis circuit 10, and a protection circuit 13. The protection diode 14 clamps the VCC voltage so that the voltage at the VCC terminal does not exceed a predetermined voltage.

[0043] The hysteresis circuit 10 monitors whether the voltage at the VCC terminal has fallen below a predetermined value. The hysteresis circuit 10 outputs a protection signal UVLO, which is L level when the VCC voltage is low and H level when the VCC voltage reaches a predetermined high voltage. When the protection signal UVLO is L level, the voltage at the gate terminal of the switching element Q1 is fixed at L level. This prevents the switching element Q1 from switching when the VCC voltage is low. For example, the hysteresis circuit 10 may set the protection signal UVLO to L level when the VCC voltage falls below 9V. Alternatively, the hysteresis circuit 10 may transition the protection signal UVLO from L level to H level when the VCC voltage rises above 18V. For example, when the switching power supply 200 is started or restarted, the hysteresis circuit 10 sets the protection signal UVLO to H level when the gradually rising VCC voltage exceeds 18V.

[0044] The protection circuit 13 monitors the internal voltage generated by the internal power supply 11. If any of the internal voltages fall outside a preset tolerance range, the protection circuit 13 stops the switching operation of the switching element Q1.

[0045] The control circuit 100 includes a PWM circuit 22, an oscillation frequency control unit 24, an oscillator 26, a common timer unit 300, a control pulse generation unit 32, a logical AND circuit 31, an inverter 33, a logical AND circuit 34, and a control signal output unit 20. The control signal output unit 20 outputs a control signal OUT that controls the switching element Q1 according to the input control pulse. The control signal output unit 20 levels-shifts the control pulse to a signal from 0V to VCC voltage and outputs it. In other words, the control signal output unit 20 outputs 0V when the control pulse is at an L level and outputs the VCC voltage when it is at an H level. When the control signal is 0V, the switching element Q1 is in the off state, and when the control signal OUT is at the VCC voltage, the switching element Q1 is in the on state.

[0046] The control signal output unit 20 outputs 0V regardless of the control pulse as long as an L-level signal is input to the enable terminal EN. The hysteresis circuit 10 and protection circuit 13 described above stop the switching operation of the switching element Q1 by inputting an L-level signal to the enable terminal EN of the control signal output unit 20.

[0047] The PWM circuit 22, common timer unit 300, oscillator 26, and control pulse generation unit 32 generate control pulses. The oscillator 26 generates an oscillation signal that defines the cycle of the control pulses. The oscillation frequency control unit 24 controls the frequency of the oscillation signal. The oscillator 26 may generate a triangular wave signal Vosc and a square wave signal Dmax as oscillation signals. The period of the oscillation signal may be set by the resistance value of resistor R8 connected to the RT terminal. The triangular wave signal Vosc and the square wave signal Dmax are synchronized. In this example, the signal level of the triangular wave signal Vosc increases during the period when the square wave signal Dmax is at a high level, and the signal level of the triangular wave signal Vosc decreases during the period when the square wave signal Dmax is at a low level.

[0048] The PWM circuit 22 compares the Vfb voltage at the FB terminal with the signal level of the triangular wave signal Vosc. In this example, the PWM circuit 22 outputs a high level when the voltage of the triangular wave signal Vosc exceeds the Vfb voltage, and outputs a low level when the voltage of the triangular wave signal Vosc is below the Vfb voltage.

[0049] A resistor 68 is provided between the FB terminal and the high-potential line (Vdd). As described above, a current corresponding to the output voltage Vout flows through the FB terminal. Since this current flows through resistor 68, the voltage at the FB terminal... Vfb This is determined by the resistance value Rfb of resistor 68 and the value of the current. In this example, as the output voltage Vout increases, the Vfb voltage decreases, and as the output voltage Vout decreases, the Vfb voltage increases.

[0050] The control pulse generation unit 32 generates pulses in each cycle of the oscillation signal generated by the oscillator 26. Each cycle of the oscillation signal defines the switching cycle of the switching element Q1. In this example, the control pulse generation unit 32 is a set-reset flip-flop. The set terminal of the control pulse generation unit 32 receives the on-trigger signal ONtrg output by the common timer unit 300. The output of the control pulse generation unit 32 transitions to a high level in accordance with the rising edge of the on-trigger signal ONtrg. The common timer unit 300 generates an on-trigger signal with a pulse width shorter than the square wave signal Dmax in accordance with the rising edge of the square wave signal Dmax. Major Outputs trg.

[0051] The output terminal of the AND circuit 31 is connected to the reset terminal of the control pulse generation unit 32. The AND circuit 31 outputs the AND of the output of the PWM circuit 22 and the output of the inverter 33. The inverter 33 outputs the inverted second timer signal Tonmin output by the common timer unit 300. The second timer signal Tonmin is a signal that defines the minimum period for which the switching element Q1 should be kept in the ON state at the start of each switching cycle of the switching element. In this example, the second timer signal Tonmin is a signal that shows an H level from the start timing of each switching cycle until the said minimum period has elapsed, and shows an L level from the time the said minimum period has elapsed until the start timing of the next switching cycle. In other words, the second timer signal Tonmin is a signal that is H level for the period during which the switching element Q1 should be kept in the ON state, and L level for the period during which the switching element Q1 may be in the OFF state. The common timer unit 300 outputs the second timer signal Tonmin, which is H level for the said minimum period from the rising edge timing of the square wave signal Dmax. The common timer unit 300 may change the minimum period according to the load of the switching power supply 200.

[0052] The inverter 33 inverts the second timer signal Tonmin and inputs it to the AND circuit 31. As long as the second timer signal Tonmin is at a high level, no high-level signal is input to the reset terminal of the control pulse generation unit 32. As a result, the output of the control pulse generation unit 32 remains at a high level from the start timing of each switching cycle until a predetermined minimum period has elapsed. After the predetermined period has elapsed, the output of the control pulse generation unit 32 transitions to a low level when the signal output by the PWM circuit becomes high. In other words, the control pulse generation unit 32 outputs a high level until the predetermined minimum period has elapsed and the voltage of the triangular wave signal Vosc exceeds the Vfb voltage. As a result, the control pulse generation unit 32 outputs a control pulse in each switching cycle with a pulse width adjusted according to the level of the Vfb voltage.

[0053] In this example, the control pulse width increases as the Vfb voltage increases (i.e., the output voltage Vout is low), and decreases as the Vfb voltage decreases (i.e., the output voltage Vout is high). This suppresses fluctuations in the output voltage Vout.

[0054] The AND circuit 34 may input the AND of the output of the control pulse generation unit 32 and the square wave signal Dmax to the control signal output unit 20. This allows the upper limit of the pulse width of each control pulse to be defined by the pulse width of the square wave signal Dmax. The AND circuit 34 may also input the AND of the output of the control pulse generation unit 32, the oscillation signal (square wave signal), and the inverted output of the set reset circuit 30 to the control signal output unit 20. The set reset circuit 30 fixes the output of the AND circuit 34 to an L level when an overcurrent of the switching element Q1 is detected.

[0055] The control circuit 100 has a first protection unit 110. The first protection unit 110 turns off the switching element Q1 and stops the drain current Ids flowing through the switching element Q1 when the drain current Ids exceeds a first threshold. In this example, the first protection unit 110 fixes the output of the control pulse generation unit 32 of the oscillation signal for that cycle to an L level when the drain current Ids flowing through the switching element Q1 exceeds a first threshold. This prevents excessive current from flowing through the switching element Q1. The first protection unit 110 receives a current detection signal CS, which indicates the magnitude of the drain current Ids, from the CS terminal. In this example, the current detection signal CS is a negative voltage signal whose absolute value increases as the drain current Ids increases.

[0056] The first protection unit 110 includes a voltage comparison unit 36 ​​and a reference voltage generation unit 38. The reference voltage generation unit 38 generates a reference voltage corresponding to the first threshold described above. In the example in Figure 2, the reference voltage is -0.17V. The voltage comparison unit 36 ​​compares the current detection signal CS with the reference voltage. The voltage comparison unit 36 ​​outputs an H-level current limiting signal LS1 when the current detection signal CS is below the reference voltage (in this example, when the absolute value of the current detection signal CS is greater than the absolute value of the reference voltage), and outputs an L-level current limiting signal LS1 when the current detection signal CS is equal to or greater than the reference voltage (in this example, when the absolute value of the current detection signal CS is less than or equal to the absolute value of the reference voltage).

[0057] The current limit signal LS1 output by the voltage comparison unit 36 ​​is input to the set terminal of the set reset circuit 30. The first timer signal LEB output by the common timer unit 300 is input to the reset terminal of the set reset circuit 30. The first timer signal LEB is a signal that defines the invalid period for the overcurrent detection described above. In this example, the first timer signal LEB is a signal that shows an H level from the start timing of each switching cycle until the invalid period has elapsed, and shows an L level from the time the invalid period has elapsed until the start timing of the next switching cycle. In other words, the first timer signal LEB is a signal that is H level during the period when overcurrent of the switching element Q1 is not detected, and L level during the period when overcurrent of the switching element Q1 is detected. The common timer unit 300 outputs the first timer signal LEB, which is H level only during the invalid period, from the rising edge timing of the square wave signal Dmax.

[0058] The inverting output QB of the set-reset circuit 30 is fixed at a high level from the start of each switching cycle until the inactive period has elapsed. If an overcurrent in the switching element Q1 is detected between the end of the inactive period and the start of the next switching cycle, the output QB transitions to a low level. When the inverting output QB of the set-reset circuit 30 reaches a low level, the AND gate 34 interrupts the control pulse for that cycle, and the switching element Q1 turns off. As a result, if an overcurrent is detected after the inactive period has elapsed, the switching element Q1 for that cycle is controlled to turn off, thereby suppressing the increase in drain current Ids.

[0059] In this example, the oscillation frequency control unit 24 controls the oscillation frequency of the oscillation signal output by the oscillator 26 according to the resistance value of the resistor R8 connected to the RT terminal. As described above, the oscillation frequency of the oscillation signal defines the switching frequency of the switching element Q1. The oscillation frequency control unit 24 also controls the oscillation frequency in the oscillator 26 based on the Vfb voltage at the FB terminal. The oscillation frequency control unit 24 may increase the oscillation frequency in the oscillator 26 as the Vfb voltage decreases (i.e., as the load on the switching power supply 200 decreases). The oscillation frequency control unit 24 determines whether the switching power supply 200 is in a normal load state or a light load state based on the Vfb voltage, and may increase the oscillation frequency in the light load state compared to the oscillation frequency in the normal load state. This reduces the switching loss of the switching element Q1 in the light load state.

[0060] The control circuit 100 may have a load determination unit 60. The load determination unit 60 determines whether the switching power supply 200 is in a light load state or a normal load state by comparing the Vfb voltage with a predetermined reference voltage Vfbstb. The load determination unit is an example of a discrimination circuit. The load determination unit 60 outputs a light load signal VstbL which is L level when the Vfb voltage is less than or equal to the reference voltage Vfbstb (i.e., in a light load state) and H level when the Vfb voltage is greater than the reference voltage Vfbstb (i.e., in a normal load state). The common timer unit 300 may change the minimum period that defines the minimum ON width of the switching element Q1 according to the light load signal VstbL. In this example, the common timer unit 300 makes the minimum period for the switching power supply 200 to be in a light load state longer than the minimum period for the normal load state. This allows the ON width of the switching element Q1 to be kept relatively large even when the switching power supply 200 is in a light load state, and increases the energy sent to the secondary side in each switching cycle. As a result, the oscillation frequency control unit 24 can maintain the output voltage Vout even when it reduces the switching frequency according to the load condition, and can further reduce the switching frequency when the load condition becomes lighter.

[0061] The control circuit 100 may have a stop determination unit 62. The stop determination unit 62 determines whether the output voltage Vout of the switching power supply 200 has become too high by comparing the Vfb voltage with a predetermined reference voltage Vfboff. The reference voltage Vfboff may be lower than the reference voltage Vfbstb. For example, if the switching element Q1 is switched when the switching power supply 200 is in an unloaded state, the power sent to the secondary side of the switching power supply 200 will be large, causing the output voltage Vout to become too high and resulting in an overvoltage. The stop determination unit 62 outputs a determination signal fboffL that is L level when the Vfb voltage is less than or equal to the reference voltage Vfboff, and H level when the Vfb voltage is greater than the reference voltage Vfboff. The common timer unit 300 does not output a trigger signal ONtrg during the period when the determination signal fboffL is at the L level. This allows the switching operation of the switching element Q1 to be stopped when the output voltage Vout becomes an overvoltage.

[0062] The PWM circuit 22 may receive the Vss voltage from the SS terminal. The PWM circuit 22 may compare the lower of the Vss voltage and the Vfb voltage with the triangular wave signal Vosc. A current Iss flows through the SS terminal from the current source 40. When the switching power supply 200 is started, the capacitor C4 connected to the SS terminal is charged by the current Iss, and the Vss voltage gradually rises. During the period when the Vss voltage is lower than the Vfb voltage, the PWM circuit 22 compares the Vss voltage with the triangular wave signal Vosc, so the pulse width of the control pulse gradually increases in accordance with the Vss voltage. This allows for a soft start by gradually increasing the drain current Ids when the switching power supply 200 is started.

[0063] The control circuit 100 may have a transistor 46 located between the SS terminal and the GND potential. Turning on the transistor 46 brings the Vss voltage to the GND potential. The control circuit 100 may have an inverter 48 that controls the transistor 46. In this example, the inverter 48 inverts the enable signal EN output by the AND circuit 54 and inputs it to the transistor 46.

[0064] The AND circuit 54 outputs the AND of the protection signal UVLO and the protection circuit 13 as the enable signal EN. The enable signal EN is input to the enable terminal EN of the control signal output unit 20. In other words, the AND circuit 54 stops the switching operation of the switching element Q1 when an abnormality is detected in either the protection circuit 13 or the hysteresis circuit 10.

[0065] Figure 3 shows an example of the configuration of the common timer unit 300. In this example, the common timer unit 300, after the invalid period has elapsed, calculates the remaining minimum period. Timekeeping In this example, the start timings of the deactivation period and the minimum period are the same, and the minimum period is longer than the deactivation period. The start timings of the deactivation period and the minimum period may be the start timings of their respective switching cycles.

[0066] The common timer unit 300 in this example includes a common capacitor 302, a charge / discharge control unit 310, a comparison unit 305, an inactive period output unit 321, a minimum period output unit 322, a first one-shot circuit 332, a second one-shot circuit 338, a flip-flop 350, a switch 340, a switch 342, and various logic circuits. The logic circuits include inverters (inverting circuits), AND circuits, OR circuits, etc. The common timer unit 300 charges the common capacitor 302 with a predetermined charging current and outputs the minimum period and inactive period based on the timing when the charging voltage VCT of the common capacitor 302 reaches a predetermined voltage. Timekeeping do.

[0067] The charge / discharge control unit 310 controls the charging and discharging of the common capacitor 302. The charge / discharge control unit 310 starts charging the common capacitor 302 at a common start timing for the minimum period and the inactive period. This common timing may also be the same as the start timing for the ON period of the switching element Q1. The charge / discharge control unit 310 also discharges the common capacitor 302 when its charging voltage VCT reaches a predetermined first set voltage. This timing is the end timing of the inactive period. After discharging the common capacitor 302, the charge / discharge control unit 310 recharges the common capacitor 302. The charge / discharge control unit 310 also discharges the common capacitor 302 when its charging voltage VCT reaches a predetermined second set voltage. This timing is the end timing of the minimum period. In this example, the first set voltage and the second set voltage are the same.

[0068] The comparison unit 305 outputs a signal indicating whether the charging voltage VCT of the common capacitor 302 has reached the first set voltage or the second set voltage. In this example, the comparison unit 305 has an inverter 304 and an inverter 306. The charging voltage VCT is input to the inverter 304. When the charging voltage VCT is equal to or greater than the threshold voltage of the inverter 304, the output of the inverter 304 becomes L level, and when the charging voltage VCT is less than the threshold voltage, the output of the inverter 304 becomes H level. In other words, the threshold voltage of the inverter 304 in this example corresponds to the first set voltage and the second set voltage. By using the inverter 304, it is possible to determine whether the charging voltage VCT has reached the first set voltage or the second set voltage with a simple configuration. The inverter 306 inverts the output of the inverter 304 and outputs it.

[0069] The charge / discharge control unit 310 may make the charging current for the first period, from the start of charging of the common capacitor 302 until the charging voltage VCT reaches the first set voltage, different from the charging current for the second period, from the discharge of the common capacitor 302 until the common capacitor 302 is recharged and the charging voltage VCT reaches the second set voltage. In other words, the charge / discharge control unit 310 changes the value of the charging current used to charge the common capacitor 302 before and after the end of the inactivity period. This allows the lengths of the first and second periods to be controlled, and thereby the lengths of the inactivity period and the minimum period to be controlled, respectively. The first period corresponds to the inactivity period, and the sum of the first and second periods corresponds to the minimum period. Alternatively, the lengths of the first and second periods can also be controlled by changing the first set voltage and the second set voltage without changing the charging current. In this case, the comparison unit 305 has a voltage comparator that compares the charging voltage VCT with each set voltage. By adjusting each period by changing the charging current, the configuration of the comparison unit 305 can be simplified.

[0070] The charge / discharge control unit 310 in this example includes a current source 311, a current source 312, a logical OR circuit 313, a switch 314, an inverter 315, a switch 316, and a switch 317. Current source 311 generates current I0, and current source 312 generates current I2. Switch 314 selects which current source to use to generate the charging current. In this example, when switch 314 is ON, the sum of currents I0 and I2 becomes the charging current, and when switch 314 is OFF, current I2 becomes the charging current. In this example, the charging current is controlled by whether or not current I0 is added to current I2. In other examples, the charging current may be controlled by selectively selecting between current I0 and current I2.

[0071] The OR circuit 313 controls the switch 314. The OR circuit 313 outputs the inverted OR of the light load signal VstbL shown in Figure 2 and the output of the inverter 315. The inverter 315 outputs a signal that is high level in the first period and low level in the second period. In other words, the OR circuit 313 outputs a high level when it is the second period and the light load signal VstbL indicates a light load state. The OR circuit 313 also outputs a low level when it is the first period or when at least one of the following conditions is met: it is the first period or it is a normal load state. When the OR circuit 313 outputs a high level, the switch 314 turns off and the charging current becomes I2. When the OR circuit 313 outputs a low level, the switch 314 turns on and the charging current becomes I0+I2. In other words, in a light load state, the charging current I0+I2 in the first period is greater than the charging current I2 in the second period. For this reason, the first period in this example is shorter than the second period.

[0072] Switches 316 and 317 switch between charging and discharging the common capacitor 302. In this example, switches 316 and 317 are complementary CMOS transistors. When switch 316 is on and switch 317 is off, the common capacitor 302 is charged; when switch 316 is off and switch 317 is on, the common capacitor 302 is discharged.

[0073] The first one-shot circuit 332 outputs a first one-shot signal OS1 with a shorter pulse width than the square wave signal Dmax, in accordance with the rising edge of the square wave signal Dmax. The first one-shot signal OS1 may be output from the ONtrg terminal as an on-trigger signal ONtrg. In this example, the AND circuit 334 outputs the AND of the first one-shot signal OS1 and the decision signal fboffL as the on-trigger signal ONtrg. In other words, the AND circuit 334 outputs the first one-shot signal OS1 as the on-trigger signal ONtrg when the output voltage Vout is not an overvoltage (fboffL=H). That is, when there is no overvoltage, the first one-shot signal OS1 and the on-trigger signal ONtrg refer to the same signal. The on-trigger signal ONtrg defines the start timing of each switching cycle.

[0074] The invalid period output unit 321 receives the on-trigger signal O N In response to trg, the first timer signal LEB is transitioned to the H level. Similarly, the minimum period output unit 322 transitions the second timer signal Tonmin to the H level in response to the on trigger signal ONtrg. The inactive period output unit 321 in this example is a flip-flop whose output transitions to the H level in response to the first set signal Set1 and to the L level in response to the first reset signal Rst1. The minimum period output unit 322 in this example is a flip-flop whose output transitions to the H level in response to the second set signal Se12 and to the L level in response to the second reset signal Rst2. The first set signal Set1 and the second set signal Set2 in this example are the on trigger signal ONtrg. The first reset signal Rst1 is a signal output by the inverter 306, and the second reset signal is a signal output by the reset control unit 352.

[0075] The inactive period output unit 321 outputs a first timer signal LEB indicating the end of the inactive period (or first period) when the charging voltage VCT of the common capacitor 302 reaches a first set voltage, after the start timing defined by the on-trigger signal ONtrg. In this example, the inactive period output unit 321 transitions the first timer signal LEB to a low level when the inactive period ends. The inactive period output unit 321 also discharges the common capacitor 302 and recharges it when the inactive period ends.

[0076] The output terminal of the inverter 306 is connected to the reset terminal R1 of the inactive period output unit 321. In other words, when the charging voltage VCT of the common capacitor 302, which began charging at the start timing, reaches the first set voltage and the output of the inverter 306 transitions to the H level, the first timer signal LEB transitions to the L level. The period during which the first timer signal LEB is at the H level corresponds to the inactive period (first period). On-trigger signal to start the next switching cycle Major The output of the inactive period output unit 321 is fixed at an L level until trg is input to the set terminal of the inactive period output unit 321. The inactive period output unit 321 may also receive a reset signal Reset to initialize the state of the control circuit 100. When the reset signal Reset is received, the output of the inactive period output unit 321 transitions to an L level.

[0077] The first timer signal LEB is output to the LEB terminal and is also input to the control terminals of switches 316 and 317 via inverter 336, second one-shot circuit 338, OR circuit 346, and switch 342. Inverter 336 inverts and outputs the first timer signal LEB. The second one-shot circuit 338 outputs a second one-shot signal OS2 with a shorter pulse width than the first timer signal LEB, depending on the rising edge of the signal output by inverter 336. In other words, the second one-shot circuit 338 outputs the short-pulse second one-shot signal OS2 at the timing when the inactive period (first period) ends.

[0078] The second one-shot signal OS2 is input to switch 342 via the OR circuit 346. Switches 340 and 342 switch whether to control switches 316 and 317 using either the output of inverter 336 or the output of OR circuit 346. Switch 340 is off in light load conditions (VstbL=L) and on in normal load conditions (VstbL=H). Switch 342 is on in light load conditions (VstbL=L) and off in normal load conditions (VstbL=H). When switch 340 is on, the output of inverter 336 is input to switches 316 and 317, and when switch 340 is off, the output of OR circuit 346 is input to switches 316 and 317. In other words, in light load conditions, the charging and discharging of the common capacitor 302 is controlled according to the second one-shot circuit OS2. When the inactive period ends under light load conditions, a short pulse, the second one-shot signal OS2, is input to the control terminals of switches 316 and 317, turning switch 317 ON and switch 316 OFF. As a result, when the inactive period (first period) ends, the common capacitor 302 is discharged for the period during which the second one-shot signal OS2 is at a high level. one When the shot signal OS2 reaches a high level, the output of the flip-flop 350 transitions to a high level, and the switch 314 turns off. Therefore, when the inactive period (first period) ends, the charging current decreases from I0 + I2 to I2.

[0079] When the second one-shot signal OS2 reaches a low level, switch 316 turns on and switch 317 turns off, and recharging of the common capacitor 302 begins. When the charging voltage VCT of the recharged common capacitor 302 reaches the second set voltage (the same as the first set voltage in this example), and the output of inverter 306 transitions to a high level again, the minimum period output section 322 is reset, and the second timer signal Tonmin transitions to a low level. The period during which the second timer signal Tonmin is at a high level corresponds to the minimum period (first period + second period).

[0080] A reset control unit 352 is connected to the reset terminal R1 of the minimum period output unit 322. The reset control unit 352 outputs a logical AND of the output of the inverter 306 and the mask signal Msk output by the flip-flop 350. The flip-flop 350 outputs an L level during the first period and an H level during other periods. As a result, even if the output of the inverter 306 transitions to an H level at the end of the first period, the second reset signal Rst2 to the minimum period output unit 322 is masked to an L level, and the second timer signal Tonmin remains at an H level. On the other hand, if the output of the inverter 306 transitions to an H level again at the end of the second period, the second reset signal Rst2 transitions to an H level, the minimum period output unit 322 is reset, and the second timer signal Tonmin transitions to an L level. A reset signal Reset to initialize the state of the control circuit 100 may also be input to the minimum period output unit 322. When the reset signal Reset is input, the output of the minimum period output section 322 transitions to a low level.

[0081] The output terminal of the OR circuit 348 is connected to the set terminal of the flip-flop 350. The OR circuit 348 outputs the OR of the second one-shot signal OS2 and the light load signal VstbL. In other words, the OR circuit 348 inputs an H-level signal to the set terminal of the flip-flop 350 when at least one of the following conditions is met: the system is under normal load conditions, or the second one-shot signal OS2 is at an H level. The on-trigger signal ONtrg is input to the reset terminal R1 of the flip-flop 350. In other words, the flip-flop 350 outputs an L-level mask signal Msk from the time the on-trigger signal ONtrg transitions to an H level until the first period ends, and then outputs an H-level mask signal Msk after the first period ends until the on-trigger signal ONtrg transitions to an H level again. The flip-flop 350 may also receive a reset signal Reset to initialize the state of the control circuit 100. When the reset signal Reset is input, the output of flip-flop 350 transitions to a low level. This configuration allows for the generation of a second timer signal Tonmin, which shows a high level for a minimum period and a low level for other periods.

[0082] Inverter 354 inverts the second timer signal Tonmin and inputs it to the OR circuit 346. The OR circuit 346 inputs the OR of the second one-shot signal OS2 and the output of inverter 354 to the control terminals of switches 316 and 317 via switch 342. The OR circuit 346 keeps the common capacitor 302 discharged from the end of the minimum period until the next switching cycle begins.

[0083] Figure 4 is a timing chart showing an example of the operation of the control circuit 100 under light load conditions (VstbL=L). In this example, the oscillator 26 generates a triangular wave signal Vosc that transitions between 1V and 3V. The oscillator 26 also outputs a square wave signal Dmax synchronized with the triangular wave signal Vosc. The square wave signal Dmax is at a high level when the triangular wave signal Vosc is rising, and when the triangular wave signal Vosc is falling. period The signal level becomes L. Under light load conditions, the oscillation frequency control unit 24 lowers the oscillation frequency of the oscillator 26. As a result, the period (corresponding to the switching cycle) of the triangular wave signal Vosc becomes relatively long.

[0084] Figure 4 shows the Vfb voltage along with the triangular wave signal Vosc. The PWM circuit 22 outputs an H level when the voltage of the triangular wave signal Vosc exceeds the Vfb voltage, and outputs an L level when the voltage of the triangular wave signal Vosc is below the Vfb voltage.

[0085] The first one-shot circuit 332 outputs a first one-shot signal OS1 with a short pulse width at the start timing t0 of each switching cycle. The second timer signal Tonmin output by the minimum period output unit 322 and the first timer signal LEB output by the inactive period output unit 321 transition to a high level in response to the first one-shot signal OS1. Also, in response to the first one-shot signal OS1, charging of the common capacitor 302 begins, and the charging voltage Vct increases. The slope of the charging voltage Vct is determined by the charging current I0 + I2.

[0086] At timing t1, when the charging voltage Vct reaches the first set voltage Th1, the first timer signal LEB output by the inactive period output unit 321 transitions to the L level. Note that during the first period (t0~t1), the mask signal Msk is at the L level, so at timing t1, the minimum period output unit 322 is not reset, and the second timer signal Tonmin remains at the H level. Also at timing t1, the second one-shot circuit 338 outputs a second one-shot signal OS2 with a short pulse width. This discharges the common capacitor 302. When the second one-shot signal OS2 transitions to the L level, the common capacitor 302 is recharged. In this example, the slope of the charging voltage Vct during recharging is determined by the charging current I2, so the slope of the charging voltage Vct during the second period becomes gentler.

[0087] At timing t2, when the charging voltage Vct reaches the second set voltage Th2, the second timer signal Tonmin output by the minimum period output unit 322 transitions to the L level. When the second timer signal Tonmin transitions to the L level, the common capacitor 302 is discharged by the inverter 354, etc. In this example, timing t0 to t1 corresponds to the inactive period and the first period, timing t1 to t2 corresponds to the second period, and timing t0 to t2 corresponds to the minimum period. In this example, the second period is longer than the first period.

[0088] When the first one-shot signal OS1 is generated at timing t0, the control signal OUT for the switching element Q1 transitions to a high level, and the switching element Q1 turns on. As described above, when the switching element Q1 turns on, turn-on noise may occur in the current detection signal CS, which may lead to false detection of overcurrent. In this example, the first timer signal LEB disables overcurrent detection during the inactive period t0-t1. Therefore, false detection of overcurrent can be suppressed.

[0089] The control pulse generation unit 32 outputs a control signal OUT having a pulse width from the time a one-shot pulse is input until the timing when the voltage of the triangular wave signal Vosc exceeds the Vfb voltage. In this example, during the second period t1-t2, the voltage of the triangular wave signal Vosc exceeds the Vfb voltage. However, due to the second timer signal Tonmin, the control signal OUT is maintained at a high level during the minimum period t0-t2. This prevents the on-period of the switching element Q1 from becoming too short, allows the switching frequency to be appropriately reduced, and suppresses switching losses.

[0090] As explained in Figure 4, when performing light-load operation, the control circuit 100 uses an inactive period and a minimum period to turn off the switching element Q1 if an overcurrent is detected after the inactive period has elapsed in each switching cycle. The control circuit 100 also controls the period during which the switching element Q1 is turned on in each switching cycle to be longer than the minimum period. If light-load operation is performed within a switching cycle and an overcurrent is detected after the inactive period has elapsed but before the minimum period, the control circuit 100 may turn off the switching element Q1. The control circuit 100 may prioritize the operation of turning off the switching element Q1 when an overcurrent is detected over the operation of maintaining the switching element Q1 in the on state for the minimum period.

[0091] Figure 5 is a timing chart showing an example of the operation of the control circuit 100 under normal load conditions (VstbL=H). As explained in Figure 3, under normal load conditions, the output of the OR circuit 313 is L The level is fixed, and the charging current is fixed to I0 + I2. Also, when switch 340 is on and switch 342 is off, the charging and discharging of the common capacitor 302 is controlled by the first timer signal LEB. 、When the first timer signal LEB is at a high level, the common capacitor 302 is charged, and when the first timer signal LEB is at a low level, the common capacitor 302 is discharged. Also, since the output of the OR circuit 348 is fixed at a high level, the mask signal Msk is at a low level only while the first one-shot signal OS1 is at a high level, and at a high level during other periods.

[0092] The triangular wave signal Vosc and the square wave signal Dmax are the same as in the example in Figure 4. However, under normal load conditions, the oscillation frequency control unit 24 increases the oscillation frequency of the oscillator 26. As a result, the period (corresponding to the switching cycle) of the triangular wave signal Vosc becomes relatively short. The PWM circuit 22 outputs an H level when the voltage of the triangular wave signal Vosc exceeds the Vfb voltage, and outputs an L level when the voltage of the triangular wave signal Vosc is below the Vfb voltage, similar to the example in Figure 4.

[0093] The first one-shot circuit 332 outputs a first one-shot signal OS1 with a short pulse width at the start timing of each switching cycle. The second timer signal Tonmin output by the minimum period output unit 322 and the first timer signal LEB output by the inactive period output unit 321 transition to a high level in response to the first one-shot signal OS1. In addition, charging of the common capacitor 302 begins in response to the first one-shot signal OS1, and the charging voltage Vct increases.

[0094] When the charging voltage Vct reaches the first set voltage Th1, the first timer signal LEB output by the inactive period output unit 321 transitions to the L level. Under normal load conditions, the mask signal Msk at that timing is at the H level, so the second timer signal Tonmin output by the minimum period output unit 322 also transitions to the L level. In other words, under normal load conditions, the inactive period and the minimum period are the same.

[0095] Furthermore, when the charging voltage Vct reaches the first set voltage Th1, the second one-shot circuit 338 outputs a second one-shot signal OS2 with a short pulse width. In this example, the charging and discharging of the common capacitor 302 is controlled by the first timer signal LEB. Therefore, the common capacitor 302 is kept in a discharged state until the next switching cycle starts.

[0096] In this example as well, the first timer signal LEB disables overcurrent detection during the inactive period. This suppresses false detection of overcurrent. Furthermore, the second timer signal Tonmin limits the pulse width of the control signal OUT to be longer than the minimum period. In the example in Figure 5, since the period until the triangular wave signal Vosc exceeds the Vfb voltage is longer than the minimum period, the control signal OUT maintains a high level until the triangular wave signal Vosc exceeds the Vfb voltage. As shown in Figure 5, the control circuit 100 in normal operation does not use the minimum period but uses the inactive period, thereby controlling the switching element to turn off if an overcurrent is detected after the inactive period has elapsed in each switching cycle.

[0097] Figure 6 shows an example configuration of the oscillation frequency control unit 24 and the oscillator 26. In this example, the oscillation frequency control unit 24 includes an amplifier 402, an amplifier 410, a transistor 416, a resistor Rs, a resistor Rf, and a power supply 406.

[0098] Amplifier 402 has a voltage Vfb input to its positive terminal, and its negative terminal and output terminal are connected by a resistor Rf. A resistor Rs and a power supply 406 are connected in series between the negative terminal of amplifier 402 and ground potential. Let point A be the point connected to the output terminal of amplifier 402, and point B be the point connected to the negative terminal. Since the voltage at point B of amplifier 402 is equal to the Vfb voltage, the voltage at point A of amplifier 402 is (Vfb - Vstb0) × (Rs + Rf) / Rs + Vstb0. Vstb0 is the voltage of power supply 406.

[0099] The output terminal of amplifier 402 is connected to the first positive terminal of amplifier 410. A constant voltage, for example, 2.5V, is applied to the second positive terminal of amplifier 410. Amplifier 410 operates using the lower of the voltages applied to the first and second positive terminals. The emitter terminal of transistor 416 is connected to the negative terminal of amplifier 410. Amplifier 410 operates so that the lower of the voltages applied to the first and second positive terminals is equal to the voltage at the RT terminal.

[0100] The control terminal of transistor 416 is connected to the output terminal of amplifier 410. 。 The emitter terminal of transistor 416 is connected to the RT terminal. The collector terminal of transistor 416 is connected to the oscillator 26. The collector current flowing through transistor 416 controls the oscillation frequency of oscillator 26.

[0101] The oscillator 26 generates a Miller current corresponding to the collector current and charges the capacitor C0 with this Miller current. When the charging voltage reaches a predetermined voltage (e.g., 3V), the capacitor C0 is discharged. When the charging voltage drops to a predetermined voltage (e.g., 1V), the capacitor C0 is recharged. By repeating this operation, the oscillator 26 generates an oscillation signal (Vosc, Dmax) having an oscillation frequency corresponding to the collector current. A description of each element of the oscillator 26 is omitted.

[0102] Figure 7 shows the relationship between the oscillation frequency of oscillator 26 and the Vfb voltage. The oscillation frequency under normal load is shown as the normal oscillation frequency. Under normal load, oscillator 26 oscillates at a constant normal oscillation frequency corresponding to the resistor R8 connected to the RT terminal. When the load is reduced, the output voltage Vout of the switching power supply 200 increases and the Vfb voltage decreases.

[0103] Figure 8 shows the relationship between the voltage at the RT terminal and the Vfb voltage. The voltage characteristics at point A of amplifier 402 are shown by a dashed line.

[0104] As shown in Figure 8, when the Vfb voltage drops to a predetermined VoscDec, the voltage at point A drops to, for example, 2.5V.

[0105] The amplifier 410 operates such that the lower of the voltages applied to the first positive terminal and the second positive terminal is equal to the voltage at the RT terminal. Therefore, in the region where the Vfb voltage is below VoscDec, the RT terminal voltage decreases as the Vfb voltage decreases. Consequently, the current flowing through the resistor R8 at the RT terminal decreases in proportion to the RT terminal voltage, and the charging and discharging current of the capacitor C0 of the oscillator 26 also decreases by the same ratio. This reduces the oscillation frequency and thus the switching frequency.

[0106] Figure 9 shows the waveform of the charging voltage of capacitor C0. As shown in Figure 9, the oscillation frequency changes with the voltage RT at the RT terminal.

[0107] Figure 10 shows the ON width (pulse width) of the control signal OUT and the Vfb voltage. of This diagram shows the relationship. Figure 10 shows the lengths of the second timer signal Tonmin under light load and normal load conditions. As shown in Figure 10, when the Vfb voltage is greater than or equal to Vfbstb, the second timer signal Tonmin under normal load conditions is set, and when the Vfb voltage is less than Vfbstb, the second timer signal Tonmin under light load conditions is set.

[0108] When the ON width of the control signal OUT is small under light load conditions, the ON loss decreases, and the effect of switching loss increases. Also, the Vfb voltage does not decrease easily, making it difficult to reduce switching loss and reducing efficiency under light load conditions. For this reason, the control circuit 100 under light load conditions minimum By setting a larger ON width (length of the second timer signal Tonmin), a larger amount of energy is maintained to the secondary side during a single switching cycle. This makes it easier to lower the Vfb voltage, reduce the oscillation frequency, decrease the switching frequency, and reduce losses.

[0109] When the load decreases and the Vfb voltage falls below Vfbstb, the second timer signal Tonmin becomes longer. The switching of the second timer signal Tonmin is performed by a load determination unit 60 (see Figure 2), which is different from the frequency reduction in the oscillation frequency control unit 24. Since the ON width of the control signal OUT is not narrower than the pulse width of the second timer signal Tonmin, when the pulse width of the second timer signal Tonmin increases, the oscillation frequency stabilizes at a lower state.

[0110] As the load further decreases and the Vfb voltage drops to Vfboff, the stop determination unit 62 fixes the control signal OUT to a low level, stopping the switching operation of the switching element Q1. When the load becomes this light, the Vfb voltage slowly fluctuates around the Vfboff voltage. As a result, the switching element Q1 performs intermittent switching operations and stabilizes in a state where the switching frequency is further reduced.

[0111] Under normal load conditions, as shown in Figure 5, the Vfb voltage increases, and the pulse width of the control signal OUT increases. However, the load may change suddenly, or other factors may cause the pulse width of the control signal OUT to change suddenly. In this case, if the pulse width of the second timer signal Tonmin is set to a large value, as in the case of light load conditions, the pulse width of the control signal OUT will be forcibly maintained at a large value, which may cause a buzzing sound or a sudden large current to flow through the switching element Q1. By setting the second timer signal Tonmin to a small value under normal load conditions, the buzzing sound or sudden large current can be suppressed.

[0112] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention. [Explanation of Symbols]

[0113] 10...Hysteresis circuit, 11...Internal power supply, 13...Protection circuit, 14...Protection diode, 20...Control signal output section, 22...PWM circuit, 24...Oscillation frequency control section, 26...Oscillator, 30...Set reset circuit, 31...Logic AND circuit, 32...Control pulse generation section, 33...Inverter, 34...Logic AND circuit, 36...Voltage comparison section, 38... • Reference voltage generation unit, 40... Current source, 46... Transistor, 48... Inverter, 54... Logic AND circuit, 60... Load determination unit, 62... Stop determination unit, 68... Resistor, 100... Control circuit, 110... First protection unit, 200... Switching power supply, 205... Power supply circuit, 210... Primary side circuit, 220... Secondary side circuit, 230... Power supply circuit, 240... Voltage detection unit, 300... Common timer unit, 302... Common capacitor, 304... Inverter, 305... Comparison unit, 306... Inverter, 310... Charge / discharge control unit, 311, 312... Current source, 313... OR circuit, 314... Switch, 315... Inverter, 316, 317... Switch, 321... Inactive period output unit, 322... Minimum period output unit 332...First one-shot circuit, 334...Logic AND circuit, 336...Inverter, 338...Second one-shot circuit, 340, 342...Switches, 346, 348...Logic OR circuits, 350...Flip-flop, 352...Reset control unit, 354...Inverter, 402...Amplifier, 406...Power supply, 410...Amplifier, 416...Transistor

Claims

1. A control circuit that controls the on-period and off-period in a switching cycle of a switching element that controls the main current flowing through a transformer of a switching power supply, turns off the switching element when an overcurrent is detected after an inactive period has elapsed in the switching cycle, and controls the period during which the switching element remains on in the switching cycle to be greater than or equal to a minimum period, The system includes a common timer unit that outputs a first timer signal defining the invalid period and a second timer signal defining the minimum period. The start timing of the invalid period and the minimum period are the same. The common timer unit, after timing the invalid period, timing the remainder of the minimum period, The aforementioned common timer unit is Common capacitor, A charge / discharge control unit that starts charging the common capacitor at the aforementioned start timing and controls the charging and discharging of the common capacitor, When the voltage of the common capacitor reaches the first set voltage after the start timing, the invalid period output unit outputs the first timer signal indicating the end timing of the invalid period, discharges the common capacitor, and recharges the common capacitor. After the common capacitor has been discharged, when the common capacitor reaches the second set voltage, the minimum period output unit outputs the second timer signal indicating the end timing of the minimum period. A control circuit.

2. The charge / discharge control unit changes the value of the charging current used to charge the common capacitor before and after the end of the inactive period. The control circuit according to claim 1.

3. The charge / discharge control unit reduces the charging current to a lower value than before the end of the inactive period after the inactive period has ended. The control circuit according to claim 2.

4. The first set voltage and the second set voltage are the same voltage. The control circuit according to any one of claims 1 to 3.

5. The inactive period output unit is a flip-flop that receives a first set signal according to the start timing, receives a first reset signal when the voltage of the common capacitor reaches the first set voltage, and outputs the first timer signal. The minimum period output unit is a flip-flop that receives a second set signal according to the start timing, receives a second reset signal when the voltage of the common capacitor reaches the second set voltage, and outputs the second timer signal. The control circuit includes a reset control unit that masks the input of the second reset signal to the minimum period output unit from the start timing until the output of the invalid period output unit transitions in accordance with the first reset signal. The control circuit according to any one of claims 1 to 3.

6. A control circuit that controls the on-period and off-period in a switching cycle of a switching element that controls the main current flowing through a transformer of a switching power supply, turns off the switching element when an overcurrent is detected after an inactive period has elapsed in the switching cycle, and controls the period during which the switching element remains on in the switching cycle to be greater than or equal to a minimum period, The system includes a common timer unit that outputs a first timer signal defining the invalid period and a second timer signal defining the minimum period. The common timer unit defines the minimum period regardless of the current flowing through the switching element. Control circuit.

7. A control circuit that controls the on-period and off-period in a switching cycle of a switching element that controls the main current flowing through a transformer of a switching power supply, turns off the switching element when an overcurrent is detected after an inactive period has elapsed in the switching cycle, and controls the period during which the switching element remains on in the switching cycle to be greater than or equal to a minimum period, The start timing of the invalid period and the minimum period are the same. A common timer unit that outputs a first timer signal defining the invalid period and a second timer signal defining the minimum period, A set reset circuit that receives the first timer signal, outputs an H level from the start timing until the invalid period has elapsed, and outputs an L level if the overcurrent is detected between the end of the invalid period and the start timing of the next switching cycle, A control pulse generation unit receives an on-trigger signal defining the start timing and the second timer signal, and outputs an H level until the minimum period has elapsed from the start timing, A first logical AND circuit outputs a logical AND of the output of the set reset circuit, the output of the control pulse generation unit, and a rectangular wave signal that defines the upper limit of the pulse width of the output of the control pulse generation unit. A control signal output unit outputs a control signal to control the switching element according to the logical AND. A control circuit equipped with the following features.

8. A PWM circuit that defines the timing of the end of the ON period, A second logical AND circuit outputs the logical AND of the output of the PWM circuit and the second timer signal to the reset terminal of the control pulse generation unit. The control circuit according to claim 7, comprising:

9. Multiple switching cycles exist, as they are repeated continuously. The aforementioned control circuit is The switching power supply has a discrimination circuit that determines whether to perform light-load operation or normal operation based on the magnitude of the output voltage of the switching power supply. When performing the light-load operation, the inactive period and the minimum period are used to turn off the switching element if an overcurrent is detected after the inactive period has elapsed in each switching cycle, and the period during which the switching element remains on in each switching cycle is controlled to be greater than or equal to the minimum period. When performing the normal operation described above, the minimum period is not used, and the invalid period is used instead. This allows control to be performed to turn off the switching element if an overcurrent is detected after the invalid period has elapsed in each switching cycle. The control circuit according to any one of claims 1 to 3 or 6 to 8.

10. The control circuit according to any one of claims 1 to 3, 7, or 8, wherein the start timing of the ON period, the OFF period, and the Minimum period are common.

11. The control circuit according to claim 9, which, if the light load operation was performed within the switching cycle, turns off the switching element if the overcurrent is detected after the inactive period has elapsed but before the minimum period has elapsed.

12. Transformer and A switching element that controls the main current flowing through the transformer, A control circuit that controls the on and off periods of the switching element in the switching cycle, turns off the switching element when an overcurrent is detected after the inactive period has elapsed in the switching cycle, and controls the period during which the switching element remains on in the switching cycle to be longer than the minimum period. Equipped with, The control circuit has a common timer unit that outputs a first timer signal defining the invalid period and a second timer signal defining the minimum period. The start timing of the invalid period and the minimum period are the same. The common timer unit, after timing the invalid period, timing the remainder of the minimum period, The aforementioned common timer unit is Common capacitor, A charge / discharge control unit that starts charging the common capacitor at the aforementioned start timing and controls the charging and discharging of the common capacitor, When the voltage of the common capacitor reaches the first set voltage after the start timing, the invalid period output unit outputs the first timer signal indicating the end timing of the invalid period, discharges the common capacitor, and recharges the common capacitor. After the common capacitor has been discharged, when the common capacitor reaches the second set voltage, the minimum period output unit outputs the second timer signal indicating the end timing of the minimum period. A switching power supply having [a certain feature].

13. A transformer, A switching element that controls the main current flowing through the transformer, A control circuit that controls the on and off periods of the switching element in the switching cycle, turns off the switching element when an overcurrent is detected after the inactive period has elapsed in the switching cycle, and controls the period during which the switching element remains on in the switching cycle to be longer than the minimum period. Equipped with, The control circuit has a common timer unit that outputs a first timer signal defining the invalid period and a second timer signal defining the minimum period. The common timer unit defines the minimum period regardless of the current flowing through the switching element. Switching power supply.

14. A transformer, A switching element that controls the main current flowing through the transformer, A control circuit that controls the on and off periods of the switching element in the switching cycle, turns off the switching element when an overcurrent is detected after the inactive period has elapsed in the switching cycle, and controls the period during which the switching element remains on in the switching cycle to be longer than the minimum period. Equipped with, The start timing of the invalid period and the minimum period are the same. The aforementioned control circuit is A common timer unit that outputs a first timer signal defining the invalid period and a second timer signal defining the minimum period, A set reset circuit that receives the first timer signal, outputs an H level from the start timing until the invalid period has elapsed, and outputs an L level if the overcurrent is detected between the end of the invalid period and the start timing of the next switching cycle, A control pulse generation unit receives an on-trigger signal defining the start timing and the second timer signal, and outputs an H level until the minimum period has elapsed from the start timing, A first logical AND circuit outputs a logical AND of the output of the set reset circuit, the output of the control pulse generation unit, and a rectangular wave signal that defines the upper limit of the pulse width of the output of the control pulse generation unit. A control signal output unit outputs a control signal to control the switching element according to the logical AND. A switching power supply having [a certain feature].

15. The control circuit is A PWM circuit that defines the timing of the end of the ON period, A second logical AND circuit outputs the logical AND of the output of the PWM circuit and the second timer signal to the reset terminal of the control pulse generation unit. A switching power supply according to claim 14, comprising:

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