Vibration device

Abstract

To provide a vibration device that can effectively use a wiring layer and can reduce the size of an integrated circuit device.SOLUTION: A vibration device has: an oscillator; an integrated circuit device that oscillates the oscillator to generate an oscillation signal; a container that accommodates the oscillator and the integrated circuit device; and metal bumps that are joined to the integrated circuit device and electrically connect the integrated circuit device and the container to each other. The integrated circuit device has pads that are joined to the metal bumps, and a circuit that is arranged at a position overlapping the metal bumps in plan view of the pads. When the width of the pad is W1, and the width of the metal bump is W2, W1 / W2≥1.08.SELECTED DRAWING: Figure 5

Description

[[Technical Field]]

[0001] The present invention relates to a vibration device. [[Background Art]]

[0002] In the semiconductor integrated circuit described in Patent Document 1, a connection pad is arranged on an upper layer of an active element. A reinforcing structure formed of a dummy pattern that does not contribute to the logic function of the circuit is formed between the connection pad and the active element. This suppresses damage to the active element caused by stress applied during wire bonding to the connection pad. [[Prior Art Documents]] [[Patent Documents]]

[0003] [[Patent Document 1]] Japanese Unexamined Patent Application Publication No. 2005-236277 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0004] However, in the semiconductor integrated circuit of Patent Document 1, since a part of the wiring layer in the semiconductor integrated circuit is used as a dummy pattern, the wiring layer cannot be effectively utilized, which causes a problem of leading to an increase in size of the semiconductor integrated circuit. [[Means for Solving the Problem]]

[0005] The vibration device according to this application example includes a vibrator, an integrated circuit device that causes the vibrator to oscillate and generates an oscillation signal, a container that houses the vibrator and the integrated circuit device, and a metal bump bonded to the integrated circuit device and electrically connecting the integrated circuit device and the container, wherein the integrated circuit device includes a pad bonded to the metal bump, and a circuit arranged at a position overlapping the metal bump in a plan view of the pad, The integrated circuit device is flip-chip mounted in the container via the metal bumps, The circuit is positioned in a location that overlaps with the pad in the plan view. The pad includes a ground pad, an oscillator connection pad, a clock pad, and an enable pad. The circuit includes a reference voltage generation circuit that overlaps the ground pad in the plan view, an oscillator circuit that overlaps the oscillator connection pad in the plan view, an output buffer circuit that overlaps the clock pad in the plan view, and a temperature sensor circuit that overlaps the enable pad in the plan view. each Let the width of the aforementioned pad be W1. Each of the aforementioned pads corresponds to When the width of the aforementioned metal bump is W2, 2.40≧ W1 / W2 ≥ 1.08 the law of nature , The width of the metal bump is the maximum width of the metal bump in the plan view, The width of the pad is the width along the extension of the straight line that defines the maximum width. That is the case. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view of the vibration device according to the first embodiment. [Figure 2] Figure 1 is a plan view of the vibration device shown. [Figure 3] This is a block diagram showing the circuit configuration of an integrated circuit device. [Figure 4] This is a plan view showing the arrangement of each component included in an integrated circuit device. [Figure 5] This is a cross-sectional view along line AA in Figure 4. [Figure 6] This graph shows the relationship between W1 / W2 and the stress ratio. [Figure 7] This is a plan view illustrating the definitions of widths W1 and W2. [Figure 8] This is a plan view illustrating the definitions of widths W1 and W2. [Figure 9] This is a cross-sectional view of the vibration device according to the second embodiment. [Figure 10] This is a plan view showing the arrangement of each part included in the integrated circuit of the vibration device according to the third embodiment. [Modes for carrying out the invention]

[0007] The vibration device of this application example will be described in detail below based on the embodiment shown in the attached drawings.

[0008] <First Embodiment> FIG. 1 is a cross-sectional view of a vibration device according to the first embodiment. FIG. 2 is a plan view of the vibration device shown in FIG. 1. FIG. 3 is a block diagram showing a circuit configuration of an integrated circuit device. FIG. 4 is a plan view showing the arrangement of each part included in the integrated circuit device. FIG. 5 is a cross-sectional view taken along line A-A in FIG. 4. FIG. 6 is a graph showing the relationship between W1 / W2 and a stress ratio. FIGS. 7 and 8 are plan views for explaining the definitions of a width W1 and a width W2, respectively.

[0009] The vibration device 1 shown in FIG. 1 is an oscillator, and includes a package 2 as a container, a vibrator 3 and an integrated circuit device 4 housed in the package 2.

[0010] The package 2 includes a box-shaped base 21 provided with a recess 211 opening on the upper surface thereof, and a plate-shaped lid 22 that closes the opening of the recess 211 and is bonded to the upper surface of the base 21. By closing the opening of the recess 211 with the lid 22, a housing space S for housing the vibrator 3 and the integrated circuit device 4 is formed. The housing space S is airtight and is in a depressurized state, preferably a state closer to vacuum. This reduces viscous resistance and allows the vibrator 3 to be driven stably. However, the atmosphere of the housing space S is not particularly limited.

[0011] Further, the recess 211 includes a first recess 211a opening on the upper surface of the base 21, and a second recess 211b opening on the bottom surface of the first recess 211a and having a smaller opening than the first recess 211a. The vibrator 3 is fixed to the bottom surface of the first recess 211a, and the integrated circuit device 4 is fixed to the bottom surface of the second recess 211b. However, the configuration of the recess 211 is not particularly limited.

[0012] Furthermore, a pair of connection terminals T1 are arranged on the bottom surface of the first recess 211a, a plurality of internal terminals T2 are arranged on the bottom surface of the second recess 211b, and a plurality of external terminals T3 are arranged on the lower surface of the base 21. The plurality of internal terminals T2 include those that are electrically connected to the connection terminals T1 via wiring (not shown) formed in the base 21, and those that are electrically connected to the external terminals T3 via wiring (not shown) formed in the base 21. The pair of connection terminals T1 are electrically connected to the vibrator 3 via conductive bonding members B1 and B2, and the plurality of internal terminals T2 are electrically connected to the integrated circuit device 4 via metal bumps 9. As a result, the vibrator 3 is electrically connected to the integrated circuit device 4, and the integrated circuit device 4 is electrically connected to the external terminals T3. Therefore, the vibration device 1 can be electrically connected to the outside via the external terminals T3.

[0013] The constituent material of the base 21 is not particularly limited, and various ceramics such as aluminum oxide can be used. On the other hand, the constituent material of the lid 22 is not particularly limited, but it is preferable that it be a material whose coefficient of thermal expansion is similar to that of the constituent material of the base 21. For example, if the constituent material of the base 21 is a ceramic as described above, it is preferable to use an alloy such as Kovar.

[0014] As shown in Figure 2, the oscillator 3 has a vibrating substrate 31 which is an AT-cut quartz substrate, and electrodes 32 arranged on the vibrating substrate 31. The AT-cut quartz substrate has a thickness-slip vibration mode and a third-order frequency-temperature characteristic. Therefore, the oscillator 3 has excellent temperature characteristics.

[0015] The vibrating substrate 31 is rectangular, particularly rectangular, in plan view. However, the plan view shape of the vibrating substrate 31 is not particularly limited.

[0016] The electrode 32 includes a first excitation electrode 321 positioned on the upper surface of the vibrating substrate 31, and a second excitation electrode 322 positioned on the lower surface of the vibrating substrate 31 opposite the first excitation electrode 321. The region of the vibrating substrate 31 sandwiched between the first and second excitation electrodes 321 and 322 functions as the vibrating part. The electrode 32 also includes a first pad 323 and a second pad 324 positioned on the lower surface of the vibrating substrate 31, a first lead wire 325 electrically connecting the first excitation electrode 321 and the first pad 323, and a second lead wire 326 electrically connecting the second excitation electrode 322 and the second pad 324.

[0017] The configuration of the oscillator 3 is not limited to the configuration described above. For example, the vibrating substrate 31 is not limited to one formed from an AT-cut quartz substrate, but may be formed from a quartz substrate other than an AT-cut quartz substrate, such as an X-cut quartz substrate, a Y-cut quartz substrate, a Z-cut quartz substrate, a BT-cut quartz substrate, an SC-cut quartz substrate, an ST-cut quartz substrate, etc. Furthermore, the constituent material of the vibrating substrate 31 is not limited to quartz, but may be composed of piezoelectric single crystals such as lithium niobate, lithium tantalate, lithium tetraborate, langasite, potassium niobate, gallium phosphate, etc., or other piezoelectric single crystals. In addition, the oscillator 3 may be a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) oscillator as a silicon oscillator formed using a silicon substrate, etc.

[0018] Such a vibrator 3 is joined to the bottom surface of the first recess 211a via joining members B1 and B2. Furthermore, joining member B1 contacts one connection terminal T1 and the first pad 323, electrically connecting them. Similarly, joining member B2 contacts the other connection terminal T1 and the second pad 324, electrically connecting them. In other words, joining members B1 and B2 mechanically and electrically connect the base 21 and the vibrator 3.

[0019] The joining members B1 and B2 are not particularly limited as long as they possess both conductivity and bonding properties, but in this embodiment, conductive adhesives such as polyimide-based, epoxy-based, silicone-based, and acrylic-based adhesives in which a conductive filler such as silver filler is dispersed are used. By using a conductive adhesive, the joining members B1 and B2 become relatively soft, and for example, thermal stress caused by the difference in thermal expansion coefficients between the base 21 and the vibrating substrate 31 is mitigated by the joining members B1 and B2 and is less likely to be transmitted to the vibrator 3.

[0020] However, in addition to conductive adhesives, metal bumps such as gold bumps and copper bumps can also be used as joining members B1 and B2. This suppresses outgassing from joining members B1 and B2, and effectively suppresses environmental changes in the storage space S, especially the rise in pressure. Furthermore, since wetting and spreading like with adhesives does not occur, the joining members B1 and B2 can be made smaller, and the distance between them can also be narrowed. As a result, the vibration device 1 can be miniaturized.

[0021] As shown in Figure 1, the integrated circuit device 4 is flip-chip mounted on the bottom surface of the second recess 211b via a metal bump 9 with its active surface 40 facing downwards. In a typical flip-chip mounting, first, a protruding metal bump 9 is formed on the pad 42 of the integrated circuit device 4 (described later), then the integrated circuit device 4 is inverted and placed on the bottom surface of the second recess 211b, and then the integrated circuit device 4 is joined to the bottom surface of the second recess 211b by melting the metal bump 9 with a load from the head and ultrasonic vibrations from the ultrasonic horn. If necessary, resin may be sealed in the gap between the bottom surface of the second recess 211b and the integrated circuit device 4. This type of flip-chip mounting allows for space saving and miniaturization of the vibration device 1.

[0022] As shown in Figure 1, the integrated circuit device 4 includes a circuit 41 and a pad 42 that is exposed on the active surface 40 and electrically connected to the circuit 41.

[0023] Furthermore, as shown in Figure 3, circuit 41 includes an oscillator circuit 410, an output buffer circuit 411, a power supply circuit 412, a PLL circuit 413, a logic circuit 414, a non-volatile memory 415, a temperature compensation circuit 416, a temperature sensor circuit 417, a test circuit 418, and an interface circuit 419. Pad 42 includes a power supply pad PVDD, a ground pad PGND, oscillator connection pads PX1 and PX2, a clock pad PCK, and an enable pad POE. Such circuit 41 is an integrated circuit that includes passive elements such as transistors and diodes. Alternatively, it can be said that circuit 41 itself is an active element.

[0024] First, let's describe each circuit block of circuit 41. The oscillator circuit 410 is a circuit that causes the resonator 3 to oscillate. The oscillator circuit 410 is electrically connected to the resonator 3 via resonator connection pads PX1 and PX2, and generates an oscillation signal OSC by causing the resonator 3 to oscillate. Various types of oscillator circuits can be used as the oscillator circuit 410, such as inverter type, Pierce type, Colpitts type, Hartley type, etc.

[0025] The power supply circuit 412 is a DC voltage generation circuit and includes a reference voltage generation circuit 412a and a regulator 412b. This power supply circuit 412 is supplied with a power supply voltage VDD from the power supply pad PVDD and a ground voltage GND from the ground pad PGND, and supplies various power supply voltages for the internal circuits of the integrated circuit device 4.

[0026] The PLL circuit 413 receives the oscillation clock signal OSC from the oscillator circuit 410 and outputs a clock signal CK that is phase-synchronized with the oscillation signal OSC. Specifically, the PLL circuit 413 outputs a clock signal CK that is phase-synchronized with the oscillation signal OSC and has a frequency that is a multiple of the frequency of the oscillation signal OSC. The PLL circuit 413 is, for example, a fractional-N type PLL circuit that can fractionally multiply the frequency of the oscillation signal OSC.

[0027] The output buffer circuit 411 buffers the clock signal CK from the PLL circuit 413 and outputs the clock signal CKQ. This clock signal CKQ is then output to the outside via the external terminal T3 of the vibration device 1.

[0028] The logic circuit 414 is a control circuit that performs various control processes. For example, the logic circuit 414 controls various circuit blocks such as the oscillator circuit 410, output buffer circuit 411, power supply circuit 412, and temperature compensation circuit 416. The logic circuit 414 also controls the writing and reading of the non-volatile memory 415. The logic circuit 414 is, for example, an ASIC (Application Specific Integrated Circuit) circuit using automatic placement and routing, such as a gate array. The non-volatile memory 415 stores various types of information used in the integrated circuit device 4.

[0029] The temperature sensor circuit 417 is a sensor circuit that detects the temperature of the vibration device 1, particularly the temperature of the oscillator 3. The temperature compensation circuit 416 performs temperature compensation based on the temperature detection information from the temperature sensor circuit 417. For example, the temperature compensation circuit 416 generates a temperature compensation voltage VCP based on the temperature detection voltage VT from the temperature sensor circuit 417, and outputs the generated temperature compensation voltage VCP to the oscillation circuit 410, thereby performing temperature compensation for the oscillation signal OSC of the oscillation circuit 410.

[0030] Test circuit 418 is a circuit for testing the integrated circuit device 4. The circuit blocks of the integrated circuit device 4 are tested using test circuit 418. Interface circuit 419 is a circuit for performing communication, such as serial interface communication. Interface circuit 419 is a serial interface circuit such as SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit).

[0031] Next, the pads 42 will be described. The pads 42 are exposed on the active surface of the integrated circuit device 4 and are used to electrically connect the circuit 41 to the outside. Of the pads 42, the power supply pad PVDD is the pad to which the power supply voltage VDD is input. The ground pad PGND is the terminal to which the ground voltage GND is supplied. The clock pad PCK is the pad to which the clock signal CKQ is output. The oscillator connection pads PX1 and PX2 are pads to which the oscillator 3 is connected. The enable pad POE is a pad for enabling the output of the clock signal CKQ, that is, for controlling the ON / OFF state of the output of the clock signal CKQ.

[0032] Next, the arrangement of the circuits 41 and pads 42 of the integrated circuit device 4 will be described. The circuits 41 and pads 42 are arranged as shown in Figure 4. Specifically, the outer shape of the integrated circuit device 4 is rectangular and has a total of four sides: a pair of opposing sides SD1 and SD2, and a pair of opposing sides SD3 and SD4.

[0033] First, let's explain the arrangement of the circuit 41. A temperature compensation circuit 416 is located in the center of the integrated circuit device 4. A PLL circuit 413 is located at the corner where edges SD2 and SD4 intersect, a logic circuit 414 is located at the corner where edges SD1 and SD4 intersect, and a temperature sensor circuit 417 is located at the corner where edges SD2 and SD3 intersect.

[0034] Furthermore, an oscillator circuit 410 is positioned between the temperature compensation circuit 416 and edge SD3, a reference voltage generation circuit 412a is positioned between the temperature compensation circuit 416 and the PLL circuit 413, and an output buffer circuit 411 is positioned between the PLL circuit 413 and the logic circuit 414. Regulators 412b are then positioned between the temperature compensation circuit 416 and the PLL circuit 413, between the output buffer circuit 411 and the logic circuit 414, and scattered at the corners where edges SD1 and SD3 intersect.

[0035] Next, the arrangement of pads 42 will be described. The power pad PVDD is located at the corner where sides SD1 and SD3 intersect. The ground pad PGND is located overlapping with the reference voltage generation circuit 412a. The oscillator connection pads PX1 and PX2 are located overlapping with the oscillator circuit 410. The clock pad PCK is located overlapping with the output buffer circuit 411. The enable pad POE is located overlapping with the temperature sensor circuit 417.

[0036] Therefore, the metal bump 9 connected to the ground pad PGND, the oscillator connection pads PX1 and PX2, the clock pad PCK, and the enable pad POE are also positioned overlapping with the circuit 41.

[0037] The configuration and arrangement of circuit 41 and pad 42 have been described above. However, the configuration and arrangement of circuit 41 and pad 42 are not particularly limited.

[0038] Next, the cross-sectional structure of the integrated circuit device 4 will be described. As shown in Figure 5, the integrated circuit device 4 has a five-layer wiring structure consisting of metal layers ALA to ALE, such as aluminum, and the pad 42 is formed by the uppermost metal layer ALE. Specifically, a part of the metal layer ALE is exposed from the opening of the passivation film PL, and the exposed part constitutes the pad 42. In addition, the P-type substrate PSUB has a P-type well PWL and an N-type well NWL formed therein, and the N-type transistors constituting the reference voltage generation circuit 412a are formed in the P-type well PWL, and the P-type transistors are formed in the N-type well NWL.

[0039] Figure 5 schematically shows the arrangement of the ground pad PGND and the reference voltage generation circuit 412a. In reality, the layout area of ​​the transistors is sufficiently small relative to the layout area of ​​the ground pad PGND, and the number of transistors necessary to constitute the reference voltage generation circuit 412a are arranged below the ground pad PGND.

[0040] The above provides a brief explanation of the configuration of the integrated circuit device 4. In this configuration, the circuit 41 and the pad 42 are arranged to overlap in a plan view. Therefore, the space within the integrated circuit device 4 can be used effectively, and the integrated circuit device 4 can be made smaller. In addition, for example, since there is no need to avoid overlap with the circuit 41, the design freedom for the shape and dimensions of the pad 42 is increased.

[0041] While there are these advantages, there is also a disadvantage: when the integrated circuit device 4 is flip-chip mounted, the stress applied to the pad 42 is easily transmitted to the circuit 41 directly below it, increasing the risk of damage to the circuit 41. Therefore, in the integrated circuit device 4 of this embodiment, by devising the dimensional ratio between the pad 42 and the metal bump 9, the stress applied to the pad 42 during flip mounting is less likely to be transmitted to the circuit 41 directly below it, effectively suppressing damage to the circuit 41. This configuration will be described in detail below.

[0042] As shown in Figure 5, in the integrated circuit device 4 of this embodiment, when the width of the pad 42 is W1 and the width of the metal bump 9 is W2, the relationship W1 / W2 ≥ 1.08 is satisfied. By satisfying this relationship, the force applied directly beneath the pad 42 during flip-chip mounting can be reduced, and damage to the circuit 41 that overlaps with the pad 42 can be effectively suppressed. With this configuration, there is no need to place a dummy pattern as in the conventional method, nor is there a need to place the circuit 41 while avoiding the area directly beneath the pad 42. Therefore, the space within the integrated circuit device 4 can be used efficiently to arrange the circuit 41, thus enabling miniaturization of the integrated circuit device 4. The effects of this will be explained below using the graph in Figure 6.

[0043] The graph in Figure 6 shows the relationship between W1 / W2 and the stress ratio when a flip-chip is mounted under a constant stress. This figure was obtained through experimentation. The stress ratio refers to the ratio of the stress value applied directly below the pad 42 to the reference value in a configuration where a crack occurred in the circuit 41 (W1 / W2 = 1.06). Therefore, if the stress ratio exceeds 1.0, there is a possibility that a crack will occur in the circuit 41 and it will break, and if it falls below 1.0, there is a high probability that a crack will not occur in the circuit 41 and it will not break. Thus, from the graph, it can be seen that when W1 / W2 ≥ 1.08, the stress ratio is 1.0 or less, and there is a high probability that a crack will not occur in the circuit 41 and it will not break. In other words, as mentioned above, by setting W1 / W2 ≥ 1.08, the failure of the circuit 41 can be effectively suppressed.

[0044] Furthermore, it is sufficient if at least one of the pads 42 that overlap the metal bump 9 and the circuit 41 satisfies the above relationship, but it is preferable that all pads 42 satisfy the above relationship. This makes the above-mentioned effect more pronounced. In addition, although there are multiple pads 42 that overlap the metal bump 9 and the circuit 41, it is not limited to this, and there may be just one.

[0045] Here, width W2 is the maximum width of the metal bump 9 in plan view. That is, as shown in Figure 7, if the metal bump 9 is circular, it is its diameter, and as shown in Figure 8, if the metal bump 9 is elliptical, it is the length of its major axis. Also, width W1 means the width of the pad 42 on the extension of width W2. That is, as shown in Figure 7, if the metal bump 9 is circular, it means the width on any straight line L passing through the center of the metal bump 9. In this case, there are infinitely many straight lines L, but it is sufficient that the above relationship is satisfied for the width on at least one straight line L. Also, as shown in Figure 8, if the metal bump 9 is elliptical, it means the width on the straight line L that coincides with the major axis.

[0046] While there are no particular limitations as long as W1 / W2 ≥ 1.08, it is preferable that W1 / W2 ≥ 1.14, more preferably that W1 / W2 ≥ 1.20, and even more preferably that W1 / W2 ≥ 1.25. By satisfying this relationship, the stress applied directly beneath the pad 42 during flip-chip mounting is further reduced, and damage to the circuit 41 can be more effectively suppressed.

[0047] Furthermore, since the decrease in the stress ratio slows down (saturates) around W1 / W2 ≤ 1.8, the upper limit of W1 / W2 is preferably, for example, W1 / W2 ≤ 2.4, and more preferably W1 / W2 ≤ 1.8. This prevents excessive enlargement of the pad 42 or excessive miniaturization of the metal bump 9. If the pad 42 becomes excessively large, the wiring efficiency of the integrated circuit device 4 decreases, increasing the risk of the integrated circuit device 4 becoming larger. On the other hand, if the metal bump 9 becomes excessively small, the mechanical strength and bonding strength of the metal bump 9 decrease, increasing the risk of reduced reliability of the vibration device 1. Therefore, by setting W1 / W2 ≤ 2.4, the decrease in wiring efficiency of the integrated circuit device 4 and the decrease in mechanical strength of the metal bump 9 can be suppressed, resulting in a compact and reliable integrated circuit device 4.

[0048] The graph in Figure 6 shows the results obtained from experiments and simulations using a metal bump 9 with a width W2 of 85 μm. However, the width W2 is not particularly limited and can be, for example, between 50 μm and 120 μm. It has been confirmed that the same trend as in Figure 6 is observed in this range as well.

[0049] The configuration of the integrated circuit device 4 has been briefly described above, but the configuration and arrangement of the circuit 41 and the configuration and arrangement of the pads 42 are not particularly limited.

[0050] The vibration device 1 has been described above. As previously mentioned, the vibration device 1 includes an oscillator 3, an integrated circuit device 4 that causes the oscillator 3 to oscillate and generates an oscillation signal, a package 2 which is a container housing the oscillator 3 and the integrated circuit device 4, and a metal bump 9 which is joined to the integrated circuit device 4 and electrically connects the integrated circuit device 4 and the package 2. The integrated circuit device 4 also includes a pad 42 which is joined to the metal bump 9, and a circuit 41 which is positioned to overlap with the metal bump 9 in a plan view of the pad 42. When the width of the pad 42 is W1 and the width of the metal bump 9 is W2, W1 / W2 ≥ 1.08.

[0051] This configuration reduces the force applied directly beneath the pad 42 when mounting the integrated circuit device 4 onto the package 2. As a result, it becomes unnecessary to place a dummy pattern as in the conventional method, and it is also unnecessary to place the circuit 41 while avoiding the area directly beneath the pad 42. Consequently, the space within the integrated circuit device 4 can be used efficiently to arrange the circuit 41, allowing for miniaturization of the integrated circuit device 4. As a result, the vibration device 1 can be miniaturized.

[0052] Furthermore, as mentioned above, it is preferable that W1 / W2 ≥ 1.14. This makes it possible to further reduce the force applied directly beneath the pad 42 when mounting the integrated circuit device 4 onto the package 2.

[0053] Furthermore, as mentioned above, it is preferable that W1 / W2 ≥ 1.20. This makes it possible to further reduce the force applied directly beneath the pad 42 when mounting the integrated circuit device 4 onto the package 2.

[0054] Furthermore, as mentioned above, it is preferable that W1 / W2 ≥ 1.25. This makes it possible to further reduce the force applied directly beneath the pad 42 when mounting the integrated circuit device 4 onto the package 2.

[0055] Furthermore, as mentioned above, it is preferable that W1 / W2 ≤ 2.40. This prevents excessive enlargement of the pad 42 or excessive miniaturization of the metal bump 9. Therefore, a decrease in the wiring efficiency of the integrated circuit device 4 and a decrease in the mechanical strength of the metal bump 9 can be suppressed, resulting in a compact and reliable integrated circuit device 4.

[0056] Furthermore, as mentioned above, the integrated circuit device 4 is flip-chip mounted on the package 2 via metal bumps 9. This allows for space saving and miniaturization of the vibration device 1.

[0057] Furthermore, as mentioned above, the circuit is a circuit 41 that includes an active element. This allows for even greater space savings.

[0058] <Second Embodiment> Figure 9 is a cross-sectional view of the vibration device according to the second embodiment.

[0059] The vibration device 1 according to this embodiment is the same as the vibration device 1 of the first embodiment described above, except that the method of electrically connecting the integrated circuit device 4 and the package is different. In the following description, the differences between the vibration device 1 of this embodiment and the first embodiment described above will be the focus, and similar matters will not be described. Also, in the figures of this embodiment, the same reference numerals are used for components that are the same as in the previously described embodiment.

[0060] In the vibration device 1 of this embodiment, the integrated circuit device 4 and the package 2 are electrically connected by wire bonding, particularly ball bonding. When performing wire bonding, the pad 42 is used as the first bond, and metal bumps 81 are formed on the pad 42. The metal bumps 81 are also called balls. The configuration will be described in detail below.

[0061] First, in this embodiment, as shown in Figure 9, the recess 211 of the base 21 has a first recess 211a that opens to the upper surface of the base 21, a second recess 211b that opens to the bottom surface of the first recess 211a and has a smaller opening than the first recess 211a, and a third recess 211c that opens to the bottom surface of the second recess 211b and has a smaller opening than the second recess 211b. The vibrator 3 is fixed to the bottom surface of the first recess 211a, and the integrated circuit device 4 is fixed to the bottom surface of the third recess 211c.

[0062] Furthermore, the integrated circuit device 4 is fixed to the bottom surface of the third recess 211c in an inverted position from the first embodiment described above, that is, with the active surface 40 facing upwards. The integrated circuit device 4 is also fixed to the bottom surface of the third recess 211c via a bonding member B3. The bonding member B3 is not particularly limited, and various adhesives such as polyimide-based, epoxy-based, silicone-based, and acrylic-based adhesives can be used.

[0063] Furthermore, a pair of connection terminals T1 are arranged on the bottom surface of the first recess 211a, a plurality of internal terminals T2 are arranged on the bottom surface of the second recess 211b, and a plurality of external terminals T3 are arranged on the lower surface of the base 21. The plurality of internal terminals T2 include those that are electrically connected to the connection terminals T1 via wiring (not shown) formed in the base 21, and those that are electrically connected to the external terminals T3 via wiring (not shown) formed in the base 21. The pair of connection terminals T1 are each electrically connected to the vibrator 3 via conductive bonding members B1 and B2, and the plurality of internal terminals T2 are each electrically connected to the integrated circuit device 4 via bonding wires 8.

[0064] Furthermore, the bonding wire 8 has a metal bump 81 joined to the pad 42, and a wire 82 extending from the metal bump 81, with its base end joined to the internal terminal T2. With such a bonding wire 8, the integrated circuit device 4 and the package 2 can be easily electrically connected.

[0065] As described above, in the vibration device 1 of this embodiment, the integrated circuit device 4 is electrically connected to the package 2 via bonding wires 8, which include metal bumps 81 and wires 82 extending from the metal bumps 81. This allows for easy electrical connection between the integrated circuit device 4 and the package 2.

[0066] This second embodiment can also achieve the same effects as the first embodiment described above.

[0067] <Third Embodiment> Figure 10 is a plan view showing the arrangement of each part included in the integrated circuit of the vibration device according to the third embodiment.

[0068] The vibration device 1 according to this embodiment is the same as the vibration device 1 of the first embodiment described above, except that the configuration of the integrated circuit device 4 is different. In the following description, the differences between the vibration device 1 of this embodiment and the first embodiment described above will be the focus, and similar matters will not be described. Also, in the figures of this embodiment, the same reference numerals are used for components that are the same as in the previously described embodiment.

[0069] As shown in Figure 10, the integrated circuit device 4 of this embodiment is equipped with an electrostatic discharge (ESD) protection circuit 43 that protects the circuit 41 from abnormal voltages such as static electricity. This ESD protection circuit 43 is positioned overlapping with the pad 42. The ESD protection circuit 43 will be described below.

[0070] The electrostatic discharge protection circuit 43 includes a first electrostatic discharge protection circuit 431, a second electrostatic discharge protection circuit 432, a third electrostatic discharge protection circuit 433, a fourth electrostatic discharge protection circuit 434, a fifth electrostatic discharge protection circuit 435, and a sixth electrostatic discharge protection circuit 436.

[0071] Furthermore, the first electrostatic discharge protection circuit 431 is electrically connected to the power supply pad PVDD and, in a plan view, is positioned to overlap with the metal bump 9 on the power supply pad PVDD. The first electrostatic discharge protection circuit 431 absorbs charges caused by large external noises such as static electricity applied to the power supply pad PVDD, and protects the circuit block electrically connected to the power supply pad PVDD from external noise.

[0072] Furthermore, the second electrostatic discharge protection circuit 432 is electrically connected to the ground pad PGND and, in a plan view, is positioned to overlap with the metal bump 9 on the ground pad PGND. The second electrostatic discharge protection circuit 432 absorbs charges caused by large external noises such as static electricity applied to the ground pad PGND, and protects the circuit block electrically connected to the ground pad PGND from external noise.

[0073] Furthermore, the third electrostatic protection circuit 433 is electrically connected to the transducer connection pad PX1 and, in a plan view, is positioned to overlap with the metal bump 9 on the transducer connection pad PX1. The third electrostatic protection circuit 433 absorbs charges caused by large external noises such as static electricity applied to the transducer connection pad PX1, and protects the circuit block electrically connected to the transducer connection pad PX1 from external noise.

[0074] Furthermore, the fourth electrostatic protection circuit 434 is electrically connected to the transducer connection pad PX2 and, in a plan view, is positioned to overlap with the metal bump 9 on the transducer connection pad PX2. The fourth electrostatic protection circuit 434 absorbs charges caused by large external noises such as static electricity applied to the transducer connection pad PX2, and protects the circuit block electrically connected to the transducer connection pad PX2 from external noise.

[0075] Furthermore, the fifth electrostatic protection circuit 435 is electrically connected to the clock pad PCK and, in a plan view, is positioned to overlap with the metal bump 9 on the clock pad PCK. The fifth electrostatic protection circuit 435 absorbs charges caused by large external noises such as static electricity applied to the clock pad PCK, and protects the circuit block electrically connected to the clock pad PCK from external noise.

[0076] Furthermore, the sixth electrostatic protection circuit 436 is electrically connected to the enable pad POE and, in a plan view, is positioned to overlap with the metal bump 9 on the enable pad POE. The sixth electrostatic protection circuit 436 absorbs charges caused by large external noises such as static electricity applied to the enable pad POE, and protects the circuit block electrically connected to the enable pad POE from external noise.

[0077] These first electrostatic discharge protection circuits 431, second electrostatic discharge protection circuits 432, third electrostatic discharge protection circuits 433, fourth electrostatic discharge protection circuits 434, fifth electrostatic discharge protection circuits 435, and sixth electrostatic discharge protection circuits 436 are not particularly limited, but for example, they can be circuits using TVS diodes (ESD protection diodes).

[0078] However, the electrostatic discharge protection circuit 43 is not particularly limited, and for example, at least one of the first electrostatic discharge protection circuit 431, the second electrostatic discharge protection circuit 432, the third electrostatic discharge protection circuit 433, the fourth electrostatic discharge protection circuit 434, the fifth electrostatic discharge protection circuit 435, and the sixth electrostatic discharge protection circuit 436 may be omitted.

[0079] Thus, in this embodiment, the electrostatic discharge protection circuit 43 is positioned overlapping with the pad 42. Therefore, the force applied to the electrostatic discharge protection circuit 43 when the integrated circuit device 4 is flip-chip mounted can be reduced. As a result, damage to the electrostatic discharge protection circuit 43 can be effectively suppressed.

[0080] As described above, in the vibration device 1 of this embodiment, the circuit positioned in a location overlapping with the metal bump 9 is an electrostatic discharge protection circuit 43. This effectively suppresses damage to the electrostatic discharge protection circuit 43.

[0081] Although the vibration device of the present invention has been described above based on the illustrated embodiments, the present invention is not limited thereto, and the configuration of each part can be replaced with any configuration having a similar function. Furthermore, other arbitrary components may be added to the present invention. Moreover, the present invention may be a combination of any two or more configurations from the above embodiments. [Explanation of Symbols]

[0082] 1…Vibration device, 2…Package, 21…Base, 211…Recess, 211a…First recess, 211b…Second recess, 211c…Third recess, 22…Lid, 3…Oscillator, 31…Vibration substrate, 32…Electrode, 321…First excitation electrode, 322…Second excitation electrode, 323…First pad, 324…Second pad, 325…First lead wiring, 326…Second lead wiring, 4…Integrated circuit device, 40…Active surface, 41…Circuit, 410…Oscillator circuit, 411…Output band 412…Fafer circuit, 412…Power supply circuit, 412a…Reference voltage generation circuit, 412b…Regulator, 413…PLL circuit, 414…Logic circuit, 415…Non-volatile memory, 416…Temperature compensation circuit, 417…Temperature sensor circuit, 418…Test circuit, 419…Interface circuit, 42…Pad, 43…Electrostatic discharge protection circuit, 431…First electrostatic discharge protection circuit, 432…Second electrostatic discharge protection circuit, 433…Third electrostatic discharge protection circuit, 434… 4th electrostatic protection circuit, 435... 5th electrostatic protection circuit, 436... 6th electrostatic protection circuit, 8... Bonding wire, 81... Metal bump, 82... Wire, 9... Metal bump, ALA... Metal layer, ALB... Metal layer, ALC... Metal layer, ALD... Metal layer, ALE... Metal layer, B1... Bonding member, B2... Bonding member, B3... Bonding member, CK... Clock signal, CKQ... Clock signal, L... Linear, NWL... Well, OSC... Oscillation signal, PCK... Clock PGND…Ground pad, PL…Passivation film, POE…Enable pad, PSUB…Board, PVDD…Power pad, PWL…Well, PX1…Transducer connection pad, PX2…Transducer connection pad, S…Storage space, SD1…Side, SD2…Side, SD3…Side, SD4…Side, T1…Connection terminal, T2…Internal terminal, T3…External terminal, VCP…Temperature compensation voltage, VDD…Power supply voltage, VT…Temperature detection voltage, W1…Width, W2…Width

Claims

[Claim 1] The oscillator and An integrated circuit device that causes the oscillator to oscillate and generates an oscillation signal, A container for housing the vibrator and the integrated circuit device, It has a metal bump that is bonded to the integrated circuit device and electrically connects the integrated circuit device and the container, The integrated circuit device comprises a pad joined to the metal bump, and a circuit positioned in a location overlapping the metal bump in a plan view of the pad. The integrated circuit device is flip-chip mounted in the container via the metal bumps, The circuit is positioned in a location that overlaps with the pad in the plan view. The pad includes a ground pad, an oscillator connection pad, a clock pad, and an enable pad. The circuit includes a reference voltage generation circuit that overlaps the ground pad in the plan view, an oscillator circuit that overlaps the oscillator connection pad in the plan view, an output buffer circuit that overlaps the clock pad in the plan view, and a temperature sensor circuit that overlaps the enable pad in the plan view. When the width of each pad is W1 and the width of each metal bump corresponding to each pad is W2, then 2.40 ≥ W1 / W2 ≥ 1.08, The width of the metal bump is the maximum width of the metal bump in the plan view, The vibration device is characterized in that the width of the pad is the width along the extension of the straight line that defines the maximum width.

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