Semiconductor optical element and method for manufacturing the same

Abstract

To provide a semiconductor optical element with which it is possible to suppress power consumption and control the wavelength of light, and a method for manufacturing the semiconductor optical element.SOLUTION: Provided is a semiconductor optical element comprising a board having an optical waveguide and a recess, a gain unit that is joined to the top of the optical waveguide on the top face of the board and that has an optical gain, and an electrode. The board has a silicon layer, the silicon layer having the optical waveguide and the recess, the recess adjoining the optical waveguide. A first region of the silicon layer is provided at the bottom of the recess and has a higher dopant concentration than that of the optical waveguide, and the electrode is electrically connected to the first region.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor optical element and a method for manufacturing the same. [Background technology]

[0002] A technique for forming a metal heater on a substrate such as an SOI (Silicon On Insulator) substrate (silicon photonics) is known (for example, Non-Patent Documents 1 and 2). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Jan Spannhake et al. “High-temperature MEMS Heater Platforms:Long-term Performance of Metal and Semiconductor Heater Materials” Sensors,6,405-419,April,2006 [Non-Patent Document 2] Adil Masood et al. “Fabrication and characterization of CMOS-compatible integrated tungsten heaters for thermo-optic tuning in silicon photonics devices” OPTICAL MATERIALS EXPRESS,Vol.4,No.7,July,2014 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] A semiconductor optical element can be formed by providing an optical waveguide on an SOI substrate and bonding an element having optical gain to the SOI substrate. By passing an electric current through a heater, the heater generates heat, which heats the optical waveguide provided on the substrate. The refractive index of the optical waveguide can be changed, thereby changing the wavelength of light. To suppress light absorption by a metal heater, the heater is moved away from the optical waveguide. However, this makes it difficult to transfer heat from the heater to the optical waveguide, increasing the heater's power consumption. Therefore, the objective is to provide a semiconductor optical element and a method for manufacturing the same that can suppress power consumption and control the wavelength of light. [Means for solving the problem]

[0005] The semiconductor optical element according to this disclosure comprises a substrate having an optical waveguide and a recess, a gain portion having optical gain and bonded to the upper surface of the substrate on the optical waveguide, and an electrode, wherein the substrate has a silicon layer, the silicon layer has the optical waveguide and the recess, the recess is adjacent to the optical waveguide, a first region of the silicon layer is provided on the bottom surface of the recess and has a higher dopant concentration than the optical waveguide, and the electrode is electrically connected to the first region.

[0006] A method for manufacturing a semiconductor optical element according to this disclosure comprises the steps of: forming a first region on the bottom surface of a recess in a substrate having an optical waveguide and a recess adjacent to the optical waveguide; joining a gain portion having optical gain to the upper surface of the substrate, which is on the optical waveguide; and forming an electrode connected to the first region, wherein the substrate has a silicon layer, the silicon layer has the optical waveguide and the recess, and the step of forming the first region is a step of forming the first region having a dopant concentration higher than that of the optical waveguide by doping the bottom surface of the recess in the silicon layer. [Effects of the Invention]

[0007] According to this disclosure, it is possible to suppress power consumption and control the wavelength of light. [Brief explanation of the drawing]

[0008] [Figure 1] FIG. 1 is a plan view illustrating the semiconductor optical device according to the first embodiment. [Figure 2A] FIG. 2A is an enlarged plan view of a substrate. [Figure 2B] FIG. 2B is a cross-sectional view taken along line A-A in FIG. 2A. [Figure 2C] FIG. 2C is a cross-sectional view taken along line B-B in FIG. 2A. [Figure 3A] FIG. 3A is a diagram illustrating the relationship between doping concentration and electrical resistance. [Figure 3B] FIG. 3B is a diagram illustrating the relationship between voltage and calorific value. [Figure 4A] FIG. 4A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 4B] FIG. 4B is a cross-sectional view taken along line A-A in FIG. 4A. [Figure 4C] FIG. 4C is a cross-sectional view taken along line B-B in FIG. 4A. [Figure 5A] FIG. 5A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 5B] FIG. 5B is a cross-sectional view taken along line A-A in FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view taken along line B-B in FIG. 5A. [Figure 6A] FIG. 6A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 6B] FIG. 6B is a cross-sectional view taken along line A-A in FIG. 6A. [Figure 6C] FIG. 6C is a cross-sectional view taken along line B-B in FIG. 6A. [Figure 7A] FIG. 7A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 7B] FIG. 7B is a cross-sectional view taken along line A-A in FIG. 7A. [Figure 7C] FIG. 7C is a cross-sectional view taken along line B-B in FIG. 7A. [Figure 8A] FIG. 8A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 8B] Figure 8B is a cross-sectional view along line AA in Figure 8A. [Figure 8C] Figure 8C is a cross-sectional view along line BB in Figure 8A. [Figure 9A] Figure 9A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 9B] Figure 9B is a cross-sectional view along line AA in Figure 9A. [Figure 9C] Figure 9C is a cross-sectional view along line BB in Figure 9A. [Figure 10A] Figure 10A is a plan view illustrating a semiconductor optical element according to the second embodiment. [Figure 10B] Figure 10B is a cross-sectional view along line CC in Figure 10A. [Figure 11A] Figure 11A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 11B] Figure 11B is a cross-sectional view along line CC in Figure 11A. [Figure 12A] Figure 12A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 12B] Figure 12B is a cross-sectional view along line CC in Figure 12A. [Figure 13A] Figure 13A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 13B] Figure 13B is a cross-sectional view along line CC in Figure 13A. [Figure 14A] Figure 14A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 14B] Figure 14B is a cross-sectional view along line CC in Figure 14A. [Figure 15A] Figure 15A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 15B] Figure 15B is a cross-sectional view along line CC in Figure 15A. [Figure 16A] Figure 16A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 16B] Figure 16B is a cross-sectional view along line CC in Figure 16A. [Modes for carrying out the invention]

[0009] [Description of Embodiments in this Disclosure] First, the contents of the embodiments of this disclosure will be listed and explained.

[0010] One embodiment of the present disclosure is a semiconductor optical element comprising (1) a substrate having an optical waveguide and a recess, a gain portion having optical gain and bonded to the upper surface of the substrate on the optical waveguide, and an electrode, wherein the substrate has a silicon layer, the silicon layer has the optical waveguide and the recess, the recess is adjacent to the optical waveguide, a first region of the silicon layer is provided on the bottom surface of the recess and has a higher dopant concentration than the optical waveguide, and the electrode is electrically connected to the first region. By passing an electric current through the first region using the electrode, the first region generates heat. The heat generated in the first region is transferred to the optical waveguide, causing a change in the temperature of the optical waveguide and a change in its refractive index. The wavelength of light can be controlled by the change in refractive index. Because the silicon layer has high thermal conductivity, heat is easily transferred from the first region to the optical waveguide. Since it is not necessary to heat the first region to a high temperature, power consumption can be suppressed. (2) In the above (1), an insulating film may be provided on the silicon layer and covering the optical waveguide and the recess. By providing an insulating film, light can be strongly confined in the optical waveguide. The thermal conductivity of the silicon layer is higher than that of the insulating film. Heat generated in the first region is easily transferred to the optical waveguide. Wavelength can be controlled and power consumption can be suppressed. (3) In (1) or (2) above, the recesses may be provided on both sides of the optical waveguide, and the first region may be provided in each of the recesses on both sides of the optical waveguide. Since heat is transferred to the optical waveguide from both sides, the temperature can be changed effectively. (4) In any of (1) to (3) above, the doping concentration in the first region is 2 × 10 20 cm -3 The above is 1 x 10 22 cm -3The following is also acceptable: The electrical resistance of the first region can be set to an appropriate value. Setting the electrical resistance of the first region to an appropriate value makes it easier for current to flow through the first region. When current flows, the first region generates heat. (5) In any of (1) to (4) above, the electrical resistance of the first region may be 1000Ω or less. Setting the electrical resistance of the first region to an appropriate value makes it easier for current to flow through the first region. When current flows, the first region generates heat. (6) In any of (1) to (5) above, the distance between the optical waveguide and the first region may be 100 nm or more. This can suppress the absorption of light by carriers in the first region. (7) In any of (1) to (6) above, the optical waveguide may form a ring resonator, and the first region may be provided in the portion of the recess adjacent to the ring resonator. The wavelength of light can be controlled by changing the temperature of the ring resonator. (8) In any of (1) to (7) above, a diffraction grating may be provided in the portion of the optical waveguide to which the gain portion is joined, and the first region may be provided in the portion of the recess that is aligned with the diffraction grating. The wavelength of light can be controlled by changing the temperature of the diffraction grating. (9) In any of (1) to (8) above, the first region may have a connection portion, the connection portion may be located opposite to the optical waveguide, and the electrode may be connected to the connection portion. This can suppress the absorption of light by the electrode. (10) A method for manufacturing a semiconductor optical element, comprising the steps of: forming a first region on the bottom surface of the recess in a substrate having an optical waveguide and a recess adjacent to the optical waveguide; joining a gain portion having optical gain to the top surface of the substrate, which is on the optical waveguide; and forming an electrode connected to the first region, wherein the substrate has a silicon layer, the silicon layer has the optical waveguide and the recess, and the step of forming the first region is to dope the bottom surface of the recess in the silicon layer to form the first region having a dopant concentration higher than that of the optical waveguide. By passing an electric current through the first region using the electrode, the first region generates heat. The heat generated in the first region is transferred to the optical waveguide, causing a change in the temperature of the optical waveguide and a change in its refractive index. The wavelength of light can be controlled by the change in refractive index. Because the silicon layer has high thermal conductivity, heat is easily transferred from the first region to the optical waveguide. Since it is not necessary to heat the first region to a high temperature, power consumption can be suppressed.

[0011] [Details of the embodiments of this disclosure] Specific examples of semiconductor optical elements and methods for manufacturing the same according to embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to these examples and is intended to include all modifications within the meaning and scope of the claims as indicated by the claims.

[0012] <First Embodiment> Figure 1 is a plan view illustrating a semiconductor optical element 100 according to the first embodiment. As shown in Figure 1, the semiconductor optical element 100 is a hybrid type tunable laser element having a substrate 10 and a gain unit 30. The substrate 10 is, for example, an SOI (Silicon on Insulator) substrate. The gain unit 30 is a light-emitting element having optical gain.

[0013] As shown in Figure 1, two sides of the substrate 10 are parallel to the X-axis. Two other sides of the substrate 10 are parallel to the Y-axis. The X-axis, Y-axis, and Z-axis directions are orthogonal to each other. The top surface of the substrate 10 is parallel to the XY plane. The top surface of the substrate 10 is covered with a cladding layer 32 (insulating film), but in Figure 1, the cladding layer 32 is shown transparently.

[0014] The substrate 10 has an optical waveguide 20 on its upper surface. The optical waveguide 20 has loop mirrors 22 and 24 and ring resonators 26 and 28. The optical waveguide 20 is curved to form the loop mirrors 22 and 24. The optical waveguide 20 becomes ring-shaped to form the ring resonators 26 and 28. From one end 10a of the substrate 10 toward the opposite end 10b, the loop mirror 22, ring resonator 26, ring resonator 28, and loop mirror 24 are arranged in this order. One end 20a of the optical waveguide 20 is located at the end 10b of the substrate 10 and functions as a light emission port.

[0015] The portion of the optical waveguide 20 between the ring resonators 26 and 28 is defined as portion 23. Portion 23 extends linearly along the X-axis, and a gain section 30 is joined to this portion. The gain section 30 has tapered sections 31 at both ends in the X-axis direction. The optical waveguide 20 has tapered sections 21 in the portion that overlaps with the tapered sections 31 of the gain section 30. The tapered sections 21 and 31 become thinner as they move away from the gain section 30.

[0016] The gain section 30 is formed of, for example, a III-V compound semiconductor. The gain section 30 has an n-type cladding layer, an active layer, and a p-type cladding layer. The n-type cladding layer is formed of, for example, n-type indium phosphide (n-InP). The p-type cladding layer is formed of, for example, p-type indium phosphide (p-InP). The active layer has a multi-quantum well (MQW) structure and includes multiple well layers and a barrier layer. The well layers and barrier layer are formed of, for example, undoped gallium indium arsenide (i-GaInAs). An n-type electrode 34 is connected to the n-type cladding layer. A p-type electrode 36 is connected to the p-type cladding layer. Electrode 34 is formed of a metal such as an alloy of gold, germanium, and Ni (AuGeNi). Electrode 36 is formed of a metal such as a laminate of titanium, platinum, and gold (Ti / Pt / Au). Electrodes 34 and 36 may have an Au wiring layer.

[0017] Regions 40 (first region) are provided near the ring resonator 26, near the ring resonator 28, and near portion 23 of the optical waveguide 20. Regions 40 function as heaters and are shown as shaded areas in Figure 1.

[0018] Figure 2A is an enlarged plan view of the substrate 10. In Figure 2A, the cladding layer 32 is seen through. Figure 2B is a cross-sectional view along line AA in Figure 2A. Figure 2C is a cross-sectional view along line BB in Figure 2A. As shown in Figures 2B and 2C, the substrate 10 has a substrate 12, a box layer 14, and a silicon (Si) layer 16. The substrate 12, the box layer 14, and the Si layer 16 are stacked in this order in the Z-axis direction. The substrate 12 and the Si layer 16 are made of Si. The box layer 14 and the cladding layer 32 are made of, for example, silicon oxide (SiO2). The thickness of the box layer 14 is, for example, 2 μm. The thickness of the Si layer 16 is, for example, 220 nm. The top surface of the Si layer 16 is covered by the cladding layer 32. The thickness of the cladding layer 32 is, for example, 1.2 μm.

[0019] As shown in Figures 2A to 2C, the Si layer 16 has an optical waveguide 20, a recess 25, and a terrace 27. The recess 25 is adjacent to the optical waveguide 20 and is provided on both sides of the optical waveguide 20. The terrace 27 is located outside the recess 25. That is, the optical waveguide 20 is located between the recess 25. The optical waveguide 20 and the recess 25 are located between the two terraces 27. A cladding layer 32 is embedded in the recess 25. The top and sides of the optical waveguide 20 are covered with the cladding layer 32. Although not shown, the portion of the recess 25 below the gain section 30 is not filled with the cladding layer 32 and is a cavity.

[0020] The upper surface of the optical waveguide 20, the bottom surface of the recess 25, and the upper surface of the terrace 27 are formed of Si layer 16. The upper surface of the optical waveguide 20 and the upper surface of the terrace 27 are located at the same height in the Z-axis direction. The bottom surface of the recess 25 is recessed lower than the upper surface of the optical waveguide 20 and the upper surface of the terrace 27. The distance from the bottom surface of the recess 25 to the upper surfaces of the optical waveguide 20 and the terrace 27 (depth D1 of the recess 25) is, for example, 190 nm. The width W1 of the recess 25 is, for example, 5 μm. The width W2 of the optical waveguide 20 is, for example, 500 nm.

[0021] A region 40 is provided on the bottom surface of each of the two recesses 25. The optical waveguide 20 is sandwiched between the two regions 40. Region 40 has a higher doping concentration than the optical waveguide 20 of the Si layer 16. The dopants are, for example, boron (B) and phosphorus (P).

[0022] As shown in Figure 2A, region 40 extends in the same direction as the optical waveguide 20. The length L1 of region 40 in the X-axis direction is, for example, 100 μm. Region 40 is spaced apart from the optical waveguide 20 and the terrace 27. The distance L2 between region 40 and the optical waveguide 20 is, for example, 100 nm. The width W3 of region 40 is, for example, 2 μm. The thickness T1 of region 40 is, for example, 30 nm.

[0023] Region 40 extends away from the optical waveguide 20 and has a connection portion 42 at its extended end. An electrode 44 is electrically connected to each of the two connection portions 42. The electrode 44 is in contact with the connection portion 42 of region 40 and is connected to a pad 45. The pad 45 is provided on the upper surface of the terrace 27. As shown in Figure 2B, the electrode 44 and the pad 45 are exposed from the cladding layer 32. The electrode 44 is made of a metal such as silver (Ag), aluminum (Al), nickel (Ni), or titanium (Ti). The cladding layer 32 covers the upper and side surfaces of the optical waveguide 20. The cladding layer 32 may cover the entire surface of the semiconductor optical element 100 except for the metal portion.

[0024] Figures 2A and 2C illustrate the vicinity of portion 23 of the optical waveguide 20. Regions 40, electrodes 44, and pads 45 are also provided near the ring resonators 26 and 28.

[0025] By applying voltage to electrodes 34 and 36, a current is passed through the gain section 30. When a current passes through the gain section 30, carriers are injected into the active layer of the gain section 30. Due to the injection of carriers, the gain section 30 emits light. The gain section 30 and the optical waveguide 20 of the substrate 10 are evanescently photocoupled. Because tapered sections 21 and 31 are provided, light reflection is suppressed, and light transitions from the gain section 30 to the optical waveguide 20 and propagates through the optical waveguide 20. The optical waveguide 20 is covered with a cladding layer 32. The Si optical waveguide 20 has a higher refractive index than the SiO2 cladding layer 32. Because light can be strongly confined in the optical waveguide 20, light loss is suppressed.

[0026] The wavelength of the light is selected by ring resonators 26 and 28. The light is repeatedly reflected by two loop mirrors 22 and 24, causing laser oscillation. A portion of the light passes through loop mirror 24 and is emitted out of end 20a toward the outside of the semiconductor optical element 100.

[0027] To change the wavelength of light, a voltage is applied to region 40 using the pad 45 and electrode 44 shown in Figure 2A. Region 40 has a higher doping concentration than the rest of the Si layer 16, and therefore has lower electrical resistance. When a voltage is applied, a current flows through region 40. When a current flows, Joule heat is generated in region 40. The heat is transferred from region 40 to the optical waveguide 20, changing the temperature of the optical waveguide 20. The refractive index of the optical waveguide 20 changes due to the temperature change. In the semiconductor optical element 100 shown in Figure 1, the refractive index of portion 23 of the optical waveguide 20 and the refractive indices of the ring resonators 26 and 28 can be changed. The optical path length also changes due to the change in refractive index. This allows the oscillation wavelength of light to be adjusted.

[0028] Figure 3A illustrates the relationship between doping concentration and electrical resistance. Region 40 is assumed to be a rectangular parallelepiped. The electrical resistance is calculated assuming a length L1 of 100 μm, a thickness T1 of 30 nm, and a width W3 of 2 μm. The horizontal axis of Figure 3A represents the doping concentration in region 40. The vertical axis represents the electrical resistance of region 40. As shown in Figure 3A, the electrical resistance of region 40 decreases as the doping concentration increases. (Doping concentration of 2 × 10⁻¹⁰) 20 cm -3 In the above cases, the electrical resistance will be 1000Ω or less. Doping concentration is 8 × 10 20 cm -3 In this case, the electrical resistance will be approximately 300Ω.

[0029] Figure 3B illustrates the relationship between voltage and heat generation. The horizontal axis represents the voltage applied to region 40. The vertical axis represents the heat generation in region 40. The shape and size of region 40 are the same as those used in the simulation in Figure 3A. In the solid line example in Figure 3B, the electrical resistance of region 40 is 300Ω. In the dotted line example, the electrical resistance is 500Ω. In the dashed line example, the electrical resistance is 1000Ω. At the same voltage, the lower the electrical resistance, the greater the current flowing through region 40 and the greater the heat generation. Increasing the voltage increases the heat generation. The heat generation is proportional to the square of the voltage.

[0030] (Manufacturing method) Figures 4A to 9C illustrate the manufacturing method of the semiconductor optical element 100, and are plan views and cross-sectional views corresponding to Figures 2A to 2C. The gain unit 30 shown in Figure 1 is manufactured from a wafer separate from the substrate 10.

[0031] As shown in Figures 4A to 4C, recesses 25 are formed in the Si layer 16 of the substrate 10 by, for example, dry etching. Dry etching proceeds partway through the Si layer 16, forming the bottom surface of the recess 25 (the surface of the Si layer 16). The portion of the Si layer 16 that is not dry-etched becomes the optical waveguide 20 and the terrace 27.

[0032] As shown in Figures 5A to 5C, a resist 50 is formed on the upper surface of the Si layer 16. Resist patterning is performed to form an opening 50a in the resist 50. The opening 50a is located above the recess 25 and penetrates the resist 50. The bottom surface of the recess 25 is exposed through the opening 50a.

[0033] As shown in Figures 6A to 6C, a region 40 is formed by implanting ions into the bottom surface of the recess 25. The ions are boron (B) ions and phosphorus (P) ions, etc. The depth to which the ions are implanted is, for example, 30 nm. Ions are implanted from the bottom surface of the recess 25 to the interface between the Si layer 16 and the box layer 14, forming region 40. Region 40 has a higher doping concentration and lower electrical resistance compared to the parts of the Si layer 16 other than region 40. Ions are not implanted in the parts of the Si layer 16 covered with resist 50. In other words, region 40 is a doped part. No intentional doping is performed on the parts of the Si layer 16 other than region 40. After ion implantation, the resist 50 is removed.

[0034] The surface of the Si layer 16 of the substrate 10 and the underside of the gain portion 30 are activated by plasma irradiation or the like. The gain portion 30 is brought into contact with the Si layer 16 and pressurized to bond the gain portion 30 shown in Figure 1 to the substrate 10. Mesas and tapered portions 31 are formed on the gain portion 30 by etching or the like.

[0035] As shown in Figures 7A and 7C, the cladding layer 32 is formed by, for example, plasma CVD (Chemical Vapor Deposition). The cladding layer 32 fills the inside of the recess 25 and covers the top and sides of the optical waveguide 20. As shown in Figure 7B, in the cross-section of region 40 including the connection portion 42, the cladding layer 32 covers the top and sides of the optical waveguide 20. In the cross-section of region 40 including the connection portion 42, the cladding layer 32 is not formed in the area from the middle of the recess 25 to the middle of the terrace 27. A part of region 40 (the connection portion 42) is exposed from the cladding layer 32. The cladding layer 32 is also not formed on the gain portion 30.

[0036] As shown in Figures 8A to 8C, a resist 52 is provided on the substrate 10 and the cladding layer 32. Resist patterning is performed to form an opening 52a in the resist 52. The opening 52a is located above the connecting portion 42 of region 40 and penetrates the resist 52. The connecting portion 42 of region 40 is exposed through the opening 52a.

[0037] As shown in Figures 9A and 9B, electrodes 44 are formed on the connection portion 42, for example, by vacuum deposition and lift-off. The resist 52 is removed. Pads 45 to be connected to the electrodes 44 are formed in the Si layer 16 (see Figures 2A and 2B). Electrodes connected to the gain portion 30 are also formed by vacuum deposition or the like. The semiconductor optical element 100 is formed through the above steps.

[0038] According to the first embodiment, the Si layer 16 of the substrate 10 has an optical waveguide 20 and a region 40. Region 40 is provided in the recess 25 and has a higher doping concentration than the optical waveguide 20. The electrical resistance of region 40 is lower than that of the optical waveguide 20. By passing current from electrode 44 to region 40, Joule heat is generated in region 40. In other words, region 40 functions as a heater. The heat generated in region 40 is transferred to the optical waveguide 20, causing a change in the temperature of the optical waveguide 20 and a change in its refractive index. The change in the refractive index of the optical waveguide 20 changes the phase of the light propagating through the optical waveguide 20, and thus changes the wavelength of the light. It is possible to control the wavelength of light and suppress power consumption.

[0039] As shown in FIG. 2C, the clad layer 32 is provided on the Si layer 16, and covers the optical waveguide 20 and the recess 25. The clad layer 32 is formed of, for example, SiO2 and has a lower refractive index than the Si layer 16. Providing the clad layer 32 can confine light in the optical waveguide 20 and suppress loss. On the other hand, the thermal conductivity of the clad layer 32 is lower than that of the Si layer 16. When a metal heater is provided on the clad layer 32, heat from the heater is less likely to be transferred to the optical waveguide 20. In order to change the temperature of the optical waveguide 20 using the heater on the clad layer 32, the heater needs to be heated to a high temperature. This increases the power consumption of the heater. There is also a risk that reliability in high-temperature environments may decrease.

[0040] According to the first embodiment, the region 40 of the Si layer 16 functions as a heater. The thermal conductivity of the Si layer 16 is approximately 100 times that of the clad layer 32. Heat is easily transferred from the region 40 to the optical waveguide 20. Therefore, power consumption can be suppressed. Because the Si layer 16 has high thermal conductivity, it is not necessary to heat the region 40 to a higher temperature compared to a metal heater. Reliability in high-temperature environments is improved.

[0041] As shown in FIG. 2A, the recesses 25 are provided on both sides of the optical waveguide 20, and the regions 40 are also provided on both sides of the optical waveguide 20. By providing the regions 40 on both sides of the optical waveguide 20, heat is efficiently transferred from the two regions 40. The temperature of the optical waveguide 20 can be changed efficiently. The region 40 may be provided on one of the left side and the right side of the optical waveguide 20, and may not be provided on the other. That is, the region 40 may be provided on at least one of the two sides of the optical waveguide 20.

[0042] As shown in FIGS. 6A to 6C, the region 40 can be formed by implanting ions into the Si layer 16, so the process for manufacturing the region 40 is simple.

[0043] The doping concentration of the region 40 is, for example, 2×10 20 cm -3 or more, and 1×10 22 cm -3The following is also acceptable. The electrical resistance of region 40 will be 1000Ω or less and several tens of ohms or more. Current flows through region 40, generating heat. To increase the amount of heat generated, the doping concentration in region 40 can be increased and the electrical resistance lowered. For example, the doping concentration in region 40 can be 8 × 10⁻⁶. 20 cm -3 The electrical resistance is set to 300Ω. By setting the electrical resistance to an appropriate value, current flows more easily into region 40. As current flows, region 40 generates heat.

[0044] As the distance L2 between the optical waveguide 20 and region 40 decreases, heat is more easily transferred from region 40 to the optical waveguide 20. The carrier density in region 40 is higher than in the parts of the Si layer 16 other than region 40. As the distance L2 decreases, light is more easily absorbed by the carriers in region 40. Increasing the distance L2 suppresses light absorption. When region 40 is doped with n-type ions, the electrical resistance of region 40 is 300Ω, and the distance L2 = 100nm, the light loss is 0.001dB / cm. Light loss can be kept low at L2 = 100nm. Light loss can be suppressed by setting the distance L2 to 100nm or more.

[0045] As shown in Figure 1, region 40 is located near portion 23 of the optical waveguide 20 and the ring resonators 26 and 28. The refractive index of portion 23 of the optical waveguide 20 changes. The refractive index of the ring resonators 26 and 28 changes. The wavelength of light can be adjusted. Region 40 may be located at a position other than those described above on the substrate 10.

[0046] Region 40 has a connection portion 42. The connection portion 42 is located opposite the optical waveguide 20, and an electrode 44 is connected to it. By passing current through the electrode 44 to region 40, region 40 generates heat. Since the connection portion 42 extends away from the optical waveguide 20, the electrode 44 is spaced apart from the optical waveguide 20. This suppresses light absorption by the metal electrode 44.

[0047] <Second Embodiment> Figure 10A is a plan view illustrating a semiconductor optical element 200 according to the second embodiment. Figure 10B is a cross-sectional view along line CC in Figure 10A. The same configuration as in the first embodiment will not be described.

[0048] As shown in Figures 10A and 10B, an optical waveguide 20 is provided on the substrate 10. The optical waveguide 20 is linear and extends in the X-axis direction from one end of the substrate 10 to the opposite end. The optical waveguide 20 has a diffraction grating 55 in the center in the X-axis direction. Periodically arranged irregularities on the upper surface of the Si layer 16 function as the diffraction grating 55. A gain section 30 is bonded to the diffraction grating 55. The semiconductor optical element 200 is a distributed feedback (DFB) laser element.

[0049] Recesses 25 are provided on both sides of the optical waveguide 20. Terraces 27 are provided outside the recesses 25. Regions 40 are provided on the bottom surfaces of the two recesses 25. Regions 40 are located on both sides of the gain section 30 and the diffraction grating 55. The cladding layer 32 is provided on the optical waveguide 20 and the recesses 25, but not on the gain section 30 or near the electrodes 44 and pads 45.

[0050] The gain section 30 has a cladding layer 60, an active layer 62, a cladding layer 64, and a contact layer 66. The cladding layer 60 is bonded to the upper surface of the Si layer 16 of the substrate 10. The active layer 62, cladding layer 64, and contact layer 66 are stacked on top of the cladding layer 60 in this order. The cladding layer 60 and the active layer 62 are provided on the optical waveguide 20, the recess 25, and the terrace 27. The gain section 30 has a mesa 67. The mesa 67 is formed from the cladding layer 64 and the contact layer 66. The mesa 67 has a narrower width than the cladding layer 60 and the active layer 62 and is located on the optical waveguide 20 and the recess 25.

[0051] The gain section 30 is covered with an insulating film 61. The insulating film 61 has openings at positions spaced apart from the mesa 67 and has raised openings on the mesa 67. Electrode 34 is provided at a position spaced apart from the mesa 67 and is electrically connected to the cladding layer 60. Electrode 36 is located on the mesa 67 and is electrically connected to the contact layer 66.

[0052] The cladding layer 60 is formed of, for example, n-type indium phosphide (n-InP). The cladding layer 64 is formed of, for example, p-InP. The contact layer 66 is formed of, for example, p-type indium gallium arsenide (p-InGaAs). The active layer 62 has a multi-quantum well structure (MQW) and includes multiple well layers and multiple barrier layers. The well layers and barrier layers are formed of, for example, undoped gallium indium arsenide (i-GaInAs).

[0053] As shown in Figures 10A and 10B, a highly doped region 40 is provided on the bottom surface of the recess 25. In the cross-section shown in Figure 10B, the upper surface of the optical waveguide 20 is in contact with the lower surface of the cladding layer 60. As shown in Figure 10A, the optical waveguide 20 has a diffraction grating 55 in the portion that overlaps with the gain section 30.

[0054] By applying voltage to electrodes 34 and 36, a current flows through the gain section 30. Upon carrier injection, the gain section 30 emits light. The wavelength of light oscillation is determined by the diffraction grating 55. To change the wavelength of light, a voltage is applied to the region 40 using pads 45 and electrode 44. When current flows, Joule heat is generated in the region 40. The heat is transferred from the region 40 to the diffraction grating 55, changing the temperature of the diffraction grating 55. The refractive index of the diffraction grating 55 changes due to the temperature change. The wavelength of light oscillation can be adjusted by changing the refractive index.

[0055] (Manufacturing method) Figures 11A to 16B illustrate the manufacturing method of the semiconductor optical element 200, and are plan views and cross-sectional views corresponding to Figures 10A and 10B. As shown in Figures 11A and 11B, dry etching is performed on the Si layer 16 of the substrate 10 to form the recesses 25 and the diffraction grating 55.

[0056] As shown in Figures 12A and 12B, a resist 70 is formed on the upper surface of the Si layer 16. The resist 70 has an opening 70a above the recess 25. Ion implantation is performed to form a region 40 on the bottom surface of the recess 25. After ion implantation, the resist 70 is removed.

[0057] As shown in Figures 13A and 13B, the gain section 30 is joined. The lower surface of the cladding layer 60 and the upper surface of the Si layer 16 of the gain section 30 are activated by plasma irradiation. The gain section 30 is joined to the Si layer 16 by bringing the cladding layer 60 and the Si layer 16 into contact.

[0058] As shown in Figures 14A and 14B, a mesa 67 is formed on the gain section 30, for example by dry etching. As shown in Figures 15A and 15B, an insulating film 61 is formed on the surface of the gain section 30, for example by plasma CVD. A cladding layer 32 is formed on the upper surface of the Si layer 16. The insulating film 61 and the cladding layer 32 may be formed from the same material, or they may be formed simultaneously in a single process.

[0059] As shown in Figures 16A and 16B, electrodes 44 are formed on the upper surface of region 40 by vacuum deposition or the like. Openings are formed in the insulating film 61 by etching or the like. Electrodes 34 and 36 are formed in these openings by vacuum deposition or the like. Pads 45 are formed by plating or the like. The semiconductor optical element 200 is formed through the above steps.

[0060] According to the second embodiment, the Si layer 16 of the substrate 10 has a region 40. The heat generated in region 40 can change the temperature of the diffraction grating 55 and thus change the refractive index. By changing the refractive index of the diffraction grating 55, the phase of the light propagating through the optical waveguide 20 changes, and the wavelength of the light can be changed. By providing region 40 in the Si layer 16, power consumption can be reduced compared to a metal heater.

[0061] As shown in Figure 10A, the recesses 25 are provided on both sides of the diffraction grating 55, and the regions 40 are also provided on both sides of the diffraction grating 55. By providing regions 40 on both sides of the diffraction grating 55, heat is efficiently transferred from the two regions 40. Temperature changes can be efficiently performed. The regions 40 may be provided on at least one of the two sides of the diffraction grating 55.

[0062] The gain section 30 is bonded to the diffraction grating 55. Therefore, it is difficult to provide a metal heater near the diffraction grating 55. According to the second embodiment, a region 40 is provided in the recess 25 in the vicinity of the diffraction grating 55. The temperature of the diffraction grating 55 can be changed by the heat generated in region 40. The substrate 10 may have a diffraction grating 55 and a ring resonator. Regions 40 may be provided near the diffraction grating 55 and near the ring resonator.

[0063] Although embodiments of this disclosure have been described in detail above, this disclosure is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of this disclosure as described in the claims. [Explanation of symbols]

[0064] 10, 12 circuit boards 10a, 10b, 20a end 14 Box Layers 16 Si layer 20 Optical waveguide 21, 31 Tapered section 22, 24 Loop Mirror 23 parts 25 recesses 26, 28 Ring resonators 27 Terrace 30 Gain section 34, 36, 44 electrodes 45 pads 32, 60, 64 cladding layers 40 areas 42 Connection part 50, 52, 70 resistance 50a, 52a, 70a opening 55 Diffraction grating 61 Insulating film 62 Active layer 66 Contact Layers 67 Mesa 100, 200 semiconductor optical elements

Claims

1. A substrate having an optical waveguide and a recess, On the upper surface of the substrate, there is a gain section having optical gain that is bonded to the optical waveguide, It comprises electrodes and, The substrate has a silicon layer, The silicon layer has the optical waveguide and the recess, The recess is adjacent to the optical waveguide, The first region of the silicon layer is provided on the bottom surface of the recess and has a higher dopant concentration than the optical waveguide. The electrode is a semiconductor optical element electrically connected to the first region.

2. The semiconductor optical element according to claim 1, comprising an insulating film provided on the silicon layer and covering the optical waveguide and the recess.

3. The recesses are provided on both sides of the optical waveguide. The semiconductor optical element according to claim 1 or claim 2, wherein the first region is provided in each of the recesses on both sides of the optical waveguide.

4. The doping concentration in the first region is 2 × 10⁻⁶ ２０ cm －３ The above is 1 x 10 ２２ cm －３ The semiconductor optical element according to claim 1 or claim 2, wherein the following applies:

5. The semiconductor optical element according to claim 1 or claim 2, wherein the electrical resistance of the first region is 1000 Ω or less.

6. The semiconductor optical element according to claim 1 or claim 2, wherein the distance between the optical waveguide and the first region is 100 nm or more.

7. The optical waveguide forms a ring resonator, The semiconductor optical element according to claim 1 or claim 2, wherein the first region is provided in the portion of the recess adjacent to the ring resonator.

8. A diffraction grating is provided in the portion of the optical waveguide to which the gain section is joined. The semiconductor optical element according to claim 1 or claim 2, wherein the first region is provided in the portion of the recess that is aligned with the diffraction grating.

9. The first region has a connecting portion, The aforementioned connection portion is located opposite to the optical waveguide. The semiconductor optical element according to claim 1 or claim 2, wherein the electrode is connected to the connection portion.

10. A substrate having an optical waveguide and a recess adjacent to the optical waveguide, comprising the step of forming a first region on the bottom surface of the recess, A step of bonding a gain section having optical gain to the upper surface of the substrate and onto the optical waveguide, The process includes forming an electrode connected to the first region, The substrate has a silicon layer, The silicon layer has the optical waveguide and the recess, A method for manufacturing a semiconductor optical device, wherein the step of forming the first region is to dope the bottom surface of the recess in the silicon layer to form the first region having a dopant concentration higher than that of the optical waveguide.

Images