Quantum devices and their construction methods

Abstract

To facilitate testing of a coupling circuit that is configured to couple a plurality of quantum bits, before the coupling circuit is operated as an element of a quantum computer.SOLUTION: A quantum device 3 comprises: a first quantum chip 1 that includes at least two quantum bits 10-1, 10-2 arranged on a first plane 18 of a substrate 17; and a second quantum chip 2 that includes a coupling circuit 20 formed on a first plane 28 of a second substrate 27. The first quantum chip includes at least two vias 11-1, 11-2 that penetrate both planes. The second quantum chip includes a coupling port for testing the coupling circuit and a first pad for input and / or output of a signal. The first pad and the coupling port are electrically connected to each other for the test, and the first pad and the coupling port are disconnected from each other after the test. In the first quantum chip, each of the at least two quantum bits electrically connects to the coupling circuit of the second quantum chip via the at least two vias.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a quantum device and a method of configuring the same. [Background Art]

[0002] A quantum computer is a computer capable of massively parallel computing that utilizes the principles of quantum mechanics such as superposition and quantum entanglement. Among quantum computers, the type called gate-type is known to be capable of solving specific problems such as prime factorization and database search at an overwhelmingly higher speed than the currently mainstream von Neumann computers. Further, the type called annealing-type is expected to solve combinatorial optimization problems at high speed with high accuracy.

[0003] In a gate-type quantum computer, qubits often have a network in which they are coupled via frequency-variable couplers through two-body interaction (see, for example, Patent Document 1). As shown in FIG. 10, Patent Document 1 comprises a plurality (two) of qubits (fixed-frequency quantum circuits) 10A-1 and 10A-2 formed on the same wiring layer, and a coupling circuit (tunable coupler) 20A capacitively coupled to the qubits. The coupling circuit (tunable coupler) 20A has a loop provided with a Josephson junction, and the frequency (resonant frequency) is modulated by changing the current passing through the inductively coupled control line 30 to change the magnetic flux penetrating the loop. FIG. 10 corresponds to FIG. 2 of Patent Document 1, and the reference numerals are modified from those in FIG. 2 of Patent Document 1.

[0004] On the other hand, in annealing-type quantum computers (for example, quantum computers that solve combinatorial optimization problems by setting them up as an Ising model), in addition to two-body interactions like gate-type systems, there have been proposals that have a network of Josephson parametric oscillators (JPOs) coupled by four-body interactions (Non-Patent Literature 1). A group of four JPOs (called a plaquette in Non-Patent Literature 1) is a central component of the architecture and can be expanded pyramid-like with a square lattice necessary for implementing the LHZ (Lechner, Hauke, Zoller) scheme (see Non-Patent Literature 2). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Special Publication No. 2021-516389 [Non-patent literature]

[0006] [Non-Patent Document 1] Shruti Puri, et. al., "Quantum annealing with all-to-all connected nonlinear oscillators", Nature Communications Vol. 8, 15785 (2017) [Non-Patent Document 2] Wolfgang Lechner, et. al., "A quantum annealing architecture with all-to-all connectivity from logical interactions", Science Advances, 23 Oct 2015 Vol 1, Issue 91, e1500838 (2015) [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] In the related technologies mentioned above, as illustrated in Figure 10, the qubits and coupling circuits (couplers) are arranged on the same wiring layer. It is generally difficult to wire dedicated input / output and control signal lines for testing a coupling circuit that is surrounded by multiple qubits on the same wiring layer. This difficulty becomes even more apparent when the number of qubits interacting via the coupling circuit increases, such as in a coupling circuit that performs four-body interaction with four qubits.

[0008] Furthermore, it is desirable to have a configuration that facilitates the individual testing (such as characterization and operational verification) of coupling circuits before they are assembled as quantum devices or before they are operated as elements of a quantum computer. Similarly, it is desirable to facilitate the individual testing of qubits before they are operated as elements of a quantum computer.

[0009] Therefore, the object of this disclosure is to provide a quantum device and a method for configuring a quantum device that facilitates testing of coupling circuits that combine multiple qubits, for example, before they are operated as elements of a quantum computer. [Means for solving the problem]

[0010] According to this disclosure, quantum devices are A first substrate and a first quantum chip having at least two qubits on a first surface of the first substrate, The second substrate and the second quantum chip having a coupling circuit on the first surface of the second substrate for interacting the at least two qubits, It is equipped with. The first quantum chip has at least two vias that are electrically connected to the at least two qubits disposed on the first surface of the first substrate and penetrate from the first surface of the first substrate to the second surface opposite to the first surface. The second quantum chip further comprises, on the first surface of the second substrate, a coupling port for testing the coupling circuit and a first pad for inputting and / or outputting test signals to the coupling circuit. In the second quantum chip, the first pad and the coupling port are electrically connected for testing the coupling circuit, and after the test, the second quantum chip, with the connection between the first pad and the coupling port disconnected, is bonded to the first quantum chip. In the first quantum chip bonded to the second quantum chip, the at least two qubits are each electrically connected to the coupling circuit of the second quantum chip via the at least two vias.

[0011] According to this disclosure, a method for constructing a quantum device is provided, comprising bonding a first quantum chip having at least two qubits on a first surface of a first substrate and a second quantum chip having the coupling circuit on a first surface of a second substrate. The method for constructing the quantum device includes the following steps. The first quantum chip is provided with at least two vias that are electrically connected to the at least two qubits and penetrate the first substrate of the first quantum chip from the first surface to the second surface opposite to the first surface. A coupling port for testing the coupling circuit and a first pad for inputting and / or outputting test signals to the coupling circuit are provided on the first surface of the second substrate of the second quantum chip. The coupling circuit is tested by electrically connecting the first pad on the first surface of the second quantum chip with the coupling port. After the above test, the connection between the first pad on the first surface of the second quantum chip and the coupling port is made disconnected, and then the second quantum chip and the first quantum chip are bonded together. In the first quantum chip bonded to the second quantum chip, the at least two qubits are each connected to the coupling circuit of the second quantum chip via the at least two vias. [Effects of the Invention]

[0012] According to the present disclosure, for a coupling circuit that couples a plurality of qubits, for example, testing before operating as an element of a quantum computer can be facilitated. [Brief Description of the Drawings]

[0013] [Figure 1] (A) and (C) are schematic plan views (top view, bottom view) illustrating a first quantum chip according to one embodiment, and (B) is a schematic cross-sectional view. [Figure 2] (A) and (C) are schematic plan views (top view, bottom view) illustrating a second quantum chip according to one embodiment, and (B) is a schematic cross-sectional view. [Figure 3] It is a schematic plan view illustrating a reference example in which a quantum device is configured by a single quantum chip. [Figure 4] It is a schematic plan view illustrating an example of a test setup according to one embodiment. [Figure 5] (A) to (C) are schematic cross-sectional views of the test setup in FIG. 4. [Figure 6A] It is a schematic plan view illustrating another example of a test setup according to one embodiment. [Figure 6B] It is a schematic cross-sectional view illustrating a modified example of a test setup according to one embodiment. [Figure 7] (A) and (B) are schematic cross-sectional views of a first quantum chip and a second quantum chip according to one embodiment, and (C) is a schematic cross-sectional view of a quantum device in which the first quantum chip and the second quantum chip are bonded together. [Figure 8] (A) and (C) are schematic plan views (top view, bottom view) illustrating a second quantum chip according to another embodiment, and (B) is a schematic cross-sectional view. [Figure 9](A) to (C) are schematic cross-sectional views illustrating another embodiment. [Figure 10] It is a schematic plan view illustrating the related art. MODE FOR CARRYING OUT THE INVENTION

[0014] Several embodiments will be described below with reference to the drawings. FIG. 1 is a diagram illustrating an embodiment. FIGS. 1(A) and 1(C) are a schematic plan view of a first surface of a first semiconductor chip having a plurality of qubits formed on a substrate using semiconductor microfabrication technology (referred to as a "first quantum chip") and a schematic plan view of a second surface opposite to the first surface, and FIG. 1(B) is a schematic cross-sectional view taken along line A-A' of FIG. 1(A). Note that in FIG. 1, for simplicity, the first quantum chip 1 provided with two qubits is exemplified, but the number of qubits mounted on the first quantum chip 1 is not limited to two, and it goes without saying that a configuration including more than two qubits such as four qubits may be employed, for example.

[0015] Referring to Figure 1(A), the first qubit 10-1 and the second qubit 10-2 are superconducting qubits and are formed on the first surface 18 of the substrate (also called a "chip substrate") 17 (see Figure 1(B)) using mainly a superconducting material. The substrate 17 is, for example, silicon (Si), but other electronic materials such as sapphire or compound semiconductor materials (Group IV, Group III-V, Group II-VI) may also be used. Furthermore, while it is preferable for the substrate 17 to be a single crystal, it may also be polycrystalline or amorphous. The wiring pattern in Figure 1(A) may be formed by depositing (depositing) a superconducting material onto the first surface 18 of the substrate 17 and then patterning it. Although not particularly limited, the first qubit 10-1 and the second qubit 10-2 may include a SQUID (superconducting quantum interference device, SQUID) in which multiple Josephson junctions are arranged in a loop, such as a Josephson parametric oscillator. In this case, the first qubit 10-1 and the second qubit 10-2 may be configured as, for example, a lumped-parameter circuit. Alternatively, they may be distributed-parameter circuits. Note that in Figure 1(A), the first qubit 10-1 and the second qubit 10-2 are shown as circular shapes for simplicity, with electrode patterns and the like omitted, but the planar shape of the qubits can be arbitrary, such as a T-shape or a cross shape.

[0016] The first qubit 10-1 and the second qubit 10-2 are connected via coupling ports 13A-1 and 13A-2, which are mainly made of superconducting material, to transmission lines 12A-1 and 12A-2, which are mainly made of superconducting material, by capacitive or dielectric coupling. Transmission lines 12A-1 and 12A-2 are connected to the first and second vias 11-1 and 11-2, respectively.

[0017] The first and second pads 15-1 and 15-2 are mainly made of superconducting material and are connected to coupling ports 13B-1 and 13B-2, respectively, via transmission lines 12B-1 and 12B-2.

[0018] In Figure 1(A), the first qubit 10-1 and the second qubit 10-2 are represented as circular shapes, and the coupling ports 13A-1, 13B-1 and 13A-2, 13B-2 are schematically represented as arcs simply for the sake of drawing convenience. However, it goes without saying that the configuration is not limited to this.

[0019] Signals supplied from an external signal source (not shown) to the first and second pads 15-1 and 15-2 may be transmitted from transmission lines 12B-1 and 12B-2 to coupling ports 13B-1 and 13B-2, respectively, and applied to the first qubit 10-1 and the second qubit 10-2 by inductive or capacitive coupling. Alternatively, signals (readout signals) transmitted from the first qubit 10-1 and the second qubit 10-2 to transmission lines 12B-1 and 12B-2 via coupling ports 13B-1 and 13B-2 by inductive or capacitive coupling may be transmitted from the first and second pads 15-1 and 15-2 to an external readout circuit (not shown). In Figure 1(A), the first set of pad 15-1, transmission line 12B-1, and coupling port 13B-1 may be provided separately for the signal applied to the first qubit 10-1 and the signal from the first qubit 10-1 (readout signal). The same applies to the second qubit 10-2. Furthermore, if the first qubit 10-1 and the second qubit 10-2 include, for example, a Josephson parametric oscillator, the configuration may further include lines (pads, transmission lines, coupling ports) that supply microwave pulse signals to each of the first qubit 10-1 and the second qubit 10-2.

[0020] In the first quantum chip 1, for example, Nb (niobium) or Al (aluminum) is used as the superconducting material (wiring material), but it is not limited to these. Any metal that becomes superconducting when cooled to extremely low temperatures may be used, such as niobium nitride, indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), titanium nitride, Mo (molybdenum), Ta (tantalum), tantalum nitride, and alloys containing at least one of these. If the first qubit 10⁻¹ and the second qubit 10⁻² include a Josephson junction, a first aluminum film may be formed on the first surface 18 of the substrate 17 by oblique deposition and oxidized to form a tunnel oxide film (AlOx), and a second aluminum film may be formed by oblique deposition from the opposite direction to the previous deposition to form a Josephson junction (Al / AlOx / Al).

[0021] The first and second vias 11-1 and 11-2 are through vias consisting of vertical holes penetrating the substrate 17 from the first surface 18 to the second surface 19. As shown in Figure 1(B), they may be filled vias in which the inside of the via hole is filled with a conductive material (mainly a superconducting material is used). Alternatively, they may be conformal vias in which a conductive material (mainly a superconducting material is used) is formed to a constant thickness along the shape of the via hole. When the substrate 17 is silicon, the first and second vias 11-1 and 11-2 are also called through silicon vias (TSVs). In this case, although not particularly limited, the first and second vias 11-1 and 11-2 may be formed in the wafer process, for example, after the wiring process on the first surface 18 of the substrate 17 (via lasting). In via lasting, via holes in the silicon substrate are made using methods such as etching or laser beam, and the conductive material is filled into the via holes using plating. Alternatively, via holes (through holes) may be made in the substrate 17 first, and then a wiring pattern may be formed on the first surface 18 of the substrate 17.

[0022] As shown in Figure 1(C), at the point where the second via 11-2 contacts the second surface 19 of the first quantum chip 1 (open end), a pad (via pad) 14 may be made mainly of a superconducting material to cover the end face of the second via 11-2. With such a structure, signals can be transmitted from the first qubit 10-1 and the second qubit 10-2 to the second surface 19 of the substrate 17 via the coupling ports 13A-1 and 13A-2 and the first and second vias 11-1 and 11-2, respectively, while maintaining coherence (i.e., maintaining the phase of the high-frequency current).

[0023] While not particularly limited, in Figure 1(A), transmission lines 12A-1, 12A-2, 12B-1, and 12B-2 may be configured as coplanar waveguides with both longitudinal sides surrounded by a ground plane (ground pattern) not shown, separated by gaps. The first and second vias 11-1 and 11-2 may be configured such that, except for the connection points with transmission lines 12A-1 and 12A-2, they are surrounded by a ground plane (ground pattern) not shown, separated by gaps. Similarly, the first qubit 10-1 and the second qubit 10-2 may be configured such that, except for the parts facing the coupling ports 13A-1 and 13B-1, and the coupling ports 13A-2 and 13B-2, they are surrounded by a ground plane (ground pattern) not shown, separated by gaps.

[0024] Figure 2 is a schematic example of a second quantum chip 2 equipped with a coupling circuit 20 formed on a substrate using semiconductor microfabrication technology. Figures 2(A) and (C) are schematic plan views of the first surface (front) and second surface (back) of the second quantum chip 2, and Figure 2(B) is a schematic cross-sectional view along the line B-B' in Figure 2(A).

[0025] Referring to Figure 2(A), in the second quantum chip 2, a coupling circuit 20 for coupling the first qubit 10-1 and the second qubit 10-2 is fabricated mainly from a superconducting material on the first surface 28 of the substrate 27 (see Figure 2(B)). The substrate 27 of the second quantum chip 2 (also called the "chip substrate") is preferably made of the same material as the substrate 17 of the first quantum chip 1 described above, taking into consideration the shrinkage (linear shrinkage rate) of the substrate when cooled to extremely low temperatures. The wiring pattern in Figure 2(A) may be formed by depositing (depositing) a superconducting material onto the first surface 28 of the substrate 27 and then patterning it. Preferably, the same superconducting material as the superconducting material of the first quantum chip 1 described above is used. Note that in Figure 2(A), for simplicity, the coupling circuit 20 is not shown as a wiring pattern and is schematically represented as a rectangle (square), but of course the shape of the coupling circuit 20 is not limited to a square. Although not particularly limited, the coupling circuit 20 may consist of a circuit including one Josephson junction, or it may include a SQUID or a ring modulator (see Non-Patent Document 1), etc.

[0026] The coupling circuit 20 is connected to the first and second vias 21-1 and 21-2 by transmission lines 22A-1 and 22A-2, which are mainly made of superconducting material.

[0027] As shown in Figure 2(B), in the second quantum chip 2, the first and second vias 21-1 and 21-2 function as superconducting transmission lines that penetrate the substrate 27 from the first surface 28 to the second surface 29. The first and second vias 21-1 and 21-2 are through-vias consisting of vertical holes that penetrate the substrate 27 from the first surface 28 to the second surface 29, and as shown in Figure 2(B), they may be filled vias in which the inside of the via hole is filled with a conductive material (mainly a superconducting material is used). Alternatively, they may be conformal vias in which a conductive material (mainly a superconducting material is used) is formed to a constant thickness along the shape of the via hole. When the substrate 27 of the second quantum chip 2 is silicon, the first and second vias 21-1 and 21-2 are also called through-silicon vias (TSVs). In this case, the first and second vias 21-1 and 21-2 may be installed after the wiring process on the first surface 28 of the substrate 27. Alternatively, via holes (through holes) may be made in the substrate 27 first, and then a wiring pattern may be formed on the first surface 28 of the substrate 27. The conductive material (mainly superconducting material) for the first and second vias 21-1 and 21-2 may be the same material as the conductive material for the first and second vias 11-1 and 11-2 of the first quantum chip 1 described above.

[0028] As shown in Figures 2(B) and 2(C), a pad 24 is provided at the point where the second surface 29 of the substrate 27 is in contact, so as to cover the end face of the second via 21-2. The pad 24 may be made of a superconducting material.

[0029] Referring again to Figure 2(A), the first pad 25-1 and the second pad 25-2 are bonding pads that are bonded to a printed circuit board (PCB) (not shown) with bonding wires, and may be made mainly of superconducting material. The first pad 25-1 may be a pad for inputting and outputting signals for testing (characterization evaluation, operation verification, etc.) the coupling circuit 20. The second pad 25-2 may be a pad for inputting control signals to the coupling circuit 20.

[0030] Pads 26-1 and 26-2 are bonded together with bonding wires (not shown) for testing the coupling circuit 20, and may be made primarily of superconducting material. Transmission line 22C is made primarily of superconducting material and connects the first pad 25-1 to pad 26-2. Transmission line 22B is made primarily of superconducting material and connects pad 26-1 to coupling port 23-1. Coupling port 23-1 is made primarily of superconducting material and is inductively or capacitively coupled to the coupling circuit 20. During testing of the coupling circuit 20, by connecting pads 26-2 and 26-1 with bonding wires (not shown), transmission line 22C, pads 26-2 and 26-1, and transmission line 22B become connecting lines that electrically connect the first pad 25-1 to coupling port 23-1. Except during testing, the connection between pad 26-2 and pad 26-1 is disconnected, and the transmission line between the first pad 25-1 and coupling port 23-1 is electrically disconnected (disconnected).

[0031] The spacing between pads 26-1 and 26-2 may be set such that the high-frequency signal (electromagnetic wave signal) of the coupling circuit 20 does not leak to the transmission line 22C side when transmitted from coupling port 23-1 through transmission line 22B due to capacitive coupling between pads 26-1 and 26-2. Alternatively, a ground pattern (not shown) may be provided between pads 26-1 and 26-2 to reduce capacitive coupling between them.

[0032] The transmission line 22D is mainly made of superconducting material and connects the second pad 25-2 and the coupling port 23-2. The coupling port 23-2 is mainly made of superconducting material and transmits the control signals transmitted from the second pad 25-2 through the transmission line 22D to the coupling circuit 20 by dielectric coupling or capacitive coupling. The path consisting of the second pad 25-2, the transmission line 22D, and the coupling port 23-2 is used to input control signals to the coupling circuit 20 when the coupling circuit 20 is operated as an element of a quantum computer (i.e., even when the coupling circuit 20 is not being tested).

[0033] While not particularly limited, transmission lines 22A-1, 22A-2, 22B, 22C, and 22D may be coplanar waveguides in which both longitudinal sides are surrounded by a ground plane (ground pattern) not shown, separated by a gap. Alternatively, the parts of the coupling circuit 20 other than those connected to the first and second vias 21-1 and 21-2, and those facing the coupling ports 23-1 and 23-2 may be surrounded by a ground plane (ground pattern) not shown, separated by a gap.

[0034] Figure 3 is a schematic plan view illustrating a quantum device (reference example) in which the first qubit 10-1, the second qubit 10-2, and the coupling circuit 20, as described with reference to Figures 1 and 2, are provided on the same wiring layer of a single semiconductor chip (quantum chip). In Figure 3, the shapes of the qubits, coupling circuit, and coupling ports are the same as in Figures 1 and 2. Figure 3 is also a reference diagram that clarifies the correspondence between the elements of each chip when a quantum device consisting of a single quantum chip is divided into the first quantum chip 1 in Figure 1 and the second quantum chip 2 in Figure 2, and the elements of the single quantum chip before division. The coupling ports 13B-1 and 13B-2, which are connected to the first and second pads 15-1 and 15-2 respectively via transmission lines 12B-1 and 12B-2, are inductively or capacitively coupled to the first qubit 10-1 and the second qubit 10-2. Note that Figure 3 does not show the wiring patterns for applying control signals to the coupling circuit 20 (for example, the wiring patterns for the second pad 25-2, transmission line 22D, and coupling port 23-2 in Figure 2(A), or the control line 30 in Figure 10).

[0035] As explained with reference to Figures 1 and 2, by fabricating the first qubit 10-1 and the second qubit 10-2, and the coupling circuit 20 that connects them, for example, by two-body interaction, on the first quantum chip 1 and the second quantum chip 2, respectively, it is possible to independently test the first quantum chip 1 and the second quantum chip 2 (e.g., evaluate the characteristics of the circuit and verify its operation).

[0036] Figure 4 is a schematic plan view illustrating an example of a test setup of the coupling circuit 20 of the second quantum chip 2 in Figure 2(A), schematically showing the first surface 28 of the second quantum chip 2 and the plane of the printed circuit board 31 housing the second quantum chip 2. It should be noted that in the schematic plan view of Figure 4, the second quantum chip 2 is shown larger than the size of the printed circuit board 31 to illustrate its dimensions, and the sizes of the second quantum chip 2 and the printed circuit board 31 are not limited to the example in Figure 4.

[0037] In the example shown in Figure 4, a printed circuit board 31 connected to a measuring device (not shown) is used to test (characterize, verify operation, etc.) the coupling circuit 20 of the second quantum chip 2. On the first surface 28 of the second quantum chip 2, as explained with reference to Figure 2(A), in addition to the coupling circuit 20 and the first and second vias 21-1 and 21-2, there is a coupling port 23-1, a pad 26-1 connected to the coupling port 23-1 via a transmission line 22B, a pad 26-2 located near the pad 26-1, and a first pad (input / output pad) 25-1 connected to the pad 26-2 via a transmission line 22C, which serve as lines (wiring patterns) for inputting and outputting test signals to the coupling circuit 20. A second pad (control pad) 25-2 is provided, connected to the coupling port 23-2 via a transmission line 22D, which serves as a line (wiring pattern) for applying control signals to the coupling circuit 20.

[0038] In the example shown in Figure 4, an opening 32 is provided near the center of the printed circuit board 31 to position the second quantum chip 2 with its first surface 28 facing upwards. The planar shape of the opening 32 on the printed circuit board 31 is a rectangle corresponding to the second quantum chip 2. On the opposite sides of the opening 32 on the printed circuit board 31, bonding pads 33-1 to 33-3 and 33-4 to 33-6 for wire bonding to the first and second pads 25-1 and 25-2 on the first surface 28 of the second quantum chip 2 are arranged at a predetermined pitch. In addition to the left and right sides of the opening 32, the bonding pads on the printed circuit board 31 may also be arranged opposite to the top and bottom sides. Although not particularly limited, if the size of the second quantum chip 2 is on the order of millimeters in both length and width, and the printed circuit board 31 is on the order of centimeters in both length and width, the wiring pitch of the second quantum chip 2, which is manufactured using semiconductor microfabrication technology, will differ from the wiring pitch of the printed circuit board 31. Therefore, if multiple pads 25 on the first surface 28 of the second quantum chip 2 are aligned, the pitch conversion may be performed on the printed circuit board 31 side.

[0039] The second quantum chip 2 is housed in the opening 32 of the printed circuit board 31 with its second surface 29 facing downwards. Figure 5(A) schematically illustrates the cross-section along the line C-C' in Figure 4. In the example shown in Figure 5(A), the opening 32 of the printed circuit board 31 is provided with a support portion 37 that contacts the outer edge of the second surface 29 of the second quantum chip 2. When the second quantum chip 2 is housed in the opening 32 of the printed circuit board 31, the height of the first pad 25-1 on the first surface 28 of the second quantum chip 2 may be made the same as the height of the bonding pad 33-1 of the printed circuit board 31. In this state, the first and second pads 25-1 and 25-2 of the second quantum chip 2 and the bonding pads 33-1 and 33-4 of the printed circuit board 31 are connected by bonding wires 34-1 and 34-2 (see Figure 4), respectively. The opening (cutout) 32 of the printed circuit board 31 may be an opening that penetrates from the front surface to the back surface of the printed circuit board 31. In the example of Figure 5(A), the printed circuit board 31 may be placed on a base (holder) not shown. In the example of Figure 5(B), the opening 32 of the printed circuit board 31 is a bottomed opening with a gap provided below the second surface of the second quantum chip 2. In the example of Figure 5(C), the opening 32 of the printed circuit board 31 is a bottomed opening whose depth is set to be the same as the height of the second quantum chip 2. In this case, the entire bottom surface of the opening 32 of the printed circuit board 31 becomes the support portion 37 for the second surface 29 of the substrate 27 of the second quantum chip 2. Note that in Figures 5(A) to (C), the heights of the second quantum chip 2 and the printed circuit board 31 are shown schematically. This is because, for example, if the thickness of the second quantum chip 2 is on the order of 10 to 100 μm and the thickness of the printed circuit board 31 is on the order of mm (for example, about 1.6 mm), it becomes difficult to represent the elements of the second quantum chip 2 in a drawing.

[0040] Referring to Figure 4, when testing the coupling circuit 20 on the first surface 28 of the second quantum chip 2, the first pad (input / output pad) 25-1 on the first surface 28 of the second quantum chip 2 is connected to the bonding pad 33-1 of the printed circuit board 31, and the second pad (control pad) 25-2 of the second quantum chip 2 is connected to the bonding pad 33-4 of the printed circuit board 31, respectively, by bonding wires 34-1 and 34-2. Also, the pads 26-1 and 26-2 on the first surface 28 of the second quantum chip 2 are connected by a bonding wire 34-3. Although not particularly limited, the bonding wires 34-1 to 34-3 are made of a superconducting material such as Al. In Figure 4, an example of multiple (2) bonding wires connected in parallel is shown as bonding wires connecting each pad, for example from the viewpoint of connection reliability, but of course, the number of bonding wires connecting each pad may be just one.

[0041] Bonding pads 33-1 to 33-3 and 33-4 to 33-6 are connected to connectors 35-1 to 35-3 and 35-4 to 35-6, respectively, by transmission lines 36-1 to 36-3 and 36-4 to 36-6. Preferably, high-frequency coaxial connectors are used for these connectors, and they are connected to an unshown measuring device (measuring electronics) for input / output or control via a high-frequency cable (coaxial cable) as shown in the figure. In Figure 4, connectors 35-1 to 35-3 and 35-4 to 35-6 are arranged at the same pitch as bonding pads 33-1 to 33-3 and 33-4 to 33-6, but of course, the configuration is not limited to this. Bonding pads 33-1 to 33-3 and 33-4 to 33-6, and transmission lines 36-1 to 36-3 and 36-4 to 36-6 may be made of a normal conductive material containing copper (e.g., an aluminum alloy). In a measurement device (not shown) such as a network analyzer or spectrum analyzer, a signal may be supplied from the first pad 25-1 of the second quantum chip 2 to the coupling circuit 20 via the coupling port 23-1 through the connector 35-1, transmission line 36-1, and bonding pad 33-1 of the printed circuit board 31, to perform high-frequency characteristic evaluation (S-parameter measurement) and measurement of the resonant frequency of the coupling circuit 20 (operation verification). In this case, the resonant frequency of the coupling circuit 20 may be controlled by a control signal (DC signal or microwave pulse) applied to the coupling circuit 20 from the second pad (control pad) 25-2. The measurement device is installed at room temperature outside the dilution refrigerator (not shown).

[0042] According to this embodiment, the above test setup allows testing (characterization and operational verification) of the coupling circuit 20 fabricated on the second quantum chip 2 to be performed before the second quantum chip 2 is configured as a quantum device, and therefore before it is operated as an element of a quantum computer. The testing of the second quantum chip 2 is performed while it is cooled to an extremely low temperature in a dilution refrigerator.

[0043] In the example shown in Figure 4, a printed circuit board 31 is used to evaluate the characteristics of the second quantum chip. However, the test may also be performed using a probe (high-frequency probe) mounted on a high-frequency test fixture (not shown), for example. In this case, a high-frequency signal from a measuring device (not shown) may be supplied from the high-frequency probe (not shown) via a high-frequency cable (not shown) to the first pad 25-1 on the first surface 28 of the substrate 27 of the second quantum chip 2, or the signal from the first pad 25-1 may be received by the high-frequency probe (not shown) and supplied to the measuring device (not shown) via a high-frequency cable (not shown). Alternatively, a control signal may be provided from a probe (not shown) to the second pad 25-2 on the first surface 28 of the substrate 27 of the second quantum chip 2.

[0044] Similar to the second quantum chip 2, the first quantum chip 1 can also be tested (characterization and operation verification, etc.) before being operated as an element in a quantum computer by preparing a printed circuit board and a high-frequency probe.

[0045] Figure 6A is a schematic plan view illustrating an example of a test setup for testing the first qubit 10-1 and the second qubit 10-2 of the first quantum chip 1, as described with reference to Figure 1, using a printed circuit board. Figure 6A schematically shows the configuration of the first surface 18 of the first quantum chip 1 and the printed circuit board 31 housing the first quantum chip 1. In Figure 6A, the printed circuit board is shown as the printed circuit board 31 described with reference to Figure 4 simply for the sake of clarity, but a separate printed circuit board may be prepared for testing the first quantum chip 1, and is not limited to the printed circuit board 31 in Figure 4. The first quantum chip 1 is housed in the opening 32 of the printed circuit board 31 with its second surface 29 facing downwards, similar to the second quantum chip 2 described above.

[0046] Referring to Figure 6A, in the first quantum chip 1, the first and second pads 15-1 and 15-2 are connected to bonding pads 33-1 and 33-4 of the printed circuit board 31 by bonding wires 34A-1 and 34A-2, respectively. In the test of the first qubit 10-1 (characterization, operation verification, etc.), a signal from a measuring device (not shown) is transmitted to the first pad 15-1 of the first quantum chip 1 via connector 35-1, transmission line 36-1, bonding pad 33-1, and bonding wire 34A-1 of the printed circuit board 31, and then supplied to the first qubit 10-1 via coupling port 13B-1 from transmission line 12B-1. Alternatively, the signal transmitted from the first qubit 10-1 to the transmission line 12B-1 via the coupling port 13B-1 may be transmitted via the bonding wire 34A-1 to the bonding pad 33-1 of the printed circuit board 31, the transmission line 36-1, and the connector 35-1, for measurement to be performed. In the transmission path between the connector 35-1 and the measurement device (not shown), the input and output of the signal may be switched, for example, by a circulator. Similarly, in testing the second qubit 10-2 (characterization, operation verification, etc.), a signal from a measuring device (not shown) may be transmitted to the second pad 15-2 of the first quantum chip 1 via the connector 35-4, transmission line 36-4, bonding pad 33-4, and bonding wire 34A-2 of the printed circuit board 31, and then to the second qubit 10-2 via the coupling port 13B-2 from the transmission line 12B-2. The signal transmitted from the second qubit 10-2 to the transmission line 12B-2 via the coupling port 13B-2 may then be transmitted via the bonding wire 34A-2 to the bonding pad 33-4, transmission line 36-4, and connector 35-4 of the printed circuit board 31, and the measurement may be performed. As a result of the test, no defects were detected in either the first qubit 10-1 or the second qubit 10-2, and the first quantum chip 1 was confirmed to be a good product. In this case, the bonding wires 34A-1 and 34A-2 are removed.

[0047] Figure 6B is a schematic plan view illustrating an example of a test setup when testing is performed using a printed circuit board 31, similar to Figure 6A, for the first quantum chip 1, which is further configured to include a set of test coupling ports, test pads, and lines connecting them, for each of the first quantum chip 1 and the second quantum chip 2. Referring to Figure 6B, the first surface 18 of the first quantum chip 1 has, in addition to the configuration in Figure 1(A), a third pad 15-3 and a fourth pad 15-4 connected to the first qubit 10-1 and the second qubit 10-2 via coupling ports 13C-1 and 13C-2, respectively. When testing the first qubit 10-1 and the second qubit 10-2, the first, second, third, and fourth pads 15-1, 15-2, 15-3, and 15-4 are connected to the bonding pads 33-1, 33-4, 33-3, and 33-6 of the printed circuit board 31 using bonding wires 34A-1, 34A-2, 34B-1, and 34B-2, respectively. Furthermore, pads 16-1 and 16-3, which are connected to the third and fourth pads 15-3 and 15-4 via transmission lines 12C-1 and 12C-2, respectively, and pads 16-2 and 16-4, which are connected to coupling ports 13C-1 and 13C-2, respectively, are connected to the bonding wires 34C-1 and 34C-2, respectively. Furthermore, the third and fourth pads 15-3 and 15-4, the transmission lines 12C-1 and 12C-2, the pads 16-1 to 16-4, and the coupling ports 13C-1 and 13C-2 are mainly fabricated from superconducting materials.

[0048] In the test of the first qubit 10-1, a signal from a measuring device (not shown) is transmitted to the first pad 15-1 of the first quantum chip 1 via connector 35-1, transmission line 36-1, bonding pad 33-1, and bonding wire 34A-1 on the printed circuit board 31, and then to the first qubit 10-1 via coupling port 13B-1 from transmission line 12B-1. The state of the first qubit 10-1 at this time may be transmitted from coupling port 13C-1, pad 16-2, bonding wire 34C-1, pad 16-1, transmission line 12C-1, third pad 15-3, bonding wire 34B-1 to bonding pad 33-3, transmission line 36-3, and connector 35-3 on the printed circuit board 31, and then measured. Similarly, in the test of the second qubit 10-2, a signal from a measuring device (not shown) is transmitted to the second pad 15-2 of the first quantum chip 1 via connector 35-4, transmission line 36-4, bonding pad 33-4, and bonding wire 34A-2 on the printed circuit board 31, and then to the second qubit 10-2 via the coupling port 13B-2 from the transmission line 12B-2. The state of the second qubit 10-2 at this time may be transmitted from the coupling port 13C-2, pad 16-4, bonding wire 34C-2, pad 16-3, transmission line 12C-2, and fourth pad 15-4, via bonding wire 34B-2 to bonding pad 33-6, transmission line 36-6, and connector 35-6, and then measured by the measuring device (not shown).

[0049] Alternatively, a control signal may be applied to the third pad 15-3 of the first quantum chip 1 via connector 35-3, transmission line 36-3, bonding pad 33-3, and bonding wire 34B-1 from a measuring device (not shown), and a control signal may be applied to the first qubit 10-1 via transmission line 12C-1, pad 16-1, bonding wire 34C-1, pad 16-2, and coupling port 13C-1, and the first qubit 10-1 may be tested using the signal path of connector 35-1, transmission line 36-1, bonding pad 33-1, bonding wire 34A-1, first pad 15-1, transmission line 12B-1, and coupling port 13B-1, similar to Figure 6A. Similarly, a control signal may be applied to the fourth pad 15-4 of the first quantum chip 1 via connector 35-6, transmission line 36-6, bonding pad 33-6, and bonding wire 34B-2 from a measuring device (not shown), and a control signal may be applied to the second qubit 10-2 via transmission line 12C-2, pad 16-3, bonding wire 34C-2, pad 16-4, and coupling port 13C-2, and the first qubit 10-1 may be tested using the signal path of connector 35-4, transmission line 36-4, bonding pad 33-4, bonding wire 34A-2, second pad 15-2, transmission line 12B-2, and coupling port 13B-2, as in Figure 6A.

[0050] As a result of the test, no defects were detected in either the first qubit 10-1 or the second qubit 10-2, and the first quantum chip 1 was confirmed to be a good product. In this first quantum chip 1, the bonding wires 34A-1, 34A-2, 34B-1, 34B-2, 34C-1, and 34C-2 are all removed. In the first quantum chip 1, the two sets of paths consisting of the first and second pads 15-1 and 15-2, the transmission lines 12B-1 and 12B-2, and the coupling ports 13B-1 and 13B-2 are used for inputting and outputting signals to the first qubit 10-1 and the second qubit 10-2 when operating as an element of a quantum computer (i.e., even when not testing the first qubit 10-1 and the second qubit 10-2). Note that in Figure 6B, the orientation of pads 15-3 and 15-4 is shown horizontally simply for the convenience of drawing creation. However, by arranging the bonding pads 33-3 and 33-6 on the upper and lower sides of the opening 32 of the printed circuit board 31, the orientation of pads 15-3 and 15-4 will be vertical, similar to the first and second pads 15-1 and 15-2.

[0051] Figure 7 illustrates the bonding of a first quantum chip 1 and a second quantum chip 2 in one embodiment. The second surface (back surface) 19 of the first quantum chip 1 (Figure 7(A)), which has passed the test for the first qubit 10-1 and the second qubit 10-2, and the second surface (back surface) 29 of the second quantum chip 2 (Figure 7(B)), which has passed the test for the coupling circuit 20, are placed facing each other and bonded together as shown in Figure 7(C). The bonding of the first quantum chip 1 and the second quantum chip 2 may be done by direct bonding of clean surfaces, or by bonding via a metal intermediate layer such as bump metal.

[0052] The bonding wires 34-1 to 34-3 (Figure 4) used when testing the second quantum chip 2 are removed before bonding it to the first quantum chip 1. These bonding wires 34-1 to 34-3 can be removed physically, for example, using tweezers, or by burning them off with a focused laser beam. Removing the bonding wires 34-1 to 34-3 disconnects the coupling circuit 20 from the first pad 25-1 (Figure 4), which is unnecessary when operating as a quantum computer element. Specifically, pads 26-1 and 26-2 are disconnected, and the coupling port 23-1 is disconnected from the first pad 25-1. Similarly, the bonding wires 34A-1, 34A-2, 34B-1, 34B-2, 34C-1, and 34C-2 (Figures 6A and 6B) used during the testing of the first qubit 10-1 and the second qubit 10-2 of the first quantum chip 1 are also removed.

[0053] When bonding the first quantum chip 1 and the second quantum chip 2, the end face of the first via 11-1 on the second surface 19 of the substrate 17 of the first quantum chip 1 and the end face of the second via 21-2 on the second surface 29 of the substrate 27 of the second quantum chip 2 are aligned, connecting the first via 11-1 of the first quantum chip 1 and the second via 21-2 of the second quantum chip 2. In other words, the first via 11-1 of the first quantum chip 1 and the second via 21-2 of the second quantum chip 2 can be used as a superconducting transmission line in which the effects of resistance loss, impedance mismatch, and reflections are significantly reduced or eliminated.

[0054] According to this embodiment, by forming a pad 14 to cover the end face of the second via 11-2 on the second surface 19 of the substrate 17 of the first quantum chip 1, and a pad 24 to cover the end face of the second via 21-2 on the second surface 29 of the substrate 27 of the second quantum chip 2, it is possible to relax the accuracy of alignment and significantly improve tolerance when bonding the second surface 19 of the first quantum chip 1 and the second surface 29 of the second quantum chip 2.

[0055] In a quantum device 3 formed by bonding a first quantum chip 1 and a second quantum chip 2, the first qubit 10-1 and the second qubit 10-2 are coupled via coupling ports 13A-1 and 13A-2, first and second vias 11-1 and 11-2, and coupling circuit 20.

[0056] In this embodiment, the configuration in which the first qubit 10-1, the second qubit 10-2, and the coupling circuit 20 are fabricated on the same quantum chip (Figure 3) is substantially identical to the circuit configuration. Furthermore, before bonding the first quantum chip 1 and the second quantum chip 2 together, the first qubit 10-1, the second qubit 10-2, and the coupling circuit 20 were tested individually, and it was verified that the first quantum chip 1, the second quantum chip 2, and the coupling circuit 20 were all good products. Therefore, when operating the quantum device 3 as an element of a quantum computer, it is not necessary to connect test signal lines.

[0057] In the embodiment described above, vias penetrating the substrates 17 and 27 are provided on both the first quantum chip 1 and the second quantum chip 2, respectively. However, vias may be provided on only one of the first quantum chip 1 or the second quantum chip 2. Below, as an example of another embodiment, the first quantum chip 1 is provided with at least two vias 11-1 and 11-2 penetrating the substrate 17, similar to Figure 1, while the second quantum chip 2', unlike Figure 2, does not have vias penetrating the substrate 27. Note that the first quantum chip 1 is the same as the one described in the embodiment described above, so its description will be omitted.

[0058] Figure 8(A) is a schematic plan view illustrating the second quantum chip 2'. Referring to Figure 8(A), the second quantum chip 2' has pads 26A-1 and 26A-2 made mainly of superconducting material on the first surface 28 of the substrate 27, at the positions where vias 21-1 and 21-2 in Figure 2(A) are located. As shown in Figure 8(B), the second quantum chip 2' does not have vias 21-1 and 21-2 penetrating the substrate 27 as shown in Figure 2(B), and as shown in Figure 8(C), the second surface 29 of the substrate 27 does not have pads 24 as shown in Figure 2(C). In the second quantum chip 2', the coupling circuit 20, coupling ports 23-1, 23-2, pads 26-1, 26-2, 26A-1, 26A-2, transmission lines 22A-1, 22A-2, 22B, 22C, 22D, and pads 25-1, 25-2 are mainly made of superconducting material, and the superconducting material is the same as the superconducting material of the first quantum chip 1 and the second quantum chip 2 described with reference to Figures 1 and 2. Also, the substrate 27 of the second quantum chip 2' is the same as the substrate 27 of the second quantum chip 2 described with reference to Figure 2.

[0059] In this embodiment, testing of the coupling circuit 20 of the second quantum chip 2' is performed as in Figure 4, by placing the second quantum chip 2' in the opening 32 of the printed circuit board 31 with the first surface 28 of the substrate 27 facing upwards, connecting the pads 33-1 and 33-4 of the printed circuit board 31 to the first and second pads 25-1 and 25-2 of the second quantum chip 2' with bonding wires 34-1 and 34-2, respectively, and further connecting the pads 26-1 and 26-2 with bonding wire 34-3. As in the embodiments described above, high-frequency characteristic evaluation (S-parameter measurement) and measurement of the resonant frequency of the coupling circuit 20 (operation confirmation) may be performed using a measurement device not shown. Alternatively, similar to the embodiment described above, the pads 26-1 and 26-2 may be connected with bonding wire 34-3, and the test may be performed by applying a probe (not shown) to the first pad 25-1 and the second pad 25-2, which are arranged on the first surface 28 of the substrate 27 of the second quantum chip 2. The probe (not shown) is mounted on a test fixture (high-frequency test fixture) or the like (not shown) and connected to a measuring device (not shown). In this embodiment, the test of the first qubit 10-1 and the second qubit 10-2 of the first quantum chip 1 may be performed in the same manner as described with reference to Figure 6A.

[0060] In this embodiment as well, the first quantum chip 1 and the second quantum chip 2' that have passed the tests are bonded together. Figure 9 illustrates the bonding of the first quantum chip 1 and the second quantum chip 2' in this embodiment. The second surface (back side) 19 of the first quantum chip 1 (Figure 9(A)), which has passed the tests for the first qubit 10-1 and the second qubit 10-2, and the first surface (front side) 28 of the second quantum chip 2' (Figure 9(B)), which has passed the tests for the coupling circuit 20, are placed facing each other and bonded together as shown in Figure 9(C).

[0061] In the example shown in Figure 7, which was referenced in the description of the embodiment above, the second surface 19 of the substrate 17 of the first quantum chip 1 and the second surface 29 of the substrate 27 of the second quantum chip 2 were bonded together (Figure 7(C)). However, in this embodiment, the quantum device 3' is formed by bonding the second surface 19 of the substrate 17 of the first quantum chip 1 and the first surface 28 of the substrate 27 of the second quantum chip 2'. The bonding of the second surface 19 of the substrate 17 of the first quantum chip 1 and the first surface 28 of the substrate 27 of the second quantum chip 2' may be performed by direct bonding or bonding via an intermediate metal layer such as a bump, as in the case of Figure 7.

[0062] In this embodiment, the end faces of the first and second vias 11-1 and 11-2 on the second surface 19 of the substrate 17 of the first quantum chip 1 and the first and second pads 26A-1 and 26A-2 on the first surface 28 of the substrate 27 of the second quantum chip 2' are aligned so that they overlap each other. This makes it possible to realize a configuration in which the first qubit 10-1 and the second qubit 10-2 interact as two bodies via the coupling ports 13A-1 and 13A-2, the first and second vias 11-1 and 11-2, and the coupling circuit 20.

[0063] In this embodiment, the second quantum chip 2' does not have the vias 21-1 and 21-2 provided on the second quantum chip 2 in the embodiment described with reference to Figure 2. Therefore, processes such as drilling via holes through the substrate 27 and embedding conductive material in via holes are unnecessary, making it easier to manufacture compared to the second quantum chip 2. Also, since the second quantum chip 2' does not have vias, there is no transmission loss (resistive loss (conductor loss)) due to vias. On the other hand, the second surface 19 of the substrate 17 of the first quantum chip 1 is in contact with the upper surface of the coupling circuit 20. Therefore, it should be noted that attention should be paid to waveform distortion and changes in the operating frequency of the coupling circuit 20 due to dielectric loss by the insulating (dielectric) substrate 17.

[0064] In each of the embodiments described above, a configuration in which the first qubit 10-1 and the second qubit 10-2 of the first quantum chip 1 are connected to the coupling circuit 20 of the second quantum chip 2 via the first via 11-1 and the second via 11-2, respectively, and testing thereof have been described. However, for example, even in a configuration in which the first to fourth qubits of the first quantum chip 1 are connected to the coupling circuit (four-body interaction coupling circuit) of the second quantum chip 2 via the first to fourth vias, respectively, the coupling circuit can be tested (characterization, operation verification, etc.) using a test setup similar to that in Figure 4 (the number of vias in Figure 4 is four).

[0065] The embodiments described above are further noted below (but are not limited thereto).

[0066] (Note 1) The quantum device comprises a first quantum chip comprising a first substrate and at least two qubits disposed on a first surface of the first substrate, A second quantum chip comprising a second substrate and a coupling circuit disposed on the first surface of the second substrate, Equipped with, The aforementioned first quantum chip, Each of the at least two qubits disposed on the first surface of the first substrate is electrically connected to at least two vias that penetrate from the first surface of the first substrate to the second surface opposite to the first surface, The aforementioned second quantum chip is On the first surface of the second substrate, The coupling port for testing the coupling circuit, A first pad for inputting and / or outputting a test signal to the coupling circuit, Furthermore, In the second quantum chip, the first pad and the coupling port are electrically connected for testing the coupling circuit. After testing, the second quantum chip, with the connection between the first pad and the coupling port disconnected, is bonded to the first quantum chip. In the first quantum chip bonded to the second quantum chip, the at least two qubits are each electrically connected to the coupling circuit of the second quantum chip via the at least two vias.

[0067] (Note 2) In the quantum device described in Appendix 1, the second quantum chip comprises at least two vias that penetrate from the first surface of the second substrate to the second surface opposite to the first surface, corresponding to the positions of the at least two vias on the second surface of the first quantum chip. On the first surface of the second substrate of the second quantum chip, the at least two vias are each electrically connected to the coupling circuit. The second surface of the first quantum chip and the second surface of the second quantum chip are bonded together.

[0068] (Note 3) In the quantum device described in Appendix 2, the first quantum chip is provided with a pad covering the end of at least one of the ends of the at least two vias on the second surface of the first substrate.

[0069] (Note 4) In the quantum device described in Appendix 1, the second quantum chip is provided with at least two pads on the first surface of the second substrate, corresponding to the positions of each of the at least two vias on the second surface of the first quantum chip. On the first surface of the second substrate of the second quantum chip, the at least two pads are each electrically connected to the coupling circuit. The second surface of the first quantum chip and the first surface of the second quantum chip are bonded together.

[0070] (Note 5) In the quantum device described in Appendix 4, at least one of the ends of the at least two vias on the second surface of the first substrate of the first quantum chip is provided with a pad that covers the end of the via.

[0071] (Note 6) In any of the quantum devices described in Appendix 1 to 5, The second quantum chip is located on the first surface of the second substrate. A second pad connected to the first pad via a first transmission line, The system further comprises a third pad connected to the coupling port via a second transmission line and spaced apart from the second pad, During testing of the coupling circuit, the second pad and the third pad are connected by a conductive member. After the test, the conductive member is removed, and the second pad and the third pad are electrically disconnected.

[0072] (Note 7) A quantum device comprising at least two qubits and a coupling circuit for interacting the at least two qubits, A method for constructing a quantum device comprising bonding together a first quantum chip having at least two qubits on a first surface of a first substrate and a second quantum chip having the coupling circuit on a first surface of a second substrate, The first quantum chip is provided with at least two vias that are electrically connected to the at least two qubits and penetrate the first substrate of the first quantum chip from the first surface to the second surface opposite to the first surface, On the first surface of the second substrate of the second quantum chip, a coupling port for testing the coupling circuit and a first pad for inputting and / or outputting test signals to the coupling circuit are provided. The coupling circuit is tested by electrically connecting the first pad on the first surface of the second quantum chip with the coupling port. After testing, the connection between the first pad on the first surface of the second quantum chip and the coupling port is made disconnected, and then the second quantum chip and the first quantum chip are bonded together. A method for configuring a quantum device, wherein in the first quantum chip bonded to the second quantum chip, the at least two qubits are each connected to the coupling circuit of the second quantum chip via at least two vias.

[0073] (Note 8) The method for constructing the quantum device described in Appendix 7 is: The second quantum chip is provided with at least two vias that penetrate the second substrate of the second quantum chip from the first surface to the second surface opposite to the first surface, corresponding to the positions of the at least two vias on the second surface of the first quantum chip. On the first surface of the second substrate of the second quantum chip, at least two vias are electrically connected to the coupling circuit, The second surface of the first quantum chip and the second surface of the second quantum chip are bonded together.

[0074] (Note 9) The method for constructing the quantum device described in Appendix 7 is: The first surface of the second substrate of the second quantum chip is provided with at least two pads corresponding to the positions of the at least two vias on the second surface of the first quantum chip, Each of the at least two pads is electrically connected to the coupling circuit. The second surface of the first quantum chip and the first surface of the second quantum chip are bonded together.

[0075] (Note 10) The method of constructing any of the quantum devices described in Appendix 7 to 9 is: In testing the coupling circuit of the second quantum chip, the first pad on the first surface of the second quantum chip and the bonding pad of the printed circuit board are connected with a first bonding wire. On the first surface of the second quantum chip, a second pad connected to the first pad via a first transmission line and a third pad connected to the coupling port via a second transmission line are connected by a second bonding wire. A signal is transmitted from a connector mounted on the printed circuit board to the bonding pad of the printed circuit board, via the first bonding wire to the first pad of the second quantum chip, and input to the coupling circuit via the first transmission line, the second pad, the second bonding wire, the second transmission line, and the coupling port, and / or The coupling circuit is tested using a signal transmitted from the coupling circuit of the second quantum chip through the coupling port to the second transmission line, the second bonding wire, the second pad, the first transmission line, the first pad, and transmitted from the bonding pad of the printed circuit board to the connector via the first bonding wire.

[0076] Furthermore, the disclosures of Patent Document 1 and Non-Patent Documents 1 and 2 mentioned above are incorporated herein by reference. Within the framework of the full disclosure of the present invention (including the claims), further modifications and adjustments to the embodiments or examples are possible based on the fundamental technical concept. Also, within the framework of the claims of the present invention, various combinations or selections of various disclosed elements (including each element in each appendix, each element in each embodiment, each element in each drawing, etc.) are possible. In other words, the present invention naturally includes various modifications and alterations that a person skilled in the art could make in accordance with the full disclosure, including the claims, and the technical concept. [Explanation of Symbols]

[0077] 1. The first quantum chip (quantum chip) 2.2' Second quantum chip (quantum chip) 3.3' Quantum Devices 10⁻¹, 10A⁻¹ First qubit 10⁻², 10A⁻² Second qubit 11-1 First Beer 11-2 Second Beer 12A-1, 12A-2, 12B-1, 12B-2, 12C-1, 12C-2 transmission lines 13A-1, 13A-2, 13B-1, 13B-2, 13C-1, 13C-2 coupling ports 14 pads (beer pads) 15-1 First pad 15-2 Second pad 15-3 Third pad 15-4 Fourth Pad 16-1~16-4 Pads (Bonding Pads) 17 circuit boards 18. The first side 19. Second side 20, 20A combined circuit 21-1, 21-2 Beer 22A-1, 22A-2, 22B, 22C, 22D transmission lines 23-1, 23-2 coupling ports 24 pads 25-1 First pad (input / output pad) 25-2 Second pad (control pad) 26-1, 26-2, 26A-1, 26A-2 pads 27 Circuit board (second circuit board) 28. First surface 29. Second side (reverse side) 30 control lines 31 Printed circuit boards 32 Aperture 33-1~33-6 Pads (Bonding Pads) 34-1~34-3, 34A-1, 34A-2, 34B-1, 34B-2, 34C-1, 34C-2 Bonding Wires 35-1~35-6 Connectors 36-1~36-6 Transmission lines 37 Support part

Claims

1. A first quantum chip comprising a first substrate and at least two qubits disposed on a first surface of the first substrate, A second quantum chip comprising a second substrate and a coupling circuit disposed on the first surface of the second substrate, Equipped with, The first quantum chip is Each of the at least two qubits disposed on the first surface of the first substrate has at least two vias that are electrically connected to each of the at least two qubits and penetrate from the first surface of the first substrate to the second surface opposite to the first surface, The second quantum chip described above is On the first surface of the second substrate, The coupling port for testing the coupling circuit, A first pad for inputting and / or outputting a test signal to the coupling circuit, Furthermore, In the second quantum chip, the first pad and the coupling port are electrically connected for testing the coupling circuit. After the above test, the second quantum chip, with the connection between the first pad and the coupling port disconnected, is bonded to the first quantum chip. A quantum device in which the first quantum chip bonded to the second quantum chip is electrically connected to the coupling circuit of the second quantum chip via at least two vias, each of the at least two qubits.

2. The second quantum chip comprises at least two vias that penetrate from the first surface of the second substrate to the second surface opposite to the first surface, corresponding to the positions of the at least two vias on the second surface of the first quantum chip. On the first surface of the second substrate of the second quantum chip, the at least two vias are each electrically connected to the coupling circuit. The quantum device according to claim 1, wherein the second surface of the first quantum chip and the second surface of the second quantum chip are bonded together.

3. The quantum device according to claim 2, wherein at least one of the ends of the at least two vias on the second surface of the first substrate of the first quantum chip is provided with a pad covering the end of the via.

4. The second quantum chip is provided with at least two pads on the first surface of the second substrate, corresponding to the positions of each of the at least two vias on the second surface of the first quantum chip. On the first surface of the second substrate of the second quantum chip, the at least two pads are each electrically connected to the coupling circuit. The quantum device according to claim 1, wherein the second surface of the first quantum chip and the first surface of the second quantum chip are bonded together.

5. The quantum device according to claim 4, wherein at least one of the ends of the at least two vias on the second surface of the first substrate of the first quantum chip is provided with a pad covering the end of the via.

6. The second quantum chip described above is On the first surface of the second substrate, A second pad connected to the first pad via a first transmission line, A third pad connected to the coupling port via a second transmission line, Furthermore, During testing of the coupling circuit, the second pad and the third pad are connected by a conductive member. The quantum device according to any one of claims 1 to 5, wherein after the test, the conductive member is removed and the second pad and the third pad are electrically disconnected.

7. A quantum device comprising at least two qubits and a coupling circuit for interacting the at least two qubits, A method for constructing a quantum device comprising bonding together a first quantum chip having at least two qubits on a first surface of a first substrate and a second quantum chip having the coupling circuit on a first surface of a second substrate, The first quantum chip is provided with at least two vias that are electrically connected to the at least two qubits and penetrate the first substrate of the first quantum chip from the first surface to the second surface opposite to the first surface. On the first surface of the second substrate of the second quantum chip, a coupling port for testing the coupling circuit and a first pad for inputting and / or outputting test signals to the coupling circuit are provided. The coupling circuit is tested by electrically connecting the first pad on the first surface of the second quantum chip with the coupling port. After the above test, the connection between the first pad on the first surface of the second quantum chip and the coupling port is made disconnected, and then the second quantum chip and the first quantum chip are bonded together. A method for configuring a quantum device, wherein in the first quantum chip bonded to the second quantum chip, the at least two qubits are each connected to the coupling circuit of the second quantum chip via at least two vias.

8. The second quantum chip is provided with at least two vias corresponding to the positions of the at least two vias on the second surface of the first quantum chip, which penetrate the second substrate of the second quantum chip from the first surface to the second surface opposite to the first surface. On the first surface of the second substrate of the second quantum chip, at least two vias are electrically connected to the coupling circuit, A method for constructing a quantum device according to claim 7, wherein the second surface of the first quantum chip and the second surface of the second quantum chip are bonded together.

9. On the first surface of the second substrate of the second quantum chip, at least two pads are provided, corresponding to the positions of the at least two vias on the second surface of the first quantum chip. Each of the at least two pads is electrically connected to the coupling circuit. A method for constructing a quantum device according to claim 7, wherein the second surface of the first quantum chip and the first surface of the second quantum chip are bonded together.

10. In testing the coupling circuit of the second quantum chip, The first pad on the first surface of the second quantum chip and the bonding pad of the printed circuit board are connected by a first bonding wire. On the first surface of the second quantum chip, a second pad connected to the first pad via a first transmission line and a third pad connected to the coupling port via a second transmission line are connected by a second bonding wire. A signal is transmitted from a connector mounted on the printed circuit board to the bonding pad of the printed circuit board, via the first bonding wire, to the first pad of the second quantum chip, and input to the coupling circuit via the first transmission line, the second pad, the second bonding wire, the second transmission line, and the coupling port, and / or A method for configuring a quantum device according to claim 7, wherein the coupling circuit is tested using a signal transmitted from the coupling circuit of the second quantum chip through the coupling port to the second transmission line, the second bonding wire, the second pad, the first transmission line, the first pad, and transmitted from the bonding pad of the printed circuit board to the connector via the first bonding wire.

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