Silicon carbide semiconductor equipment

Abstract

To provide a silicon carbide semiconductor device capable of suppressing bipolar deterioration.SOLUTION: A p++ type outer periphery contact region 43 is provided in an edge termination region, and surrounds an active region in a rectangular shape in which a corner is circularly curved. The p++ type outer periphery contact region 43 faces a gate runner on a front surface of a semiconductor substrate 30 via an insulation layer. The active region is provided with a p++ type region 44 facing a gate pad on the front surface of the semiconductor substrate 30 via the insulation layer. The p++ type outer periphery contact region 43 and the p++ type region 44 are provided separated from a p++ type contact region 6 forming a source electrode and a source contact. The p++ type contact region 6 and a contact hole 11a in which the source contact is formed are arranged in a uniform layout over the whole active region so that the center side and the end side of the active region become the same layout.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] This invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field-effect transistors with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) have a body diode built into the semiconductor substrate. The body diode of a MOSFET is p ++ Type-type contact region and p-type base region and n - Type drift region and n + This is a parasitic PIN (p-intrinsic-n) diode formed at the pn junction (main junction) with the drain region.

[0003] This section describes the structure of a conventional SiC-MOSFET using silicon carbide (SiC) as the semiconductor material. Figure 8 is a plan view showing the layout of a conventional silicon carbide semiconductor device as seen from the front side of the semiconductor substrate. Figures 9-11 are plan views showing enlarged portions of Figure 8. Figures 9-11 show p ++ Different layout examples of the type contact region 111 are shown. Figures 9-11 all show (a) the portion of the rectangular frame AA in Figure 8 (near the corner of the active region 101) and (b) the portion of the rectangular frame BB in Figure 8 ( p ++ type This shows the vicinity of the corner of region 114.

[0004] The conventional silicon carbide semiconductor device 110 shown in Figures 8-11 is a vertical SiC-MOSFET equipped with a general trench gate structure (not shown) on the front side of the semiconductor substrate 100 in the active region 101. The trench gate structure consists of a p-type base region and n + Type source area, p ++ It consists of a type contact region 111 (see Figures 9-11), a gate trench, a gate insulating film, and a gate electrode. ++-type contact region 111, p-type base region and n - -type drift region and n + -type drain region forms a body diode via a pn junction (not shown).

[0005] The gate trenches extend in a stripe shape along the first direction X parallel to the front surface of the semiconductor substrate 100. Between adjacent gate trenches (mesa portions), between the front surface of the semiconductor substrate 100 and the p-type base region, in contact with the p-type base region, n + -type source region and p ++ -type contact region 111 is selectively provided. n + -type source region and p ++ -type contact region 111 makes ohmic contact with a source electrode (not shown) on the front surface of the semiconductor substrate 100 via a contact hole 112 in an interlayer insulating film (not shown).

[0006] p ++ -type contact region 111 is provided spaced apart from the gate trenches at the center in the second direction Y orthogonal to the first direction X parallel to the front surface of the semiconductor substrate 100 between adjacent gate trenches (not shown), and is scattered in an island shape at a predetermined pitch in the first direction X (FIGS. 9 to 11). One p ++ -type contact region 111 constitutes one unit cell of the SiC-MOSFET (functional unit of the element: the portion surrounded by the rectangular frame 103 in FIG. 9) in the trench gate structure, and a plurality of unit cells are arranged adjacent to each other in the first and second directions X and Y, respectively.

[0007] p ++ -type contact region 111 scattered in an island shape enables reduction of cell pitch (arrangement interval of unit cells) compared to the case where p ++ -type contact region 111 extends in a stripe shape in the longitudinal direction of the gate trenches (the first direction X) with approximately the same length as the gate trenches. Compared to the center side of the active region 101 (chip center: the center of the semiconductor substrate 100), in the vicinity of the inner periphery of the p ++ -type outer peripheral contact region 113 surrounding the active region 101 and directly below a gate pad (not shown) p++ type Near the outer edge of region 114, there is a relatively large surface area p ++ A type contact area 111 is positioned.

[0008] p ++ As an example of the layout of the type contact area 111, p ++ The parts 104a, 104b facing the outer peripheral contact area 113 and the p directly below the gate pad ++ In the parts 105a and 105b opposite the type region 114, p ++ A structure is known in which the type contact region 111 extends relatively long in the first direction X (Figures 9-11). Also, in the second direction Y, p ++ Outer peripheral contact area 113 and p ++ In the parts 104b and 105b opposite the type region 114, p ++ A structure is known in which the width w101 in the second direction Y of the type contact region 111 is relatively widened (Figures 9, 10(a), 11(a)).

[0009] Furthermore, in the second direction Y, the outermost (chip edge side: edge side of semiconductor substrate 100) p ++ The end 111a of the type contact region 111 is p ++ A structure is known in which the portion 104c of the outer peripheral contact region 113 of the mold, facing the corner 113a, has a fan-shaped planar shape with a central angle of 90 degrees, having a curved arc along the inner circumference of the corner 113a. Furthermore, in this portion 104c, p ++ p adjacent to the end 111a of the fan-shaped planar contact region 111 ++ A structure is known in which the type contact region 111 is extended relatively long in the first direction X (Figures 10(a), 11(a)).

[0010] The outermost p in the second direction Y ++ The end 111a of the type contact region 111 has a width corresponding to the radius R101 of the fan-shaped planar shape, and has multiple adjacent p in the second direction Y. ++ Type contact area 111 and p ++It is positioned protruding between the outer peripheral contact area 113 of the mold (Figures 10(a), 11(a)). Figure 11(a) shows that, compared to Figure 10(a), p ++ This shows the case where the radius R101 of the end 111a of the type contact region 111 is increased by about 10 times. The contact hole 112 is exposed to p ++ It has a planar shape that is approximately the same size and shape as the type contact area 111 (not shown in Figure 11(a)).

[0011] p ++ The outer peripheral contact region 113 is provided in the edge termination region 102 between the front surface of the semiconductor substrate 100 and the p-type base region (not shown), in contact with the p-type base region. ++ The outer peripheral contact region 113 is electrically connected to the source electrode. ++ The outer peripheral contact region 113 surrounds the active region 101, which has a roughly rectangular planar shape, in a roughly rectangular shape along the boundary between the active region 101 and the edge termination region 102. ++ The corners 113a of the outer contact region 113 of the mold are curved in an arc shape with a predetermined curvature.

[0012] p ++ The p-type region 114 is provided in the active region 101 between the front surface of the semiconductor substrate 100 and the p-type base region, in contact with the p-type base region, and faces the gate pad on the front surface of the semiconductor substrate 100 via an insulating layer. ++ The type region 114 is located near the boundary between the active region 101 and the edge termination region 102, p ++ It is electrically connected to the source electrode via the outer peripheral contact region 113. ++ The mold region 114 has a substantially rectangular planar shape that faces the entire surface of the gate pad, which has a substantially rectangular planar shape.

[0013] In the conventional silicon carbide semiconductor device 110 described above, unlike during normal operation (when the drain-source is forward-biased), the drain-source is reverse-biased during the dead time of synchronous rectification of the SiC-MOSFET and during energy regeneration to the load side by the SiC-MOSFET. Therefore, p++ Type 1 contact region 111 and p-type base region and n - Type drift region and n + When the pn junction (main junction) with the drain region is forward-biased, the body diode conducts, and a forward current (hole current) flows through the body diode.

[0014] As a conventional SiC-MOSFET, p ++ The outer peripheral contact area of ​​the mold is in the longitudinal direction of the gate trench, n + A device has been proposed that improves current controllability by gate voltage control by positioning the type source region separately from the gate trench, or by positioning it separately from the gate trench in the short direction of the gate trench (see, for example, Patent Document 1 below). In Patent Document 1 below, p ++ The type contact regions and contact holes are scattered at predetermined intervals along the longitudinal direction of the gate trench, and each contact hole has a different p ++ The contact area is exposed. [Prior art documents] [Patent Documents]

[0015] [Patent Document 1] Japanese Patent Publication No. 2020-004876 [Overview of the Initiative] [Problems that the invention aims to solve]

[0016] However, in the conventional silicon carbide semiconductor device 110 described above (see Figures 8-11), when the body diode conducts (forward current conduction), so-called bipolar degradation (forward current conduction degradation due to the body diode) occurs, such as an increase in the on-voltage Von and an increase in the forward voltage Vf. The reason for this is that the conduction of the body diode causes basal plane dislocations (BPDs) to grow in the semiconductor substrate 100, which uses silicon carbide as the semiconductor material, resulting in stacking faults (SFs) and thus increasing conduction losses.

[0017] The semiconductor substrate 100 is n + n becomes the type drain region + The structure is formed by epitaxially growing a predetermined conductivity type epitaxial layer on a starting substrate, and the trench gate structure is formed in the surface region of the epitaxial layer. When the body diode conducts, a forward current flows through the body diode, p ++ From the type contact region 111 through the p-type base region, n - The number of holes injected into the drift region is n - The silicon carbide recombines with electrons within the drift region. The energy of light or other sources close to the band gap of the silicon carbide emitted by this recombination causes the BPD in the semiconductor substrate 100 to grow, resulting in stacking faults.

[0018] BPD is n + It is commonly found in type starting substrates, and generally, n + The BPD of the starting substrate is n + Type starting substrate and n - Type epitaxial layer (n - From the interface with the drift region (type drift region) - Within the mold drift region, along the (0001) plane, it grows in the <11-20> direction at an angle corresponding to the off-angle (usually around 4 degrees), forming a stacking fault. The stacking fault grows to the vicinity of the pn junction interface, and further n - The type drift region expands in the <1-100> direction. This expansion of stacking faults occurs when holes reach a critical concentration of 1 × 10⁻¹⁰. 15 / cm 3 This process proceeds throughout the entire active region present. Stack faults act as resistance components in the electron flow, leading to increased conduction losses and bipolar degradation.

[0019] p ++ In the parts where the contact region 111 and contact hole 112 are relatively long or wide, such as parts 104a-104c, 105a, and 105b, the semiconductor substrate 100 The internal resistance of the body diode decreases, making it easier for the forward current (hole current) to flow through the body diode, and thus increasing the hole current density. As a result, n + Type starting substrate and n -The hole current density at the interface with the epitaxial layer increases, exceeding the threshold for stacking fault growth. For example, in conventional structures (see Figures 8-11), the forward current density of the body diode is 200 A / cm². 2 ~400A / cm 2 The inventors have confirmed that stacking faults appear when this condition is met.

[0020] The purpose of this invention is to provide a silicon carbide semiconductor device that can suppress bipolar degradation in order to solve the problems of the prior art described above. [Means for solving the problem]

[0021] To solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention has the following features: An active region is provided on a semiconductor substrate made of silicon carbide. A first semiconductor region of a first conductivity type is provided inside the semiconductor substrate. A second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first semiconductor region in the active region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface and the second semiconductor region. A fourth semiconductor region of a second conductivity type is selectively provided between the first main surface and the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. A trench penetrates the third and second semiconductor regions and reaches the first semiconductor region. A gate electrode is provided inside the trench via a gate insulating film. An interlayer insulating film is provided on the first main surface and covers the gate electrode. A contact hole is provided that penetrates the interlayer insulating film in the depth direction and reaches the first main surface. The contact hole exposes the fourth semiconductor region and the third semiconductor region. The first electrode is in contact with the third semiconductor region and the fourth semiconductor region through the contact hole. The second electrode is in contact with the second main surface of the semiconductor substrate. A fifth semiconductor region of second conductivity type is selectively provided between the first main surface and the first semiconductor region, separated from the fourth semiconductor region. The fifth semiconductor region surrounds the active region and is electrically connected to the first electrode.The fourth semiconductor region is arranged in a uniform layout across the entire active region. The contact holes are also arranged in a uniform layout across the entire active region. The trenches extend in a stripe-like manner in a first direction parallel to the first main surface. The active region has a rectangular planar shape with its corners curved in an arc shape. The inner circumference of the fifth semiconductor region has a rectangular planar shape with its corners curved in an arc shape along the active region, and the shortest distance from the fourth semiconductor region to the fifth semiconductor region is equal in the first direction between all adjacent trenches.

[0022] Furthermore, the silicon carbide semiconductor device according to this invention is, in the above invention ,before The fourth semiconductor region is characterized by being positioned between all adjacent trenches, having the same width in a second direction parallel to the first main surface and perpendicular to the first direction, and extending linearly with the same length in the first direction.

[0023] Furthermore, the silicon carbide semiconductor device according to this invention is, in the above invention ,before The fourth semiconductor region is characterized by being located between all adjacent trenches, having the same dimensions and planar shape, and being equally spaced in the first direction.

[0026] Furthermore, the silicon carbide semiconductor device according to this invention includes, in the above-described invention, a sixth semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor region, which is selectively provided between the first main surface and the second semiconductor region, separated from the fourth semiconductor region, and electrically connected to the first electrode. Among all the trenches adjacent to each other, the shortest distance from the fourth semiconductor region to the sixth semiconductor region in the first direction is equal between the trenches facing the sixth semiconductor region in the first direction.

[0027] Furthermore, the silicon carbide semiconductor device according to this invention, in the invention described above, includes a gate pad provided on the interlayer insulating film, separated from the first electrode, and electrically connected to the gate electrode. The entire surface of the gate pad is characterized in that it faces the sixth semiconductor region via the interlayer insulating film.

[0028] Furthermore, the silicon carbide semiconductor device according to this invention is, in the above invention ,beforeThe fourth semiconductor region facing the corner of the active region and the fourth semiconductor region facing the outer periphery connecting the corners of the active region in the first direction are characterized in that the shortest distance to the outer periphery of the active region is equal in the first direction.

[0029] Furthermore, the silicon carbide semiconductor device according to this invention, in the invention described above, comprises a starting substrate made of silicon carbide and a first conductivity type epitaxial layer. The starting substrate becomes a seventh semiconductor region of the first conductivity type with a higher impurity concentration than the first semiconductor region. The first conductivity type epitaxial layer is provided on the starting substrate and is characterized by becoming the first semiconductor region.

[0030] According to the invention described above, variations in the internal resistance of the semiconductor substrate within the plane of the active region can be suppressed. As a result, variations in the current density of the forward current (hole current) of the body diode within the plane of the active region can be suppressed, and therefore, even when the body diode conducts, an increase in the hole current density within the semiconductor substrate can be suppressed. [Effects of the Invention]

[0031] The silicon carbide semiconductor device according to the present invention has the effect of suppressing bipolar degradation. [Brief explanation of the drawing]

[0032] [Figure 1] This is a plan view showing the layout of a silicon carbide semiconductor device according to an embodiment, as seen from the front side of the semiconductor substrate. [Figure 2] This is a cross-sectional view showing the cross-sectional structure along the cutting line A-A' in Figure 1. [Figure 3] This is a cross-sectional view showing the cross-sectional structure along the cutting line B-B' in Figure 1. [Figure 4] This is a cross-sectional view showing the cross-sectional structure at the cutting line C-C' in Figure 1. [Figure 5] This is a plan view showing an enlarged view of a partial layout example from Figure 1. [Figure 6] This is a plan view showing an enlarged view of a partial layout example from Figure 1. [Figure 7A] This diagram shows the layout of the p++ type contact region for each sample in the experimental example. [Figure 7B] This is a chart showing the verification results for each sample in the experimental example. [Figure 8] This is a plan view showing the layout of a conventional silicon carbide semiconductor device as seen from the front side of the semiconductor substrate. [Figure 9] This is a plan view showing an enlarged portion of Figure 8. [Figure 10] This is a plan view showing an enlarged portion of Figure 8. [Figure 11] This is a plan view showing an enlarged portion of Figure 8. [Modes for carrying out the invention]

[0033] Preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - prefixes to n and p indicate higher and lower impurity concentrations, respectively, than layers or regions without these prefixes. In the following description of embodiments and accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. In this specification, in Miller index notation, "-" indicates a bar attached to the exponent immediately following it, and a "-" before the exponent indicates a negative exponent. Furthermore, "approximately the same" means that they are identical in design and include variations due to manufacturing tolerances, for example, variations within ±5%.

[0034] (Embodiment) The structure of the silicon carbide semiconductor device according to the embodiment will be described. Figure 1 is a plan view showing the layout of the silicon carbide semiconductor device according to the embodiment as seen from the front side of the semiconductor substrate. Figures 2 to 4 are cross-sectional views showing the cross-sectional structure at the cutting lines A-A', B-B', and C-C' in Figure 1, respectively. Figure 2 shows the cell structure of the SiC-MOSFET arranged in the active region 51. Figure 2 shows four adjacent unit cells (functional units of the device). Figure 3 shows the structure of a part of the edge termination region 52. Figure 4 shows the structure directly below the gate pad 14 (n + The structure of the drain region (side 1) is shown.

[0035] Figures 5 and 6 are plan views showing enlarged versions of some layout examples from Figure 1. Figures 5 and 6 include p ++ Different layout examples of the type contact area 6 are shown. In both Figures 5 and 6, (a) shows the portion of the rectangular frame D in Figure 1 (near the corner (vertex of the rectangle) 51a of the active area 51), and (b) shows the portion of the rectangular frame E in Figure 1 (p directly below the gate pad 14). + Figures 5 and 6 show the vicinity of the corner of type region 44. ++ To clarify the layout of the type contact region 6, the p of each part that constitutes the trench gate structure in the active region 51 ++ Only the contact area 6 and contact hole 11a are shown; other parts are omitted from the illustration.

[0036] The silicon carbide semiconductor device 10 according to the embodiment shown in Figures 1 to 6 is a vertical SiC-MOSFET with a trench gate structure on the front side of the silicon carbide semiconductor substrate (semiconductor chip) 30 in the active region 51. The active region 51 is the region in which the main current (drift current) flows in a direction perpendicular to the front surface of the semiconductor substrate 30 when the silicon carbide semiconductor device 10 is turned on. Multiple unit cells of the same SiC-MOSFET structure are arranged adjacent to each other in the active region 51. The active region 51 has a substantially rectangular planar shape, for example, with its corners 51a beveled and curved in an arc shape, and is located approximately in the center of the semiconductor substrate 30 (center of the chip).

[0037] The edge termination region 52 is the region between the active region 51 and the edge (chip edge) of the semiconductor substrate 30, and surrounds the active region 51 in a roughly rectangular shape. The edge termination region 52 has the function of mitigating the electric field on the front side of the semiconductor substrate 30 and maintaining the breakdown voltage. Breakdown voltage is the limit voltage at which the silicon carbide semiconductor device 10 will not malfunction or be destroyed at the operating voltage. A general breakdown voltage structure such as a field limiting ring (FLR) composed of a p-type region 48 or a junction termination extension (JTE) structure is arranged in the edge termination region 52.

[0038] The semiconductor substrate 30 is made of n + n - The semiconductor substrate 30 is formed by sequentially epitaxially growing epitaxial layers 32 and 33, which will become a p-type drift region (first semiconductor region) 2 and a p-type base region (second semiconductor region) 4. The first main surface on the side of the p-type epitaxial layer 33 is the front surface, and n + The second main surface (n) on the mold starting substrate 31 side + The back surface of the mold starting substrate 31 is considered the back surface. + The front surface of the mold starting substrate 31 is a (0001) surface having an off-angle of about 4 degrees in the <11-20> direction, for example. + The starting substrate 31 is n + This is the drain region (seventh semiconductor region) 1.

[0039] The trench gate structure has a p-type base region 4, n + Type source region (third semiconductor region) 5, p ++ It consists of a type contact region (fourth semiconductor region) 6, a gate trench 7, a gate insulating film 8, and a gate electrode 9. The gate trench 7 penetrates the p-type epitaxial layer 33 from the front surface of the semiconductor substrate 30 in the depth direction Z and n - The gate trench 7 reaches the first conductive epitaxial layer (first conductive epitaxial layer) 32 and terminates inside the n-type JFET region 3, which will be described later. The gate trench 7 extends in a stripe shape in a first direction X parallel to the front surface of the semiconductor substrate 30.

[0040] The longitudinal direction (first direction X) of the gate trench 7 is, for example, the <11-20> direction, and the transverse direction of the gate trench 7 (second direction Y, which is parallel to the front surface of the semiconductor substrate 30 and orthogonal to the first direction X) is, for example, the <1-100> direction. A gate electrode 9 is provided inside the gate trench 7 with a gate insulating film 8 interposed therebetween. Between adjacent gate trenches 7 (mesa portions), between the front surface of the semiconductor substrate 30 and n - -type drift region 2, a p-type base region 4, an n + -type source region 5 and a p ++ -type contact region 6 are each selectively provided.

[0041] p ++ -type contact region 6, p-type base region 4 and p + -type regions 21 and 22 described below, and n-type JFET region 3 described below, n-type current diffusion region 3a described below, n - -type drift region 2 and n + -type drain region 1 form a body diode (parasitic pin diode) through a pn junction (main junction) 34. An n + -type source region 5 and a p ++ -type contact region 6 are diffusion regions formed by ion implantation inside a p-type epitaxial layer 33. A portion of the p-type epitaxial layer 33 excluding these diffusion regions formed by ion implantation is the p-type base region 4. The p-type base region 4 is provided over the entire area between mutually adjacent gate trenches 7.

[0042] n + -type source region 5 and a p ++ -type contact region 6 are selectively provided between the front surface of the semiconductor substrate 30 and the p-type base region 4. An n + -type source region 5 and a p ++ -type contact region 6 are in contact with the p-type base region 4 at the lower surface (the surface on the n + -type drain region 1 side), and are in ohmic contact with the source electrode (first electrode) 12 at the front surface of the semiconductor substrate 30. An n +The mold source region 5 is in contact with the gate insulating film 8 at the side wall of the gate trench 7 and extends in the first direction X for approximately the same length as the gate trench 7 (length in the longitudinal direction). ++ The type contact region 6 is provided away from the gate trench 7, n + Adjacent to type source region 5. ++ The contact region 6 is arranged in a uniform layout across the entire active region 51.

[0043] p ++ The uniform layout of the contact area 6 is as follows: p ++ The type contact area 6 is provided in all mesa portions with substantially the same planar shape and substantially the same dimensions. Specifically, p ++ The type contact region 6 extends linearly in the first direction X with approximately the same width (width in the second direction Y) and approximately the same length at approximately the center of the second direction Y of each mesa portion (Figure 5), or is scattered in an island-like manner at a predetermined pitch in the first direction X with approximately the same dimensions and approximately the same planar shape (Figure 6). That is, p ++ The contact areas 6 are arranged in either a stripe pattern, all terminating at approximately the same position in the first direction X, or in a dot pattern (matrix pattern) with approximately the same dimensions and planar shape, and equally spaced in the first direction X.

[0044] P in the first direction X ++ From the type contact region 6 to the edge termination region 52, the following p ++ It is preferable that the shortest distance x1 to the outer peripheral contact region 43 of the mold is approximately the same for all mesa portions. In this case, all gate trenches 7 terminate at approximately the same position in the first direction X. That is, even if the corner 51a of the active region 51 is curved in an arc shape, the outermost (tip end side) p in the second direction Y ++ The end of the type contact region 6 is different from the conventional structure (see Figure 9(a)) ++ Without terminating inward in the first direction X beyond the type contact region 6, other p in the first direction X ++ The end of the type contact area 6 and omitted Terminate at the same position.

[0045] P in the first direction X ++ Type contact area 6 to p ++ Even if the shortest distance x1 to the outer peripheral contact region 43 becomes relatively slightly longer (for example, by about 1 μm to 2 μm) near the corner 51a of the active region 51, this is acceptable because the current density of the forward current of the body diode increases by only about 1%. For example, p ++ When the type contact region 6 extends linearly in the first direction X, the end is located near the corner 51a of the active region 51. ++ Regarding the length of the type contact region 6 (length extending in the first direction X), other p ++ The effects of this embodiment can be obtained if the length of the contact area 6 is within -5%.

[0046] P in the first direction X ++ Type contact area 6 to p ++ The shortest distance x1 to the outer peripheral contact area 43 is p ++ Type contact region 6 (in each mesa portion, p ++ When the type contact region 6 is scattered in an island-like manner in the first direction X, the outermost p in the first direction X ++ From the type contact area 6) to p ++ This is the distance in the first direction X to the outer peripheral contact region 43 of the mold. Also, p ++ The width of the type contact region 6 in the second direction Y is all p ++ The contact region 6 is approximately the same, and the outermost p is in the second direction Y. ++ The layout at the edge of the type contact area 6 will not be one in which the width is locally widened as in the conventional structure (see Figures 10(a) and 11(a)).

[0047] Furthermore, in the first direction X, p, which will be described later, ++ In all mesa portions facing the mold region 44, in the first direction X, p ++ Type contact area 6 to p ++ The shortest distance x2 to type region 44 is approximately the same. In the first direction X, p ++ In the mesa portion facing the mold region 44, in the first direction X, p ++ Type contact area 6 to p ++ The shortest distance x2 to type region 44 is p++ Type contact region 6 (in each mesa portion, p ++ When the type contact region 6 is scattered in an island-like manner in the first direction X, the most p in the first direction X ++ p on the type region 44 side ++ p of the contact area 6) ++ From the end of type region 44, p ++ This is the distance in the first direction X to type region 44.

[0048] Also, the outermost p in the second direction Y ++ Type contact region 6 (i.e., p in the second direction Y) ++ p opposite the outer peripheral contact area 43 ++ Type contact region 6) and the most p in the second direction Y ++ p on the type region 44 side ++ Type contact region 6 (i.e., p in the second direction Y) ++ p opposite type region 44 ++ The type contact region 6) is the central side of the active region 51. ++ It is arranged in the same layout as the type contact area 6, and unlike the conventional structure (see Figures 10 and 11), other p ++ The layout should not be one in which the width in the second direction Y is wider than the contact area 6, nor should it be a layout with a different planar shape.

[0049] Thus, the corner 51a of the active region 51 is curved in an arc shape, or the active region 51 is partially p ++ Even if the type region 44 is positioned, the layout will be almost the same on both the central and peripheral sides of the active region 51, with a uniform layout throughout the entire active region 51. ++ A type contact region 6 is arranged. p ++ The contact area 6 has relatively long or wide parts, unlike conventional structures (Figure 9 The parts indicated by symbols 104a~104c, 105a, and 105b in section 11 do not exist. Approximately the same length, approximately the same shape, and approximately the same distance mean that they are the same length, the same shape, and the same distance, respectively, within the range of tolerances due to variations in the manufacturing process.

[0050] 1 p ++ A single unit cell of a SiC-MOSFET is formed by a trench gate structure including a type contact region 6. Specifically, p ++ When the contact region 6 extends linearly in the first direction X, the unit cell of the SiC-MOSFET (the area enclosed by the dashed line 53 in Figure 5) is linear in the first direction X and multiple units are arranged adjacent to each other in the second direction Y. ++ When the contact regions 6 are scattered in an island-like manner, the unit cell of the SiC-MOSFET (the area enclosed by the dashed line 53 in Figure 6) is p ++ They are scattered in an island-like pattern at the same pitch as the type contact area 6, and multiple units are arranged adjacent to each other in the first and second directions X and Y, respectively.

[0051] Furthermore, in the active region 51, between the front surface of the semiconductor substrate 30 and the p-type base region 4, there is a n-type base region in contact with the p-type base region 4. + Type source region 5 and p ++ Separated from the type contact area 6, p ++ A type region (sixth semiconductor region) 44 is selectively provided. ++ The mold region 44 faces the gate pad 14 on the front surface of the semiconductor substrate 100 via the interlayer insulating film 11. ++ Type region 44 is p, which will be described later. ++ Connected to the outer peripheral contact area 43, p ++ It is electrically connected to the source electrode 12 via the outer peripheral contact region 43. ++ The mold region 44 has a roughly rectangular planar shape with approximately the same dimensions as the gate pad 14, and faces the entire surface of the gate pad 14.

[0052] p ++ The p-type region 44 is a diffusion region formed by ion implantation inside the p-type epitaxial layer 33. ++ Type region 44 is, for example, p ++ It is formed simultaneously with the type contact region 6. ++ Type region 44 and p (described later) ++ A unit cell of a SiC-MOSFET may be placed between the outer peripheral contact region 43 of the mold. ++ Type region 44 and p++ The p of the unit cell located between the outer peripheral contact region 43 and the type ++ Regarding the type contact region 6, the p of other unit cells ++ Since it is arranged in the same layout as the type contact area 6, as described above, p ++ The layout of the contact region 6 is uniform throughout the entire active region 51.

[0053] p-type base region 4 and n - Between the type drift region 2 and the bottom surface of the gate trench 7, n + Deep within the drain region 1 side, p + Type regions 21 and 22 and n-type JFET region 3 are selectively provided. + Type regions 21, 22 and n-type JFET region 3 and n - An n-type current diffusion region 3a is provided between the n-type drift region 2 and the n-type JFET region 3. The n-type current diffusion region 3a has approximately the same impurity concentration as the n-type JFET region 3, or the n-type JFET region 3 and n - This is the impurity concentration between the type drift region 2 and the specified region. + n-type regions 21, 22, n-type JFET region 3, and n-type current diffusion region 3a are n - This is a diffusion region formed inside the type epitaxial layer 32 by ion implantation. + n-type regions 21 and 22 and n-type JFET region 3 are n + The drain region 1 side may be terminated at the same depth position, or p + Type regions 21, 22 and n - An n-type current diffusion region 3a may extend between the n-type drift region 2 and the n-type current diffusion region 3a.

[0054] p + The n-type regions 21 and 22 are fixed at the potential of the source electrode 12 and have the function of depleting (or depleting the n-type JFET region 3, or both) when the SiC-MOSFET (silicon carbide semiconductor device 10) is off, thereby mitigating the electric field applied to the gate insulating film 8. + The mold regions 21 and 22 extend linearly in the first direction X for approximately the same length as the gate trench 7. +The mold region 21 is provided separately from the p-type base region 4 and faces the bottom surface of the gate trench 7 in the depth direction Z. + The mold region 21 may be in contact with the gate insulating film 8 at the bottom of the gate trench 7, or it may be separated from the gate trench 7.

[0055] p + The type region 22 is adjacent to the p-type base region 4 between the gate trenches 7 and the p + It is located separately from the type region 21. + The mold region 22 is positioned approximately at the center of the second direction Y of the mesa section (between adjacent gate trenches 7), and in the depth direction Z, p ++ It faces the type contact area 6. + The width of the second direction Y of type region 22 is the width of adjacent p + It is appropriately set according to the width of the n-type JFET (Junction FET) region 3 in the second direction Y between type regions 21 and 22, p ++ The width of the second direction Y of the type contact region 6 may be greater than or equal to, and p ++ The width of the contact region 6 in the second direction Y may be narrower than the width of the contact region 6.

[0056] p + Type region 22 is n + The part on the drain region 1 side and n + The impurity concentration may be approximately the same as that of the source region 5, or n + The part on the drain region 1 side and n + The n-type source region 5 may be a two-layer structure with different impurity concentrations stacked on top of each other. The n-type current spreading region 3a is a so-called current spreading layer (CSL) that reduces carrier spreading resistance. The n-type JFET region 3 is p + Adjacent to type regions 21 and 22, the upper surface (n + The surface on the source region 5 side is in contact with the p-type base region 4, and the bottom surface (n + The n-type current diffusion region 3a is in contact with the drain region 1 side. The n-type JFET region 3 is a region for guiding the electron current toward the lower surface with low resistance.

[0057] Furthermore, the n-type JFET region 3 extends to the gate trench 7 in the second direction Y and contacts the gate insulating film 8. The n-type JFET region 3 is not required. If the n-type JFET region 3 is not provided, instead of the n-type JFET region 3, n-type current diffusion regions 3a are arranged in adjacent p + The mold regions 21 and 22 extend to the p-type base region 4, and in the second direction Y, it reaches the gate trench 7 and comes into contact with the gate insulating film 8. - Among the type epitaxial layer 32, the diffusion region due to ion implantation (p + The portion excluding the n-type regions 21, 22, n-type JFET region 3, and n-type current diffusion region 3a) is n - This is type drift region 2.

[0058] The interlayer insulating film 11 is provided over the entire surface of the front surface of the semiconductor substrate 30 and covers the gate electrode 9. Contact holes 11a are provided in the interlayer insulating film 11 in a uniform layout throughout the entire active region 51. That is, the contact holes 11a are provided in all mesa portions with substantially the same planar shape and substantially the same dimensions, n + Type source region 5 and p ++ The contact area 6 is exposed. Specifically, the contact holes 11a extend linearly in the first direction X (strip-like in the plane of the active area 51) in each mesa portion with approximately the same width (width in the second direction Y) and approximately the same length in the first direction X. All p of the same mesa portion are exposed to the contact holes 11a of each mesa portion. ++ The entire surface of the type contact area 6 is exposed.

[0059] The source electrode 12 is connected to the front surface of the semiconductor substrate 30 via the contact hole 11a of the interlayer insulating film 11. + Type source region 5 and p ++ Ohmic contact is made with the type contact region 6, n + Type source area 5, p ++The source electrode 12 is electrically connected to the p-type contact region 6 and the p-type base region 4. The source electrode 12 covers almost the entire surface of the front surface of the semiconductor substrate 30 in the active region 51. The source electrode 12 has a roughly rectangular planar shape (not shown) with a portion recessed inward (towards the center of the chip). The source electrode 12 also serves as a source pad (electrode pad). A gate pad 14 is provided on the interlayer insulating film 11 in the active region 51, separated from the source electrode 12.

[0060] All gate electrodes 9 are electrically connected to the gate pad 14 via gate runners, which will be described later. The gate pad 14 has, for example, a roughly rectangular planar shape (not shown). The gate pad 14 is provided, for example, in a recessed area of ​​the source electrode 12 near the boundary between the active region 51 and the edge termination region 52, with three sides facing the source electrode 12. The drain electrode (second electrode) 13 is on the back surface (n) of the semiconductor substrate 30. + It is provided on the entire surface of the back surface of the starting substrate 31. The drain electrode 13 makes ohmic contact with the back surface of the semiconductor substrate 30, n + Type drain region 1(n + It is electrically connected to the mold starting substrate 31).

[0061] In the edge termination region 52, between the active region 51 and the breakdown structure, the front surface of the semiconductor substrate 30 and n - Between the active region 51 and the n-type drift region 2, the p-type base region 4 extends. Hereinafter, the portion of the p-type base region 4 extending to the edge termination region 52 will be referred to as the p-type base extension portion 42. The p-type base extension portion 42 and n - Between type drift region 2 and p + A type region 41 is provided. + Type region 41 is, for example, p of active region 51 + This is a diffusion region formed simultaneously with the p-type region 22 within the p-type epitaxial layer 33. + The type region 41 is directly below the gate pad 14 (n + p-type base region 4 and n (on the drain region 1 side) - It may extend between the type drift region 2 and the other region.

[0062] Between the front surface of the semiconductor substrate 30 and the p-type base extension portion 42, a p-type base extension portion 42 is in contact with the p-type base extension portion 42. ++ A type outer peripheral contact region (fifth semiconductor region) 43 is provided. ++ The outer peripheral contact region 43 is, for example, the p of the active region 51. ++ This is a diffusion region formed simultaneously within the p-type epitaxial layer 33 and the type-type contact region 6. ++ The outer peripheral contact region 43 surrounds the active region 51 in a roughly rectangular shape along the boundary between the active region 51 and the edge termination region 52. ++ The corners 43a of the outer peripheral contact area 43 of the mold are curved in an arc shape with a predetermined curvature. ++ p ++ Type regions 44 are linked.

[0063] p ++ The outer peripheral contact region 43 of the p-type is electrically connected to the source electrode 12 via the p-type base extension portion 42. ++ The p-type outer peripheral contact region 43 has the function of suppressing the potential rise in the region directly below the gate pad 14 (p-type outer peripheral region 40) due to a sharp increase in the voltage applied to the drain electrode 13. ++ The surface of the outer peripheral contact region 43 (the front surface of the semiconductor substrate 30) is covered with a field oxide film 45. ++ Type outer peripheral contact area 43, p-type base extension portion 42 and p + The p-type outer peripheral region 40, formed by stacking the type regions 41, surrounds the active region 51 in a roughly rectangular shape.

[0064] A field oxide film 45 is provided between the front surface of the semiconductor substrate 30 and the interlayer insulating film 11 in the edge termination region 52. The field oxide film 45 may extend between the front surface of the semiconductor substrate 30 and the interlayer insulating film 11 in the active region 51 so as to face the entire surface of the gate pad 14. A gate polysilicon wiring layer 46 is provided between the field oxide film 45 and the interlayer insulating film 11 between the active region 51 and the breakdown structure. A gate metal wiring layer 47 is provided on the gate polysilicon wiring layer 46 via contact holes 11b of the interlayer insulating film 11.

[0065] The gate metal wiring layer 47 is connected to the gate pad 14. The gate polysilicon wiring layer 46 and the gate metal wiring layer 47 form a gate runner surrounding the active region 51. The gate electrode 9 is connected to the gate polysilicon wiring layer 46 at the longitudinal end of the gate trench 7. All gate electrode 9 are electrically connected to the gate pad 14 via the gate polysilicon wiring layer 46 and the gate metal wiring layer 47. The entire surface of the gate runner is connected in the depth direction Z via an insulating layer (field oxide film 45 and interlayer insulating film 11) ++ Type outer peripheral contact area 43, p-type base extension portion 42 and p + It opposes all of type domain 41.

[0066] The operation of the silicon carbide semiconductor device 10 (SiC-MOSFET) according to this embodiment will be described. During normal operation, a positive voltage is applied to the drain electrode 13 relative to the source electrode 12 (the drain-source is forward biased), p ++ Type 6 contact area, p-type base area 4 and p + type regions 21 and 22, n-type JFET region 3, and n-type current diffusion regions 3a and n - Type drift regions 2 and n + The drain region 1 and the pn junction 34 are reverse-biased. In this state, if the voltage applied to the gate electrode 9 is less than the gate threshold voltage, the SiC-MOSFET remains in the off state.

[0067] On the other hand, when a positive voltage is applied to the drain electrode 13 relative to the source electrode 12 and a voltage greater than the gate threshold voltage is applied to the gate electrode 9, a channel (n-type inversion layer) is formed in the p-type base region 4 along the side wall of the gate trench 7. As a result, n + Type drain region 1 to n - n-type drift region 2, n-type current diffusion region 3a, n-type JFET region 3, and n through the channel + A main current (drift current) flows towards the source region 5, and the SiC-MOSFET (silicon carbide semiconductor device 10) turns on.

[0068] Furthermore, during the dead time of synchronous rectification of the SiC-MOSFET, and during energy regeneration to the load side by the SiC-MOSFET, the drain-source connection is reverse-biased. Therefore, p ++ Type 6 contact area, p-type base area 4 and p + type regions 21 and 22, n-type JFET region 3, and n-type current diffusion regions 3a and n - Type drift regions 2 and n + When the pn junction 34 of the drain region 1 is forward-biased, the body diode conducts (forward current flows), and p ++ The forward current of the body diode flows inside the outer peripheral contact region 43 of the type.

[0069] As mentioned above, p ++ The uniform layout of the contact region 6 and contact holes 11a across the entire active region 51 suppresses variations in the internal resistance of the semiconductor substrate 30 within the plane of the active region 51. This suppresses variations in the current density of the forward current (hole current) of the body diode within the plane of the active region 51, and even when the body diode conducts, n + Type starting substrate 31 and n - The hole current density at the interface with the type epitaxial layer 32 is less likely to exceed the threshold for stacking fault (SF) growth.

[0070] Therefore, compared to the conventional structure (see Figures 8-11), n ​​when the body diode conducts, +This makes it possible to suppress the growth of stacking faults from basal plane dislocations (BPDs) in the starting substrate 31. Specifically, in the conventional structure, the current density of the forward current of the body diode is 200 A / cm². 2 ~400A / cm 2 While stacking faults appeared when the current density of the forward current of the body diode was 500 A / cm², in this embodiment, the current density of the forward current of the body diode was 500 A / cm². 2 The inventors have confirmed that stacking faults appear when the stacking pressure reaches a certain level.

[0071] As described above, according to the embodiment, p forms source contact with the source electrode. ++ The type contact region and the contact holes where the source contact is formed are arranged uniformly throughout the entire active region, with the same layout both on the central and edge sides of the active region. This suppresses variations in the internal resistance of the semiconductor substrate within the plane of the active region, and suppresses variations in the current density of the forward current (hole current) of the body diode within the plane of the active region. Therefore, even when the body diode conducts, n + Type starting substrate and n - This method can suppress the increase in hole current density at the interface with the epitaxial layer, thereby suppressing bipolar degradation.

[0072] (Example of experiment) p ++ The relationship between the layout of the contact region 6 and bipolar degradation was investigated. Figure 7A shows the p for each sample in the experimental example. ++ This is a diagram showing the layout of the contact area. Figure 7B is a diagram showing the verification results for each sample in the experimental example. Figure 7B shows the probability of bipolar degradation failure occurring for each sample in the experimental example (semiconductor chips on which vertical SiC-MOSFETs were fabricated), expressed as the number of semiconductor chips with bipolar degradation failure (numerator) relative to the total number of semiconductor chips evaluated (denominator). A semiconductor chip in which the on-voltage Von increased by 10% before and after conduction of the body diode is considered to have bipolar degradation failure.

[0073] The design conditions for experimental samples 1 to 7 are shown in Figure 7A. Samples 1 to 4 are trench gate vertical SiC-MOSFETs with the structure of the silicon carbide semiconductor device 10 (see Figures 1 to 6) according to the above-described embodiment, and have a uniform layout throughout the entire active region 51. ++ A type contact region 6 is positioned. Specifically, samples 1 to 3 are p ++ The type contact region 6 was extended in a stripe-like manner in the first direction X with the same width and length across the entire active region 51 (Figure 5). Sample 4 was p ++ The type contact regions 6 were scattered in an island-like (dot-like) pattern across the entire active region 51, with the same dimensions and planar shape (Figure 6).

[0074] Samples 1-3 had cell pitches of 4.5 μm, 5 μm, and 7 μm, respectively, and the p-value was calculated based on the area (surface area) of one unit cell. ++ Area of ​​contact region 6 ratio (Hereafter, p ++ The area occupancy of the contact region 6 was set to 22.2%, 20%, and 14.2%, respectively. Sample 4 had a cell pitch of 6 μm, and p ++ The area occupancy rate of type contact region 6 was set to 16.7%. For all samples 1 to 4, p ++ The layout of the contact region 6 is the same on both the central and peripheral sides of the active region 51 (indicated as "uniform" in the diagram). Sample 1~ 3 In both cases, the contact holes 11a were arranged in a stripe pattern extending in the first direction X with the same width and length.

[0075] Samples 5-7 had p scattered in an island-like (dot-like) pattern in the active region. ++ This is a vertical SiC-MOSFET with a planar gate structure in which the surface area of ​​the type contact region is locally increased. For all samples 5 to 7, the cell pitch is 10.2 μm, and p ++ The area occupancy rate of the type contact region was set to 13.7%. Specifically, for samples 5-7, the outermost p in the second direction Y was set. ++ The contact region is made to extend linearly in the first direction X, and the width in the second direction Y is made relatively wider (as shown in Figures 9(a) and 10(a) of the conventional structure p++ In the second direction Y of the type contact region 111, p ++ (This corresponds to the portion 104b facing the outer peripheral contact area 113 of the mold).

[0076] In addition, samples 6 and 7 have the outermost p in the second direction Y. ++ The end of the type contact region in the second direction Y has a fan-shaped planar shape with a central angle of 90 degrees, having a curved arc along the inner circumference of the corner of the active region in the portion facing the corner of the active region (as shown in Figures 9(a) and 10(a) of the conventional structure p ++ p of contact area 111 ++ (This corresponds to the portion 104c opposite the corner 113a of the outer peripheral contact region 113 of the mold). The outermost p in the second direction Y of samples 6 and 7 ++ The radii r (corresponding to R101) at the ends of the fan-shaped planar shape in the second direction Y of the contact region were set to 30 μm and 300 μm, respectively.

[0077] Figure 7B shows the results of verifying the presence or absence of bipolar degradation defects by conducting current through the body diodes of samples 1 to 7 in these experimental examples under different conditions (the results for sample 4 are omitted from the figure). Measurements 1 to 13 in Figure 7B are set so that the larger the measurement number (measurement No.), the more severe the conditions, with a generally larger current load. In measurements 1 to 3, a forward current density of 100 A / cm² was applied to the body diodes of the SiC-MOSFETs. 2 , 200A / cm 2 and 300 A / cm 2 A DC current was applied for 20 minutes. In Measurement 4, a forward current density of 100 A / cm² was applied to the body diode of the SiC-MOSFET. 2 A direct current was then applied for 60 minutes.

[0078] In measurement 5, the forward current density across the body diode of the SiC-MOSFET was 400 A / cm². 2 A DC current was applied for 5 minutes twice. In measurement 6, a forward current density of 350 A / cm² was applied to the body diode of the SiC-MOSFET. 2 A DC current was applied for 20 minutes. In measurements 7-13, the forward current density across the body diode of the SiC-MOSFET was 400 A / cm².2 , 500A / cm 2 , 600A / cm 2 700 A / cm² 2 , 800 A / cm 2 900 A / cm² 2 and 1000 A / cm 2 A pulsed current was then applied for 20 minutes.

[0079] For each sample in the experimental example, for samples 1-3, measurements were performed sequentially from measurement 4 to measurement 13. For samples 1-3, measurements 1-3, which have a lower current load than measurement 4, were not performed. For sample 4, measurement 4 was performed. For samples 5 and 6, measurements were performed sequentially from measurement 1 to measurement 9, where bipolar degradation defects occurred in all evaluation chips (evaluated semiconductor chips). For samples 5 and 6, measurements 10-13, which have a higher current load than measurement 9, were not performed. For sample 7, measurements were performed sequentially from measurement 1 to measurement 7, where bipolar degradation defects occurred in all evaluation chips. For sample 7, measurements 8-13, which have a higher current load than measurement 7, were not performed.

[0080] Figure 7B shows, in bold, the results of measurement conditions where the current load on the evaluation chip was increased and the number of defective chips increased. From the results of samples 5-7 in the experimental example shown in Figure 7B, p is observed in the part opposite the corner of the active region. ++ It was confirmed that increasing the surface area of ​​the type contact region relatively increases the likelihood of bipolar degradation failure occurring at low current densities (measurement conditions with small measurement No.). The outermost p in the second direction Y ++ In sample 7, where the radius r at the end of the fan-shaped planar shape in the second direction Y of the type contact region is large at 300 μm, it was confirmed that stacking faults concentrated and occurred from the contact holes that exposed the end of the fan-shaped planar shape.

[0081] On the other hand, from the results of samples 1 to 3 in the experimental example shown in Figure 7B, it was confirmed that samples 1 to 3 had a lower probability of bipolar degradation failure even under measurement conditions with a larger current load compared to samples 5 to 7. In other words, as with the silicon carbide semiconductor device 10 according to the embodiment described above, the layout is the same on both the central and edge sides of the active region 51, and a uniform layout is provided throughout the entire active region 51. ++ By arranging the type contact region 6 and the contact hole 11a, n + Type starting substrate 31 and n - It was confirmed that the increase in hole current density at the interface with the type epitaxial layer 32 can be suppressed, thereby suppressing bipolar degradation.

[0082] Furthermore, from the results of samples 1-3 in the experimental example shown in Figure 7B, p ++ It was confirmed that the smaller the area occupancy of the type contact region 6, the lower the probability of bipolar degradation failure. Therefore, p ++ A smaller area occupancy rate for the contact region 6 is preferable. Although not shown in the diagram, measurement 4 was performed on sample 4, and it was confirmed that no bipolar degradation defects occurred in any of the evaluation chips of sample 4. For sample 4, the presence or absence of bipolar degradation defects was estimated by detecting stacking faults based on photoluminescence (PL) in the semiconductor substrate 30.

[0083] p of sample 4 ++ The area occupancy rate of the type contact region 6 is the same as that of sample 2. ++ Area occupancy of type contact region 6 and p of sample 3 ++ It is set between the area occupancy rate of the type contact region 6. Therefore, if measurements 5 to 13 are performed sequentially on sample 4, it is presumed that the probability of bipolar degradation failure occurring between the verification results of sample 2 and the verification results of sample 3 can be obtained as the verification result of sample 4. Therefore, with a uniform layout throughout the entire active region 51, p ++It was confirmed that if the type contact region 6 and contact hole 11a are arranged, bipolar degradation defects can be suppressed regardless of the layout pattern.

[0084] As described above, the present invention is subject to various modifications, and in each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, the cell pitch, etc., are appropriately set according to the required specifications. For example, the cell pitch and p of samples 1 to 4 of the experimental example corresponding to the silicon carbide semiconductor device (vertical SiC-MOSFET with trench gate structure) according to the above embodiment ++ The area occupancy rate of the contact region is an example, assuming a cell pitch of approximately 5.2 μm, p ++ The area occupancy rate of the contact region may be set to approximately 19.2%.

[0085] Furthermore, even when electrode pads other than the gate pad are provided in the active region, p is provided directly below the electrode pad in the same manner as directly below the gate pad. ++ A type region is positioned. p directly below this electrode pad ++ Type region and p of SiC-MOSFET ++ Regarding the positional relationship in the first and second directions with respect to the type contact area, the p directly below the gate pad ++ Type region and p of SiC-MOSFET ++ The positional relationship in the first and second directions with respect to the contact area is set similarly. [Industrial applicability]

[0086] As described above, the silicon carbide semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices, power supply devices for various industrial machines, and the like. [Explanation of Symbols]

[0087] 1 n + Type drain region 2 n - Type drift region 3 n-type JFET area 3a n-type current diffusion region 4 p-type base region 5 n + Type source area 6 p ++ Type Contact Area 7 Gate Trench 8 gate insulating film 9. Postal Service 10 Silicon Carbide Semiconductor Devices 11 Interlayer insulating film 11a, 11b Contact holes 12 Source electrodes 13 Drain electrode 14 Gate Pads 21,22,41 p + type area 30 Semiconductor substrates 31 n + Mold starting substrate 32 n - Type epitaxial layer 33 p-type epitaxial layer 34 pn junction (main junction) 40 p type outer area 42 p-type base extension 43 p ++ Outer peripheral contact area 43a p ++ Corner of the outer contact area of ​​the mold 44 p ++ type area 45 Field Oxide Film 46-gate polysilicon wiring layer 47 Gate metal wiring layer 48. p-type region of pressure-resistant structure 51 Active region 51a Corner of the active area 52 Edge Termination Region X First direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z-direction (depth) x1 p in the first direction ++ From the type contact area to p ++ Shortest distance to the outer contact area of ​​the mold x2 p in the first direction ++From the contact area to the p directly below the gate pad ++ Shortest distance to the type domain

Claims

1. An active region provided on a semiconductor substrate made of silicon carbide, A first semiconductor region of a first conductivity type provided inside the semiconductor substrate, In the active region, a second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first semiconductor region, A third semiconductor region of a first conductivity type is selectively provided between the first main surface and the second semiconductor region, A fourth semiconductor region of a second conductivity type, having a higher impurity concentration than the second semiconductor region, is selectively provided between the first main surface and the second semiconductor region. A trench that penetrates the third semiconductor region and the second semiconductor region and reaches the first semiconductor region, A gate electrode is provided inside the trench via a gate insulating film, An interlayer insulating film is provided on the first main surface and covers the gate electrode, A contact hole that penetrates the interlayer insulating film in the depth direction and reaches the first main surface, exposing the fourth semiconductor region and the third semiconductor region, A first electrode in contact with the third semiconductor region and the fourth semiconductor region through the contact hole, A second electrode in contact with the second main surface of the semiconductor substrate, A fifth semiconductor region of second conductivity type is selectively provided between the first main surface and the first semiconductor region, separated from the fourth semiconductor region, surrounding the active region, and electrically connected to the first electrode. Equipped with, The fourth semiconductor region is arranged in a uniform layout across the entire area of ​​the active region. The contact holes are arranged in a uniform layout throughout the entire active region. The trench extends in a stripe-like manner in a first direction parallel to the first main surface, The active region has a rectangular planar shape with its corners curved in an arc shape. The silicon carbide semiconductor device is characterized in that the inner circumference of the fifth semiconductor region has a rectangular planar shape with its corners curved in an arc shape along the active region, and the shortest distance from the fourth semiconductor region to the fifth semiconductor region is equal in the first direction between all adjacent trenches.

2. The silicon carbide semiconductor device according to Claim 1, characterized in that the fourth semiconductor region is arranged between all adjacent trenches, has the same width in a second direction parallel to the first main surface and perpendicular to the first direction, and extends linearly with the same length in the first direction.

3. The silicon carbide semiconductor device according to Claim 1, characterized in that the fourth semiconductor regions are each located between all adjacent trenches and are equally spaced in the first direction with the same dimensions and the same planar shape.

4. A sixth semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor region is provided between the first main surface and the second semiconductor region, selectively provided apart from the fourth semiconductor region and electrically connected to the first electrode, The silicon carbide semiconductor device according to claim 1, characterized in that, among all the trenches adjacent to each other, the shortest distance from the fourth semiconductor region to the sixth semiconductor region in the first direction is equal between the trenches facing the sixth semiconductor region in the first direction.

5. The interlayer insulating film is provided with a gate pad located on the interlayer insulating film, separated from the first electrode, and to which the gate electrode is electrically connected, The silicon carbide semiconductor device according to claim 4, characterized in that the entire surface of the gate pad faces the sixth semiconductor region via the interlayer insulating film.

6. The silicon carbide semiconductor device according to claim 1, characterized in that the fourth semiconductor region facing the corner of the active region in the first direction and the fourth semiconductor region facing the outer periphery connecting the corners of the active region in the first direction are equal in the shortest distance to the outer periphery of the active region in the first direction.

7. The semiconductor substrate is A starting substrate made of silicon carbide, which forms a seventh semiconductor region of the first conductivity type with a higher impurity concentration than the first semiconductor region, The silicon carbide semiconductor device according to claim 1, comprising a first conductivity type epitaxial layer which forms the first semiconductor region, provided on the starting substrate.

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