Semiconductor multilayer substrate, light-emitting component, light-emitting device, measuring device, and method for manufacturing a semiconductor multilayer substrate

Abstract

To provide a semiconductor laminate substrate, etc., in which the resonance wavelength of a light emitting element is easier to ascertain than in the case where the resonance of the light emitting element and the resonance due to the influence of a thyristor have the same resonance wavelength.SOLUTION: A semiconductor laminate substrate has a substrate, and a laminated structure including a first semiconductor laminate provided on the substrate and processed into a light emitting element, and a second semiconductor laminate provided on the first semiconductor laminate and processed into at least one thyristor, in which the laminate structure is adjusted such that the two resonance wavelengths due to the influence of the thyristor are located on both sides of a resonance wavelength of the light emitting element.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a semiconductor multilayer substrate, a light-emitting component, a light-emitting device, a measuring device, and a method for manufacturing a semiconductor multilayer substrate. [Background technology]

[0002] Patent Document 1 describes a semiconductor laminate substrate comprising a substrate, a first semiconductor laminate provided on the substrate and processed into a light-emitting element, and a second semiconductor laminate provided on the first semiconductor laminate via a tunnel junction layer or a metallic conductive III-V compound layer and processed into a drive unit that includes a thyristor and drives the light-emitting element. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-006502 [Overview of the project] [Problems that the invention aims to solve]

[0004] When evaluating the quality of products containing light-emitting elements, the resonant wavelength of the light-emitting element, determined from the product's reflection profile, is used. In this case, when a light-emitting element and a thyristor used to drive the light-emitting element are stacked on the same substrate, the reflection profile of the product includes information about the resonance due to the thyristor as well as the resonance of the light-emitting element. In such a product, if the resonance of the light-emitting element and the resonance due to the thyristor have the same resonant wavelength, it becomes difficult to determine the resonant wavelength of the light-emitting element from the reflection profile. The present invention aims to provide a semiconductor multilayer substrate, etc., that makes it easier to determine the resonant wavelength of a light-emitting element compared to the case where the resonance of the light-emitting element and the resonance due to the influence of a thyristor have the same resonant wavelength. [Means for solving the problem]

[0005] The invention according to claim 1 comprises: a substrate; and a laminated structure provided on said substrate, the laminated structure including a first semiconductor laminated body to be processed into a light-emitting element and a second semiconductor laminated body provided on said first semiconductor laminated body to be processed into at least one thyristor, wherein said laminated structure is adjusted such that two resonance wavelengths caused by the influence of said thyristor are located on both sides of the resonance wavelength of said light-emitting element The adjustment of the laminated structure was performed by adjusting the thickness of at least one layer of the second semiconductor laminate. , which is a semiconductor laminated substrate. Claim 2 The invention according to is characterized in that said second semiconductor laminated body comprises at least an anode layer, a first gate layer, a second gate layer and a cathode layer, and the adjustment of said laminated structure is performed by adjusting the thickness of at least one of said anode layer and said cathode layer of said second semiconductor laminated body. The invention according to claim 1 is the semiconductor laminated substrate described. Claim 3 The invention according to is characterized in that the adjustment of said laminated structure is performed by making at least one of said anode layer and said cathode layer thicker than said first gate layer and said second gate layer. The invention according to claim 2 is the semiconductor laminated substrate described. Claim 4 The invention according to is the semiconductor laminated substrate according to claim 1, characterized in that said laminated structure includes an intermediate layer provided between said first semiconductor laminated body and said second semiconductor laminated body, and the adjustment of said laminated structure is performed by adjusting the thickness of said intermediate layer. Claim 5 The invention according to is the semiconductor laminated substrate according to claim 4 described, characterized in that said intermediate layer is composed of an n-type semiconductor. Claim 6 The invention according to is the semiconductor laminated substrate according to claim 1, characterized in that the adjustment of said laminated structure is performed such that, with the interval between two resonance wavelengths caused by the influence of said thyristor being defined as 100%, the resonance wavelength of said light-emitting element is located within a range of ±30% from the average of the two resonance wavelengths caused by the influence of said thyristor. Claim 7The invention described herein comprises a substrate on which a laminated structure is formed, including a first semiconductor laminate and a second semiconductor laminate superimposed on the first semiconductor laminate; at least one light-emitting element composed of the first semiconductor laminate; and at least one thyristor composed of the second semiconductor laminate, which, when turned on, causes the light-emitting element to emit light or increases the amount of light emitted, wherein the laminated structure is adjusted such that two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element. The adjustment of the laminated structure was performed by adjusting the thickness of at least one layer of the second semiconductor laminate. This is a light-emitting component characterized by the following features. Claim 8 The invention described herein comprises a substrate on which a laminated structure is formed, including a first semiconductor laminate and a second semiconductor laminate superimposed on the first semiconductor laminate; a light-emitting unit having at least one light-emitting element made of the first semiconductor laminate; and a drive unit including at least one thyristor made of the second semiconductor laminate for driving the light-emitting element, wherein the laminated structure is adjusted so that two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element. The adjustment of the laminated structure was performed by adjusting the thickness of at least one layer of the second semiconductor laminate. This is a light-emitting device characterized by the following features. Claim 9 The invention described herein comprises a substrate on which a laminated structure is formed, including a first semiconductor laminate and a second semiconductor laminate superimposed on the first semiconductor laminate; a light-emitting unit having at least one light-emitting element made of the first semiconductor laminate; a drive unit including at least one thyristor made of the second semiconductor laminate for driving the light-emitting element; and a measurement unit that performs measurements relating to an object based on light emitted from the light-emitting unit and reflected by the object, wherein the laminated structure is adjusted so that two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element. The adjustment of the laminated structure was performed by adjusting the thickness of at least one layer of the second semiconductor laminate. This is a measuring device characterized by the following features. Claim 10The invention described herein is a method for manufacturing a semiconductor laminate substrate, comprising: a first laminate formation step of forming a first semiconductor laminate on a substrate which is processed into at least one light-emitting element; and a second laminate formation step of forming a second semiconductor laminate on the first semiconductor laminate formed by the first laminate formation step which is processed into at least one thyristor, wherein the second laminate formation step is characterized by forming a semiconductor layer whose thickness is determined such that two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element. Claim 11 The invention described herein comprises: a first laminate formation step of forming a first semiconductor laminate on a substrate which is processed into at least one light-emitting element; an intermediate layer formation step of forming an intermediate layer on the first semiconductor laminate formed by the first laminate formation step; and a second laminate formation step of forming a second semiconductor laminate on the intermediate layer formed by the intermediate layer formation step which is processed into at least one thyristor, wherein the intermediate layer formation step is performed such that the two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element. Thickness A method for manufacturing a semiconductor laminated substrate, characterized by forming the determined intermediate layer. [Effects of the Invention]

[0006] Claim 1, 7 According to the inventions described in 8, 9, 10, and 11, a semiconductor laminated substrate is provided that makes it easier to determine the resonance wavelength of a light-emitting element compared to the case where the resonance of the light-emitting element and the resonance due to the influence of a thyristor have the same resonance wavelength. Claim 2 According to the invention described herein, the influence on the characteristics of the drive unit is suppressed compared to the case where the thickness of the first gate layer and the second gate layer is adjusted. Claim 3 According to the invention described herein, the influence on the characteristics of the drive unit is suppressed compared to the case in which the first gate layer and the second gate layer are thicker than the anode layer and the cathode layer. Claim 4According to the invention described herein, the influence on the characteristics of the light-emitting element is suppressed compared to the case where only the thickness of the layers of the first semiconductor laminate is adjusted. Claim 5 According to the invention described above, the driving voltage is reduced compared to the case where the intermediate layer is made of a p-type semiconductor. Claim 6 According to the invention described above, it becomes easier to determine the resonant wavelength of a light-emitting element compared to the case where the resonant wavelength of the light-emitting element is located outside the range. [Brief explanation of the drawing]

[0007] [Figure 1] This figure shows an example of a schematic configuration of a measuring device to which an embodiment of the present invention is applied. [Figure 2] This figure illustrates an example configuration of a light-emitting device to which an embodiment of the present invention is applied. [Figure 3] This is an example of a planar layout and cross-sectional view of a light-emitting chip to which the first embodiment is applied. Figure 3(a) is a planar layout of the light-emitting chip, and Figure 3(b) is a cross-sectional view of Figure 3(a) along line IIIB-IIIB. [Figure 4] This is an enlarged cross-sectional view of an island in which a VCSEL and a setting thyristor are stacked in a light-emitting chip to which the first embodiment is applied. [Figure 5] This is a timing chart illustrating an example of the operation of a light-emitting device and light-emitting chip. [Figure 6] This diagram illustrates the manufacturing process of a semiconductor laminate to which the first embodiment is applied. Figure 6(a) shows the process of forming a semiconductor laminate to be processed into a VCSEL, Figure 6(b) shows the process of forming a tunnel junction layer, and Figure 6(c) shows the process of forming a semiconductor laminate to be processed into a thyristor. [Figure 7] These figures correspond to the reflectance spectra; Figure 7(a) shows the reflectance spectrum when only a semiconductor laminate is formed on the substrate, and Figure 7(b) shows the reflectance spectrum when a laminated structure is formed. [Figure 8] This figure illustrates the reflectance spectrum of a comparative example semiconductor multilayer substrate. [Figure 9] This diagram illustrates the processing steps from a semiconductor multilayer substrate to a light-emitting chip. Figure 9(a) shows the process of forming n-ohmic electrodes, Figure 9(b) shows the process of separating into islands, and Figure 9(c) shows the process of exposing the p-gate layer. [Figure 10] This diagram illustrates the processing steps from a semiconductor multilayer substrate to a light-emitting chip. Figure 10(d) shows the process of forming p-ohmic electrodes, Figure 10(e) shows the process of forming a protective layer, and Figure 10(f) shows the process of forming various wirings and back-side electrodes. [Figure 11] Figure 11(a) is a diagram illustrating the light-emitting chip and semiconductor laminated substrate to which the second embodiment is applied. Figure 11(a) is an enlarged cross-sectional view of an island in which a VCSEL and a setting thyristor are stacked in a light-emitting chip to which the second embodiment is applied, and Figure 11(b) is a diagram showing the stacked structure of a semiconductor laminated substrate to which the second embodiment is applied. [Modes for carrying out the invention]

[0008] Hereinafter, with reference to the attached drawings, the first and second embodiments of the present invention will be described in detail. In both embodiments, the description will be based on the case where the semiconductor laminated substrate to which the embodiment of the present invention is applied is processed into a light-emitting chip, which is an example of a light-emitting component, and applied to a measuring device for measuring the three-dimensional shape of an object.

[0009] <First Embodiment> (Measuring device 1000) First, a first embodiment of the present invention will be described. Figure 1 shows an example of a schematic configuration of a measuring device 1000 to which an embodiment of the present invention is applied. The measuring device 1000 is a device that measures the three-dimensional shape of an object based on the so-called ToF (Time of Flight) method, which uses the time of flight of light, and is an example of a measuring device that performs measurements on an object. As shown in the figure, the measuring device 1000 comprises a light-emitting device 1 that emits light for measurement, a three-dimensional sensor 20 that receives light reflected from the object, and a system control unit 30 that controls the measuring device 1000 as a system.

[0010] The light-emitting device 1 emits light for measurement, directed towards the object. More specifically, the light-emitting device 1 comprises a light-emitting chip 10 equipped with a vertical cavity surface-emitting laser (VCSEL) (described later using Figure 2), which is an example of a light-emitting element, and a light-emitting control unit 110 that controls the emission of light from the light-emitting chip 10. The light-emitting device 1 will be described in detail later using Figures 2 to 5.

[0011] The three-dimensional sensor 20 acquires light that has been reflected back from an object (reflected light). Then, using the Time of Flight (ToF) method, it outputs distance information to the object based on the time from the emission of light to the reception of the reflected light. The three-dimensional sensor 20 is an example of a light-receiving unit that receives light that has been reflected back from an object.

[0012] The system control unit 30 controls the light-emitting device 1 and the three-dimensional sensor 20 to control the entire measuring device 1000 as a system. The system control unit 30 also includes a shape identification unit 30A that identifies the three-dimensional shape of an object based on distance information output from the three-dimensional sensor 20. The system control unit 30 is, for example, a computer including a CPU, ROM, RAM, etc., and the ROM includes non-volatile rewritable memory, such as flash memory. The program stored in the ROM is then loaded into the RAM, and the CPU executes the program to configure the shape identification unit 30A.

[0013] In the measuring device 1000 to which an embodiment of the present invention is applied, the time from when the light-emitting device 1 emits light until when the light is reflected by the object and received by the three-dimensional sensor 20 (time of flight of light) is measured, and distance information is output based on this time. Then, based on the distance information output from the three-dimensional sensor 20, the shape identification unit 30A identifies the three-dimensional shape of the object. In this way, the three-dimensional shape is measured in the measuring device 1000 based on the ToF method. The shape identification unit 30A is an example of a measuring unit that performs measurements on the object.

[0014] (Light-emitting device 1) Figure 2 is a diagram illustrating an example configuration of a light-emitting device 1 to which an embodiment of the present invention is applied, and corresponds to an equivalent circuit diagram of the light-emitting device 1. As described using Figure 1, the light-emitting device 1 comprises a light-emitting chip 10 and a light-emitting control unit 110.

[0015] (Light emission control unit 110) The light emission control unit 110 includes a transfer signal generation unit 120, a lighting signal generation unit 140, a reference potential supply unit 160, and a power supply potential supply unit 170, and controls the light emission of the light emission chip 10. The transfer signal generation unit 120 generates transfer signals φ1 and φ2 to sequentially transfer the ON state to multiple transfer thyristors T (described later). The lighting signal generation unit 140 generates a lighting signal φI that supplies current to light up (emit light) multiple VCSELs (described later). The reference potential supply unit 160 supplies the reference potential Vsub. The power supply potential supply unit 170 supplies the power supply potential Vga.

[0016] (Light-emitting chip 10) The light-emitting chip 10 comprises a light-emitting section 11, a drive section 12, and a transfer section 13. The light-emitting chip 10 also includes terminals for receiving signal inputs: a φ1 terminal, a φ2 terminal, a Vga terminal, a φI terminal, and a Vsub terminal. The light-emitting unit 11 is equipped with a vertical cavity surface-emitting laser (VCSEL). Hereafter, the vertical cavity surface-emitting laser (VCSEL) will be simply referred to as "VCSEL". In the example shown in Figure 2, there are 128 VCSELs, from VCSEL1 to VCSEL4, ..., VCSEL127, VCSEL128 (which will be referred to as VCSEL if not distinguished). The light-emitting chip 10 (or light-emitting device 1) emits light towards the target object by emitting light from these VCSELs.

[0017] The drive unit 12 is equipped with 128 setting thyristors S1 to S4, ..., S127, S128 (referred to as setting thyristor S when not distinguished) corresponding to the VCSEL1 to VCSEL4, ..., VCSEL127, VCSEL128 of the light-emitting unit 11. The anode of the VCSEL with the same number is connected to the cathode of the setting thyristor S, thereby connecting the VCSEL with the same number to the setting thyristor S in series. As will be described in detail using Figure 3(b), the setting thyristors S are stacked on top of the VCSELs formed on the substrate 80. The setting thyristor S is an example of a thyristor that, when turned on, causes the VCSEL to emit light or increases the amount of light emitted. Furthermore, "on the VCSEL" or "above the VCSEL" does not only refer to a state of direct contact with the VCSEL, but also includes a state of being located above it without direct contact. The same applies to similar expressions such as "on the circuit board" or "above the circuit board." Similarly, expressions such as "below the VCSEL" also include a state of being located below it without direct contact.

[0018] The transfer unit 13 comprises 128 transfer thyristors T1 to T4, ..., T127, T128 (referred to as transfer thyristor T if not distinguished) and 128 lower diodes UD1 to UD4, ..., UD127, UD128 (referred to as lower diode UD if not distinguished). For each of the transfer thyristors T1 to T128 and lower diodes UD1 to UD128, a transfer thyristor T and a lower diode UD of the same number are connected in series. As will be described in detail using Figure 3(b), the transfer thyristors T are stacked on lower diodes UD formed on the substrate 80.

[0019] Furthermore, the transfer unit 13 is equipped with two transfer thyristors T1 to T128 in numerical order, and a coupling diode D1 to D4, ..., D126, D127 (referred to as coupling diode D if not distinguished) between each pair. For example, transfer thyristors T1 and T2 are paired together, and a coupling diode D1 is provided between these pairs.

[0020] The transfer unit 13 also includes one start diode SD. Furthermore, the transfer unit 13 includes power line resistors Rg1 to Rg4, ..., Rg127, Rg128 (or power line resistor Rg if not distinguished), and current limiting resistors R1 and R2 provided to prevent excessive current from flowing through the first transfer signal line 72 to which the first transfer signal φ1 (described later) is supplied and the second transfer signal line 73 to which the second transfer signal φ2 is supplied.

[0021] The VCSEL1 to VCSEL128 of the light-emitting section 11, the setting thyristors S1 to S128 of the drive section 12, the transfer thyristors T1 to T128 of the transfer section 13, the lower diodes UD1 to UD128, the coupling diodes D1 to D127, and the power line resistors Rg1 to Rg128 are arranged in numerical order on the light-emitting chip 10, from one side (left side in Figure 2) to the other side (right side in Figure 2).

[0022] In the example shown in Figure 2, the number of VCSELs in the light-emitting section 11, the setting thyristors S in the drive section 12, the transfer thyristors T in the transfer section 13, the lower diodes UD, and the power line resistors Rg are each set to 128. The number of coupling diodes D is 127, which is one less than the number of transfer thyristors T. The number of VCSELs, setting thyristors S, transfer thyristors T, lower diodes UD, power line resistors Rg, and coupling diodes D are not limited to those shown above and may be set to predetermined numbers. Also, the number of transfer thyristors T may be greater than the number of VCSELs.

[0023] The VCSEL, lower diode UD, coupling diode D, and start diode SD described above are two-terminal semiconductor devices with an anode terminal and a cathode terminal. The thyristors (setting thyristor S, transfer thyristor T) are three-terminal semiconductor devices with an anode terminal, a gate terminal, and a cathode terminal. Note that terminals may be abbreviated and enclosed in parentheses below.

[0024] In the light-emitting chip 10 to which the first embodiment is applied, and in the light-emitting chip 10-2 to which the second embodiment described later is applied, the VCSEL, setting thyristor S, lower diode UD, transfer thyristor T, coupling diode D, power line resistor Rg, and start diode SD are configured as a so-called integrated circuit by a semiconductor stack epitaxially grown on a common semiconductor substrate (hereinafter referred to as substrate 80). Here, the semiconductor stack is composed of a III-V compound semiconductor such as GaAs, AlGaAs, or AlAs as an example. In the following, the side of the substrate 80 on which the VCSELs, etc., are formed, that is, the side on which the semiconductor stack is formed, may be referred to as the "front surface," and the opposite side may be referred to as the "back surface."

[0025] Next, we will explain the electrical connections of each element in the light-emitting chip 10. The anodes of the VCSEL and the lower diode UD are connected to the substrate 80, forming a so-called anode common configuration. A reference potential Vsub is supplied to these anodes via the back electrode 91, which is a Vsub terminal located on the back surface of the substrate 80. The cathodes of the VCSELs are connected to the anodes of the setting thyristor S. The cathodes of the lower diode UD are connected to the anodes of the transfer thyristor T. Note that this connection is an example configuration when using a p-type substrate 80. When using an n-type substrate, the polarity is reversed, and when using an intrinsic (i) type substrate without added impurities, a terminal for supplying the reference potential Vsub is provided on the surface of the substrate.

[0026] Along the arrangement of the transfer thyristors T, the cathodes of the odd-numbered transfer thyristors T1, T3, T5, ..., T125, T127 are connected to the first transfer signal line 72. The first transfer signal line 72 is then connected to the φ1 terminal via a current limiting resistor R1. The first transfer signal φ1 is supplied to this φ1 terminal from the transfer signal generation unit 120 of the light emission control unit 110. Furthermore, along the arrangement of the transfer thyristors T, the cathodes of the even-numbered transfer thyristors T2, T4, T6, ... T126, T128 are connected to the second transfer signal line 73. The second transfer signal line 73 is connected to the φ2 terminal via a current limiting resistor R2. The second transfer signal φ2 is supplied to this φ2 terminal from the transfer signal generation unit 120 of the light emission control unit 110.

[0027] Each cathode of the setting thyristor S is connected to the illumination signal line 75. The illumination signal line 75 is connected to the φI terminal. In the light-emitting chip 10, the illumination signal φI is supplied to the φI terminal from the illumination signal generation unit 140 of the light-emitting control unit 110 via a current-limiting resistor RI provided on the outside of the light-emitting chip 10. The illumination signal φI supplies the current for illumination (light emission) of the VCSEL.

[0028] Each of the transfer thyristors T1 to T128, specifically gates Gt1 to Gt128 (referred to as gate Gt if not distinguished), is connected one-to-one to the corresponding gates Gs1 to Gs128 (referred to as gate Gs if not distinguished) of the setting thyristors S1 to S128. Therefore, gates Gt1 to Gt128 and gates Gs1 to Gs128 with the same number are electrically at the same potential. Thus, for example, gate Gt1 (gate Gs1) is used to indicate that they have the same potential.

[0029] The gates Gt1 to Gt128 of the transfer thyristors T1 to T128 are paired in numerical order, and coupling diodes D1 to D127 are connected between each of these gates. In other words, coupling diodes D1 to D127 are directly connected so that they are sandwiched between the gates Gt1 to Gt128. The orientation of coupling diode D1 is such that current flows from gate Gt1 to gate Gt2. The same applies to the other coupling diodes D2 to D127.

[0030] The gate Gt (gate Gs) of the transfer thyristor is connected to the power line 71 via a power line resistor Rg, which is provided corresponding to each transfer thyristor T. The power line 71 is connected to the Vga terminal. The power potential Vga is supplied to the Vga terminal from the power potential supply unit 170 of the light emission control unit 110. The gate Gt1 of the transfer thyristor T is connected to the cathode of the start diode SD. On the other hand, the anode of the start diode SD is connected to the second transfer signal line 73.

[0031] Figure 3 shows an example of a plan layout and cross-sectional view of a light-emitting chip 10 to which the first embodiment is applied. Figure 3(a) is a plan layout of the light-emitting chip 10, and Figure 3(b) is a cross-sectional view taken along line IIIB-IIIB in Figure 3(a). In Figure 3(a), the right side is the +x direction and the upper side is the +y direction, and in Figure 3(b), the upper side is the +y direction. Note that the protective layer 90, which will be described later, is omitted in Figure 3(a).

[0032] Figure 3(a) shows the area centered around VCSEL1-VCSEL4, setting thyristors S1-S4, transfer thyristors T1-T4, and lower diodes UD1-UD4. For convenience, an example is shown where the VCSELs are arranged in a single line (in the x-direction in Figure 3(a)), but the arrangement of the VCSELs is not limited and may, for example, be arranged two-dimensionally across the x and y directions. Furthermore, the Vsub terminal (backside electrode 91) provided on the back surface of the substrate 80 is shown extended outside the substrate 80.

[0033] In Figure 3(b), a cross-sectional view along the IIIB-IIIB line in Figure 3(a), the following components are shown from the bottom (-y direction): setting thyristor S1 / VCSEL1, transfer thyristor T1 / lower diode UD1, coupling diode D1, and power line resistor Rg1. Note that setting thyristor S1 and VCSEL1 are stacked. Similarly, transfer thyristor T1 and lower diode UD1 are stacked.

[0034] First, the cross-sectional structure of the light-emitting chip 10 will be explained with reference to Figure 3(b). The light-emitting chip 10 has a p-type anode layer 81, a light-emitting layer 82, and an n-type cathode layer 83 arranged in order on a p-type substrate 80 (substrate 80), which constitute the VCSEL and the lower diode UD. As will be described in detail later, in the light-emitting chip 10, the p-type anode layer 81 and the n-type cathode layer 83 are composed of a distributed Bragg reflector (DBR) (hereinafter referred to as the DBR layer), which is made up of multiple semiconductor layers having a refractive index difference stacked on top of each other. Therefore, below, the p-type anode layer 81 will be referred to as the p-anode (DBR) layer 81, and the n-type cathode layer 83 will be referred to as the n-cathode (DBR) layer 83.

[0035] Furthermore, a tunnel junction (tunnel diode) layer 84 (tunnel junction layer 84) is provided on the n-cathode (DBR) layer 83. Furthermore, on the tunnel junction layer 84, a p-type anode layer 85 (p-anode layer 85), an n-type gate layer 86 (n-gate layer 86), a p-type gate layer 87 (p-gate layer 87), and an n-type cathode layer 88 (n-cathode layer 88) are provided in order, constituting a setting thyristor S, a transfer thyristor T, a coupling diode D, and a power line resistor Rg. In the following, the notation in parentheses will be used. The same applies to other cases.

[0036] As shown in Figure 3(b), the light-emitting chip 10 has a protective layer 90 made of an insulating material that covers the surface and sides of each island. In addition, on the side of the protective layer 90 opposite to the substrate 80 relative to the VCSEL, a light output port 90A is provided for emitting light from the VCSEL. In other words, in the example of Figure 3(b), a portion of the n-cathode layer 88 of the setting thyristor S is not covered by the protective layer 90.

[0037] Elements such as the VCSEL, lower diode UD, setting thyristor S, transfer thyristor T, and coupling diode D are composed of multiple islands 301, 302, 303 separated by etching away a portion of each of the above layers. Note that these islands are sometimes referred to as mesas, and the etching process that forms these islands (mesas) is sometimes referred to as mesa etching. In the light-emitting chip 10, these islands 301, 302, and 303 are connected to the power supply line 71, the first transfer signal line 72, the second transfer signal line 73, the lighting signal line 75, and other wiring via through-holes (indicated by circles in Figure 3(a)) provided in the protective layer 90. The following explanation will omit further details regarding the protective layer 90 and the through-holes.

[0038] Furthermore, as shown in Figure 3(b), a back electrode 91, which serves as a Vsub terminal, is provided on the back surface of the substrate 80.

[0039] Here, the notations for the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 correspond to their functions when forming a VCSEL and a lower diode UD. That is, the p-anode (DBR) layer 81 functions as an anode, and the n-cathode (DBR) layer 83 functions as a cathode. Furthermore, the notations for the p-anode layer 85, n-gate layer 86, p-gate layer 87, and n-cathode layer 88 correspond to their functions when forming a setting thyristor S and a transfer thyristor T. That is, the p-anode layer 85 functions as an anode, the n-gate layer 86 and p-gate layer 87 function as gates, and the n-cathode layer 88 functions as a cathode. Furthermore, when each of the above layers constitutes a coupling diode D and a power line resistor Rg, they have different functions, as will be described later.

[0040] The multiple islands of the light-emitting chip 10 include those that lack a portion of the following layers: p-anode (DBR) layer 81, light-emitting layer 82, n-cathode (DBR) layer 83, tunnel junction layer 84, p-anode layer 85, n-gate layer 86, p-gate layer 87, and n-cathode layer 88. For example, island 301 lacks a portion of the n-cathode layer 88.

[0041] Next, we will describe an example of a planar layout for the light-emitting chip 10. As shown in Figure 3(a), island 301 is provided with VCSEL1 and setting thyristor S1. Island 302 is provided with lower diode UD1, transfer thyristor T1, and coupling diode D1. Island 303 is provided with power line resistor Rg1. Island 304 is provided with start diode SD. In addition, island 305 is provided with current limiting resistor R1, and island 306 is provided with current limiting resistor R2.

[0042] Furthermore, multiple islands similar to islands 301, 302, and 303 are formed in parallel on the light-emitting chip 10. These islands are equipped with VCSEL2 to VCSEL128, setting thyristors S2 to S128, lower diodes UD2 to UD128, transfer thyristors T2 to T128, coupling diodes D2 to D127, etc., in the same way as islands 301, 302, and 303.

[0043] Here, we will explain islands 301 to 306 in detail with reference to Figures 3(a) and 3(b). As shown in Figure 3(b), the VCSEL1 provided on the island 301 consists of a p-anode (DBR) layer 81, an emissive layer 82, and an n-cathode (DBR) layer 83. The setting thyristor S consists of a p-anode layer 85, an n-gate layer 86, a p-gate layer 87, and an n-cathode layer 88, which are stacked via a tunnel junction layer 84 stacked on the n-cathode (DBR) layer 83 of the VCSEL1.

[0044] Then, in island 301, an n-type ohmic electrode 321 (n-ohmic electrode 321) provided on the n-cathode layer 88 (region 311) is used as the cathode electrode. In addition, a p-type ohmic electrode 331 (p-ohmic electrode 331) provided on the p-gate layer 87 exposed by removing the n-cathode layer 88 is used as the electrode for gate Gs1 (sometimes referred to as gate terminal Gs1). The n-ohmic electrode 321 is provided so as not to block the light emitted from the VCSEL 1, and may, for example, have a light emission port (not indicated) similar to that of the protective layer 90. In the example shown in Figure 3(b), the light emission port 90A of the protective layer 90 and the light emission port of the setting thyristor S are provided in corresponding areas, and a portion of the n-cathode layer 88 is not covered by the protective layer 90 and the n-ohmic electrode 321, and is exposed.

[0045] Here, the p-anode (DBR) layer 81 of the VCSEL may include a current-constricting layer that narrows the current. The current-constricting layer is formed when a portion of the semiconductor layer constituting the p-anode (DBR) layer, exposed by mesa etching, is oxidized from the outer edge, creating a current-blocking region where current is less likely to flow. The central portion of the semiconductor layer constituting the p-anode (DBR) layer that is not oxidized becomes a current-passing region where current flows more easily relative to the current-blocking region. Note that the current-blocking region does not need to completely block the current; it only needs to be able to concentrate the current in the current-passing region, and it is sufficient that current flows less easily through it than through the current-passing region. By incorporating such a current blocking section, power consumption can be reduced and light extraction efficiency can be improved. Light extraction efficiency refers to the amount of light that can be extracted per unit of power.

[0046] The lower diode UD1, located on island 302, is composed of a p-anode (DBR) layer 81, an emitting layer 82, and an n-cathode (DBR) layer 83, similar to a VCSEL. The transfer thyristor T1, similar to the setting thyristor S1, is composed of a p-anode layer 85, an n-gate layer 86, a p-gate layer 87, and an n-cathode layer 88, which are stacked via a tunnel junction layer 84 stacked on the n-cathode (DBR) layer 83 of the lower diode UD1. The n-ohmic electrode 323, located on region 313 of the n-cathode layer 88, serves as the cathode terminal. Furthermore, the p-ohmic electrode 332, located on the p-gate layer 87 exposed by removing the n-cathode layer 88, serves as the gate Gt1 terminal. Similarly, the coupled diode D1 provided on island 302 is composed of a p-gate layer 87 and an n-cathode layer 88. The n-ohmic electrode 324 provided on region 314 of the n-cathode layer 88 serves as the cathode terminal. Furthermore, the p-ohmic electrode 332 provided on the p-gate layer 87, which is exposed after removing the n-cathode layer 88, serves as the anode terminal. In this case, the anode terminal of the coupled diode D is the same as that of the gate Gt1.

[0047] The power line resistor Rg1 provided on island 303 is composed of a p-gate layer 87. In other words, the power line resistor Rg1 is provided with the p-gate layer 87 between the p-ohmic electrode 333 and the p-ohmic electrode 334, which is located on the p-gate layer 87 that is exposed after removing the n-cathode layer 88, as the resistor.

[0048] The start diode SD provided on island 304 is composed of a p-gate layer 87 and an n-cathode layer 88. In other words, the start diode SD uses an n-ohmic electrode 325 provided on region 315 of the n-cathode layer 88 as its cathode terminal. Furthermore, the p-ohmic electrode 335 provided on the p-gate layer 87, which is exposed after removing the n-cathode layer 88, serves as the anode terminal. The current limiting resistors R1 on island 305 and R2 on island 306 are provided in the same way as the power line resistor Rg1 on island 303, and each of them makes the p-gate layer 87 between the two p-ohmic electrodes (unsigned) a resistor.

[0049] Next, the connection relationships between each element will be explained in Figure 3(a). The illumination signal line 75 comprises a main body 75a and several branch sections 75b. The main body 75a is provided to extend in the direction of the row of setting thyristors S / VCSEL. The branch sections 75b branch off from the main body 75a and are connected to the n-ohmic electrode 321, which is the cathode terminal of the setting thyristor S1 provided on the island 301. The same applies to the cathode terminals of the other setting thyristors S. The illumination signal line 75 is connected to the φI terminal provided on the setting thyristor S1 / VCSEL1 side.

[0050] The first transfer signal line 72 is connected to the n-ohmic electrode 323, which is the cathode terminal of the transfer thyristor T1 located on island 302. The cathode terminals of other odd-numbered transfer thyristors T, located on islands similar to island 302, are also connected to the first transfer signal line 72. The first transfer signal line 72 is connected to the φ1 terminal via a current-limiting resistor R1 located on island 305. Furthermore, the second transfer signal line 73 is connected to the n-ohmic electrode (unsigned), which is the cathode terminal of the even-numbered transfer thyristor T. The second transfer signal line 73 is connected to the φ2 terminal via a current-limiting resistor R2 provided on the island 306.

[0051] Power line 71 is connected to the p-ohmic electrode 334, which is one terminal of power line resistor Rg1 located on island 303. Another terminal of power line resistor Rg is also connected to power line 71. Power line 71 is connected to the Vga terminal.

[0052] The p-ohmic electrode 331 (gate terminal Gs1) of the setting thyristor S1 located on island 301 is connected to the p-ohmic electrode 332 (gate terminal Gt1) of island 302 by a connection wire 76. Furthermore, the p-ohmic electrode 332 (gate terminal Gt1) is connected to the p-ohmic electrode 333 of the island 303 (the other terminal of the power line resistor Rg1) by a connection wire 77. Furthermore, the n-ohmic electrode 324 (cathode terminal of coupling diode D1) located on island 302 is connected by a connection wire 79 to the p-type ohmic electrode (unsigned), which is the gate terminal Gt2 of the adjacent transfer thyristor T2. The same applies to other VCSELs, setting thyristors S, transfer thyristors T, coupling diodes D, etc., although the explanation will be omitted here.

[0053] The p-ohmic electrode 332 (gate terminal Gt1) of island 302 is connected to the n-ohmic electrode 325 (cathode terminal of start diode SD) provided on island 304 by a connection wire 78. The p-ohmic electrode 335 (anode terminal of start diode SD) is connected to the second transfer signal line 73. Note that the above connection and configuration are for when a p-type substrate 80 is used; the polarity will be reversed when an n-type substrate is used. Also, when an i-type substrate is used, a terminal for supplying the reference potential Vsub is provided on the surface of the substrate. The connection and configuration will then be the same as when using either a p-type substrate or an n-type substrate.

[0054] (Laminated structure L1) Figure 4 is an enlarged cross-sectional view of the island 301 in which the VCSEL and setting thyristor S are stacked in the light-emitting chip 10 to which the first embodiment is applied, and corresponds to a view of the cross-section of the island in which the VCSEL and setting thyristor S are stacked from the -y direction. In this state, the p-ohmic electrode 331 is not visible, so the portion of the p-ohmic electrode 331 is shown as a view from the -x direction in Figure 3(a). Note that the protective layer 90 is omitted.

[0055] As mentioned above, in the island 301 of the light-emitting chip 10, the setting thyristor S is stacked on the VCSEL via a tunnel junction layer 84. In other words, a stacked structure L1 is formed on the substrate 80, which includes the semiconductor stack Lv constituting the VCSEL, the tunnel junction layer 84, and the semiconductor stack Ls constituting the setting thyristor S. Here, in the light-emitting chip 10, semiconductor stack Lv is an example of a first semiconductor stack constituting a light-emitting element, and semiconductor stack Ls is an example of a second semiconductor constituting a thyristor. The stacked structure L1 is an example of a stacked structure including the first semiconductor stack and the second semiconductor stack.

[0056] (VCSEL / Semiconductor laminate Lv) As shown in Figure 4, the VCSEL is composed of a semiconductor laminate Lv on a p-type substrate 80, in which a p-anode (DBR) layer 81, an emissive layer 82, and an n-cathode (DBR) layer 83 are epitaxially grown in that order. The p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 are DBR layers in which multiple layers of relatively high refractive index layers and relatively low refractive index layers are alternately stacked. The p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 are configured to reflect the light emitted by the VCSEL. As mentioned above, the p-anode (DBR) layer 81 may include a current-constricting layer that narrows the current.

[0057] The light-emitting layer 82 is a quantum well structure in which well layers and barrier layers are alternately stacked. The light-emitting layer 82 may also be an intrinsic (i) type layer (i layer) without added impurities. Furthermore, the light-emitting layer 82 may be a structure other than a quantum well, for example, a quantum beam (quantum wire) or a quantum box (quantum dot). In a VCSEL, laser oscillation is achieved by resonating light at the resonant wavelength λv using two DBR layers (p-anode (DBR) layer 81 and n-cathode (DBR) layer 83) flanking the light-emitting layer 82. This light then passes through a set thyristor S and is emitted from the light output port 90A (see Figure 3).

[0058] The tunnel junction layer 84 is made of n-type impurities (dopants) added at a high concentration. ++ The layer and p with a high concentration of p-type impurities added. ++ It is a junction with a layer, and even with a reverse bias, current flows due to the tunnel effect. The tunnel junction layer 84 suppresses the current flow that would otherwise be hindered by a reverse bias between the n-cathode (DBR) layer 83 of the VCSEL and the setting thyristor S. Even with a reverse bias, current flows due to the tunnel effect.

[0059] (Setting: Thyristor S / Semiconductor Stack Ls) The configured thyristor S is composed of a semiconductor stack Ls, which is formed by epitaxially growing a p-anode layer 85, an n-gate layer 86, a p-gate layer 87, and an n-cathode layer 88 in sequence on a tunnel junction layer 84. In other words, it has a four-layer pnpn structure. In the light-emitting chip 10 to which the first embodiment is applied, the n-cathode layer 88 is thicker than the n-gate layer 86 and the p-gate layer 87, due to the adjustment of the stacked structure L1 described later using Figures 6 and 7. Also, the p-anode layer 85 is thicker than the n-cathode layer 88. In other words, if we denote the thickness of each layer in the semiconductor stack Ls constituting the set thyristor S as t(i) using the sign i of each semiconductor layer, then t(86), t(87) <t(88)<t(85)となっている。

[0060] In the above example, an ohmic electrode 331 was provided in the p-gate layer 87 to form the gate Gs of the set thyristor S, but an n-ohmic electrode may also be provided in the n-gate layer 86 to form the gate Gs of the set thyristor S.

[0061] Next, we will explain the basic operation of the thyristors (transfer thyristor T, setting thyristor S) with reference to Figures 2-4. As mentioned above, a thyristor is a semiconductor element having three terminals: an anode terminal (anode), a cathode terminal (cathode), and a gate terminal (gate). It has a pnpn structure, which is constructed by stacking p-type semiconductor layers (p-anode layer 85, p-gate layer 87) and n-type semiconductor layers (n-gate layer 86, n-cathode layer 88) on a substrate 80. Here, we assume that the forward potential (diffusion potential) Vd of the pn junction composed of the p-type semiconductor layer and the n-type semiconductor layer is 1.5V as an example. As an example, we will explain the reference potential Vsub supplied to the back electrode 91, which is the Vsub terminal, as a high-level potential (hereinafter referred to as "H") at 0V, and the power supply potential Vga supplied to the Vga terminal as a low-level potential (hereinafter referred to as "L") at -5V. Therefore, we may use the notations "H" (0V) and "L" (-5V).

[0062] First, let's explain the operation of a thyristor on its own. Here, we assume that the anode of the thyristor is 0V. A thyristor in the off state, where no current flows between the anode and cathode, will turn on when a potential lower than the threshold voltage (a negative potential with a large absolute value) is applied to the cathode. Here, the threshold voltage of the thyristor is the gate potential minus the forward potential Vd (1.5V) of the pn junction. When the thyristor is turned on, its gate potential is close to the potential of the anode terminal. Here, since the anode is 0V, the gate is assumed to be 0V. Also, the cathode of the turned-on thyristor is close to the potential obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the potential of the anode. Here, since the anode is 0V, the cathode of the turned-on thyristor is close to -1.5V (a negative potential with an absolute value greater than 1.5V). Note that the cathode potential is set in relation to the power supply that provides current to the turned-on thyristor.

[0063] A thyristor in the ON state will switch to the OFF state (turn off) when the cathode reaches a potential higher than the potential required to maintain the ON state (a potential close to -1.5V as mentioned above) (a negative potential with a small absolute value, 0V or a positive potential). On the other hand, if a potential lower than the potential required to maintain the ON state (a negative potential with a large absolute value) is continuously applied to the cathode of an ON-state thyristor, and a current capable of maintaining the ON state (maintenance current) is supplied, the thyristor will remain ON.

[0064] Next, we will explain the operation when the VCSEL and the setting thyristor S are stacked together. The setting thyristor S is stacked with the VCSEL and connected in series. Therefore, the potential of the illumination signal φI is divided between the VCSEL and the setting thyristor S. Here, we will assume that the voltage applied to the VCSEL as a result of the voltage division is -1.7V. Then, when the setting thyristor S is in the off state, -3.3V is applied to the setting thyristor S.

[0065] As described above, if the threshold voltage of the off-state setting thyristor S is greater than -3.3V in absolute value, the potential applied to the cathode of the setting thyristor S is lower than the threshold voltage, causing the setting thyristor S to turn on. Then, current flows between the series-connected VCSEL and the setting thyristor S, and the VCSEL lights up. On the other hand, if the threshold voltage of the setting thyristor S is less than -3.3V in absolute value, the setting thyristor S does not turn on and remains in the off state. When the setting thyristor S turns on, the voltage applied to the series-connected VCSEL and setting thyristor S decreases in absolute value due to the current limiting resistor RI. However, if the voltage applied to the setting thyristor S is sufficient to maintain its ON state, the setting thyristor S remains ON. As a result, the VCSEL also continues to emit light.

[0066] (Operation of light-emitting device 1) Next, the operation of the light-emitting device 1 will be explained with reference to Figures 1 to 5. Figure 5 is a timing chart illustrating an example of the operation of the light-emitting device 1 and the light-emitting chip 10. Figure 5 is a timing chart for the part that controls the illumination (light emission) / de-illumination (non-illumination) of the five VCSELs, VCSEL1 to VCSEL5, of the light-emitting chip 10. In Figure 5, VCSEL1, VCSEL2, and VCSEL3 are illuminated (light emission), while VCSEL4 is de-illuminated (non-illumination).

[0067] In Figure 5, assume that time progresses alphabetically from time a to time k. In this case, VCSEL1 is controlled to be lit or not lit (referred to as lit control) during period T(1), VCSEL2 during period T(2), VCSEL3 during period T(3), and VCSEL4 during period T(4). Note that periods T(1), T(2), T(3), ... are of the same length, and when they are not distinguished, they are referred to as period T. In the following, "H" (0V) and "L" (-5V) may be abbreviated as "H" and "L".

[0068] The first transfer signal φ1 transmitted to terminal φ1 and the second transfer signal φ2 transmitted to terminal φ2 are signals having two potentials, "H" and "L". The waveforms of the first transfer signal φ1 and the second transfer signal φ2 are repeated in units of two consecutive periods T (for example, period T(1) and period T(2)).

[0069] The first transmission signal φ1 transitions from "H" to "L" at the start time b of period T(1), and from "L" to "H" at time f. Then, at the end time i of period T(2), it transitions from "H" to "L". The second transfer signal φ2 is "H" (0V) at the start time b of period T(1), and transitions from "H" to "L" at time e. Then, at the end time i of period T(2), it transitions from "L" to "H". Comparing the first transfer signal φ1 and the second transfer signal φ2, the second transfer signal φ2 corresponds to the first transfer signal φ1 shifted backward by a period T on the time axis. On the other hand, the waveform of the second transfer signal φ2 in period T(1) and the waveform in period T(2) are repeated from period T(3) onward. The reason why the waveform of the second transfer signal φ2 in period T(1) is different from that in period T(3) onward is that period T(1) is the period when the light-emitting device 1 starts operating.

[0070] As described later, the set of transfer signals, consisting of the first transfer signal φ1 and the second transfer signal φ2, propagates the ON state of the transfer thyristor T in numerical order, thereby designating the VCSEL with the same number as the ON transfer thyristor T as the target for ON or OFF (lighting control).

[0071] Next, we will explain the ignition signal φI supplied to the φI terminal. The ignition signal φI is a signal that has two potentials, "H" and "L". Here, we will explain the lighting signal φI during the lighting control period T(1) for VCSEL1. The lighting signal φI is "H" at the start time b of period T(1), transitions from "H" to "L" at time c, then transitions from "L" to "H" at time d, and remains "H" at time e.

[0072] (1) Time a At time a, the reference potential supply unit 160 of the light emission control unit 110 of the light emission device 1 sets the reference potential Vsub to "H". The power supply potential supply unit 170 of the light emission control unit 110 sets the power supply potential Vga to "L". The transfer signal generation unit 120 of the light emission control unit 110 sets the first transfer signal φ1 and the second transfer signal φ2 to "H". As a result, the φ1 terminal and φ2 terminal of the light emission chip 10 become "H". The potential of the first transfer signal line 72 connected to the φ1 terminal via the current limiting resistor R1 also becomes "H", and the second transfer signal line 73 connected to the φ2 terminal via the current limiting resistor R2 also becomes "H". Then, the lighting signal generation unit 140 of the light emission control unit 110 sets the lighting signal φI to "H". As a result, the φI terminal of the light emission chip 10 becomes "H" via the current limiting resistor RI, and the lighting signal line 75 connected to the φI terminal also becomes "H".

[0073] The anode of the setting thyristor S (p-anode layer 85) is connected to the cathode of the VCSEL (n-cathode (DBR) layer 83) via the tunnel junction layer 84, and the anode of the VCSEL (p-anode (DBR) layer 81) is connected to the Vsub terminal set to "H". The anode of the transfer thyristor T (p-anode layer 85) is connected to the cathode of the lower diode UD (n-cathode (DBR) layer 83) via the tunnel junction layer 84, and the anode of the lower diode UD (p-anode (DBR) layer 81) is connected to the Vsub terminal set to "H".

[0074] The cathodes of the odd-numbered transfer thyristors T1, T3, and T5 are connected to the first transfer signal line 72 and are set to "H". The cathodes of the even-numbered transfer thyristors T2, T4, and T6 are connected to the second transfer signal line 73 and are set to "H". Therefore, both the anode and cathode of the transfer thyristors T are "H", and they are in the off state. Similarly, both the anode and cathode of the lower diode UD are "H", and it is in the off state.

[0075] The cathode terminal of the setting thyristor S is connected to the "H" (0V) illumination signal line 75. Therefore, both the anode and cathode of the setting thyristor S are "H", and it is in the off state. Similarly, both the anode and cathode of the VCSEL are "H", and it is in the off state.

[0076] As mentioned above, gate Gt1 is connected to the cathode of start diode SD. Gate Gt1 is connected to power line 71 at power supply potential Vga ("L") via power line resistor Rg1. The anode terminal of start diode SD is connected to the second transfer signal line 73 and to the "H" φ2 terminal via current limiting resistor R2. Therefore, start diode SD is forward biased, and the cathode (gate Gt1) of start diode SD is at the value obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the potential of the anode ("H") of start diode SD (""). Also, when gate Gt1 is at -1.5V, coupling diode D1 is forward biased because its anode (gate Gt1) is at -1.5V and its cathode is connected to power line 71 ("L") via power line resistor Rg2. Therefore, the potential of gate Gt2 is -3V, which is the potential of gate Gt1 (-1.5V) minus the forward potential Vd (1.5V) of the pn junction. Furthermore, coupling diode D2 is forward biased because its anode (gate Gt1) is -3V and its cathode is connected to power line 71 ("L") via power line resistor Rg2. Therefore, the potential of gate Gt3 is -4.5V, which is the potential of gate Gt2 (-3V) minus the forward potential Vd (1.5V) of the pn junction. However, gates Gt with numbers 4 and above are not affected by the fact that the anode of start diode SD is "H", and the potential of these gates Gt is "L", which is the potential of power line 71.

[0077] Since gate Gt is gate Gs, the potential of gate Gs is the same as the potential of gate Gt. Therefore, the threshold voltages for transfer thyristor T and setting thyristor S are the potentials of gate Gt and Gs minus the forward potential Vd (1.5V) of the pn junction. That is, the threshold voltage for transfer thyristor T1 and setting thyristor S1 is -3V, the threshold voltage for transfer thyristor T2 and setting thyristor S2 is -4.5V, the threshold voltage for transfer thyristor T3 and setting thyristor S3 is -6V, and the threshold voltage for transfer thyristor T and setting thyristor S with numbers 4 or higher is -6.5V.

[0078] (2) Time b At time b shown in Figure 5, the first transfer signal φ1 transitions from "H" to "L". As a result, the light-emitting device 1 starts operating. When the first transfer signal φ1 transitions from "H" to "L", the potential of the first transfer signal line 72 transitions from "H" to "L" via the φ1 terminal and the current limiting resistor R1. As a result, the voltage applied to the transfer thyristor T1 is -3.3V, and the transfer thyristor T1, which has a threshold voltage of -3V, turns on. At this time, current flows through the lower diode UD1, causing it to transition from the off state to the on state. With the transfer thyristor T1 turning on, the potential of the first transfer signal line 72 becomes close to -3.2V (a negative potential with an absolute value greater than 3.2V), which is the anode potential of the transfer thyristor T1 (the potential applied to the lower diode UD1, which is -1.7V) minus the forward potential Vd (1.5V) of the pn junction. Note that the threshold voltage for transfer thyristor T3 is -6V, and the threshold voltage for transfer thyristor T5 is -6.5V. The voltage applied to transfer thyristors T3 and T5 is -1.5V, which is the sum of the voltage applied to the VCSEL (1.7V) and -3.2V. Therefore, transfer thyristors T3 and T5 do not turn on. On the other hand, even-numbered transfer thyristors T cannot be turned on because the second transfer signal φ2 is "H" and the second transfer signal line 73 is "H".

[0079] When the transfer thyristor T1 turns on, the potential of gate Gt1 / Gs1 becomes "H", which is the potential of the anode of transfer thyristor T1. Then, the potential of gate Gt2 (gate Gs2) becomes -1.5V, the potential of gate Gt3 (gate Gs3) becomes -3V, the potential of gate Gt4 (gate Gs4) becomes -4.5V, and the potential of gates Gt (gate Gl) numbered 5 or higher becomes "L". As a result, the threshold voltage for setting thyristor S1 becomes -1.5V, the threshold voltage for transfer thyristor T2 and setting thyristor S2 becomes -3V, the threshold voltage for transfer thyristor T3 and setting thyristor S3 becomes -4.5V, the threshold voltage for transfer thyristor T4 and setting thyristor S4 becomes -6V, and the threshold voltage for transfer thyristors T5, T6 and setting thyristors S5, S6 becomes -6.5V. However, the first transfer signal line 72 is -1.5V due to the ON transfer thyristor T1, so the OFF odd-numbered transfer thyristors T do not turn on. The second transfer signal line 73 is "H", so the even-numbered transfer thyristors T do not turn on. Also, the illumination signal line 75 is "H", so none of the VCSELs light up.

[0080] Immediately after time b (here, this refers to the time when a steady state is reached after changes in thyristors, etc., have occurred due to the change in signal potential at time b), the transfer thyristor T1 and lower diode UD1 are in the ON state, while the other transfer thyristor T, lower diode UD, setting thyristor S, and VCSEL are in the OFF state.

[0081] (3) Time c At time c, the lighting signal φI changes from "H" to "L". When the illumination signal φI transitions from "H" to "L", the illumination signal line 75 transitions from "H" to "L" via the current limiting resistor RI and the φI terminal. As a result, -3.3V, which is the voltage applied to the VCSEL plus 1.7V, is applied to the setting thyristor S1. The setting thyristor S1, which has a threshold voltage of -1.5V, turns on, and the VCSEL1 lights up (illuminates). This brings the potential of the illumination signal line 75 to a potential close to -3.2V. Note that the setting thyristor S2 has a threshold voltage of -3V, but the voltage applied to the setting thyristor S2 is -1.5V, which is the voltage applied to the VCSEL plus -3.2V, so the setting thyristor S2 does not turn on. Immediately after time c, the transfer thyristor T1, lower diode UD1, and setting thyristor S1 are in the ON state, and VCSEL1 is lit (emitting light).

[0082] (4) Time d At time d, the lighting signal φI changes from "L" to "H". When the illumination signal φI transitions from "L" to "H", the potential of the illumination signal line 75 transitions from -3.2V to "H" via the current limiting resistor RI and the φI terminal. As a result, both the cathode of the setting thyristor S1 and the anode of VCSEL1 become "H", causing the setting thyristor S1 to turn off and VCSEL1 to turn off (become unlit). The illumination period of VCSEL1 is the period from time c when the illumination signal φI transitions from "H" to "L" to time d when the illumination signal φI transitions from "L" to "H", during which the illumination signal φI is "L". Immediately after time d, the transfer thyristor T1 is in the ON state.

[0083] (5) Time e At time e, the second transfer signal φ2 transitions from "H" to "L". At this point, the period T(1) for controlling the illumination of VCSEL1 ends, and the period T(2) for controlling the illumination of VCSEL2 begins. When the second transfer signal φ2 transitions from "H" to "L", the potential of the second transfer signal line 73 transitions from "H" to "L" via the φ2 terminal. As mentioned above, the transfer thyristor T2 turns on because the threshold voltage is -3V. At this time, current flows through the lower diode UD2, causing it to transition from the off state to the on state. As a result, the potential of gate terminal Gt2 (gate terminal Gs2) becomes "H" (0V), the potential of gate Gt3 (gate Gs3) becomes -1.5V, the potential of gate Gt4 (gate Gs4) becomes -3V, the potential of gate Gt5 (gate Gs5) becomes -4.5V, and the potential of gate Gt6 (gate Gs6) becomes -5V. Immediately after time e, the transfer thyristors T1 and T2, and the lower diodes UD1 and UD2 are in the ON state.

[0084] (6) Time f At time f, the first transfer signal φ1 transitions from "L" to "H". When the first transfer signal φ1 transitions from "L" to "H", the potential of the first transfer signal line 72 transitions from "L" to "H" via the φ1 terminal. As a result, the ON transfer thyristor T1 turns off, with both its anode and cathode becoming "H". At this time, both the anode and cathode of the lower diode UD1 also become "H", transitioning from the ON state to the OFF state. As a result, the potential of gate Gt1 (gate Gs1) changes toward the power supply potential Vga ("L") of power supply line 71 via the power supply line resistor Rg1. This causes the coupling diode D1 to be in a state where the potential is applied in the direction in which no current flows (reverse bias). Therefore, the effect of gate Gt2 (gate Gs2) being "H" does not affect gate Gt1 (gate Gs1). In other words, the transfer thyristor T with gate Gt connected by a reverse-biased coupling diode D will not turn on even when the threshold voltage becomes -6.5V and the first transfer signal φ1 or the second transfer signal φ2 becomes "L". Immediately after time f, the transfer thyristor T2 and the lower diode UD2 are in the ON state.

[0085] (7) Others At time g, when the illumination signal φI changes from "H" to "L", the setting thyristor S2 turns on, and VCSEL2 lights up (illuminates), similar to VCSEL1 and setting thyristor S1 at time c. Then, at time h, when the illumination signal φI changes from "L" to "H", the setting thyristor S2 turns off, and VCSEL2 turns off, just like VCSEL1 and setting thyristor S1 at time d. Furthermore, at time i, when the first transfer signal φ1 transitions from "H" to "L", the transfer thyristor T3 with a threshold voltage of -3V turns on, similar to the transfer thyristor T1 at time b or the transfer thyristor T2 at time e. At time i, the period T(2) for controlling the illumination of VCSEL2 ends, and the period T(3) for controlling the illumination of VCSEL3 begins. From here on, it will be a repetition of what has been explained so far.

[0086] Furthermore, if you want to keep the VCSEL off (not lit) instead of turning it on (emitting light), you can simply keep the lighting signal φI at "H" as shown in Figure 5, from time j to time k during the period T(4) in which the VCSEL4 is controlled to light up. In this way, even if the threshold voltage of the setting thyristor S4 is -1.5V, the setting thyristor S4 will not turn on, and the VCSEL will remain off (not lit).

[0087] As mentioned earlier, the gate terminals Gt of the transfer thyristor T are interconnected by coupling diodes D. Therefore, when the potential of gate Gt changes, the potential of gate Gs, which is connected to the gate Gt with the changed potential via the forward-biased coupling diode D, also changes. Consequently, the threshold voltage of the transfer thyristor T with the gate whose potential has changed changes. The transfer thyristor T turns on when the threshold voltage is higher than -3.3V (a negative value with a small absolute value) at the timing when the first transfer signal φ1 or the second transfer signal φ2 transitions from "H" to "L". Then, the setting thyristor S, whose gate Gs is connected to the gate Gt of the ON transfer thyristor T, has a threshold voltage of -1.5V. Therefore, when the lighting signal φI changes from "H" to "L", it turns on, and the VCSEL connected in series with the setting thyristor S lights up (emits light).

[0088] In other words, when the transfer thyristor T turns on, it specifies the VCSEL that is the target of the lighting control, and the "L" lighting signal φI turns on the setting thyristor S connected in series with the VCSEL that is the target of the lighting control, and lights up the VCSEL. In other words, in the light-emitting chip 10, the VCSELs light up sequentially as the ON state of the transfer thyristor T is transferred. The "H" indicator signal φI keeps the setting thyristor S in the off state and keeps the VCSEL off. In other words, the indicator signal φI sets whether the VCSEL is on or off.

[0089] Note that the voltage used in this explanation is just an example and will need to be changed depending on the emission wavelength and light intensity of the VCSEL. In that case, you should adjust the potential ("L") of the ignition signal φI.

[0090] Thus, the light-emitting device 1 has multiple elements (transfer thyristors T1 to T128, setting thyristors S1 to S128, VCSEL1 to VCSEL128, etc.), and the elements that turn on one after the other transition to the ON state. As a result, in the light-emitting device 1, the multiple setting thyristors S are individually turned on by the lighting control by the light-emitting control unit 110. When each setting thyristor S turns on, the VCSEL corresponding to that setting thyristor S lights up individually. In the measuring device 1000, the system control unit 30 further controls the output of the signal in the light emission control unit 110, thereby emitting light for measurement.

[0091] (Manufacturing of the light-emitting chip 10) Next, the manufacturing of the light-emitting chip 10 to which the first embodiment is applied will be described. The process for manufacturing the light-emitting chip 10 can be mainly divided into two parts: (1) the process of manufacturing a semiconductor laminated substrate by stacking semiconductor layers on a substrate (hereinafter referred to as "(1) the semiconductor laminated substrate manufacturing process"), and (2) the process of processing the semiconductor laminated substrate into a light-emitting chip (hereinafter referred to as "(2) the processing into a light-emitting chip process").

[0092] First, the manufacturing process of the semiconductor laminated substrate (1) will be explained using Figure 6. Note that the semiconductor laminated substrate 100 described below has semiconductor layers similar to the island 301 of the light-emitting chip 10 explained using Figure 4, so the names and reference numerals of each layer will be the same as those in Figure 4. Similarly, the names and reference numerals of the semiconductor laminate and laminated structure will also be the same as those in Figure 4. Figure 6 is a diagram illustrating the manufacturing process of a semiconductor laminate substrate 100 to which the first embodiment is applied, where Figure 6(a) shows the process of forming a semiconductor laminate Lv to be processed into a VCSEL, Figure 6(b) shows the process of forming a tunnel junction layer 84, and Figure 6(c) shows the process of forming a semiconductor laminate Ls to be processed into a thyristor.

[0093] (1-1) Process of forming a semiconductor laminate Lv First, as shown in Figure 6(a), a p-anode (DBR) layer 81, an emissive layer 82, and an n-cathode (DBR) layer 83 are epitaxially grown on a p-type substrate 80 in that order to form a semiconductor laminate Lv. Each semiconductor layer is stacked by, for example, metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The semiconductor stack Lv is a semiconductor stack that is fabricated into the VCSEL of the light-emitting chip 10, and is an example of a first semiconductor stack fabricated into a light-emitting element. Furthermore, (1-1) the process of forming the semiconductor stack Lv is an example of a first stack formation process in which the first semiconductor stack is formed on a substrate.

[0094] In the embodiments of the present invention, the substrate 80 is described as p-type GaAs as an example, but n-type GaAs or intrinsic (i) GaAs without added impurities may also be used. Furthermore, semiconductor substrates made of InP, GaN, InAs, other III-V and II-VI materials, sapphire, Si, Ge, etc., may also be used. When the substrate is changed, the material monolithically laminated on the substrate is a material that substantially matches the lattice constant of the substrate (including strain structure, strain relaxation layer, and metamorphic growth). As an example, InAs, InAsSb, GaInAsSb, etc. are used on an InAs substrate; InP, InGaAsP, etc. are used on an InP substrate; GaN, AlGaN, InGaN are used on a GaN or sapphire substrate; and Si, SiGe, GaP, etc. are used on a Si substrate. However, when the material is attached to another support substrate after crystal growth, it is not necessary for the semiconductor material to substantially match the lattice of the support substrate.

[0095] The p-anode (DBR) layer 81 is formed by stacking a plurality of semiconductor layers provided with a difference in refractive index. More specifically, the p-anode (DBR) layer 81 is formed by alternately stacking high refractive index layers having a relatively high refractive index and low refractive index layers having a relatively low refractive index. Note that the description that a high refractive index layer has "a relatively high refractive index" means that the refractive index thereof is higher than that of the low refractive index layer. Similarly, the description that a low refractive index layer has "a relatively low refractive index" means that the refractive index thereof is lower than that of the high refractive index layer. Further, the n-cathode (DBR) layer 83, similar to the p-anode (DBR) layer 81, is formed by alternately stacking high refractive index layers having a relatively high refractive index and low refractive index layers having a relatively low refractive index. As an example, the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 are made of Al 0.2 Ga 0.8 As high refractive index layers with a low Al composition, and Al 0.9 Ga 0.1 As low refractive index layers with a high Al composition, formed by a combination of said high refractive index layers and said low refractive index layers.

[0096] As described above, the light-emitting layer 82 has a quantum well structure in which well layers and barrier layers are alternately stacked, and the well layers are formed of, for example, GaAs, AlGaAs, InGaAs, GaAsP, AlGaInP, GaInAsP, GaInP, or the like. Further, the barrier layers are formed of, for example, AlGaAs, GaAs, GaInP, GaInAsP, or the like.

[0097] (1-2) Step of forming tunnel junction layer 84 Next, as shown in FIG. 6(b), a tunnel junction layer 84 is formed on the semiconductor stacked body Lv. More specifically, the tunnel junction layer 84 in the first embodiment is formed by epitaxial growth on the n-cathode (DBR) layer 83, which is the uppermost layer among the semiconductor layers constituting the semiconductor stacked body Lv. The tunnel junction layer 84 includes n-type impurities added at a high concentration to an n ++ layer and n-type impurities added at a high concentration to a p ++ layer, and is configured by a junction between said n ++ layer 84a and the p++ For example, the layer has an impurity concentration of 1 × 10⁻⁶. 20 / cm 3 The impurity concentration of a normal bond is 10 17 / cm 3 ~10 18 / cm 3 It is highly concentrated in relation to n. ++ Layers and p ++ Combinations with layers (in the following, n ++ layer / p ++ It is expressed in layers. ) For example, n ++ GaInP / p ++ GaAs,n ++ GaInP / p ++ AlGaAs,n ++ GaAs / p ++ GaAs,n ++ AlGaAs / p ++ AlGaAs,n ++ InGaAs / p ++ InGaAs,n ++ GaInAsP / p ++ GaInAsP,n ++ GaAsSb / p ++ The compound is GaAsSb. Note that combinations with mutual substitutions are also acceptable.

[0098] (1-3) Process of forming a semiconductor laminate Ls Next, as shown in Figure 6(c), a p-anode layer 85, an n-gate layer 86, a p-gate layer 87, and an n-cathode layer 88 are epitaxially grown on the tunnel junction layer 84 in that order to form a semiconductor stack Ls. The semiconductor laminate Ls is a semiconductor laminate that is processed into a setting thyristor S of the light-emitting chip 10, and is an example of a second semiconductor laminate that is processed into a thyristor. Furthermore, (1-3) the process of forming the semiconductor laminate Ls is an example of a second laminate formation process in which a second semiconductor laminate is formed on a substrate.

[0099] The p-anode layer 85 has an impurity concentration of, for example, 1 × 10⁻⁶. 18 / cm 3 p-type Al 0.9 It is formed of GaAs. Furthermore, the n gate layer 86 has an impurity concentration of, for example, 1 × 10⁻⁶.17 / cm 3 n-type Al 0.9 It is GaAs. Furthermore, the p-gate layer 87 has an impurity concentration of, for example, 1 × 10⁻⁶. 17 / cm 3 p-type Al 0.9 It is GaAs. The n-cathode layer 88 has, for example, an impurity concentration of 1 × 10⁻⁶. 18 / cm 3 n-type Al 0.9 It is GaAs. The Al composition of the p-anode layer 85, n-gate layer 86, p-gate layer 87, and n-cathode layer 88 may be changed within the range of 0 to 1. 0.9 Other compositions, such as GaInP, may be used instead of GaAs.

[0100] By following the steps described above—(1-1) forming the semiconductor laminate Lv, (1-2) forming the tunnel junction layer 84, and (1-3) forming the semiconductor laminate Ls—a laminated structure L1 including the semiconductor laminate Lv, the tunnel junction layer 84, and the semiconductor laminate Ls is formed on the substrate 80, and a semiconductor laminated substrate 100 is manufactured.

[0101] (Adjustment of the layered structure L1) Incidentally, when evaluating the quality of products including light-emitting elements, the resonant wavelength of the light-emitting element, determined from the product's reflection profile, is used. For example, the resonant wavelength of the VCSEL is used to evaluate the quality of a semiconductor laminate containing a semiconductor laminate that will be processed into a VCSEL. However, when a light-emitting element and a thyristor used to drive the light-emitting element are laminated on the same substrate, the product's reflection profile includes information on the resonance due to the thyristor as well as the resonance of the light-emitting element. In such a product, if the resonance of the light-emitting element and the resonance due to the thyristor have the same resonant wavelength, it becomes difficult to determine the resonant wavelength of the light-emitting element from the reflection profile.

[0102] Therefore, in the semiconductor laminated substrate 100, the laminated structure L1 is adjusted so that the two resonance wavelengths λs1 and λs2 due to the influence of the set thyristor S are located on both sides of the resonance wavelength λv of the VCSEL. More specifically, in the semiconductor laminated substrate 100 to which the first embodiment is applied, the laminated structure L1 is adjusted by adjusting the thickness of the semiconductor layer formed in the (1-3) semiconductor laminate Ls formation process. Furthermore, the statement "the two resonant wavelengths λs1 and λs2 are located on either side of the VCSEL's resonant wavelength λv" means that, for the two resonant wavelengths λs1 and λs2, one resonant wavelength λs1 is smaller than the resonant wavelength λv (it is a short wavelength), and the other resonant wavelength λs2 is larger than the resonant wavelength λv (it is a long wavelength).

[0103] Here, we will describe an example of the procedure for adjusting the stacked structure L1 using a reflectance spectrum as an example of a reflectance profile. Figure 7 shows the reflectance spectrum. Figure 7(a) is the reflectance spectrum when only the semiconductor laminate Lv is formed on the substrate 80, and Figure 7(b) is the reflectance spectrum when the laminated structure L1 is formed. In other words, Figure 7(b) corresponds to the reflectance spectrum of the semiconductor laminate substrate. In Figures 7(a) and (b), the horizontal axis is wavelength [nm] and the vertical axis is reflectance [-]. Figure 8 illustrates the reflectance spectrum of the comparative semiconductor laminate substrate 100'. The comparative semiconductor laminate substrate 100' is identical to semiconductor laminate substrate 100, except that the laminate structure L1 has not been adjusted.

[0104] First, (1-1) after the step of forming the semiconductor laminate Lv, the reflectance spectrum is measured when only the semiconductor laminate Lv is formed on the substrate 80. For the measurement, for example, a known reflectance measuring device may be used, and the measurement is performed by irradiating the semiconductor laminate Lv with light from the side opposite to the substrate 80 (the side on which the n-cathode (DBR) layer 83 is formed) and measuring the light that returns due to reflection. This yields, for example, the reflectance spectrum shown in Figure 7(a). In the reflectance spectrum shown in Figure 7(a), the resonance wavelength λv corresponding to the semiconductor stack Lv, i.e., the VCSEL, is observed. As indicated by the white arrows, the resonance of the VCSEL is observed as a dip (valley) in reflectance, and although it has a width, the wavelength of the part where the dip in reflectance is largest (the bottom of the valley) is identified as the resonance wavelength λv. The same applies to the resonance wavelengths λs1 and λs2 due to the influence of the set thyristor S, which will be described later.

[0105] Next, after the (1-3) step of forming the semiconductor laminate Ls, the reflectance spectrum of the obtained semiconductor laminate substrate is measured. In the measured reflectance spectrum, as shown in Figure 7(b), two new resonance wavelengths λs1 and λs2 are observed due to the influence of the set thyristor S. In the first embodiment, the laminated structure L1 is adjusted so that the resonant wavelengths λs1 and λs2 are located on both sides of the resonant wavelength λv of the VCSEL. More specifically, as shown in Figure 7(b), the manufacturing of semiconductor laminated substrate samples and measurement of the reflectance spectra are repeated, with varying thicknesses t(85) and t(88) of the p-anode layer 85 and n-cathode layer 88, until a reflectance spectrum is obtained in which the resonant wavelengths λs1 and λs2 are located on both sides of the resonant wavelength λv.

[0106] Then, when a reflectance spectrum is obtained in which the resonant wavelengths λs1 and λs2 are located on both sides of the resonant wavelength λv, the thicknesses t(85) and t(88) in that sample are determined as the thicknesses of the p-anode layer 85 and n-cathode layer 88 in the final semiconductor laminated substrate 100. Subsequently, in the manufacturing process of the semiconductor laminated substrate 100, the p-anode layer 85 and n-cathode layer 88 are formed with these thicknesses. In this way, the laminated structure L1 according to the first embodiment is adjusted. In the reflectance spectrum of the semiconductor laminated substrate 100 manufactured in this manufacturing process, the resonance wavelengths λs1 and λs2 are located on both sides of the resonance wavelength λv, similar to Figure 7(b). Therefore, when evaluating the manufactured semiconductor laminated substrate 100, the resonance wavelength λv of the VCSEL is easier to determine compared to the case where either the resonance wavelength λs1 or λs2 is equal to the resonance wavelength λv.

[0107] In the semiconductor laminated substrate 100 to which the first embodiment is applied, the laminated structure L1 is adjusted by adjusting the thickness of at least one of the p-anode layer 85 and the n-cathode layer 88. Generally, in a thyristor, changing the thickness of the gate layer has a greater impact on the characteristics of the thyristor compared to changing the thickness of the anode layer or cathode layer. Therefore, in the semiconductor laminated substrate 100, by adjusting the thickness of at least one of the p-anode layer 85 and the n-cathode layer 88, the impact on the characteristics of the set thyristor S is suppressed compared to the case where only the n-gate layer 86 and the p-gate layer 87 are changed. In other embodiments, the thicknesses of the n-gate layer 86 and the p-gate layer 87 may be varied, while the thicknesses of the p-anode layer 85 and the n-cathode layer 88 may remain unchanged.

[0108] Furthermore, as explained using Figure 4, in the light-emitting chip 10 to which the first embodiment is applied, the p-anode layer 85 and the n-cathode layer 88 are thicker than the n-gate layer 86 and the p-gate layer 87. In other words, in the semiconductor laminate substrate 100, the laminate structure L1 is adjusted by making the p-anode layer 85 and the n-cathode layer 88 thicker than the n-gate layer 86 and the p-gate layer 87. By increasing the adjustment allowance provided by the p-anode layer 85 and the n-cathode layer 88 in this way, the influence on the characteristics of the set thyristor S is suppressed compared to the case where the n-gate layer 86 and the p-gate layer 87 are thicker than the p-anode layer 85 and the n-cathode layer 88.

[0109] Furthermore, as shown in Figure 7(b), the adjustment of the laminated structure L1 in the first embodiment is performed such that the resonance wavelength λv of the VCSEL is located within ±30% of the average M of the resonance wavelengths λs1 and λs2, with the interval between the two resonance wavelengths λs1 and λs2 due to the influence of the set thyristor S set to 100%. This suppresses the overlap between the dip in reflectivity corresponding to the resonance of the set thyristor S and the dip in reflectivity corresponding to the resonance of the VCSEL, compared to the case where the resonance wavelength λv is located outside the range, making it easier to determine the resonance wavelength λv of the VCSEL.

[0110] In the comparative example semiconductor laminated substrate 100' (not shown), where the laminated structure is not adjusted, the resonance wavelength λs1 or λs2 due to the influence of the set thyristor S may be the same as the resonance wavelength λv of the VCSEL. In this case, as shown in Figure 8, the dip (trough) in the reflectance corresponding to the resonance of the set thyristor S and the dip (trough) corresponding to the resonance of the VCSEL overlap in the reflectance spectrum, making it difficult to determine the resonance wavelength λv of the VCSEL from the reflectance spectrum.

[0111] In addition, if the resonant wavelength λs1 or λs2 of the semiconductor laminated substrate 100' is the same as the resonant wavelength λv of the VCSEL, the reflectance at wavelength λv will decrease significantly, and the reflectance necessary for laser oscillation of the VCSEL cannot be secured. In contrast, in the semiconductor laminated substrate 100 to which the embodiment of the present invention is applied, the decrease in reflectance at wavelength λv is suppressed, and the reflectance necessary for laser oscillation is secured.

[0112] In the above explanation, the procedure for adjusting the laminated structure L1 was described using the actual measurement of the reflectance spectra of semiconductor laminate Lv and semiconductor laminated substrate samples as an example. Instead of actually measuring the reflectance, the reflection profile for each wavelength may be calculated using a calculation method such as the characteristic matrix method, with the thickness of the semiconductor layer to be formed as a parameter, and the laminated structure L1 may be adjusted based on the calculation results.

[0113] The semiconductor laminate manufacturing process (1) described above also includes a first laminate formation step (1-1) of forming a semiconductor laminate Lv to be processed into a VCSEL on a substrate 80, and a second laminate formation step (1-3) of forming a semiconductor laminate Ls to be processed into a set thyristor S on the semiconductor laminate Lv, wherein the second laminate formation step (1-3) is characterized by forming semiconductor layers 85 to 88 whose thickness is determined so that two resonance wavelengths λs1 and λs2 due to the influence of the set thyristor S are located on both sides of the resonance wavelength λv of the VCSEL, and can also be understood as a method for manufacturing a semiconductor laminate 100.

[0114] Next, we will explain (2) the processing steps for the light-emitting chip using Figures 9 and 10. Figures 9 and 10 illustrate the processing steps from the semiconductor laminated substrate 100 to the light-emitting chip 10. Figure 9(a) shows the process of forming n-ohmic electrodes 321, 323, 324, etc., Figure 9(b) shows the process of separating into islands 301, 302, and Figure 9(c) shows the process of exposing the p-gate layer 87. Figure 10(d) shows the process of forming p-ohmic electrodes 331, 332, etc., Figure 10(e) shows the process of forming the protective layer 90, and Figure 10(f) shows the process of forming various wiring (power lines 71, first transfer signal lines 72, second transfer signal lines 73, lighting signal lines 75, etc.) and back surface electrodes 91.

[0115] (2-1) Steps for forming n-ohmic electrodes 321, 323, 324, etc. First, as shown in Figure 9(a), n-ohmic electrodes 321, 323, 324, etc. are formed on the n-cathode layer 88, which is the uppermost layer in the semiconductor laminate substrate 100. The n-ohmic electrodes 321, 323, 324 are made of Au (AuGe), which contains Ge, for example, and can easily form ohmic contact with n-type semiconductor layers such as the n-cathode layer 88. The n-ohmic electrodes 321, 323, 324, etc., are formed, for example, by the lift-off method.

[0116] (2-2) Process of separating into islands 301 and 302 Next, as shown in Figure 9(b), the n-cathode layer 88, p-gate layer 87, n-gate layer 86, p-anode layer 85, tunnel junction layer 84, n-cathode (DBR) layer 83, light-emitting layer 82, and p-anode (DBR) layer 81 are etched in sequence to separate them into islands such as islands 301 and 302. In other words, the laminated structure L1 formed on the substrate 80 is separated into individual islands. Etching may be performed by wet etching using a sulfuric acid-based etching solution (sulfuric acid:hydrogen peroxide:water = 1:10:300 by weight), or by anisotropic dry etching (RIE) using boron chloride, etc. This etching process is sometimes called mesa etching or post-etching.

[0117] Furthermore, when a current-constricting layer is provided in the p-anode (DBR) layer 81, for example, after the step of separating into islands 301 and 302 (2-2), the semiconductor layer may be oxidized from the side (the side exposed by etching) to form a current-blocking portion. This oxidation is carried out by oxidizing Al by steam oxidation at 300-400°C. At this time, oxidation proceeds from the exposed side, and a current-blocking portion made of Al2O3, an oxide of Al, is formed around the islands 301 and 302, while the unoxidized portion becomes a current-passing portion.

[0118] (2-3) Step of exposing the p gate layer 87 Next, as shown in Figure 9(c), a portion of the n-cathode layer 88 is etched to expose the p-gate layer 87. This creates a region 311 in island 301 where the p-gate layer 87 is exposed. Additionally, regions 313 and 314 in island 302 where the p-gate layer 87 is exposed are created. Furthermore, etching may be carried out by wet etching using a sulfuric acid-based etching solution (sulfuric acid:hydrogen peroxide:water = 1:10:300 by weight ratio), anisotropic dry etching using boron chloride, etc., similar to the process of separating into islands 301 and 302 (2-2).

[0119] (2-4) Steps for forming p-ohmic electrodes 331, 332, etc. Next, as shown in Figure 10(d), p-ohmic electrodes 331, 332, etc. are formed on the exposed p-gate layer 87. In the example in Figure 10(d), the p-ohmic electrode 331 is formed in the region 311 where the p-gate layer 87 is exposed. Also, the p-ohmic electrode 332 is formed in the region 313 where the p-gate layer 87 is exposed. The p-ohmic electrodes 331 and 332 are made of materials such as Au (AuZn), which contains Zn that easily forms ohmic contacts with p-type semiconductor layers such as the p-gate layer 87, and are formed by methods such as the lift-off method.

[0120] (2-5) Steps to form the protective layer 90 Next, as shown in Figure 10(e), a protective layer 90 is formed to cover the surfaces of islands 301, 302, etc. At this time, the light-emitting port 90A (see Figure 3(b)) and through-holes (see Figure 3(a)) of the light-emitting chip 10 are also formed. The protective layer 90 is made of an insulating material such as SiO2, SiON, or SiN.

[0121] (2-6) Process of forming various wirings and back electrode 91 Finally, as shown in Figure 10(f), various wirings (power lines 71, first transfer signal lines 72, second transfer signal lines 73, lighting signal lines 75, etc.) and back surface electrodes 91 are formed. In this step, wiring is formed to connect the n-ohmic electrodes 321, 323, 324 and the p-ohmic electrodes 331, 332, etc., through through holes provided in the protective layer 90. These wirings are made of metallic materials such as Al or Au.

[0122] Thus, in the embodiment of the present invention, the semiconductor laminated substrate 100 having a laminated structure L1 is processed into a light-emitting chip 10 by steps (2-1) to (2-6). As mentioned above, the laminated structure L1 is adjusted so that the two resonant wavelengths λs1 and λs2, due to the influence of the set thyristor S, are located on both sides of the resonant wavelength λv of the VCSEL (see Figure 7). Therefore, the light-emitting chip 10 to which the first embodiment is applied is an example of a light-emitting component in which the laminated structure has been adjusted so that the two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element. Furthermore, the light-emitting device 1 and the measuring device 1000 using the light-emitting chip 10 are examples of a light-emitting device and a measuring device, respectively, in which the laminated structure has been adjusted so that the two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element.

[0123] When evaluating the light-emitting chip 10, light-emitting device 1, or measuring device 1000 as a product, for example, the thickness of the semiconductor layers constituting the island 301 of the light-emitting chip 10 can be measured using a transmission electron microscope (TEM), and calculations can be performed using the characteristic matrix method based on the thickness of each layer. The reflection profile obtained from the calculation includes information on resonance due to the influence of the set thyristor S as well as the resonance of the VCSEL, but as mentioned above, since the stacked structure L1 is adjusted, the resonance wavelength λv of the VCSEL is easy to determine.

[0124] Thus, according to the semiconductor laminated substrate 100, light-emitting chip 10, light-emitting device 1, measuring device 1000, and manufacturing method of the semiconductor laminated substrate 100 to which the first embodiment is applied, it becomes easier to determine the resonance wavelength λv of the VCSEL compared to the case where the resonance of the VCSEL and the resonance due to the influence of the set thyristor S have the same resonance wavelength.

[0125] <Second Embodiment> The second embodiment differs from the first embodiment in that the laminated structure L2 includes an intermediate layer 89 provided between the semiconductor laminate Lv and the semiconductor laminate Ls, and the laminated structure L2 is adjusted by adjusting the thickness of this intermediate layer 89. Figure 11 illustrates the light-emitting chip 10-2 and semiconductor laminated substrate 100-2 to which the second embodiment is applied. Figure 11(a) is an enlarged cross-sectional view of the island in which the VCSEL and setting thyristor S are stacked in the light-emitting chip 10-2 to which the second embodiment is applied, and Figure 11(b) shows the stacked structure L2 of the semiconductor laminated substrate 100-2 to which the second embodiment is applied. In Figures 11(a) and (b), the same reference numerals are used for parts that are the same as in Figures 4 and 6(c), and their descriptions are omitted. Note that Figure 11(a) is shown in the same way as the light-emitting chip 10 to which the first embodiment shown in Figure 4 is applied, with the p-ohmic electrode 331 visible and the protective layer 90 omitted.

[0126] As shown in Figure 11(a), the light-emitting chip 10-2 has a laminated structure L2 that includes a semiconductor laminate Lv constituting the VCSEL, a tunnel junction layer 84, an intermediate layer 89, and a semiconductor laminate Ls constituting the setting thyristor S.

[0127] The intermediate layer 89 is not limited as long as it can maintain the electrical connection between the VCSEL and the setting thyristor S. GaInP, GaAs, AlGaAs, etc. may be used, and as long as it can maintain the electrical connection, for example, an impurity concentration of 10 17 / cm 3 ~10 20 / cm 3 Materials of a certain degree are used. However, since n-type semiconductors generally have a lower resistivity than p-type semiconductors, by constructing the intermediate layer 89 with an n-type semiconductor, the drive voltage of the VCSEL can be reduced compared to when it is constructed with a p-type semiconductor. Furthermore, the intermediate layer 89 can be located anywhere between the semiconductor stack Lv and the semiconductor stack Ls, and may be above or below the tunnel junction layer 84.

[0128] In FIG. 11(a), an example is shown in which an intermediate layer 89 formed of one n-type semiconductor layer is provided below the tunnel junction layer 84. The thickness of the intermediate layer 89 is greater than that of the n-gate layer 86 and the p-gate layer 87 of the set thyristor S. It is also thicker than the p-anode layer 85 and the n-cathode layer 88. In other words, when the thickness of each layer in the semiconductor stacked body Ls constituting the set thyristor S is expressed as t(i) using the reference sign i of each semiconductor layer, the relationship t(86), t(87) < t(85), t(88) < t(89) is satisfied. The magnitude relationship of the thicknesses of the respective layers is the same in the semiconductor stacked substrate 100-2 shown in FIG. 11(b).

[0129] The light-emitting chip 10-2 is manufactured by processing the semiconductor stacked substrate 100-2 shown in FIG. 11(b). In the example shown in the figure, the semiconductor stacked substrate 100-2 differs from the semiconductor stacked substrate 100 only in that it includes the intermediate layer 89. Therefore, to manufacture the semiconductor stacked substrate 100-2, in the (1) semiconductor stacked substrate manufacturing step described with reference to FIG. 6, a step of forming the intermediate layer 89 may be provided after the step of (1-1) forming the semiconductor stacked body Lv and before the step of (1-3) forming the semiconductor stacked body Ls. Furthermore, processing from the semiconductor stacked substrate 100-2 into the light-emitting chip 10-2 may be performed in the same manner as the (2) processing step into a light-emitting chip described with reference to FIGS. 9 and 10.

[0130] Here, in the semiconductor stacked substrate 100-2 to which the second embodiment is applied, the stacked structure L2 is adjusted by adjusting the thickness of the intermediate layer 89, so that the two resonance wavelengths λs1 and λs2 influenced by the set thyristor S are located on both sides of the resonance wavelength λv of the VCSEL. In addition, in the examples shown in FIGS. 11(a) and (b), the stacked structure L2 is adjusted by adjusting both the thickness of the intermediate layer 89 and the thicknesses of the p-anode layer 85 and the n-cathode layer 88. The adjustment of the stacked structure L2 may be performed by adjusting the thickness of the intermediate layer 89 and the like using the same procedure as in the first embodiment. In this way, by adjusting the thickness of the intermediate layer 89 and thereby adjusting the stacked structure L2, the influence on the characteristics of the set thyristor S is suppressed compared to the case where only the thickness of the semiconductor layers constituting the semiconductor stack Ls is adjusted.

[0131] As mentioned above, in the example shown in Figures 11(a) and (b), the intermediate layer 89 is thicker than the n-gate layer 86 and the p-gate layer 87, and also thicker than the p-anode layer 85 and the n-cathode layer 88. In this way, when adjusting the stacked structure L2, increasing the adjustment range provided by the intermediate layer 89 further suppresses the influence on the characteristics of the set thyristor S. Alternatively, the thickness of the intermediate layer 89 may be adjusted without adjusting the thickness of the p-anode layer 85 and the n-cathode layer 88. In this case as well, the influence on the characteristics of the set thyristor S is suppressed. Furthermore, the thicknesses of the n-gate layer 86 and the p-gate layer 87 may also be adjusted.

[0132] In the second embodiment, as in the first embodiment, it is preferable to adjust the stacked structure L2 so that the resonant wavelength λv of the VCSEL is within ±30% of the average M of the two resonant wavelengths λs1 and λs2 due to the influence of the set thyristor S (see Figure 7(b)).

[0133] In the semiconductor laminated substrate 100-2, the light-emitting chip 10-2, and the manufacturing method of the semiconductor laminated substrate 100 to which the second embodiment is applied, similar to the first embodiment, it becomes easier to determine the resonance wavelength λv of the VCSEL compared to the case where the resonance of the VCSEL and the resonance due to the influence of the set thyristor S have the same resonance wavelength. The same effect is also achieved in the light-emitting device 1 and measuring device 1000 to which the light-emitting chip 10-2 is applied instead of the light-emitting chip 10.

[0134] The semiconductor laminated substrate 100 to which the first embodiment described above is applied and the semiconductor laminated substrate 100-2 to which the second embodiment is applied are also understood as semiconductor laminated substrates comprising a substrate 80, a semiconductor laminate Lv provided on the substrate 80 and processed into a VCSEL, and laminated structures L1 and L2 provided on the semiconductor laminate Lv and including a semiconductor laminate Ls processed into a setting thyristor S, wherein the laminated structures L1 and L2 are adjusted so that two resonance wavelengths λs1 and λs2 due to the influence of the setting thyristor S are located on both sides of the resonance wavelength λv of the VCSEL.

[0135] <Examples of variations, etc.> In the first and second embodiments described above, a tunnel junction layer 84 is provided between the semiconductor laminate Lv and the semiconductor laminate Ls. The tunnel junction layer 84 is not an essential component; for example, a layer of a metallic conductive III-V compound may be provided instead of the tunnel junction layer 84. Furthermore, the laminated structures such as semiconductor laminated substrates to which the embodiments of the present invention are applied are not limited to those described above. Other layers may be added or some layers removed, as long as it is not inconsistent.

[0136] Furthermore, in the first and second embodiments, a light output port 90A is provided in the protective layer 90, and light from the VCSEL is emitted through this light output port 90A. Depending on the composition of the semiconductor layers constituting the tunnel junction layer 84 and the setting thyristor S, some of the light from the VCSEL may be reflected or absorbed by the tunnel junction layer 84 and the setting thyristor S, which may reduce the light extraction efficiency. Therefore, in the first and second embodiments, the semiconductor layer, tunnel junction layer 84, and intermediate layer 89 constituting the setting thyristor S below the light output port 90A may be removed by etching to expose the VCSEL. In addition, as in the example in Figure 11, if the intermediate layer 89 is provided directly above the VCSEL, GaInP or the like may be used for the intermediate layer 89, and the intermediate layer 89 may be used as a so-called etching stop layer.

[0137] The measuring device 1000 can be used to measure the three-dimensional shape of an object, measure the distance to an object, and recognize an object from its identified three-dimensional shape. For example, the measuring device 1000 can be mounted on a portable information processing device and used to recognize the face of a user attempting to access it. In other words, it acquires the three-dimensional shape of the accessing user's face, identifies whether or not access is permitted, and only allows the use of the device (information processing device) if the user is recognized as an authorized user. The measuring device 1000 can also be used in cases where the three-dimensional shape of an object is continuously measured, such as in augmented reality (AR) technology. Furthermore, the application range of the light-emitting device 1 is not limited to measuring devices, but can be applied to various uses as a light source.

[0138] Although embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the embodiments described above. It is clear from the claims that combinations of the above embodiments, as well as various modifications or improvements to the above embodiments, are also included in the technical scope of the present invention.

[0139] <Note> (((1))) circuit board and The laminated structure includes a first semiconductor laminate provided on the substrate and processed into a light-emitting element, and a second semiconductor laminate provided on the first semiconductor laminate and processed into at least one thyristor. A semiconductor laminated substrate characterized in that the laminated structure is adjusted so that the two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element. (((2))) The semiconductor laminated substrate according to (((1))), characterized in that the adjustment of the laminated structure is performed by adjusting the thickness of at least one layer of the second semiconductor laminate. (((3))) The second semiconductor stack comprises at least an anode layer, a first gate layer, a second gate layer, and a cathode layer. The semiconductor laminated substrate according to (((2))), characterized in that the adjustment of the laminated structure is performed by adjusting the thickness of at least one of the anode layer and the cathode layer of the second semiconductor laminate. (((4))) The semiconductor laminated substrate according to (((3))), characterized in that the adjustment of the laminated structure is performed by making at least one of the anode layer and the cathode layer thicker than the first gate layer and the second gate layer. (((5))) The laminated structure includes an intermediate layer provided between the first semiconductor laminate and the second semiconductor laminate. The semiconductor laminated substrate according to (((1))) to (((4))), characterized in that the adjustment of the laminated structure is performed by adjusting the thickness of the intermediate layer. (((6))) The semiconductor laminated substrate according to (((5))), characterized in that the intermediate layer is composed of an n-type semiconductor. (((7))) The semiconductor laminated substrate according to (((1))) to (((6))), characterized in that the adjustment of the laminated structure is performed such that the resonance wavelength of the light-emitting element is located within ±30% of the average of the two resonance wavelengths due to the influence of the thyristor, with the interval between the two resonance wavelengths due to the influence of the thyristor being set to 100%. (((8))) A substrate having a laminated structure formed on it, which includes a first semiconductor laminate and a second semiconductor laminate overlapping the first semiconductor laminate, A first semiconductor stack comprising at least one light-emitting element, The device comprises the second semiconductor stack described above, and includes at least one thyristor which, when turned on, causes the light-emitting element to emit light or increases the amount of light emitted, A light-emitting component characterized in that the laminated structure is adjusted so that the two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element. (((9))) A substrate having a laminated structure formed on it, which includes a first semiconductor laminate and a second semiconductor laminate overlapping the first semiconductor laminate, A light-emitting section having at least one light-emitting element composed of the first semiconductor stack, The device includes a drive unit that drives the light-emitting element, which includes at least one thyristor composed of the second semiconductor stack, A light-emitting device characterized in that the laminated structure is adjusted so that the two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element. (((10))) A substrate having a laminated structure formed on it, which includes a first semiconductor laminate and a second semiconductor laminate overlapping the first semiconductor laminate, A light-emitting section having at least one light-emitting element composed of the first semiconductor stack, A drive unit that drives the light-emitting element, including at least one thyristor composed of the second semiconductor stack, The system comprises a measuring unit that performs measurements on an object based on the light emitted from the light-emitting unit and reflected by the object, A measuring device characterized in that the stacked structure is adjusted so that the two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element. (((11))) A first laminate formation step of forming a first semiconductor laminate on a substrate which is processed into at least one light-emitting element, The process includes a second laminate formation step of forming a second semiconductor laminate, which is processed into at least one thyristor, on the first semiconductor laminate formed by the first laminate formation step, A method for manufacturing a semiconductor laminate, characterized in that the second laminate formation step involves forming a semiconductor layer whose thickness is determined such that the two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element. (((12))) A first laminate formation step of forming a first semiconductor laminate on a substrate which is processed into at least one light-emitting element, An intermediate layer formation step is performed to form an intermediate layer on the first semiconductor laminate formed by the first laminate formation step, The process comprises a second laminate formation step of forming a second semiconductor laminate, which is processed into at least one thyristor, on the intermediate layer formed by the intermediate layer formation step, A method for manufacturing a semiconductor laminated substrate, characterized in that the intermediate layer formation step is characterized by forming an intermediate layer in which the two resonant wavelengths due to the influence of the thyristor are determined to be located on both sides of the resonant wavelength of the light-emitting element.

[0140] According to the semiconductor multilayer substrates described in (((1))), (((8))) to (((12))), a semiconductor multilayer substrate is provided that makes it easier to determine the resonance wavelength of the light-emitting element compared to the case where the resonance of the light-emitting element and the resonance due to the influence of the thyristor have the same resonance wavelength. According to the semiconductor laminate substrate described in (((2))), the influence on the characteristics of the light-emitting element is suppressed compared to the case where the thickness of the layers of the first semiconductor laminate is adjusted. According to the semiconductor multilayer substrate described in (((3))), the influence on the characteristics of the drive unit is suppressed compared to the case where the thickness of the first gate layer and the second gate layer is adjusted. According to the semiconductor laminate substrate described in (((4))), the influence on the characteristics of the drive unit is suppressed compared to the case where the first gate layer and the second gate layer are thicker than the anode layer and the cathode layer. According to the semiconductor laminate substrate described in (((5))), the influence on the characteristics of the light-emitting element is suppressed compared to the case where only the thickness of the layers of the first semiconductor laminate is adjusted. According to the semiconductor multilayer substrate described in (((6))), the driving voltage is lower compared to the case where the intermediate layer is composed of a p-type semiconductor. According to the semiconductor multilayer substrate described in (((7))), it becomes easier to determine the resonant wavelength of the light-emitting element compared to the case where the resonant wavelength of the light-emitting element is located outside the range. [Explanation of Symbols]

[0141] 1…Light-emitting device, 10,10-2…Light-emitting chip, 100,100-2…Semiconductor multilayer substrate, 1000…Measuring device, L1,L2…Laminated structure, Lv,Ls…Semiconductor stack, S…Setting thyristor, VCSEL…Vertical cavity surface-emitting laser

Claims

1. circuit board and The laminated structure includes a first semiconductor laminate provided on the substrate and processed into a light-emitting element, and a second semiconductor laminate provided on the first semiconductor laminate and processed into at least one thyristor. The laminated structure is adjusted so that the two resonant wavelengths due to the influence of the thyristor are located on either side of the resonant wavelength of the light-emitting element. A semiconductor laminated substrate characterized in that the adjustment of the laminated structure is performed by adjusting the thickness of at least one layer of the second semiconductor laminate.

2. The second semiconductor stack comprises at least an anode layer, a first gate layer, a second gate layer, and a cathode layer. The semiconductor laminated substrate according to claim 1, characterized in that the adjustment of the laminated structure is performed by adjusting the thickness of at least one of the anode layer and the cathode layer of the second semiconductor laminate.

3. The semiconductor laminated substrate according to claim 2, characterized in that the adjustment of the laminated structure is performed by making at least one of the anode layer and the cathode layer thicker than the first gate layer and the second gate layer.

4. The laminated structure includes an intermediate layer provided between the first semiconductor laminate and the second semiconductor laminate. The semiconductor laminated substrate according to claim 1, characterized in that the adjustment of the laminated structure is performed by adjusting the thickness of the intermediate layer.

5. The semiconductor laminate substrate according to claim 4, characterized in that the intermediate layer is made of an n-type semiconductor.

6. The semiconductor laminated substrate according to claim 1, characterized in that the adjustment of the laminated structure is performed such that the resonance wavelength of the light-emitting element is located within ±30% of the average of the two resonance wavelengths due to the influence of the thyristor, with the interval between the two resonance wavelengths due to the influence of the thyristor being set to 100%.

7. A substrate having a laminated structure formed on it, which includes a first semiconductor laminate and a second semiconductor laminate superimposed on the first semiconductor laminate, A first semiconductor stack comprising at least one light-emitting element, The device comprises the second semiconductor stack described above, and includes at least one thyristor which, when turned on, causes the light-emitting element to emit light or increases the amount of light emitted, The laminated structure is adjusted so that the two resonant wavelengths due to the influence of the thyristor are located on either side of the resonant wavelength of the light-emitting element. The light-emitting component is characterized in that the adjustment of the laminated structure is performed by adjusting the thickness of at least one layer of the second semiconductor laminate.

8. A substrate having a laminated structure formed on it, which includes a first semiconductor laminate and a second semiconductor laminate superimposed on the first semiconductor laminate, A light-emitting section having at least one light-emitting element composed of the first semiconductor stack, The device includes a drive unit that drives the light-emitting element, which includes at least one thyristor made of the second semiconductor stack, The laminated structure is adjusted so that the two resonant wavelengths due to the influence of the thyristor are located on either side of the resonant wavelength of the light-emitting element. The light-emitting device is characterized in that the adjustment of the laminated structure is performed by adjusting the thickness of at least one layer of the second semiconductor laminate.

9. A substrate having a laminated structure formed on it, which includes a first semiconductor laminate and a second semiconductor laminate superimposed on the first semiconductor laminate, A light-emitting section having at least one light-emitting element composed of the first semiconductor stack, A drive unit that drives the light-emitting element, including at least one thyristor made of the second semiconductor stack, The system comprises a measuring unit that performs measurements on an object based on the light emitted from the light-emitting unit and reflected by the object, The laminated structure is adjusted so that the two resonant wavelengths due to the influence of the thyristor are located on either side of the resonant wavelength of the light-emitting element. The measuring device is characterized in that the adjustment of the laminated structure is performed by adjusting the thickness of at least one layer of the second semiconductor laminate.

10. A first laminate formation step of forming a first semiconductor laminate on a substrate which will be processed into at least one light-emitting element, The process includes a second laminate formation step of forming a second semiconductor laminate, which is processed into at least one thyristor, on the first semiconductor laminate formed by the first laminate formation step, A method for manufacturing a semiconductor laminate substrate, characterized in that the second laminate formation step involves forming a semiconductor layer whose thickness is determined such that the two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element.

11. A first laminate formation step of forming a first semiconductor laminate on a substrate which will be processed into at least one light-emitting element, An intermediate layer formation step is performed to form an intermediate layer on the first semiconductor laminate formed by the first laminate formation step, The process includes a second laminate formation step of forming a second semiconductor laminate, which is processed into at least one thyristor, on the intermediate layer formed by the intermediate layer formation step, A method for manufacturing a semiconductor laminate, characterized in that the intermediate layer formation step involves forming an intermediate layer whose thickness is determined such that the two resonant wavelengths due to the influence of the thyristor are located on both sides of the resonant wavelength of the light-emitting element.

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