Manufacturing method for silicon carbide semiconductor devices

Abstract

To provide a method for manufacturing a silicon carbide semiconductor device capable of reducing or alleviating the warpage of a silicon carbide semiconductor substrate and reducing the occurrences of conveyance failures, stage chuck failures, and patterning failures, etc. in a manufacturing apparatus.SOLUTION: A method for manufacturing a silicon carbide semiconductor device includes the steps of: preparing a silicon carbide semiconductor substrate 30 provided with a first semiconductor layer of a first conductivity type on the front surface side of a starting substrate of the first conductivity type; forming a first semiconductor region 5 of a second conductivity type in the first semiconductor layer by ion injection; relaxing the warpage of the silicon carbide semiconductor substrate 30 after forming the first semiconductor region 5; forming a second semiconductor layer 3 of the second conductivity type in the first semiconductor layer by ion injection; forming a third semiconductor layer 7 of the first conductivity type on a surface layer of the second semiconductor layer 3 by ion injection; activating the first semiconductor region 5, second semiconductor layer 3, and third semiconductor layer 7 formed by ion injection; and forming a trench 18 reaching the first semiconductor layer through the third semiconductor layer 7 and the second semiconductor layer 3 in a position facing a depth direction of the first semiconductor layer 4.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be the next-generation semiconductor material to replace silicon (Si). Semiconductor devices using silicon carbide as the semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) have various advantages compared to conventional semiconductor devices using silicon as the semiconductor material, such as being able to reduce the resistance of the device in the ON state to a fraction of that of silicon, and being usable in environments with higher temperatures (above 200°C). This is due to the inherent characteristics of the material itself, such as the fact that the band gap of silicon is about three times larger than that of silicon, and the dielectric breakdown field strength is nearly an order of magnitude greater than that of silicon.

[0003] To date, silicon carbide semiconductor devices that have been commercialized include Schottky barrier diodes (SBDs) and vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with planar gate or trench gate structures.

[0004] The structure of conventional silicon carbide semiconductor devices will be explained using a trench-type MOSFET as an example. In a trench-type MOSFET, n + n + A type buffer layer and an n-type silicon carbide epitaxial layer are deposited. + The surface side opposite to the starting substrate side is provided with an n-type high-concentration region. + On the surface layer opposite to the starting substrate side, the first p + A type-based region is selectively provided. In the n-type high-concentration region, a second p-type region is provided so as to cover the entire bottom surface of the trench. + A type base region is selectively provided.

[0005] Further, the conventional trench-type MOSFET further includes a p-type base region, an n + -type source region, a p ++ -type contact region, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, a back surface electrode, a trench, a source electrode pad and a drain electrode pad. The source electrode is provided on the n + -type source region and the p ++ -type contact region, and a source electrode pad is provided on the source electrode.

[0006] SiC has a problem that the diffusion coefficient of impurities in SiC is extremely small compared to Si. When forming an impurity layer by ion implantation, it is difficult to form the impurity layer deep in the depth direction. For this reason, when forming a structure in the vertical direction of a substrate like a trench-type MOSFET, an impurity layer is formed by combining ion implantation and epitaxial growth.

[0007] Conventionally, in a trench-type MOSFET, an impurity layer is formed, for example, as follows. First, an n + -type starting substrate has an n + -type buffer layer and an n-type silicon carbide epitaxial layer deposited on the front surface thereof. Next, n-type impurities are ion-implanted to form an n-type high-concentration region. Next, p-type impurities are ion-implanted to form a first p + -type base region and a second p + -type base region. Next, an n-type silicon carbide layer is epitaxially grown. Next, p-type impurities are ion-implanted to form a p-type base region. Next, n-type impurities are ion-implanted to form an n + -type source region. Next, p-type impurities are ion-implanted to form a p ++ -type contact region. After that, activation treatment is performed to form a trench. As described above, the impurity layer is formed by combining ion implantation and epitaxial growth.

[0008] On the other hand, epitaxial growth can create substrate defects, degrading the properties of semiconductor devices. Furthermore, epitaxial growth equipment incurs significant costs for process control and maintenance. Therefore, development is progressing on silicon carbide semiconductor devices that avoid epitaxial growth and instead combine conventional energy ion implantation (~900 KeV) with high-acceleration ion implantation (acceleration of 1 MeV or more) to implant impurities to deeper locations, forming the impurity layer solely through ion implantation.

[0009] Furthermore, when substrate thinning is introduced into the silicon carbide semiconductor device manufacturing process, a method for manufacturing silicon carbide semiconductor devices is known that controls the amount of wafer warping by removing at least a portion of the processed altered layer formed on the grinding surface, thereby reducing the amount of wafer warping that occurs in the subsequent electrode formation process on the back and front surfaces to a value that does not affect the manufacturing process (see Patent Document 1 below).

[0010] Furthermore, a method for manufacturing a silicon carbide semiconductor device is known, which includes a step of implanting predetermined ions into a second main surface of a SiC epitaxial substrate on which a SiC epitaxial growth layer with a thickness of 50 μm or more is disposed, thereby forming an ion implantation region that controls the warping of the SiC epitaxial substrate (see Patent Document 2 below). [Prior art documents] [Patent Documents]

[0011] [Patent Document 1] Patent No. 5550738 [Patent Document 2] Patent No. 6272488 [Overview of the Initiative] [Problems that the invention aims to solve]

[0012] In the manufacturing of semiconductor devices, forming an impurity layer by ion implantation can cause the semiconductor substrate to warp. This problem is particularly pronounced in silicon carbide semiconductor devices, where the diffusion coefficient of impurities is extremely low, due to the high acceleration and high concentration of ions implanted, sometimes resulting in warping of several hundred micrometers or more. Conventionally, semiconductor devices were manufactured by combining ion implantation and epitaxial growth, so the warping canceled out due to the difference in their warping directions, resulting in warping of only a few tens of micrometers. However, when forming an impurity layer by ion implantation alone, the warping of the substrate is not mitigated. In that case, there are problems such as transport failures within the manufacturing equipment, stage chuck failures, and patterning failures.

[0013] The present invention aims to provide a method for manufacturing a silicon carbide semiconductor device that can reduce or mitigate warping of the silicon carbide semiconductor substrate, thereby reducing or suppressing the occurrence of transport defects, stage chuck defects, patterning defects, etc., within the manufacturing equipment. [Means for solving the problem]

[0014] To solve the above-mentioned problems and achieve the objectives of the present invention, the method for manufacturing a silicon carbide semiconductor device according to this invention has the following features. First, a first step is performed to prepare a silicon carbide semiconductor substrate in which a first semiconductor layer of the first conductivity type with a lower impurity concentration than that of the starting substrate is provided on the front side of a starting substrate of the first conductivity type. Next, a second step is performed to form a first semiconductor region of the second conductivity type within the first semiconductor layer by ion implantation. Next, a third step is performed to correct the warping of the silicon carbide semiconductor substrate after the formation of the first semiconductor region. Next, a fourth step is performed to form a second semiconductor layer of the second conductivity type within the first semiconductor layer by ion implantation. Next, a fifth step is performed to form a third semiconductor layer of the first conductivity type on the surface layer of the second semiconductor layer by ion implantation. Next, a sixth step is performed to activate the first semiconductor region, the second semiconductor layer, and the third semiconductor layer formed by ion implantation. Next, a seventh step is performed in which a trench is formed at a position opposite the first semiconductor region in the depth direction, penetrating the third semiconductor layer and the second semiconductor layer and reaching the first semiconductor layer. Next, an eighth step is performed in which a gate electrode is formed inside the trench via a gate insulating film. Next, a ninth step is performed in which a first electrode is formed in contact with the third semiconductor layer and the second semiconductor layer. Next, a tenth step is performed in which a second electrode is formed on the back surface of the starting substrate.

[0015] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to this invention, in the invention described above, after the fifth step, 6 The process further includes an 11th step of performing a process to correct the warping of the silicon carbide semiconductor substrate prior to the process.

[0016] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to this invention is characterized in that, in the second step described above, a second semiconductor region of a second conductivity type is further formed between the trenches in the first semiconductor layer by ion implantation.

[0017] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to this invention is characterized in that, in the above-described invention, the process for correcting the warp is to form a crushed layer on the back surface of the silicon carbide semiconductor substrate.

[0018] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the crushed layer is formed by grinding the back surface of the silicon carbide semiconductor substrate.

[0019] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the crushed layer is formed with a thickness of 100 nm or more and 500 nm or less.

[0020] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to this invention is characterized in that, in the above-described invention, the process for correcting the warp reduces the amount of warp of the silicon carbide semiconductor substrate to less than 100 μm.

[0021] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the process of restoring the warp is performed after ion implantation is performed each time ion implantation is carried out.

[0022] According to the invention described above, a crushed layer is formed by grinding the second main surface of the silicon carbide semiconductor substrate. This reduces the amount of warping of the silicon carbide semiconductor substrate caused by ion implantation, thereby reducing the amount of warping of the silicon carbide semiconductor substrate. As a result, it is possible to reduce or suppress the occurrence of transport defects, stage chuck defects, patterning defects, etc., within the manufacturing equipment. [Effects of the Invention]

[0023] The silicon carbide semiconductor device manufacturing method according to the present invention has the effect of reducing or mitigating warping of the silicon carbide semiconductor substrate, thereby reducing or suppressing the occurrence of transport defects, stage chuck defects, patterning defects, etc., within the manufacturing equipment. [Brief explanation of the drawing]

[0024] [Figure 1] This is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to an embodiment. [Figure 2]This is a flowchart illustrating the outline of the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 3] This is a schematic cross-sectional view (part 1) showing the state during the manufacturing process of a silicon carbide semiconductor device according to an embodiment. [Figure 4] This is a schematic cross-sectional view (part 2) showing the state during the manufacturing process of a silicon carbide semiconductor device according to the embodiment. [Figure 5] This is a schematic cross-sectional view (part 3) showing the state during the manufacturing process of a silicon carbide semiconductor device according to the embodiment. [Figure 6] This is a schematic cross-sectional view (part 4) showing the state during the manufacturing process of a silicon carbide semiconductor device according to the embodiment. [Figure 7] This is a schematic cross-sectional view (part 5) showing the state during the manufacturing process of a silicon carbide semiconductor device according to the embodiment. [Figure 8] This is a schematic cross-sectional view (part 6) showing the state during the manufacturing process of a silicon carbide semiconductor device according to the embodiment. [Figure 9] This is a schematic cross-sectional view (part 7) showing the state during the manufacturing process of a silicon carbide semiconductor device according to the embodiment. [Figure 10] This graph shows the relationship between the depth of the crushed layer and the amount of wafer warping. [Modes for carrying out the invention]

[0025] Preferred embodiments of the method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - prefixes to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these prefixes. In the following description of embodiments and attached drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. In this specification, in the notation of Miller indices, "-" indicates a bar attached to the exponent immediately following it, and a "-" before the exponent indicates a negative exponent. Furthermore, it is preferable to include up to 5% variation when describing the same or equivalent components, taking into account manufacturing variations.

[0026] (Embodiment) The semiconductor device according to the present invention is constructed using a wide-bandgap semiconductor. In the embodiment, a silicon carbide semiconductor device, for example, one made using silicon carbide (SiC) as the wide-bandgap semiconductor, will be described using a trench-type MOSFET 50 as an example. Figure 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment. In Figure 1, only the active region through which the main current flows in the trench-type MOSFET 50 is shown.

[0027] As shown in Figure 1, the silicon carbide semiconductor device according to the embodiment is n + On the first main surface (front surface) of the mold starting substrate 1, for example, the (0001) surface (Si surface), n + Type buffer layer 16 and the first n - A silicon carbide epitaxial layer 2 has been deposited.

[0028] n + The starting substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). + The buffer layer 16 has, for example, a film thickness of 1 μm or more and 5 μm or less, and contains 1 × 10⁻¹⁶ nitrogen. 17 / cm 3 The above 1 x 10 18 / cm 3The following is a highly doped layer with high concentrations of doping. + The type buffer layer 16 is the first n - Promotes the recombination of holes from the silicon carbide epitaxial layer 2, n + The hole concentration reaching the mold starting substrate 1 is controlled to suppress the occurrence and expansion of stacking faults.

[0029] 1st n - The silicon carbide epitaxial layer 2 is n + A low concentration of impurities, such as nitrogen, is doped into the starting substrate 1, which has a lower impurity concentration than the starting substrate 1. - This is a type drift layer. 1st n - n + The surface side opposite to the mold starting substrate 1 side is the 2n - A type silicon carbide layer 6 is formed. Second n - The type silicon carbide layer 6 is n + Lower than the starting substrate 1, the first n - This is a high-concentration n-type drift layer with a higher impurity concentration than the type silicon carbide epitaxial layer 2, for example, doped with nitrogen. + Type starting substrate 1 and n - Silicon carbide epitaxial layer 2 and second n - The silicon carbide layer 6 and the p-type base layer 3, described later, are combined to form a silicon carbide semiconductor substrate.

[0030] n + A back electrode (drain electrode) is provided on the second main surface (back surface, i.e., the back surface of the silicon carbide semiconductor substrate) of the mold starting substrate 1. The back electrode constitutes the drain electrode. A drain electrode pad 14 is provided on the surface of the back electrode.

[0031] A trench gate structure is formed on the first main surface side (p-type base layer 3 side) of the silicon carbide semiconductor substrate. Specifically, the trench 18 is n + From the surface opposite to the mold starting substrate 1, the second n penetrates the p-type base layer 3. -It reaches the silicon carbide layer 6. Along the inner wall of the trench 18, a gate insulating film 9 is formed at the bottom and side walls of the trench 18, and a gate electrode 10 is formed inside the gate insulating film 9 in the trench 18. The gate insulating film 9 makes the gate electrode 10 first n - Silicon carbide epitaxial layer 2, 2nd n - The p-type silicon carbide layer 6 and the p-type base layer 3 are insulated from each other. A portion of the gate electrode 10 may protrude from above the trench 18 (towards the source electrode pad 15) towards the source electrode pad 15.

[0032] 1st n - Type silicon carbide epitaxial layer 2 and second n - Inside the silicon carbide layer 6, the first p + Type region 4 and 2p + Type region 5 is selectively provided. 1p + Type region 4 extends to a position deeper than the bottom of trench 18, on the drain side. (1p) + The lower end (drain-side end) of mold region 4 is located closer to the drain than the bottom of trench 18. (1p) + The mold region 4 is located between the trenches 18. As shown in Figure 1, the first p + Type region 4 is p, which will be described later. ++ It is in contact with type contact area 8, but p ++ A configuration in which the contact area 8 is not in contact with the first p + The upper surface of type region 4 is the second nth - It is provided on the surface layer of the type silicon carbide layer 6 and is in contact with the lower surface of the p-type base layer 3.

[0033] 2nd p. + The lower end of mold region 5 is located on the drain side of the bottom of trench 18. (2p) + The mold region 5 is formed at a position opposite the bottom of the trench 18 in the depth direction z. + The width of mold region 5 is wider than the width of trench 18. The bottom of trench 18 is 2p + It may reach type region 5, or the p-type base layer 3 and the second p + The second nth region sandwiched within type region 5 -Located within the silicon carbide layer 6, the second p + It does not need to be in contact with type region 5. 2p + The upper surface of mold region 5 may be on the drain side or the source side of the bottom of trench 18. (1p) + Type region 4 and 2p + For example, region 5 is doped with aluminum (Al).

[0034] 1st p. + By extending a portion of the type region 4 toward the trench 18 side, the second p + It has a structure connected to type region 5. In this case, the first p + Part of type region 4 is 1p + Type region 4 and 2p + In the direction x in which the type region 5 is aligned (hereinafter referred to as the first direction), and in the direction y perpendicular to it (hereinafter referred to as the second direction), the second n - It may have a planar layout in which the silicon carbide layer 6 is repeatedly arranged alternately with the first p + Part of type region 4 and 2p + It is sufficient that at least one part of type region 5 is connected. This allows for the second p + Type region 5 and the first n - When avalanche yielding occurs at the junction of the silicon carbide epitaxial layer 2, the holes generated can be efficiently relocated to the source electrode 13, reducing the load on the gate insulating film 9 and thus improving reliability.

[0035] 1st n - A p-type base layer 3 is provided on the first main surface side of the substrate of the silicon carbide epitaxial layer 2. The impurity concentration of the p-type base layer 3 is, for example, the first p + The impurity concentration may be lower than that of type region 4. This allows for lowering the concentration of the p-type base layer 3 to reduce the threshold voltage, while suppressing the expansion of the depletion layer in the p-type base layer 3, thereby avoiding a decrease in breakdown voltage due to punch-through. Inside the p-type base layer 3, on the first main surface side of the substrate, n + Type source region 7 and p ++ A type contact region 8 is selectively provided. Also, n +-type source region 7 and p ++ -type contact region 8 are in contact with each other.

[0036] Although only two trench MOS structures are illustrated in FIG. 1, more trench-structured MOS gate (insulated gate made of metal-oxide-semiconductor) structures may be arranged in parallel.

[0037] An interlayer insulating film 11 is provided on the entire first main surface side of a silicon carbide semiconductor base so as to cover a gate electrode 10 embedded in a trench 18. A source electrode 13 is connected to n + -type source region 7 and p ++ -type contact region 8 through a contact hole opened in the interlayer insulating film 11. The source electrode 13 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad 15 is provided on the source electrode 13.

[0038] (Method for Manufacturing Silicon Carbide Semiconductor Device According to Embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to the embodiment will be described. FIG. 2 is a flowchart showing an outline of the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIGS. 3 to 9 are cross-sectional views schematically showing states during the manufacturing of the silicon carbide semiconductor device according to the embodiment.

[0039] First, as shown in FIG. 3, n made of n-type silicon carbide + -type starting substrate (starting substrate of a first conductivity type) 1 is provided with a first n - -type silicon carbide epitaxial layer (first semiconductor layer of the first conductivity type) 2 and n + -type buffer layer 16 is deposited is prepared as a silicon carbide semiconductor substrate 30 (first step). The n + -type starting substrate used in the present embodiment has a diameter of 150 mm. The silicon carbide semiconductor substrate 30 may be purchased, or a substrate including only n + -type starting substrate 1 may be purchased, and n + -type buffer layer 16 and the first n -An n-type silicon carbide epitaxial layer 2 may be formed to serve as the aforementioned silicon carbide semiconductor substrate 30. In this case, an n + -type starting substrate 1, on the first main surface thereof, an n-type silicon carbide n- + -type buffer layer 16 is epitaxially grown. Next, on the n- + -type buffer layer 16, while doping an n-type impurity such as a nitrogen atom, a first n-type silicon carbide n- - -type silicon carbide epitaxial layer 2 is grown.

[0040] Next, on the first n- - -type silicon carbide epitaxial layer 2, on the surface thereof, a resist mask (not shown) having desired openings is formed by photolithography. Then, as shown in FIG. 4, a p-type impurity such as an aluminum atom is ion-implanted by ion implantation, thereby forming, in the first n- - -type silicon carbide epitaxial layer 2, a first p- + -type region (second semiconductor region of a second conductivity type) 4 and a second p- + -type region (first semiconductor region of a second conductivity type) 5 at an impurity concentration of, for example, 3×10 18 / cm 3 (step S1: second step).

[0041] Next, a first warpage correction process for correcting warpage of the silicon carbide semiconductor substrate 30 is performed (step S2: third step). Due to the ion implantation in step S1, the silicon carbide semiconductor substrate 30 warps into a convex mountain shape on the front surface, and for example, a warpage of about 300 μm occurs. Since the first p- + -type region 4 and the second p- + -type region 5 are formed in deep regions, ion implantation at high acceleration (1 MeV or more) is performed. For this reason, the warpage of the silicon carbide semiconductor substrate 30 in the mountain shape becomes large, so it is necessary to perform a warpage correction process that reduces the amount of warpage of the silicon carbide semiconductor substrate 30. In the warpage correction process, for example, the wafer warpage amount of the silicon carbide semiconductor substrate 30 is reduced to less than 100 μm. The wafer warpage amount is the difference between the height of the highest portion and the height of the lowest portion of the silicon carbide semiconductor substrate 30.

[0042] Figure 10 is a graph showing the relationship between the depth of the fractured layer and the amount of wafer warpage. In Figure 10, the vertical axis represents the amount of wafer warpage in μm, and the horizontal axis represents the depth of the fractured layer in nm. The fractured layer is a layer in which the crystallinity of SiC has been broken down, and the depth (film thickness) of the fractured layer can be measured by observing the cross-section of the silicon carbide semiconductor substrate 30 with a TEM (Transmission Electron Microscope).

[0043] As shown in Figure 10, wafer warping occurs when a crushing layer is formed. When a crushing layer is formed on the back surface of the silicon carbide semiconductor substrate 30, a concave, bowl-shaped warp occurs on the front surface of the silicon carbide semiconductor substrate 30. Thus, when a crushing layer is formed, warping occurs in the opposite direction to the warp of the silicon carbide semiconductor substrate 30 caused by ion implantation, making it possible to correct the warp of the silicon carbide semiconductor substrate 30.

[0044] Therefore, in this embodiment, a crushed layer is formed with a thickness of 100 nm to 500 nm by grinding the second main surface of the silicon carbide semiconductor substrate 30. As shown in Figure 10, the wafer warpage is 200 μm to 450 μm, reducing the warpage of the silicon carbide semiconductor substrate 30 caused by ion implantation, and reducing the warpage of the silicon carbide semiconductor substrate 30 to less than 100 μm. For example, if a crushed layer of about 300 nm is formed, as shown in Figure 10, the silicon carbide semiconductor substrate 30 will warp in a bowl shape of about 330 μm. As a result, the warpage of the silicon carbide semiconductor substrate 30 will be several tens of μm. In addition, back grinding (BG), which is used to thin the silicon carbide semiconductor substrate 30, is used to form the crushed layer. In BG, the silicon carbide semiconductor substrate 30 is mechanically ground from the second main surface (back surface) side with a grinder or the like. Furthermore, in order to form a fractured layer of about 300 nm, grinding of about 10 to 14 μm is sufficient, and in this embodiment, grinding of 12 μm is performed.

[0045] In step S1, the second p protects the bottom of the trench 18. + Formation of type region 5 is necessary, but the first p between trenches 18 +It is also possible for no type region 4 to be formed. In this case, the second p + After forming the mold region 5, the first warping correction process in step S2 is performed.

[0046] Next, the 1st n - A resist mask (not shown) with desired openings is formed on the surface of the silicon carbide epitaxial layer 2 by photolithography. Then, as shown in Figure 5, a second n-type impurity such as nitrogen is doped by ion implantation to form a second n-type impurity layer approximately 0.7 μm thick. - For example, the silicon carbide layer 6 is 2 × 10 17 / cm 3 Formation is carried out at the following impurity concentration (Step S3).

[0047] Next, n - A resist mask (not shown) with desired openings is formed on the surface of the silicon carbide epitaxial layer 2 by photolithography. Then, as shown in Figure 6, a p-type base layer (second semiconductor layer of the second conductivity type) 3 with a thickness of approximately 0.5 μm is implanted by ion implantation, for example, 3 × 10⁻¹⁶. 17 / cm 3 Formation is carried out with the following impurity concentration (Step S4: 4th step).

[0048] Next, a resist mask (not shown) with desired openings is formed on the surface of the p-type base layer 3 by photolithography. Then, as shown in Figure 7, an n-type resist mask with a thickness of approximately 0.5 μm is formed by ion implantation. + For example, the source layer (third semiconductor layer of the first conductivity type) 7 is 1 × 10 19 / cm 3 Formed with the following impurity concentration (Step S5: Fifth step).

[0049] Next, an ion implantation mask having a predetermined opening is formed, n + A portion of the p-type source layer 7 and a portion of the p-type base layer 3 are ion-implanted with p-type impurities such as aluminum, as shown in Figure 8. ++ For example, the contact area 8 is 1 × 10 20 / cm 3 Formation is carried out at the impurity concentration (Step S6).

[0050] Next, a second unbending process is performed to correct the warp of the silicon carbide semiconductor substrate 30 (step S7). Because ions are implanted only on the front side by ion implantation, the silicon carbide semiconductor substrate 30 warps in a convex, mountain-like shape on the front side, resulting in a warp of approximately 250 μm, for example. Therefore, in this embodiment, a crushed layer is formed with a thickness of 100 nm to 500 nm by grinding the second main surface of the silicon carbide semiconductor substrate 30. According to Figure 10, the wafer warp becomes 200 μm to 450 μm, reducing the amount of warp of the silicon carbide semiconductor substrate 30 caused by ion implantation, and reducing the warp of the silicon carbide semiconductor substrate 30 to less than 100 μm. For example, if a crushed layer of about 200 nm is formed, according to Figure 10, a bowl-shaped warp of about 260 μm occurs in the silicon carbide semiconductor substrate 30. Therefore, the warp of the silicon carbide semiconductor substrate 30 becomes several tens of μm. Furthermore, in order to form a fractured layer of about 200 nm, grinding of about 8 to 12 μm is sufficient, and in this embodiment, grinding of 10 μm is performed.

[0051] If the amount of warping of the silicon carbide semiconductor substrate 30 caused by ion implantation does not affect subsequent processes, the second warping correction process in step S7 does not need to be performed. However, the second n - Type silicon carbide layer 6, p-type base layer 3, n + Type source layer 7 and p ++ The contact region 8 is normally subjected to accelerated ion implantation, but since warping occurs in each step, it is preferable to perform a second warping correction treatment.

[0052] In this embodiment, the first p + Type region 4 and 2p + After forming the mold region 5, the first warp correction process is performed, p ++ Although a second warp correction process is performed after the formation of the mold contact region 8, the warp correction process may be performed after each ion implantation. Furthermore, if the amount of warping of the silicon carbide semiconductor substrate 30 caused by ion implantation does not affect subsequent processes, the warp correction process may not be performed.

[0053] Next, heat treatment is performed in an inert gas atmosphere at approximately 1750°C to activate the impurity regions formed by ion implantation (Step S8: 6th step). Note that each ion implantation region may be activated collectively with a single heat treatment, or the heat treatment may be performed each time ion implantation is carried out. Furthermore, the order of Step S8 and Step S9 may be reversed. That is, the activation treatment may be performed after the formation of the trench 18.

[0054] Next, n + A trench-forming mask with predetermined openings is formed on the surface of the mold source region 7 by photolithography, for example, using an oxide film. Next, as shown in Figure 9, dry etching is performed. + The p-type source region 7 and the p-type base layer 3 penetrate the second p + A trench 18 is formed that reaches the mold region 5 (Step S9: 7th step). Next, the trench-forming mask is removed.

[0055] For the formation of the trenches 18, it is preferable that the silicon carbide semiconductor substrate 30 has minimal warping and that the surface of the silicon carbide semiconductor substrate 30 is flat; therefore, the second warping correction treatment is performed before the formation of the trenches 18. Since the warping of the silicon carbide semiconductor substrate 30 is eliminated by the activation treatment, it is preferable to perform the activation treatment before the formation of the trenches 18.

[0056] Next, n + Type source region 7 and p ++ A gate insulating film 9 is formed along the surface of the mold contact region 8 and the bottom and side walls of the trench 18. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1300°C in an oxygen-containing gas atmosphere. Alternatively, this gate insulating film 11 may be formed by deposition by a chemical reaction such as high-temperature oxidation (HTO).

[0057] Next, a polycrystalline silicon layer, for example, doped with phosphorus atoms, is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed to fill the trench 18. The gate electrode 10 is formed by patterning this polycrystalline silicon layer using photolithography and leaving it inside the trench 18 (step 8).

[0058] Next, an insulating film is formed on the surface of the gate electrode 10. For example, a thermal oxide film is formed by annealing in an oxygen atmosphere at 1000°C. Next, the surface is protected with a protective film, for example, by forming it with a photoresist. Next, the insulating film formed on the back surface, the gate electrode, and the gate insulating film are all removed by dry etching. Next, the protective film formed on the surface is removed by an ashing and peeling process. In this case, ashing in an oxygen plasma and peeling with SPM were performed.

[0059] Next, a film of, for example, phosphorus glass is deposited to a thickness of about 1 μm to cover the gate insulating film 9 and the gate electrode 10, thereby forming an interlayer insulating film 11. Next, the interlayer insulating film 11 and the gate insulating film 10 are patterned by photolithography. + Type source region 7 and p ++ A contact hole is formed, exposing the type contact region 8. Next, a conductive film, such as nickel, which will become the source electrode (first electrode) 13, is deposited inside the contact hole and on the interlayer insulating film 11 by, for example, sputtering (step 9). Next, heat treatment at about 700°C is performed to selectively react the conductive film with silicon carbide, and then the unreacted portion of the conductive film is selectively removed, leaving the source electrode 13 only inside the contact hole. + Type source region 7 and p ++ The contact area 8 and the source electrode 13 are brought into contact.

[0060] Next, a metal film that will become the source electrode pad 15 is formed on the source electrode 13 and the interlayer insulating film 11 on the front surface of the silicon carbide semiconductor substrate, for example, by sputtering. At this time, a barrier metal (not shown) made of titanium or titanium nitride may be formed first. The thickness of the portion of the electrode pad on the interlayer insulating film 11 may be, for example, 5.5 μm. The electrode pad may be formed of, for example, aluminum (Al-Si) containing silicon at a ratio of 1%. Next, the metal film is selectively removed to form the source electrode pad 15.

[0061] Next, n + After covering the front surface of the mold starting substrate 1 with a protective film (not shown) for protection, n + By polishing the mold starting substrate 1 from the back side, n + The mold starting substrate 1 may be thinned to achieve the product thickness.

[0062] Next, n + On the second main surface of the mold starting substrate 1, conductive films that will serve as drain electrodes (not shown), such as a molybdenum film and a nickel film, are successively deposited by, for example, a sputtering method. After that, heat treatment such as laser annealing is performed, n + A drain electrode is formed by reacting a molded starting substrate 1 with a conductive film to form an ohmic junction.

[0063] Next, a drain electrode pad (second electrode) 14 is formed on the surface of the drain electrode, for example, by depositing titanium, nickel, and gold in that order (step 10). In this way, the silicon carbide semiconductor device shown in Figure 1 is completed.

[0064] As described above, according to the embodiment, a crushed layer is formed by grinding the second main surface of the silicon carbide semiconductor substrate. This reduces the amount of warping of the silicon carbide semiconductor substrate caused by ion implantation, and the amount of warping of the silicon carbide semiconductor substrate can be reduced to less than 100 μm. Therefore, it is possible to reduce or suppress the occurrence of transport defects, stage chuck defects, patterning defects, etc., within the manufacturing equipment.

[0065] As described above, the present invention can be modified in various ways without departing from the spirit of the invention, and in each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, etc. can be set in various ways according to the required specifications. Furthermore, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present invention also holds true if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial applicability]

[0066] As described above, the silicon carbide semiconductor device manufacturing method according to the present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and igniters for automobiles. [Explanation of Symbols]

[0067] 1 n + Mold starting substrate 2 1stn - Silicon carbide epitaxial layer 3. p-type base layer 4 1st p. + type area 5 2nd p. + type area 6 2nd n - mold silicon carbide layer 7 n + Type source area 8 p ++ Type Contact Area 9 Gate insulating film 10 Guard Station 11 Interlayer insulating film 13 Source electrode 14 Drain electrode pads 15 Source electrode pads 16 n + Type buffer layer 18 Trench 30 Silicon carbide semiconductor substrate 50 Trench-type MOSFETs

Claims

1. A first step is to prepare a silicon carbide semiconductor substrate in which a first semiconductor layer of the first conductivity type with a lower impurity concentration than that of the first conductivity type is provided on the front side of a first conductivity type starting substrate, A second step involves forming a first semiconductor region of a second conductivity type within the first semiconductor layer by ion implantation, A third step is to perform a process to correct the warping of the silicon carbide semiconductor substrate after forming the first semiconductor region, A fourth step involves forming a second semiconductor layer of a second conductivity type within the first semiconductor layer by ion implantation, A fifth step involves forming a third semiconductor layer of the first conductivity type on the surface layer of the second semiconductor layer by ion implantation, A sixth step of activating the first semiconductor region, the second semiconductor layer, and the third semiconductor layer formed by ion implantation, A seventh step involves forming a trench that penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer at a position opposite the first semiconductor region in the depth direction, An eighth step is to form a gate electrode inside the trench via a gate insulating film, A ninth step of forming a first electrode in contact with the third semiconductor layer and the second semiconductor layer, A tenth step involves forming a second electrode on the back surface of the starting substrate, Includes, The method for manufacturing a silicon carbide semiconductor device is characterized in that the process for correcting the warp is to form a crushed layer on the back surface of the silicon carbide semiconductor substrate.

2. A first step of preparing a silicon carbide semiconductor substrate, wherein a first semiconductor layer of the first conductivity type having a lower impurity concentration than the starting substrate is provided on the front side of the first conductivity type starting substrate, A second step involves forming a first semiconductor region of a second conductivity type within the first semiconductor layer by ion implantation, A third step is to perform a process to correct the warping of the silicon carbide semiconductor substrate after forming the first semiconductor region, A fourth step involves forming a second semiconductor layer of a second conductivity type within the first semiconductor layer by ion implantation, A fifth step involves forming a third semiconductor layer of the first conductivity type on the surface layer of the second semiconductor layer by ion implantation, A sixth step of activating the first semiconductor region, the second semiconductor layer, and the third semiconductor layer formed by ion implantation, A seventh step involves forming a trench that penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer at a position opposite the first semiconductor region in the depth direction, An eighth step is to form a gate electrode inside the trench via a gate insulating film, A ninth step of forming a first electrode in contact with the third semiconductor layer and the second semiconductor layer, A tenth step involves forming a second electrode on the back surface of the starting substrate, Includes, After the fifth step, and before the sixth step, A method for manufacturing a silicon carbide semiconductor device, further comprising an eleventh step of performing a process to restore the warp of the silicon carbide semiconductor substrate.

3. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, characterized in that, in the second step, a second semiconductor region of a second conductivity type is further formed between the trenches in the first semiconductor layer by ion implantation.

4. The method for manufacturing a silicon carbide semiconductor device according to claim 2, characterized in that the process of correcting the warp is to form a crushed layer on the back surface of the silicon carbide semiconductor substrate.

5. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 4, characterized in that the crushed layer is formed by grinding the back surface of the silicon carbide semiconductor substrate.

6. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 4, characterized in that the crushed layer is formed with a thickness of 100 nm or more and 500 nm or less.

7. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, characterized in that the process for restoring the warp reduces the amount of warp of the silicon carbide semiconductor substrate to less than 100 μm.

8. A method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, characterized in that the process of restoring the warp is performed after each ion implantation.

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