Silicon carbide semiconductor equipment

Abstract

To provide a silicon carbide semiconductor device of a trench gate type, in which the leak current between a gate electrode and a source region can be suppressed.SOLUTION: A silicon carbide semiconductor device includes a drift layer 2 of a first conductivity type formed of silicon carbide, base regions 6a, 6b of a second conductivity type, main regions 7a, 7b of the first conductivity type, a gate insulating film 11 provided inside a trench 10 penetrating the main regions 7a, 7b and the base regions 6a, 6b, a gate electrode 12, and main electrodes (14, 15) provided in contact with the main regions 7a, 7b. The main regions 7a, 7b include source extension parts 71a, 71b whose bottom surface is in contact with the base regions 6a, 6b, and source contact parts 72a, 72b provided on a top surface side of the source extension parts 71a, 71b in contact with the main electrodes (14, 15), and having a 3C structure. A top surface of the gate electrode 12 is deeper than a bottom surface of the source contact parts 72a, 72b and shallower than the source extension parts 71a, 71b.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure relates to a SiC semiconductor device using silicon carbide (SiC). [Background technology]

[0002] Patent Document 1 discloses a semiconductor device in which an amorphous layer is formed by ion implanting phosphorus into a hexagonal single crystal silicon carbide substrate, the amorphous layer is recrystallized into cubic single crystal n-type silicon carbide by heat treatment, and electrodes are formed by depositing nickel onto the upper surface of the n-type silicon carbide.

[0003] Patent Document 2 describes n made of 4H-SiC + n formed on the first main surface of type SiC - Within the type epitaxial growth layer, n + Type source area and n + n formed within the source region of type + Type 3C-SiC region and p + It has a type potential fixed region and n + Type 3C-SiC region and p + A semiconductor device is disclosed in which a barrier metal film is formed in contact with a fixed potential region, and source wiring electrodes are formed on the barrier metal film.

[0004] Patent Document 3 discloses a silicon carbide MOS-type semiconductor device comprising a second-conductivity body contact region and a first-conductivity source contact region, each formed by selective ion implantation on the surface layer of a second-conductivity body region, and further having a source extension region below the source contact region, which is deeper than the tail portion below the source contact region and has a lower impurity density than the source contact region, formed by selective ion implantation. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2009-49198 [Patent Document 2] International Publication No. 2017 / 042963 [Patent Document 3] Patent No. 5369464 specification [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] In trench-gate type SiC semiconductor devices, the source region (main region) is being considered as being made of 3C-SiC to achieve ohmic contact with the source electrode (main electrode). However, 3C-SiC has more crystal defects and larger surface irregularities compared to 4H-SiC, which may lead to leakage current flowing between the gate electrode and the source region.

[0007] In view of the above issues, this disclosure aims to provide a SiC semiconductor device of the trench gate type in which the main region can make ohmic contact with the main electrode and which can suppress leakage current between the gate electrode and the main region. [Means for solving the problem]

[0008] To achieve the above objective, one aspect of the present disclosure provides a SiC semiconductor device comprising: a drift layer of a first conductivity type made of SiC; a base region of a second conductivity type made of SiC provided on the upper side of the drift layer; a main region of a first conductivity type made of SiC provided on the upper side of the base region; a gate insulating film provided inside a trench penetrating the main region and the base region; a gate electrode embedded inside the trench via the gate insulating film; and a main electrode provided in contact with the main region, wherein the main region comprises a source extension portion whose lower surface is in contact with the base region, and a source contact portion provided on the upper side of the source extension portion, in contact with the main electrode, and including a 3C structure, and the upper surface of the position of the gate electrode in contact with the gate insulating film is deeper than the lower surface of the source contact portion and shallower than the lower surface of the source extension portion. [Effects of the Invention]

[0009] According to this disclosure, a SiC semiconductor device of the trench gate type can be provided in which the main region can make ohmic contact with the main electrode and leakage current between the gate electrode and the main region can be suppressed. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic cross-sectional view showing an example of a SiC semiconductor device according to the first embodiment. [Figure 2] This is a schematic cross-sectional view of an enlarged area A in Figure 1. [Figure 3] This is a schematic cross-sectional view of a SiC semiconductor device related to a comparative example. [Figure 4] This is a flowchart of the manufacturing method for a SiC semiconductor device according to the first embodiment. [Figure 5] This is a schematic cross-sectional view illustrating an example of a manufacturing method for a SiC semiconductor device according to the first embodiment. [Figure 6] This is a schematic cross-sectional view following Figure 5, illustrating an example of a manufacturing method for a SiC semiconductor device according to the first embodiment. [Figure 7] This is a schematic cross-sectional view following Figure 6, illustrating an example of a manufacturing method for a SiC semiconductor device according to the first embodiment. [Figure 8] This is a schematic cross-sectional view following Figure 7, illustrating an example of a manufacturing method for a SiC semiconductor device according to the first embodiment. [Figure 9] This is a schematic cross-sectional view following Figure 8, illustrating an example of a manufacturing method for a SiC semiconductor device according to the first embodiment. [Figure 10] This is a schematic cross-sectional view following Figure 9, illustrating an example of a manufacturing method for a SiC semiconductor device according to the first embodiment. [Figure 11] This is a schematic cross-sectional view following Figure 10, illustrating an example of a manufacturing method for a SiC semiconductor device according to the first embodiment. [Figure 12] This is a schematic cross-sectional view following Figure 11, illustrating an example of a manufacturing method for a SiC semiconductor device according to the first embodiment. [Figure 13]This is a schematic cross-sectional view following Figure 12, illustrating an example of a manufacturing method for a SiC semiconductor device according to the first embodiment. [Figure 14] This is a schematic cross-sectional view following Figure 13, illustrating an example of a manufacturing method for a SiC semiconductor device according to the first embodiment. [Figure 15] This is a schematic cross-sectional view following Figure 14, illustrating an example of a manufacturing method for a SiC semiconductor device according to the first embodiment. [Figure 16] This is a flowchart of the manufacturing method for a SiC semiconductor device according to the second embodiment. [Figure 17] This is a flowchart of the manufacturing method for a SiC semiconductor device according to the third embodiment. [Modes for carrying out the invention]

[0011] The first to third embodiments of this disclosure will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings. In addition, the first to third embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of this disclosure, and the technical concept of this disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0012] In this specification, the source region of a metal-oxide-semiconductor field-effect transistor (MOSFET) is "one main region (first main region)" that can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). In thyristors such as MOS-controlled electrostatic induction thyristors (SI thyristors), "one main region" can be selected as the cathode region. The drain region of a MOSFET is "the other main region (second main region)" of the semiconductor device that can be selected as the collector region in the case of an IGBT, or as the anode region in the case of a thyristor. In this specification, when simply referred to as "main region," it means either the first main region or the second main region that is reasonable according to the common technical knowledge of those skilled in the art.

[0013] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up and down will be converted to left and right, and if it is rotated 180° and observed, up and down will be inverted and read. Also, "top surface" may be read as "front surface," and "bottom surface" may be read as "back surface."

[0014] Furthermore, the following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. However, it is also acceptable to choose the conductivity types in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The + and - attached to n and p indicate semiconductor regions with relatively higher or lower impurity concentrations compared to semiconductor regions without + and - markings. However, even if two semiconductor regions are marked with the same n, this does not mean that the impurity concentrations in each semiconductor region are exactly the same.

[0015] Furthermore, SiC crystals exhibit polymorphisms, the main being cubic 3C and hexagonal 4H and 6H. Reported band gaps at room temperature are 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. The following explanation will primarily use 4H-SiC and 3C-SiC as examples.

[0016] (First Embodiment) <Structure of SiC Semiconductor Device> As shown in FIG. 1, the SiC semiconductor device according to the first embodiment is exemplified as a case including a trench gate type MOSFET as an active element. Note that FIG. 1 exemplifies a unit cell including the insulated gate electrode structures (11, 12) embedded in one trench 10, but in practice, a large number of such unit cells are periodically arranged.

[0017] The SiC semiconductor device according to the first embodiment has a first conductivity type (n - -type) drift layer 2. The drift layer 2 is formed of, for example, an epitaxial growth layer made of SiC such as 4H—SiC. The impurity concentration of the drift layer 2 is, for example, 1×10 15 cm -3 - or more, 5×10 16 cm -3 - or less. The thickness of the drift layer 2 is, for example, about 1 μm or more and 100 μm or less. The impurity concentration and thickness of the drift layer 2 can be appropriately adjusted according to breakdown voltage specifications and the like.

[0018] On the upper surface side of the drift layer 2, a first conductivity type (n-type) current spreading layer (CSL) 3 having a higher impurity concentration than the drift layer 2 is selectively provided. The lower surface of the current spreading layer 3 is in contact with the upper surface of the drift layer 2. The current spreading layer 3 is formed of, for example, an epitaxial growth layer made of SiC such as 4H—SiC. The impurity concentration of the current spreading layer 3 is, for example, 5×10 16 cm -3 - or more, 5×10 17 cm -3 - or less. Note that the current spreading layer 3 is not necessarily required to be provided, and when the current spreading layer 3 is not provided, the drift layer 2 may be provided extending to the region of the current spreading layer 3.

[0019] Base regions 6a and 6b of the second conductivity type (p-type) are provided on the upper side of the current diffusion layer 3. The lower surfaces of base regions 6a and 6b are in contact with the upper surface of the current diffusion layer 3. If the current diffusion layer 3 is not provided, the lower surfaces of base regions 6a and 6b are in contact with the upper surface of the drift layer 2. Base regions 6a and 6b are composed of epitaxially grown layers made of SiC, such as 4H-SiC. Base regions 6a and 6b may also be regions in which p-type impurities are ion-implanted into the current diffusion layer 3. The impurity concentration of base regions 6a and 6b is, for example, 1 × 10⁻⁶. 16 cm -3 The above is 1 x 10 18 cm -3 It is approximately as follows.

[0020] On the upper surface of base regions 6a and 6b, a first conductivity type (n) with a higher impurity concentration than the drift layer 2 is present. + The first main regions (source regions) 7a and 7b of the type are selectively provided. The source regions 7a and 7b are regions made of SiC in which n-type impurities have been ion-implanted into the base regions 6a and 6b.

[0021] Source region 7a is the lower layer n + A source extension section 71a of type and the upper layer n + The source contact portion 72a has a two-layer structure. The lower surface of the source extension portion 71a is in contact with the upper surface of the base region 6a. The upper surface of the source extension portion 71a is in contact with the lower surface of the source contact portion 72a. The source region 7b is the lower layer n + The source extension section 71b of type and the upper layer n + The source contact portion 72b of the mold has a two-layer structure. The lower surface of the source extension portion 71b is in contact with the upper surface of the base region 6b. The upper surface of the source extension portion 71b is in contact with the lower surface of the source contact portion 72b.

[0022] A trench 10 is provided that penetrates the source regions 7a and 7b and the base regions 6a and 6b, extending from the upper surfaces of the source regions 7a and 7b in the direction normal to the upper surfaces of the source regions 7a and 7b (depth direction). The lower surface of the trench 10 reaches the current diffusion layer 3. The width of the trench 10 is, for example, about 1 μm or less. The source region 7a and the base region 6a are in contact with the left side surface of the trench 10. The source region 7b and the base region 6b are in contact with the right side surface of the trench 10. The trench 10 may have a planar pattern that extends in a stripe-like manner in the depth direction and the front direction of the paper in Figure 1, or it may have a dot-like planar pattern.

[0023] A gate insulating film 11 is provided along the bottom surface and both sides of the trench 10. A gate electrode 12 is embedded inside the trench 10 via the gate insulating film 11. The gate insulating film 11 and the gate electrode 12 constitute a trench gate type insulated gate electrode structure (11,12).

[0024] As the gate insulating film 11, in addition to silicon oxide film (SiO2 film), any single layer film of any one of the following films can be used: silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film, or a composite film made by stacking multiple of these films. As the material for the gate electrode 12, for example, a polysilicon layer (doped polysilicon layer) with high impurity concentrations of p-type or n-type impurities added, or a high-melting-point metal such as titanium (Ti), tungsten (W), or nickel (Ni) can be used.

[0025] Inside the current diffusion layer 3, and at the bottom of the trench 10, there is a second conductive type (p +A gate bottom protection region 4b of type (type) is provided. The upper surface of the gate bottom protection region 4b is in contact with the lower surface of the trench 10. The upper surface of the gate bottom protection region 4b does not need to be in contact with the lower surface of the trench 10. The impurity concentration of the gate bottom protection region 4b is, for example, 1 × 10⁻⁶. 17 cm -3 The above is 1 x 10 19 cm -3 It is approximately as follows.

[0026] Inside the current diffusion layer 3, spaced apart from the gate bottom protection region 4b, is the second conductivity type (p + A first embedded region 4a, 4c of type (type) is provided. The first embedded regions 4a, 4c are provided to a depth similar to that of the gate bottom protection region 4b. The impurity concentration in the first embedded regions 4a, 4c is, for example, 1 × 10⁻⁶. 17 cm -3 The above is 1 x 10 19 cm -3 The extent is as follows: The first embedded regions 4a, 4c and the gate bottom protection region 4b are regions made of SiC in which p-type impurities have been ion-implanted into the current diffusion layer 3, for example. Note that in the foreground or depth of the paper in Figure 1, the p-type impurities connecting the first embedded regions 4a, 4c and the gate bottom protection region 4b are p + The connector part of the type may be selectively provided.

[0027] Second embedding regions 5a and 5b of a second conductivity type (p-type) are provided above the current diffusion layer 3 and on the upper surface side of the first embedding regions 4a and 4c. The second embedding regions 5a and 5b electrically connect the first embedding regions 4a and 4c to the base regions 6a and 6b. The lower surfaces of the second embedding regions 5a and 5b are in contact with the upper surfaces of the first embedding regions 4a and 4c. The sides of the second embedding regions 5a and 5b are in contact with the current diffusion layer 3 and the base regions 6a and 6b. The second embedding regions 5a and 5b are, for example, regions made of SiC in which p-type impurities have been ion-implanted into the current diffusion layer 3 and the base regions 6a and 6b. The impurity concentration of the second embedding regions 5a and 5b may be about the same as the impurity concentration of the first embedding regions 4a and 4c, and may be lower or higher than the impurity concentration of the first embedding regions 4a and 4c. The impurity concentration in the second embedding regions 5a and 5b is, for example, 1 × 10⁻⁶. 17 cm-3 The above is 1 x 10 19 cm -3 It is approximately as follows.

[0028] On the upper surface of the second implantation regions 5a and 5b, p is present, which has a higher impurity concentration than the second implantation regions 5a and 5b. + Base contact regions 8a and 8b of type 6a and 6b are provided. The base contact regions 8a and 8b are regions made of SiC in which p-type impurities have been ion-implanted into the base regions 6a and 6b. The impurity concentration of the base contact regions 8a and 8b is, for example, 5 × 10⁻⁶. 18 cm -3 The above 5 x 10 20 cm -3 The following applies: The base contact regions 8a and 8b may be composed of 3C-SiC or 4H-SiC.

[0029] The lower surface of the base contact area 8a is in contact with the upper surface of the second embedded area 5a, and the side surface of the base contact area 8a is in contact with the source extension portion 71a and the source contact portion 72a of the source area 7a. The lower surface of the base contact area 8b is in contact with the upper surface of the second embedded area 5b, and the side surface of the base contact area 8b is in contact with the source extension portion 71b and the source contact portion 72b of the source area 7b. The lower surfaces of the base contact areas 8a and 8b are of roughly the same depth as the lower surfaces of the source extension portions 71a and 71b of the source areas 7a and 7b, but may be shallower or deeper than the lower surfaces of the source extension portions 71a and 71b of the source areas 7a and 7b. The upper surfaces of the second embedded areas 5a and 5b are p + It is not necessary for the base contact areas 8a and 8b of the mold to be in contact with the lower surfaces.

[0030] An interlayer insulating film 13 is provided on the upper surface of the gate electrode 12. The interlayer insulating film 13 is composed of single-layer films such as silicon oxide films doped with boron (B) and phosphorus (P) (BPSG films), silicon oxide films doped with phosphorus (P) (PSG films), undoped silicon oxide films that do not contain phosphorus (P) or boron (B) and are called "NSG", silicon oxide films doped with boron (B) (BSG films), and silicon nitride films (Si3N4 films), or multilayer films of these. Contact holes 13a and 13b are provided in the interlayer insulating film 13 so as to expose the upper surfaces of the source contact portions 72a and 72b and the base contact regions 8a and 8b.

[0031] First main electrodes (source electrodes) (14, 15) are provided so as to cover the upper surfaces of the source contact portions 72a, 72b and base contact regions 8a, 8b exposed from the contact holes 13a, 13b of the interlayer insulating film 13. The source electrodes (14, 15) comprise a lower barrier metal layer 14 and an upper source wiring electrode 15. For example, the barrier metal layer 14 is made of a metal such as titanium nitride (TiN), titanium (Ti), or a TiN / Ti laminated structure with Ti as the lower layer. The barrier metal layer 14 is in direct contact with the source contact portions 72a, 72b and base contact regions 8a, 8b, and is in low-resistance ohmic contact with the source contact portions 72a, 72b and base contact regions 8a, 8b.

[0032] The source wiring electrode 15 is electrically connected to the source regions 7a, 7b and the base contact regions 8a, 8b via the barrier metal layer 14. The source wiring electrode 15 is provided separately from the gate wiring electrode (not shown) which is electrically connected to the gate electrode 12. The source wiring electrode 15 is made of a metal such as aluminum (Al), aluminum-silicon (Al-Si), aluminum-copper (Al-Cu), or copper (Cu).

[0033] On the lower side of the drift layer 2, a first conductivity type (n) with a higher impurity concentration than the drift layer 2 is present. +A second main region (drain region) 1 of the type is provided. Drain region 1 is made of a semiconductor substrate (SiC substrate) made of, for example, 4H-SiC. The impurity concentration of drain region 1 is, for example, 1 × 10⁻⁶ 19 cm -3 The above is 3 x 10 20 cm -3 The following is an example: The thickness of the drain region 1 is, for example, 30 μm or more and 500 μm or less. A dislocation conversion layer or a recombination promotion layer, which is an n-type buffer layer with a higher impurity concentration than the drift layer 2 and a lower impurity concentration than the drain region 1, may be provided between the drift layer 2 and the drain region 1.

[0034] A second main electrode (drain electrode) 16 is provided on the lower side of the drain region 1. For the drain electrode 16, a single layer film made of gold (Au), or a metal film laminated in the order of titanium (Ti), nickel (Ni), and Au from the drain region 1 side can be used, and a metal film of molybdenum (Mo), tungsten (W), etc. may be laminated as the bottom layer. Furthermore, nickel silicide (NiSi) is provided between the drain region 1 and the drain electrode 16 for ohmic contact. x A drain contact layer, such as a film, may be provided.

[0035] Figure 2 shows an enlarged cross-section of the dashed area A, which includes the source extension portion 71a and source contact portion 72a, the gate insulating film 11 and the gate electrode 12 of the source region 7a shown in Figure 1. Referring to Figure 2, the configuration of the source extension portion 71a and source contact portion 72a and the positional relationship between the source extension portion 71a and source contact portion 72a and the gate electrode 12 will be explained.

[0036] The source extension 71a is a region with fewer crystal defects than the source contact 72a, and does not inherit the crystal defects of the source contact 72a. The source extension 71a is mainly composed of 4H-SiC (4C structure). The proportion of 4H-SiC in the source extension 71a is, for example, between 90% and 100%. In addition to 4H-SiC, the source extension 71a may also contain small amounts of amorphous structure, 3C-SiC, etc.

[0037] The depth d1 from the upper surface of the source contact portion 72a to the lower surface of the source extension portion 71a is, for example, approximately 200 nm or more and 450 nm or less. The thickness of the source extension portion 71a is, for example, approximately 150 nm or more and 400 nm or less. The impurity concentration of the source extension portion 71a is lower than that of the source contact portion 72a. The impurity concentration of the source extension portion 71a is, for example, 1 × 10⁻⁶ 16 / cm 3 The above is 1 x 10 19 / cm 3 The extent is as follows: The source extension 71a contains, for example, phosphorus (P) or nitrogen (N) as an n-type impurity. The source extension 71a may also contain arsenic (As) as an n-type impurity.

[0038] The source contact region 72a is a region containing 3C-SiC (3C structure). The proportion of 3C-SiC in the source contact region 72a is, for example, 10% or more and 100% or less. The source contact region 72a may be a mixed crystal of 3C-SiC and 4H-SiC. In addition to 3C-SiC, the source contact region 72a may also contain amorphous structures, 4H-SiC, etc. Since 3C-SiC has a narrower band gap than 4H-SiC, the inclusion of 3C-SiC in the source contact region 72a allows for low-resistance ohmic contact with the source electrodes (14, 15). To achieve good ohmic contact with the source electrodes (14, 15), it is preferable that the proportion of 3C-SiC in the source contact region 72a be 10% or more.

[0039] The depth d2 from the top to the bottom surface of the source contact portion 72a (thickness of the source contact portion 72a) is, for example, approximately 30 nm or more and 100 nm or less. The impurity concentration of the source contact portion 72a is higher than the impurity concentration of the source extension portion 71a. The impurity concentration of the source contact portion 72a is, for example, 1 × 10⁻⁶ 19 / cm 3 The above is 1 x 10 22 / cm 3 The following are some examples of the characteristics of the source contact portion 72a. The source contact portion 72a may contain, for example, phosphorus (P) or arsenic (As) as n-type impurities. The source contact portion 72a may contain, for example, nitrogen (N) as n-type impurities. The source contact portion 72a may contain multiple types of n-type impurities from among P, As, and N.

[0040] The crystal structures of the source extension 71a and the source contact 72a can be differentiated by changing the element to be ion-implanted, the temperature during ion implantation, the dose (impurity concentration), and the activation temperature for each of the source extension 71a and the source contact 72a. As a method for forming the source contact 72a containing 3C-SiC, for example, by ion-implanting 4H-SiC with a high concentration of n-type impurities at room temperature, the 4H-SiC is broken down using the damage from ion implantation to form an amorphous structure. Subsequently, by performing activation annealing, the amorphous structure recrystallizes into 3C-SiC, thereby forming the source contact 72a containing 3C-SiC.

[0041] On the other hand, as a method for forming the source extension portion 71a of 4H-SiC, the source extension portion 71a can be formed while maintaining the 4H-SiC by ion implanting n-type impurities into the 4H-SiC at a high temperature (for example, around 500°C) at a concentration that does not disrupt the structure of the 4H-SiC.

[0042] As a method for measuring (observing) the crystal structure of the source extension portion 71a and the source contact portion 72a, for example, the area ratio of the crystal structure on the surface can be measured by field emission scanning electron microscopy (FE-SEM) and backscattered electron diffraction (EBSD). As an example, samples were prepared under the same conditions as the element to be ion-implanted, dose amount (impurity concentration), and activation temperature, but with the ion implantation temperature changed to two different temperatures: 500°C and room temperature (25°C). These samples were then observed using FE-SEM and EBSD. As a result, the proportion of 4H-SiC on the surface of the 500°C sample was 100%. On the other hand, in the room temperature sample, the proportion of 4H-SiC on the surface was 86%, and the proportion of 3C-SiC was 14%.

[0043] As shown in Figure 2, the upper surface (upper end) 12a of the end of the gate electrode 12 that contacts the gate insulating film 11 is located deeper than the lower surface (lower end) 72x of the source contact portion 72a that contacts the gate insulating film 11, and shallower than the lower surface (lower end) 71x of the source extension portion 71a that contacts the gate insulating film 11. The upper surface 12a of the gate electrode 12 that contacts the gate insulating film 11 may be the uppermost surface of the gate electrode 12. For example, if the entire upper surface of the gate electrode 12 is a curved surface that is convex downwards, the upper surface of the central part of the gate electrode 12 may be located deeper than the upper surface 12a of the end of the gate electrode 12.

[0044] The gate electrode 12 and the source extension portion 71a face each other via the gate insulating film 11. The gate electrode 12 and the source contact portion 72a do not face each other via the gate insulating film 11. The source contact portion 72a faces the interlayer insulating film 13 via the gate insulating film 11. The amount of indentation d0 of the source contact portion 72a of the gate electrode 12 from the upper surface is, for example, about 100 nm or more and 300 nm or less. The amount of indentation d0 of the gate electrode 12 and the position of the upper surface 12a where the gate electrode 12 contacts the gate insulating film 11 can be controlled, for example, by adjusting the etching conditions of the gate electrode 12.

[0045] The source extension portion 71b and source contact portion 72b of the source region 7b shown in Figure 1 have the same configuration as the source extension portion 71a and source contact portion 72a of the source region 7a, respectively, so redundant explanations are omitted. Also, the positional relationship between the source extension portion 71b and source contact portion 72b of the source region 7b and the gate electrode 12 is the same as the positional relationship between the source extension portion 71a and source contact portion 72a of the source region 7a and the gate electrode 12, so redundant explanations are omitted.

[0046] When the SiC semiconductor device according to the first embodiment is in operation, the source electrodes (14, 15) are at ground potential, a positive voltage is applied to the drain electrode 16, and a positive voltage above the threshold is applied to the gate electrode 12. This causes an inversion layer (channel) to form on the side of the trench 10 in the base regions 6a, 6b, resulting in an ON state. In the ON state, current flows from the drain electrode 16 to the source electrodes (14, 15) via the drain region 1, drift layer 2, current diffusion layer 3, the inversion layer in the base regions 6a, 6b, and the source regions 7a, 7b. On the other hand, if the voltage applied to the gate electrode 12 is below the threshold, no inversion layer is formed in the base regions 6a, 6b, resulting in an OFF state, and no current flows from the drain electrode 16 to the source electrodes (14, 15).

[0047] According to the SiC semiconductor device of the first embodiment, the source regions 7a and 7b have a two-layer structure consisting of a source extension portion 71a and a source contact portion 72a. The upper source extension portion 71a, which contacts the source electrodes (14, 15), contains 3C-SiC. This allows the source contact portion 72a to make low-resistance ohmic contact with the source electrodes (14, 15) without forming a silicide layer such as nickel (Ni) silicide. Therefore, compared to the case where a silicide layer is formed, problems such as peeling of the silicide layer can be suppressed.

[0048] Further, as shown in FIG. 3, suppose a case where a source region 7x containing 3C-SiC is formed in a single-layer structure, and the source region 7x faces a gate electrode 12 with a gate insulating film 11 interposed therebetween. In this case, since the source region 7x contains 3C-SiC, the source region 7x can be in ohmic contact with the source electrodes (14, 15). However, 3C-SiC has more crystal defects and larger surface irregularities than 4H-SiC, so there is a risk that leakage current I1 may flow between the gate electrode 12 and the source region 7x.

[0049] In contrast, according to the SiC semiconductor device according to the first embodiment, as shown in FIG. 2, an upper surface 12a of the gate electrode 12 is made deeper than a lower surface 72x of the source contact portion 72a and shallower than a lower surface 71x of the source extension portion 71a. As a result, the source extension portion 71a with few crystal defects in the source region 7a faces the gate electrode 12 with the gate insulating film 11 interposed therebetween, and the source contact portion 72a with many crystal defects in the source region 7a does not face the gate electrode 12 with the gate insulating film 11 interposed therebetween. Therefore, the generation of leakage current between the source region 7a and the gate electrode 12 can be suppressed.

[0050] <Method of manufacturing SiC semiconductor device> Next, an example of a method of manufacturing the SiC semiconductor device according to the first embodiment will be described. Note that the method of manufacturing the SiC semiconductor device described below is an example, and it goes without saying that the invention can be implemented by various other manufacturing methods including this modified example within the scope of the spirit described in the claims. FIG. 4 is a flowchart of some steps of the method of manufacturing the SiC semiconductor device according to the first embodiment, and the following description will be made with appropriate reference to FIG. 4.

[0051] First, n-type impurities such as nitrogen (N) are added to form an n + -type semiconductor substrate (SiC substrate) 1 made of 4H-SiC (see FIG. 1) is prepared. The upper surface of the SiC substrate 1 has, for example, an off-angle of 3° to 8° from the {0001} plane. On the upper surface of the SiC substrate 1, an n-type impurity such as N is added, forming an n-type layer having a lower impurity concentration than the SiC substrate 1 -A drift layer 2 (see Figure 1) made of n-type 4H-SiC is epitaxially grown. Next, as shown in Figure 5, n-type impurities such as N are added to the upper surface of the drift layer 2, and an n-type layer 3a made of n-type 4H-SiC with a higher impurity concentration than the drift layer 2 is epitaxially grown. The n-type layer 3a may also be formed by ion implantation of n-type impurities such as nitrogen (N) onto the upper part of the drift layer 2.

[0052] Next, an oxide film is deposited on the upper surface of the n-type layer 3a using chemical vapor deposition (CVD) or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned using photolithography and dry etching techniques. The patterned oxide film is used as an ion implantation mask to selectively ion implant p-type impurities such as aluminum (Al). Alternatively, a photoresist film may be used as the ion implantation mask instead of the oxide film. After that, the oxide film used as the ion implantation mask is removed. As a result, as shown in Figure 6, p-type impurities are deposited on the upper surface of the n-type layer 3a. + Type 1 embedded regions 4a, 4c and p + A gate bottom protection region 4b of the type is selectively formed.

[0053] Next, an n-type layer 3b (see Figure 7) made of n-type 4H-SiC is epitaxially grown on the upper surfaces of the n-type layer 3a, the first embedded regions 4a and 4c, and the gate bottom protection region 4b. As a result, a current diffusion layer 3 consisting of n-type layer 3a and n-type layer 3b is formed. Next, as shown in Figure 7, a base region 6 made of p-type 4H-SiC is epitaxially grown on the upper surface of the current diffusion layer 3.

[0054] Next, an oxide film is deposited on the upper surface of the base region 6 using CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned using dry etching technology or the like. The patterned oxide film is used as an ion implantation mask to selectively ion implant p-type impurities such as aluminum (Al). Alternatively, a photoresist film may be used as the ion implantation mask instead of the oxide film. After that, the oxide film used as the ion implantation mask is removed. As a result, as shown in Figure 8, p-type second implantation regions 5a and 5b are selectively formed on the upper surface of the first implantation regions 4a and 4c.

[0055] Next, step S11 n in Figure 4 + The mold source extension formation process is performed. + In the mold source expansion process, an oxide film 21 (see Figure 9) is deposited on the upper surface of the base region 6 using CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film 21, and the oxide film 21 is patterned using photolithography technology and dry etching technology or the like. Using the patterned oxide film 21 as an ion implantation mask, n-type impurities such as nitrogen (N) are ion implanted as shown in Figure 9. Alternatively, a photoresist film may be used as an ion implantation mask instead of the oxide film 21. As a result, n-type impurities such as nitrogen (N) are deposited on the upper part of the base region 6. + A molded source extension portion 71 is formed.

[0056] When ion implantation is performed on the source extension section 71, in order to minimize damage compared to ion implantation on the source contact section 72 described later, phosphorus (P) (atomic number 15), which has a relatively small number of atoms, is preferred as the n-type impurity, and nitrogen (N) (atomic number 7), which has an even smaller number of atoms, is more preferred. In addition to P or N, arsenic (As) (atomic number 33), which has a relatively large number of atoms, may also be implanted. The temperature during ion implantation is higher than that of ion implantation on the source contact section 72 described later, for example, set to around 300°C to 600°C. The dose during ion implantation is set when the impurity concentration of the source extension section 71 is, for example, 1 × 10⁻⁶ 16 / cm 3 The above is 1 x 10 19 / cm 3Set it to approximately the following:

[0057] Next, step S12 in Figure 4 n + The mold source contact part formation process is performed. + In the source contact formation process, as shown in Figure 10, the oxide film 21 is subsequently used as an ion implantation mask to selectively ion implant n-type impurities such as phosphorus (P). Alternatively, a photoresist film may be used as the ion implantation mask instead of the oxide film 21. As a result, n-type impurities such as phosphorus (P) are formed on the upper surface of the source extension portion 71. + A source contact portion 72 of the mold is formed.

[0058] Ion implantation of the source contact section 72 disrupts the 4C-SiC structure on the upper surface of the source extension section 71, forming an amorphous structure. To achieve higher damage compared to the ion implantation of the source extension section 71 described above, the n-type impurity is preferably P (atomic number 15), which has a relatively large number of atoms, and more preferably arsenic (As) (atomic number 33), which has a relatively large number of atoms. Nitrogen (N), which has a relatively small number of atoms, may also be implanted. In the ion implantation of the source contact section 72, the same impurities as those implanted in the source extension section 71 described above may be implanted, or different impurities may be implanted. The temperature during ion implantation is lower than the temperature during ion implantation of the source extension section 71 described above, for example, set to about 20°C or higher and 150°C or lower. The dose amount during ion implantation is the total amount of impurities implanted in the source contact section 72, including those implanted by the ion implantation of the source extension section 71 described above, so that the impurity concentration of the source contact section 72 is, for example, 1 × 10⁻⁶ 19 / cm 3 The above is 1 x 10 22 / cm 3 Set the settings to the following extent. Then, remove the oxide film 21 used as the ion implantation mask.

[0059] Next, step S13 in Figure 4 p + The process of forming a type contact region is performed. +In the type contact region formation process, an oxide film 22 is deposited on the upper surface of the base region 6 using CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film 22, and the oxide film 22 is patterned using photolithography technology and dry etching technology or the like. The patterned oxide film 22 is used as an ion implantation mask, and p-type impurities such as aluminum (Al) and boron (B) are ion implanted, as shown in Figure 11. Alternatively, a photoresist film may be used as an ion implantation mask instead of the oxide film 22. As a result, p-type impurities are formed on the upper surface of the second embedded regions 5a and 5b. + The base contact regions 8a and 8b of the type are selectively formed. Subsequently, the oxide film 22 used as an ion implantation mask is removed.

[0060] Next, the activation annealing (heat treatment) process shown in step S14 of Figure 4 is performed. In this activation annealing process, for example, by performing activation annealing at a temperature of approximately 1600°C to 1900°C, the p-type or n-type impurities ion-implanted in the first embedding regions 4a, 4c, the gate bottom protection region 4b, the second embedding regions 5a, 5b, the source expansion region 71, the source contact region 72, and the base contact regions 8a, 8b are simultaneously activated. At this time, the amorphous structure of the source contact region 72 recrystallizes to become 3C-SiC, thereby forming a source contact region 72 containing 3C-SiC.

[0061] Here, we illustrate a case where activation annealing is performed collectively after all ion implantation steps, but multiple activation annealing steps may be performed individually after each ion implantation step. Alternatively, a cap film made of carbon (C) may be formed before activation annealing, and activation annealing may be performed with the material covered by the cap film, and the cap film may be removed after activation annealing.

[0062] Next, the trench formation process in step S15 of Figure 4 is performed. In this trench formation process, an oxide film 23 (see Figure 12) is deposited on the upper surfaces of the base contact regions 8a and 8b and the source contact portion 72 using CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film 23, and the oxide film is patterned using photolithography technology and dry etching technology or the like. Using the patterned oxide film 23 as an etching mask, trenches 10 are selectively formed in the depth direction from the upper surface of the source contact portion 72 by dry etching technology such as reactive ion etching (RIE), as shown in Figure 12. Alternatively, a photoresist film may be used as an etching mask instead of the oxide film 23.

[0063] The trench 10 penetrates the source expansion portion 71, the source contact portion 72, and the base region 6, and further excavates the top of the current diffusion layer 3, reaching the gate bottom protection region 4b. The source expansion portion 71 is divided into source expansion portions 71a and 71b, the source contact portion 72 is divided into source contact portions 72a and 72b, and the base region 6 is divided into base regions 6a and 6b. The source expansion portions 71a and 71b and the source contact portions 72a and 72b form the source regions 7a and 7b. After that, the oxide film 23 used as an etching mask is removed.

[0064] Next, the gate insulating film / gate electrode formation process in step S16 of Figure 4 is performed. In this gate insulating film / gate electrode formation process, a gate insulating film 11 (see Figure 13) is formed on the lower and side surfaces of the trench 10, and on the upper surfaces of the source contact portions 72a, 72b and base contact regions 8a, 8b, using CVD technology, high-temperature oxidation (HTO) method, or thermal oxidation method. During the formation of the gate insulating film 11, heat treatment (PDA: Post Deposition Annealing) is performed at, for example, a temperature of 900°C or higher and 1350°C or lower.

[0065] Next, a polysilicon layer (doped polysilicon layer) with high concentrations of impurities such as phosphorus (P) and boron (B) is deposited to fill the inside of the trench 10 using CVD technology or the like. Subsequently, a portion of the polysilicon layer and a portion of the gate insulating film 11 are selectively removed using photolithography technology and dry etching. As a result, as shown in Figure 13, an insulated gate electrode structure (11,12) consisting of the gate insulating film 11 and the gate electrode 12 is formed. At this time, as shown in Figure 2, the amount of indentation d0 of the gate electrode 12 is adjusted so that the upper surface 12a of the gate electrode 12 in contact with the gate insulating film 11 is deeper than the lower surface (lower end) 72x of the source contact portion 72a and shallower than the lower surface (lower end) 71x of the source extension portion 71a.

[0066] Next, an interlayer insulating film 13 (see Figure 14) is deposited on the upper surface of the insulated gate electrode structure (11,12) using CVD technology or the like. A portion of the interlayer insulating film 13 is selectively removed using photolithography technology and dry etching technology, etc., to create contact holes 13a and 13b in the interlayer insulating film 13 that expose the upper surfaces of the source contact portions 72a and 72b and the base contact regions 8a and 8b, as shown in Figure 14. After that, heat treatment (reflow) may be performed to flatten the interlayer insulating film 13.

[0067] Next, using sputtering technology or vapor deposition, etc., a barrier metal layer 14 and source wiring electrodes 15 are sequentially formed to cover the upper and side surfaces of the interlayer insulating film 13 and the upper surfaces of the source contact portions 72a, 72b and base contact regions 8a, 8b, as shown in Figure 15, thereby forming source electrodes (14, 15). The barrier metal layer 14 makes low-resistance ohmic contact with the source contact portions 72a, 72b and base contact regions 8a, 8b of the source regions 7a, 7b.

[0068] Next, the SiC substrate 1 is thinned from the lower surface side by grinding or chemical mechanical polishing (CMP) or the like to adjust the thickness, thereby obtaining the drain region 1. Next, a drain electrode 16 (see FIG. 1) made of gold (Au) or the like is formed on the entire lower surface of the drain region 1 by a sputtering method, a vapor deposition method or the like. In this way, the SiC semiconductor device shown in FIG. 1 is completed.

[0069] (Second Embodiment) The SiC semiconductor device according to the second embodiment has the same configuration as the SiC semiconductor device according to the first embodiment shown in FIG. 1. As shown in FIG. 16, the method for manufacturing the SiC semiconductor device according to the second embodiment is different from the method for manufacturing the SiC semiconductor device according to the first embodiment in that an activation annealing step for an ion implantation region other than the source contact portion 72 in step S23 and an activation annealing step for the source contact portion 72 in step S25 are performed separately.

[0070] n in step S21 of FIG. 16 + The procedure before the type source extension formation step is substantially the same as the method for manufacturing the SiC semiconductor device according to the first embodiment, so redundant description is omitted. n in step S21 of FIG. 16 + The type source extension formation step corresponds to n in step S11 of FIG. 4 + It is the same as the type source extension formation step, and as shown in FIG. 9, n-type impurities are ion-implanted to obtain n + type source extension 71 is formed.

[0071] p in step S22 of FIG. 16 + The type contact region formation step corresponds to p in step S13 of FIG. 4 + It is the same as the type contact region formation step, and as shown in FIG. 11, p-type impurities are ion-implanted to obtain p + type base contact regions 8a and 8b are formed. Note that at this time, n + type source contact portion 72 is not formed.

[0072] The activation annealing step S23 in Figure 16 is the same as the activation annealing step S14 in Figure 4. For example, by performing activation annealing at a temperature of approximately 1600°C to 1900°C, the p-type or n-type impurities ion-implanted in the first embedding regions 4a, 4c, gate bottom protection region 4b, second embedding regions 5a, 5b, source expansion region 71, and base contact regions 8a, 8b are simultaneously activated. + The source contact portion 72 of the mold is not formed.

[0073] Step S24 n in Figure 16 + The mold source contact part formation process is as shown in step S12 of Figure 4. + This process is similar to the type source contact formation process, and as shown in Figure 10, n-type impurities are ion-implanted, + A source contact portion 72 of the mold is formed. Due to damage from ion implantation, the 4H-SiC contained in the source contact portion 72 is broken down, and an amorphous structure is formed.

[0074] The activation annealing step in step S25 of Figure 16 is performed at a lower temperature than the activation annealing step in step S23 of Figure 16, for example, between 1300°C and 1500°C, thereby activating the n-type impurities ion-implanted in the source contact portion 72. At this time, the amorphous structure of the source contact portion 72 recrystallizes to become 3C-SiC, thereby forming a source contact portion 72 containing 3C-SiC.

[0075] The trench formation step S26 in Figure 16 is the same as the trench formation step S15 in Figure 4, and as shown in Figure 12, the trench 10 is selectively formed in the depth direction from the upper surface of the source contact portion 72 by dry etching technology or the like.

[0076] The gate insulating film / gate electrode formation step in step S27 of Figure 16 is the same as the gate insulating film / gate electrode formation step in step S16 of Figure 4, and as shown in Figure 13, an insulated gate type electrode structure (11,12) consisting of a gate insulating film 11 and a gate electrode 12 is embedded inside the trench 10. The steps after the gate insulating film / gate electrode formation step in step S27 of Figure 16 are substantially the same as the manufacturing method of the SiC semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0077] According to the manufacturing method of the SiC semiconductor device according to the second embodiment, similar to the manufacturing method of the SiC semiconductor device according to the first embodiment, it is possible to realize a trench gate type SiC semiconductor device in which the source regions 7a and 7b can make ohmic contact with the source electrodes (14 and 15) and leakage current between the gate electrode 12 and the source regions 7a and 7b can be suppressed.

[0078] Furthermore, according to the manufacturing method of the SiC semiconductor device according to the second embodiment, the activation annealing step for the ion implantation region other than the source contact portion 72 in step S23 and the activation annealing step for the source contact portion 72 in step S25 are performed separately. Crystal defects in the 3C-SiC of the source contact portion 72 occur when the amorphous structure recrystallizes during activation annealing, but since the activation annealing step in step S25 is performed at a lower temperature than the activation annealing step in step S23, the propagation of crystal defects from the source contact portion 72 to the source extension portion 71 can be reduced or suppressed.

[0079] (Third embodiment) The SiC semiconductor device according to the third embodiment has the same configuration as the SiC semiconductor device according to the first embodiment shown in Figure 1. The manufacturing method of the SiC semiconductor device according to the third embodiment differs from the manufacturing method of the SiC semiconductor device according to the first embodiment in that, as shown in Figure 17, the heat treatment (PDA) in the gate insulating film / gate electrode formation step S36 also serves as the activation annealing of the source contact portion 72.

[0080] n in step S31 of FIG. 17 + Since the procedure prior to the n-type source extension forming step is substantially the same as the method for manufacturing a SiC semiconductor device according to the first embodiment, redundant description is omitted. n in step S31 of FIG. 17 + -type source extension forming step is the same as the n-type source extension forming step in step S11 of FIG. 4 + -type source extension forming step. As shown in FIG. 9, by ion-implanting n-type impurities, an n + -type source extension 71 is formed.

[0081] p in step S32 of FIG. 17 + -type contact region forming step is the same as the p-type contact region forming step in step S13 of FIG. 4 + -type contact region forming step. As shown in FIG. 11, by ion-implanting p-type impurities, a p + -type base contact regions 8a and 8b are formed. Note that at this time, an n + -type source contact portion 72 is not formed.

[0082] The activation annealing step of step S33 in FIG. 17 is the same as the activation annealing step of step S14 in FIG. 4. For example, by performing activation annealing at a temperature of about 1600°C or higher and 1900°C or lower, the p-type impurities or n-type impurities ion-implanted into the first buried regions 4a, 4c, the gate bottom protection region 4b, the second buried regions 5a, 5b, the source extension 71, the base contact regions 8a, 8b, and the like are activated all at once. Note that at this time, an n + -type source contact portion 72 is not formed.

[0083] n in step S34 of FIG. 17 + -type source contact portion forming step is the same as the n-type source contact portion forming step in step S12 of FIG. 4 + -type source contact portion forming step. As shown in FIG. 10, by ion-implanting n-type impurities, an n + -type source contact portion 72 is formed. Due to ion implantation damage, the 4H-SiC contained in the source contact portion 72 is damaged, and an amorphous structure is formed.

[0084] The trench formation step S35 in Figure 17 is the same as the trench formation step S15 in Figure 4, and as shown in Figure 12, the trench 10 is selectively formed in the depth direction from the upper surface of the source contact portion 72 by dry etching technology or the like.

[0085] The gate insulating film / gate electrode formation step in step S36 of Figure 17 is the same as the gate insulating film / gate electrode formation step in step S16 of Figure 4, and as shown in Figure 13, the gate insulating film 11 is formed inside the trench 10. When forming the gate insulating film 11, a heat treatment is performed at a temperature lower than that of the activation annealing step in step S33 of Figure 17, for example, between 900°C and 1350°C. This heat treatment activates the n-type impurities ion-implanted in the source contact portion 72. At this time, the amorphous structure of the source contact portion 72 recrystallizes to become 3C-SiC, thereby forming a source contact portion 72 containing 3C-SiC. Subsequently, the gate electrode 12 is embedded inside the trench 10, and an insulated gate electrode structure (11,12) consisting of the gate insulating film 11 and the gate electrode 12 is formed.

[0086] The steps following the gate insulating film / gate electrode formation process in step S36 of Figure 17 are substantially the same as those in the manufacturing method of the SiC semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0087] According to the manufacturing method of the SiC semiconductor device according to the third embodiment, similar to the manufacturing method of the SiC semiconductor device according to the first embodiment, it is possible to realize a trench gate type SiC semiconductor device in which the source regions 7a and 7b can make ohmic contact with the source electrodes (14 and 15) and leakage current between the gate electrode 12 and the source regions 7a and 7b can be suppressed.

[0088] Furthermore, according to the manufacturing method of the SiC semiconductor device according to the third embodiment, crystal defects in the 3C-SiC of the source contact portion 72 occur when the amorphous structure recrystallizes during activation annealing. However, since the heat treatment in the gate insulating film / gate electrode formation step S36 is performed at a lower temperature than the activation annealing step S33, the propagation of crystal defects from the source contact portion 72 to the source extension portion 71 can be reduced or suppressed. Moreover, since the heat treatment in the gate insulating film / gate electrode formation step S36 also serves as the activation annealing of the source contact portion 72, an increase in the number of steps can be suppressed.

[0089] (Other embodiments) As described above, the first to third embodiments of this disclosure have been presented, but the statements and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0090] For example, although a MOSFET was given as an example of a semiconductor device according to the first to third embodiments, n + Instead of drain region 1 of type p + This method is also applicable to insulated-gate bipolar transistors (IGBTs) with a collector region of a specific type. In addition to IGBTs alone, it is also applicable to reverse-conducting IGBTs (RC-IGBTs) and reverse-blocking insulated-gate bipolar transistors (RB-IGBTs).

[0091] Furthermore, the configurations disclosed in the first to third embodiments can be combined as appropriate, within the bounds of consistency. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are appropriate based on the above description. [Explanation of Symbols]

[0092] 1…Drain region (SiC substrate) 2…Drift layer 3…Current diffusion layer 3a,3b…n-type layer 4a, 4c... First implantation area 4b...Gate bottom protection area 5a, 5b…Second embedding area 6, 6a, 6b... Base region 7a,7b,7x…source area 8a, 8b... Base contact area 10…Trench 11…Gate insulating film 12… Guard gate 12a…Top surface 13…Interlayer insulating film 13a, 13b… Contact holes 14… Barrier metal layer 15…Source wiring electrodes 16…Drain electrode 21-23... Oxide film 71, 71a, 71b... Source extension section 71x…Bottom side 72, 72a, 72b... Source contact section 72x…Bottom side

Claims

1. A first-conductivity drift layer made of silicon carbide, A second conductive base region made of silicon carbide is provided on the upper surface side of the drift layer, A first conductive type main region made of silicon carbide is provided on the upper surface side of the base region, A gate insulating film is provided inside the trench that penetrates the main region and the base region, A gate electrode embedded inside the trench via the gate insulating film, A main electrode provided in contact with the main region, Equipped with, The aforementioned main region is A source extension portion whose lower surface is in contact with the base region, A source contact portion is provided on the upper side of the source extension portion, is in contact with the main electrode, and includes a 3C structure, Equipped with, The upper surface of the gate electrode at the position in contact with the gate insulating film is deeper than the lower surface of the source contact portion and shallower than the lower surface of the source extension portion. The thickness of the source contact portion is thinner than the thickness of the source extension portion. Silicon carbide semiconductor device.

2. A first conductive drift layer made of silicon carbide, A second conductive base region made of silicon carbide is provided on the upper surface side of the drift layer, A first conductive type main region made of silicon carbide is provided on the upper surface side of the base region, A second conductive base contact region made of silicon carbide is provided on the upper surface side of the drift layer in contact with the main region, A gate insulating film is provided inside the trench that penetrates the main region and the base region, A gate electrode embedded inside the trench via the gate insulating film, A main electrode provided in contact with the main region and the base contact region, Equipped with, The aforementioned main region is A source extension portion whose lower surface is in contact with the base region, A source contact portion is provided on the upper side of the source extension portion, is in contact with the main electrode, and includes a 3C structure, Equipped with, The upper surface of the gate electrode at the position in contact with the gate insulating film is deeper than the lower surface of the source contact portion and shallower than the lower surface of the source extension portion. The portion of the base contact area that contacts the main electrode has a 4H structure. Silicon carbide semiconductor device.

3. The proportion of the 3C structure included in the source contact portion is between 10% and 100%. The silicon carbide semiconductor device according to claim 1 or 2.

4. The source contact portion contains phosphorus or arsenic as an impurity. The silicon carbide semiconductor device according to claim 1 or 2.

5. The impurity concentration in the source contact area is 1 × 10 １９ / cm ３ The above is 1 x 10 ２２ / cm ３ The following is The silicon carbide semiconductor device according to claim 1 or 2.

6. The thickness of the source contact portion is 30 nm or more and 100 nm or less. The silicon carbide semiconductor device according to claim 1 or 2.

7. The source extension contains nitrogen or phosphorus as an impurity. The silicon carbide semiconductor device according to claim 1 or 2.

8. The impurity concentration in the aforementioned source expansion section is 1 × 10 １６ / cm ３ The above is 1 x 10 １９ / cm ３ The following is The silicon carbide semiconductor device according to claim 1 or 2.

9. The thickness of the source extension is 150 nm or more and 400 nm or less. The silicon carbide semiconductor device according to claim 1 or 2.

10. The amount of indentation of the gate electrode from the upper surface of the source contact portion is 100 nm or more and 300 nm or less. The silicon carbide semiconductor device according to claim 1 or 2.

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