Receiving circuit and optical receiving circuit

Abstract

To reduce frequency response fluctuation at changing gain.SOLUTION: A receiver circuit includes: a constant current circuit for generating a second differential current signal according to a first differential current signal; a current dividing circuit for outputting a third differential current signal smaller in amplitude than the second differential current signal, from a first output node and a second output node; a first load resistance element connected between a DC voltage node and the first output node; a second load resistance element connected between the DC voltage node and the second output node; a differential transimpedance amplifier circuit for outputting a differential voltage signal from a first output terminal and a second output terminal according to the third differential current signal; and a voltage regulator circuit for adjusting a gate voltage of an FET connected between a power supply line and the DC voltage node so as to reduce differences among average voltages of the first output node, the second output node, the first output terminal, and the second output terminal.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a receiving circuit and an optical receiving circuit. Background Art

[0002] Conventionally, as a variable gain amplifier circuit, a circuit using a Gilbert circuit is known (see, for example, Patent Document 1). Prior Art Literature Patent Literature

[0003] Patent Document 1 Japanese Unexamined Patent Publication No. 10-224162 Summary of Invention Problem to be Solved by Invention

[0004] In digital coherent optical transmission systems used for long-haul optical communication, performance is required to convert optical signals into electrical signals and amplify the electrical signals without distortion over a wide optical input power range. Many receiving circuits are provided with a variable gain mechanism to meet this requirement.

[0005] However, when changing the gain, the frequency characteristic of the gain may fluctuate. Fluctuations in frequency characteristics can cause distortion of electrical signals.

[0006] The present disclosure provides a receiving circuit and an optical receiving circuit capable of reducing fluctuation in frequency characteristics when gain is changed. Means for Solving the Problem

[0007] According to one aspect of the present disclosure, a constant current circuit, comprising: a first input node and a second input node to which a first differential current signal is input; a first current source connected to the first input node; and a second current source connected to the second input node, wherein the constant current circuit generates a second differential current signal in accordance with the first differential current signal; A current shunt circuit that generates a third differential current signal from the second differential current signal, comprising a first output node and a second output node that output the third differential current signal, and a current shunt circuit that sets the amplitude of the third differential current signal to be smaller than the amplitude of the second differential current signal according to the first control signal and the second control signal, DC voltage node, A load circuit comprising a first load resistance element and a second load resistance element, wherein the first load resistance element is connected between the DC voltage node and the first output node, and the second load resistance element is connected between the DC voltage node and the second output node, A differential transimpedance amplifier circuit comprising: a third input node and a fourth input node to which the third differential current signal is input; a first output terminal and a second output terminal to which a differential voltage signal is output; a first feedback resistor connected between the third input node and the second output terminal; and a second feedback resistor connected between the fourth input node and the first output terminal, wherein the differential voltage signal is generated in accordance with the third differential current signal. A voltage regulator circuit comprising an FET connected between the power line and the DC voltage node, which adjusts the gate voltage of the FET to reduce the difference in average potential between the first output node, the second output node, the first output terminal, and the second output terminal, A receiving circuit is provided that includes the following. [Effects of the Invention]

[0008] According to this disclosure, it is possible to suppress fluctuations in frequency characteristics when changing the gain. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows an example of the configuration of an optical receiving circuit according to one embodiment. [Figure 2] Figure 2 shows an example of the configuration of a receiving circuit according to the first embodiment. [Figure 3] Figure 3 shows the DC characteristics of a current shunt circuit having transistors Q1 through Q4. [Figure 4] FIG. 4 is a characteristic diagram of a receiving circuit of a comparative example that does not include a voltage regulator circuit. [Figure 5] FIG. 5 is a characteristic diagram of the receiving circuit according to the present embodiment that includes a voltage regulator circuit. [Figure 6] FIG. 6 is a diagram illustrating frequency characteristics of an O / E response of an optical receiving circuit. [Figure 7] FIG. 7 is a diagram illustrating frequency characteristics of an O / E response of an optical receiving circuit. [Figure 8] FIG. 8 is a diagram illustrating frequency characteristics of an O / E response of an optical receiving circuit of a comparative example that does not include a voltage regulator circuit. [Figure 9] FIG. 9 is a diagram illustrating a control circuit that controls a gain of a differential amplitude adjusting circuit 10. [Figure 10] FIG. 10 is a diagram illustrating a configuration example of a control circuit. [Figure 11] FIG. 11 is a diagram illustrating a configuration example of a receiving circuit according to a second embodiment. [Figure 12] FIG. 12 is a diagram illustrating a configuration example of a receiving circuit according to a third embodiment. [Figure 13] FIG. 13 is a diagram illustrating a configuration example of a receiving circuit according to a fourth embodiment. [Figure 14] FIG. 14 is an example of a differential amplifier circuit included in the receiving circuit according to the fourth embodiment. MODE FOR CARRYING OUT THE INVENTION

[0010] DESCRIPTION OF EMBODIMENTS OF THE PRESENT DISCLOSURE First, embodiments of the present disclosure will be listed and described.

[0011] (1) A receiving circuit according to a first aspect of the present disclosure includes: a constant current circuit including a first input node and a second input node to which a first differential current signal is input, a first current source connected to the first input node, and a second current source connected to the second input node, the constant current circuit generating a second differential current signal in accordance with the first differential current signal; A current shunt circuit that generates a third differential current signal from the second differential current signal, comprising a first output node and a second output node that output the third differential current signal, wherein the current shunt circuit sets the amplitude of the third differential current signal to be smaller than the amplitude of the second differential current signal in accordance with a first control signal and a second control signal; a DC voltage node; a load circuit comprising a first load resistance element and a second load resistance element, wherein the first load resistance element is connected between the DC voltage node and the first output node, and the second load resistance element is connected between the DC voltage node and the second output node; a differential transimpedance amplifier circuit comprising a third input node and a fourth input node to which the third differential current signal is input, a first output terminal and a second output terminal that output a differential voltage signal, a first feedback resistance element connected between the third input node and the second output terminal, and a second feedback resistance element connected between the fourth input node and the first output terminal, wherein the differential transimpedance amplifier circuit generates the differential voltage signal in accordance with the third differential current signal; a voltage regulator circuit comprising a FET connected between a power supply line and the DC voltage node, wherein the voltage regulator circuit adjusts the gate voltage of the FET so as to reduce a difference among respective average potentials of the first output node, the second output node, the first output terminal, and the second output terminal; comprising:

[0012] According to (1), the difference among the respective average potentials of the first output node, the second output node, the first output terminal, and the second output terminal is reduced. This suppresses deviation of the operating point of the differential transimpedance amplifier circuit from an optimal value, thereby providing a receiving circuit capable of suppressing fluctuation in frequency characteristics when gain is changed.

[0013] (2) In the above (1), the first current source supplies a first current, the second current source supplies a second current, the second current has the same current value as the current value of the first current, The second load resistance element has the same resistance value as the first load resistance element. The differential transimpedance amplifier circuit further comprises a third current source, a third load resistance element, and a fourth load resistance element. The third current source supplies the third current, The fourth load resistance element has the same resistance value as the third load resistance element. The third current may be equal to the sum of the average current flowing through the third load resistance element and the average current flowing through the fourth load resistance element.

[0014] According to (2), the third current is equal to the sum of the average current flowing through the third load resistance element and the average current flowing through the fourth load resistance element. This further suppresses the deviation of the operating point of the differential transimpedance amplifier circuit from the optimal value, and thus further suppresses fluctuations in the frequency characteristics when changing the gain.

[0015] (3) In (1) or (2) above, The differential transimpedance amplifier circuit further comprises a fifth load resistor element, The fifth load resistance element may have one end connected to the third load resistance element and the fourth load resistance element, and the other end connected to the power line.

[0016] According to (3), the fifth load resistance element has one end connected to the third load resistance element and the fourth load resistance element, and the other end connected to the power line. This allows the average current flowing through the third load resistance element and the average current flowing through the fourth load resistance element to be set to desired values ​​by the resistance value of the fifth load resistance element.

[0017] (4) The receiving circuit of a second aspect of this disclosure is The first input node and The second input node and A constant current circuit comprising a first transistor and a second transistor, wherein the first input node is connected to the collector of the first transistor and the second input node is connected to the collector of the second transistor, DC voltage node, A current shunt circuit comprising a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein the emitter of the third transistor and the emitter of the fourth transistor are connected to the first input node, the emitter of the fifth transistor and the emitter of the sixth transistor are connected to the second input node, the collector of the fourth transistor and the collector of the fifth transistor are connected to the DC voltage node, the base of the third transistor and the base of the sixth transistor receive a first control signal, and the base of the fourth transistor and the base of the fifth transistor receive a second control signal. The load circuit comprises a first load resistor element and a second load resistor element, wherein the first load resistor element is connected between the DC voltage node and the collector of the third transistor, and the second load resistor element is connected between the DC voltage node and the collector of the sixth transistor. A differential transimpedance amplifier circuit comprising a seventh transistor, an eighth transistor, a ninth transistor, a first feedback resistor, a second feedback resistor, a third load resistor, a fourth load resistor, and a fifth load resistor, wherein the base of the seventh transistor is connected to the first load resistor, the base of the eighth transistor is connected to the second load resistor, the emitter of the seventh transistor and the emitter of the eighth transistor are connected to the collector of the ninth transistor, the first feedback resistor is connected between the collector and base of the seventh transistor, the second feedback resistor is connected between the collector and base of the eighth transistor, the third load resistor is connected between the fifth load resistor and the seventh transistor, and the fourth load resistor is connected between the fifth load resistor and the eighth transistor. The first output terminal connected to the collector of the eighth transistor, The second output terminal is connected to the collector of the seventh transistor, A voltage regulator circuit comprising an FET connected between the power line and the DC voltage node, which adjusts the gate voltage of the FET to reduce the difference in average potential between the collectors of the third transistor, the sixth transistor, the seventh transistor, and the eighth transistor, It is equipped with.

[0018] According to (4), the difference in average potentials between the collectors of the third transistor, the sixth transistor, the seventh transistor, and the eighth transistor becomes smaller. As a result, the deviation of the operating point of the differential transimpedance amplifier circuit from the optimal value is suppressed, and a receiving circuit is provided that can suppress fluctuations in the frequency characteristics when the gain is changed.

[0019] (5) In any one of the above (1) to (4), The voltage regulator circuit comprises a first input resistor element, a second input resistor element, a third input resistor element, a fourth input resistor element, and an operational amplifier. The first input resistor is connected between the collector of the third transistor and the non-inverting input terminal of the operational amplifier. The second input resistor is connected between the collector of the sixth transistor and the non-inverting input terminal of the operational amplifier. The third input resistor is connected between the collector of the eighth transistor and the inverting input terminal of the operational amplifier. The fourth input resistor is connected between the collector of the seventh transistor and the inverting input terminal of the operational amplifier. The output of the operational amplifier may be electrically connected to the gate of the FET.

[0020] According to (5), the difference in average potentials between the collectors of the third transistor, the sixth transistor, the seventh transistor, and the eighth transistor is detected with high accuracy. The gate voltage of the FET is adjusted so that the detected difference becomes small, thereby further suppressing the deviation of the operating point of the differential transimpedance amplifier circuit from the optimal value. As a result, fluctuations in the frequency characteristics when changing the gain are further suppressed.

[0021] (6) In any one of the above (1) to (5), The differential transimpedance amplifier circuit may have an input impedance lower than the resistance values ​​of the first load resistance element and the second load resistance element.

[0022] According to (6), the load capacitance of the current shunt circuit is reduced, the deterioration of the frequency characteristics of the current gain is suppressed, and consequently, fluctuations in the frequency characteristics when changing the current gain are suppressed.

[0023] (7) In any one of the above (1) to (6), A reference voltage circuit that generates a reference voltage, The current extraction circuit comprises a first extraction current source connected to a first input terminal connected to the first input node and a second extraction current source connected to a second input terminal connected to the second input node, wherein the first extraction current source extracts a first feedback current from a first current signal input from the first input terminal, and the second extraction current source extracts a second feedback current from a second current signal input from the second input terminal. The system may further include a feedback control circuit that controls the withdrawal of the first feedback current and the second feedback current so that the DC voltage of the first input terminal and the DC voltage of the second input terminal are equal to the reference voltage.

[0024] According to (7), the DC current component contained in the first current signal and the second current signal is reduced. As a result, the deviation of the operating point of the differential transimpedance amplifier circuit from the optimal value is suppressed, and the fluctuation of the frequency characteristics when changing the gain can be further suppressed.

[0025] (8) In (4) or (5) above, It further includes a reference current circuit that generates a reference current, The reference current circuit may supply bias voltages to the bases of the first transistor, the second transistor, and the third transistor.

[0026] According to (8), a common bias voltage is applied to the bases of the first transistor, the second transistor, and the third transistor. This suppresses deviations from the optimal value of the operating point of the differential transimpedance amplifier circuit, thereby further suppressing fluctuations in the frequency characteristics when changing the gain.

[0027] (9) In (8) above, The aforementioned reference current circuit includes a tenth transistor, The collector of the 10th transistor is connected to the base of the 10th transistor, The base of the 10th transistor may be connected to the base of the first transistor, the base of the second transistor, and the base of the third transistor.

[0028] According to (9), the first transistor, the second transistor, and the third transistor can each form a current mirror circuit in relation to the tenth transistor. This suppresses the deviation of the operating point of the differential transimpedance amplifier circuit from the optimal value, and thus further suppresses fluctuations in the frequency characteristics when changing the gain.

[0029] (10) In (8) above, A reference voltage circuit that generates a reference voltage according to the bias voltage, The current extraction circuit comprises a first extraction current source connected to a first input terminal connected to the first input node and a second extraction current source connected to a second input terminal connected to the second input node, wherein the first extraction current source extracts a first feedback current from a first current signal input from the first input terminal, and the second extraction current source extracts a second feedback current from a second current signal input from the second input terminal. The system may further include a feedback control circuit that controls the withdrawal of the first feedback current and the second feedback current so that the DC voltage of the first input terminal and the DC voltage of the second input terminal are equal to the reference voltage.

[0030] According to (10), the DC current component contained in the first current signal and the second current signal is reduced. As a result, the deviation of the operating point of the differential transimpedance amplifier circuit from the optimal value is suppressed, and the fluctuation of the frequency characteristics when changing the gain can be further suppressed.

[0031] (11) In (10) above, The aforementioned reference voltage circuit comprises an 11th transistor and a 12th transistor, The base of the 11th transistor is connected to the base of the first transistor, the base of the second transistor, and the base of the third transistor. The collector of the 11th transistor may be connected to the emitter of the 12th transistor.

[0032] According to (11), the cascaded connection configuration of the reference voltage circuit is the same as the cascaded connection configuration of the constant current circuit and the shunt current circuit. As a result, the voltage movement of the differential output node of the current shunt circuit (the differential input node of the differential transimpedance amplifier circuit) is matched to the movement of the reference voltage in response to temperature or power supply voltage fluctuations. As a result, accurate compensation can be performed in response to temperature or power supply voltage fluctuations, and fluctuations in the frequency characteristics when changing the gain can be further suppressed.

[0033] (12) In any one of the above (1) to (6), A differential transimpedance amplifier that converts differential current to differential voltage, The circuit comprises a differential amplifier circuit for amplifying the differential voltage, The differential amplifier circuit comprises the constant current circuit, the current shunt circuit, the DC voltage node, the load circuit, the differential transimpedance amplifier circuit, the voltage regulator circuit, and the differential pair circuit. The differential pair circuit comprises a 13th transistor located at the first input node, a 14th transistor located at the second input node, and a resistive element connected between the emitter of the 13th transistor and the emitter of the 14th transistor. The base of the 13th transistor and the base of the 14th transistor may receive the differential voltage.

[0034] According to (12), in the differential amplifier circuit following the differential transimpedance amplifier, the difference between the respective average potentials becomes smaller. As a result, the deviation of the operating point of the differential transimpedance amplifier circuit from the optimal value is suppressed, and a receiving circuit capable of suppressing fluctuations in the frequency characteristics when changing the gain can be provided.

[0035] (13) The optical receiving circuit of the present disclosure is A first photodetector that generates a first current signal in response to a first optical signal, A second photodetector that generates a second current signal in response to a second optical signal, A receiving circuit as described in any one of (1) to (12) above, It may be provided.

[0036] According to (6), since the receiving circuit is provided as described in any one of (1) to (12), it is possible to provide an optical receiving circuit that can suppress fluctuations in frequency characteristics when the gain is changed.

[0037] [Details of the embodiments of this disclosure] Specific examples of the receiving circuit and optical receiving circuit of this disclosure will be described below with reference to the drawings. However, the present invention is not limited to these examples and is intended to include all modifications within the meaning and scope of the claims as defined herein.

[0038] Figure 1 shows an example of the configuration of an optical receiving circuit according to one embodiment. The optical receiving circuit 200 shown in Figure 1 generates differential voltage signals voutp and voutn in response to a first optical signal Lp and a second optical signal Ln. The pair of first optical signals Lp and second optical signals Ln are optical signals whose phases are inverted relative to each other. For example, the first optical signal Lp is the positive-phase component of a differential optical signal, and the second optical signal Ln is the negative-phase component of that differential optical signal. For example, when the intensity (also called signal strength) of the first optical signal Lp increases, the intensity of the second optical signal Ln decreases, and when the intensity of the first optical signal Lp decreases, the intensity of the second optical signal Ln increases. Also, when the intensity of the first optical signal Lp reaches its maximum value (peak value), the intensity of the second optical signal Ln reaches its minimum value (bottom value), and when the intensity of the first optical signal Lp reaches its bottom value, the intensity of the second optical signal Ln reaches its peak value. Preferably, the second optical signal Ln has a maximum amplitude equal to that of the first optical signal Lp, and an average value equal to that of the time-averaged (average) first optical signal Lp. In this way, the first optical signal Lp and the second optical signal Ln form a pair of complementary signals.

[0039] In the following explanation, in the case of differential signals, the positive-sequence and negative-sequence components will be assumed to have the same characteristics as the first optical signal Lp and the second optical signal Ln described above. For example, differential voltage signals voutp and voutn include the voltage signal voutp as the positive-sequence component and the voltage signal voutn as the negative-sequence component, which has a phase inverted from the phase of the positive-sequence component. Thus, the notation voutp and voutn indicates that the differential voltage signals voutp and voutn are composed of a pair of voltage signals voutp and voutn.

[0040] The optical receiving circuit 200 is mounted, for example, in a receiver of a digital coherent optical transmission system. The optical receiving circuit 200 comprises a first photodetector PDP, a second photodetector PDN, and a receiving circuit 100. The first photodetector PDP generates and outputs a first current signal ipdp in response to a first optical signal Lp. The second photodetector PDN generates and outputs a second current signal ipdn in response to a second optical signal Ln.

[0041] The first photodetector PDP and the second photodetector PDN are, for example, a pair of photodetectors. Preferably, the second photodetector PDN has the same electrical and optical properties as the first photodetector PDP. For example, the first photodetector PDP may be formed from the same material as the second photodetector PDN and have the same structure.

[0042] The first photodetector PDP receives a first optical signal Lp and generates a first current signal ipdp. The first photodetector PDP receives the first optical signal Lp and outputs a first current signal ipdp with a larger current value the greater the signal intensity of the received first optical signal Lp. Conversely, the first photodetector PDP outputs a first current signal ipdp with a smaller current value the less the signal intensity of the received first optical signal Lp. The first photodetector PDP outputs a first current signal ipdp whose current amplitude changes in accordance with the amplitude change of the signal intensity of the first optical signal Lp. The first photodetector PDP is, for example, a photodiode. The first photodetector PDP has a cathode to which a bias voltage Vpd is applied and an anode connected to the first input terminal INP of the receiving circuit 100. The first photodetector PDP may be, for example, a photodetector other than a photodiode. For example, if the first photodetector (PDP) is a photodiode, it is used in a reverse-biased state such that the anode voltage is lower than the cathode voltage.

[0043] The second photodetector PDN receives the second optical signal Ln and generates a second current signal ipdn. The second photodetector PDN receives the second optical signal Ln and outputs a second current signal ipdn with a larger current value the greater the signal intensity of the received second optical signal Ln. Conversely, the second photodetector PDN outputs a second current signal ipdn with a smaller current value the less the signal intensity of the received second optical signal Ln is. The second photodetector PDN outputs a second current signal ipdn whose current amplitude changes in accordance with the amplitude change of the signal intensity of the second optical signal Ln. The second photodetector PDN is, for example, a photodiode. The second photodetector PDN has a cathode to which a bias voltage Vpd is applied and an anode connected to the second input terminal INN of the receiving circuit 100. The second photodetector PDN may be a photodetector other than a photodiode. For example, if the second photodetector PDN is a photodiode, it is used in a reverse-biased state such that the anode voltage is lower than the cathode voltage.

[0044] The receiving circuit 100 generates differential voltage signals voutp and voutn in response to the first current signal ipdp and the second current signal ipdn. The differential voltage signals voutp and voutn are composed of the first voltage signal voutp and the second voltage signal voutn. For example, the first voltage signal voutp is the positive-sequence component of the differential voltage signals voutp and voutn, and the second voltage signal voutn is the negative-sequence component of the differential voltage signals voutp and voutn. For example, when the first optical signal Lp and the second optical signal Ln are a pair of complementary signals with their phases inverted, the pair of first current signals ipdp and second current signals ipdn become a pair of complementary signals with their phases inverted, constituting a single differential current signal. That is, for example, the first current signal ipdp corresponds to the positive-sequence component of the differential current signal, and the second current signal ipdn corresponds to the negative-sequence component of the differential current signal. The second current signal ipdn has a phase difference of 180° from the first current signal ipdp. The first current signal ipdp and the second current signal ipdn constitute a single differential input current ipdp, ipdn. For example, when the value (current value) of the first current signal ipdp increases, the value of the second current signal ipdn decreases, and when the value of the first current signal ipdp decreases, the value of the second current signal ipdn increases. Also, when the value of the first current signal ipdp reaches its maximum value (peak value), the value of the second current signal ipdn reaches its minimum value (bottom value), and when the value of the first current signal ipdp reaches its bottom value, the value of the second current signal ipdn reaches its peak value. Preferably, the second current signal ipdn has a maximum amplitude of the same magnitude as the maximum amplitude of the first current signal ipdp, and an average value of the same magnitude as the time average (average value) of the first current signal ipdp. In this way, the first current signal ipdp and the second current signal ipdn are a pair of complementary signals.

[0045] The receiving circuit 100 includes a first input terminal INP to which a first photodetector PDP is connected, and a second input terminal INN to which a second photodetector PDN is connected.

[0046] The first input terminal INP is electrically connected, for example, to a first photodetector PDP outside the receiving circuit 100. The first input terminal INP receives, for example, a first current signal ipdp from the first photodetector PDP. For example, when the receiving circuit 100 is formed on a semiconductor chip as an integrated circuit, the first input terminal INP is a pad of the integrated circuit. For example, the first input terminal INP is electrically connected to the anode of the first photodetector PDP via a bonding wire.

[0047] The second input terminal INN is electrically connected, for example, to a second photodetector PDN outside the receiving circuit 100. The second input terminal INN receives, for example, a second current signal ipdn from the second photodetector PDN. For example, when the receiving circuit 100 is formed on a semiconductor chip as an integrated circuit, the second input terminal INN is a pad of the integrated circuit. For example, the second input terminal INN is electrically connected to the anode of the second photodetector PDN via a bonding wire.

[0048] Figure 2 shows an example of the configuration of a receiving circuit according to the first embodiment. The receiving circuit 101 shown in Figure 2 is an example of the receiving circuit 100 (Figure 1). The receiving circuit 101 includes a differential amplitude adjustment circuit 10 and a differential TIA circuit 20. TIA is an abbreviation for transimpedance amplifier.

[0049] In the receiving circuit 101, a first current signal ipdp is input via the first input terminal INP, and a second current signal ipdn is input via the second input terminal INN. The first current signal ipdp and the second current signal ipdn are input as first differential current signals iinp and iinn. The first current signal ipdp is input as the first input current iinp, which is the positive-sequence component of the first differential current signals iinp and iinn, and the second current signal ipdn is input as the second input current iinn, which is the negative-sequence component of the first differential current signals iinp and iinn. The first current signal ipdp includes an AC component that changes over time for information transmission and a DC component that corresponds to the time average value. The first input current iinp corresponds to the AC component of the first current signal ipdp. The second current signal ipdn also includes an AC component that changes over time for information transmission and a DC component that corresponds to the time average value. The second input current iinn corresponds to the AC component of the second current signal ipdn. The DC components of the first current signal ipdp and the second current signal ipdn will be described later.

[0050] In the proper nouns for current signals, a capital "I" at the beginning represents DC (direct current), and a lowercase "i" at the beginning represents current that includes AC (alternating current) components. Whether the current signal contains only AC components or both AC and DC components, the proper noun begins with a lowercase "i". Similarly, in the names of voltage signals, a capital "V" and a lowercase "v" at the beginning represent DC voltage and voltage that includes AC components, respectively. Whether the voltage signal contains only AC components or both AC and DC components, the proper noun begins with a lowercase "v".

[0051] The first input current iinp and the second input current iinn of the AC component are input to the differential amplitude adjustment circuit 10.

[0052] The differential amplitude adjustment circuit 10 includes a constant current circuit 11, a current shunt circuit 12, and a load circuit 13. The current shunt circuit 12 is connected to the upper stage of the constant current circuit 11, and the load circuit 13 is connected to the upper stage of the current shunt circuit 12. The differential amplitude adjustment circuit 10 varies the current gain from zero to 1 according to the first control voltage Vgcp and the second control voltage Vgcn. The current gain corresponds to the ratio of the magnitude (amplitude) of the third differential current signals icbp and icbn to the magnitude (amplitude) of the first differential current signals iinp and iinn. The first input current iinp is input to the first input node IN1 of the constant current circuit 11, and the second input current iinn is input to the second input node IN2 of the constant current circuit 11. The first input node IN1 is connected to the first input terminal INP. The second input node IN2 is connected to the second input terminal INN.

[0053] The constant current circuit 11 comprises a first input node IN1 and a second input node IN2 to which first differential current signals iinp and iinn are input, a first current source 7 connected to the first input node IN1, and a second current source 8 connected to the second input node IN2. The first current source 7 is connected between the first input node IN1 and ground and supplies a first constant current Ib1. The second current source 8 is connected between the second input node IN2 and ground and supplies a second constant current Ib2. The second constant current Ib2 has the same current value as the first constant current Ib1.

[0054] The constant current circuit 11 generates second differential current signals iep and ien in response to the first differential current signals iinp and iinn. The positive-sequence component of the second differential current signals iep and ien, current iep, is generated by the constant current circuit 11 by subtracting the first input current iinp from the first constant current Ib1. Since the sum of the first input current iinp and current iep is equal to the first constant current Ib1, for example, when the first input current iinp increases, current iep decreases, and when the first input current iinp decreases, current iep increases. In other words, current iep is the inverted signal of the first input current iinp. The negative-sequence component of the second differential current signals iep and ien, current ien, is generated by the constant current circuit 11 by subtracting the second input current iinn from the second constant current Ib2. Since the sum of the second input current iinn and current ien is equal to the second constant current Ib2, for example, when the second input current iinn increases, current ien decreases, and when the second input current iinn decreases, current ien increases. In other words, current ien is the inverted signal of the second input current iinn. Therefore, the positive-sequence component current iep and the negative-sequence component current ien of the second differential current signals iep and ien are inverted with respect to the positive-sequence component iinp and the negative-sequence component iinn of the first differential current signals iinp and iinn, respectively, so the second differential current signals iep and ien are the inverted signals of the first differential current signals iinp and iinn.

[0055] The current shunt circuit 12 generates third differential current signals icbp and icbn from second differential current signals iep and ien. The current shunt circuit 12 comprises a first output node OUT1, a second output node OUT2, and transistors Q1, Q2, Q3, and Q4. The third differential current signals icbp and icbn are output from the first output node OUT1 and the second output node OUT2. Transistor Q1 is connected between the first input node IN1 and the first output node OUT1. Transistor Q2 is connected between the first input node IN1 and the DC voltage node N1, which will be described later. Transistor Q3 is connected between the second input node IN2 and the DC voltage node N1. Transistor Q4 is connected between the second input node IN2 and the second output node OUT2. It is preferable that transistors Q1, Q2, Q3, and Q4 have the same electrical characteristics.

[0056] The current shunt circuit 12 is an example of a circuit that sets the amplitude of the third differential current signals icbp and icbn to be smaller than the amplitude of the second differential current signals iep and ien, according to the first control voltage Vgcp and the second control voltage Vgcn. Because the current shunt circuit 12 makes the current gain of the differential amplitude adjustment circuit 10 1 or less, the amplitude of the third differential current signals icbp and icbn becomes equal to or smaller than the amplitude of the first differential current signals iinp and iinn. Therefore, the differential amplitude adjustment circuit 10 attenuates the first differential current signals iinp and iinn and outputs the attenuated differential current signals as the third differential current signals icbp and icbn.

[0057] The current shunt circuit 12 divides the positive-sequence component of the second differential current signals iep and ien, which is current iep, into two positive-sequence collector currents (the first shunt current icq1 output from the collector of transistor Q1 and the second shunt current icq2 output from the collector of transistor Q2). The current shunt circuit 12 also divides the negative-sequence component of the second differential current signals iep and ien, which is current ien, into two negative-sequence collector currents (the third shunt current icq3 output from the collector of transistor Q3 and the fourth shunt current icq4 output from the collector of transistor Q4).

[0058] Transistor Q1 has a first control voltage Vgcp at its base, its emitter connected to the first input node IN1, and its collector connected to the first output node OUT1. Transistor Q2 has a second control voltage Vgcn at its base, its emitter connected to the first input node IN1, and its collector connected to the DC voltage node N1. This divides the current iep into a first shunt current icq1 and a second shunt current icq2 depending on the first control voltage Vgcp and the second control voltage Vgcn. Transistor Q3 has a second control voltage Vgcn at its base, its emitter connected to the second input node IN2, and its collector connected to the DC voltage node N1. Transistor Q4 has a first control voltage Vgcp at its base, its emitter connected to the second input node IN2, and its collector connected to the second output node OUT2. As a result, the current ien is divided into a third shunt current icq3 and a fourth shunt current icq4 according to the first control voltage Vgcp and the second control voltage Vgcn.

[0059] The load circuit 13 includes a first load resistor element RL1 and a second load resistor element RL2. The first load resistor element RL1 is connected to the first output node OUT1, for example, between the DC voltage node N1 and the first output node OUT1 (the collector of transistor Q1). The second load resistor element RL2 is connected to the second output node OUT2, for example, between the DC voltage node N1 and the second output node OUT2 (the collector of transistor Q4). The second load resistor element RL2 has the same resistance value as the first load resistor element RL1.

[0060] The current shunt circuit 12 outputs the positive-sequence output current icbp, which is the positive-sequence component of the third differential current signals icbp and icbn, from the first output node OUT1 by subtracting the first shunt current icq1 from the current flowing through the first load resistance element RL1. The current shunt circuit 12 outputs the negative-sequence output current icbn, which is the negative-sequence component of the third differential current signals icbp and icbn, from the second output node OUT2 by subtracting the fourth shunt current icq4 from the current flowing through the second load resistance element RL2.

[0061] The current shunt circuit 12 changes the ratio of two positive-sequence collector currents (first shunt current icq1 and second shunt current icq2) and two negative-sequence collector currents (third shunt current icq3 and fourth shunt current icq4) using a first control voltage Vgcp and a second control voltage Vgcn. As described above, the positive-sequence output current icbp, which is the positive-sequence component of the third differential current signals icbp and icbn, is generated according to the first shunt current icq1, and the negative-sequence output current icbn, which is the negative-sequence component of the third differential current signals icbp and icbn, is generated according to the fourth shunt current icq4. The current shunt circuit 12 changes the amplitude of the positive-sequence output current icbp by changing the amplitude of the first shunt current icq1, and changes the amplitude of the negative-sequence output current icbn by changing the amplitude of the fourth shunt current icq4. The first control voltage Vgcp is an example of a first control signal. The second control voltage Vgcn is an example of a second control signal. Note that the second and third shunt currents icq2 and icq3 do not contribute to the generation of the third differential current signals icbp and icbn.

[0062] The first control voltage Vgcp should be set to a value such that transistors Q1 and Q4 do not saturate, for example. The second control voltage Vgcn should be set to a value such that transistors Q2 and Q3 do not saturate, for example. To reduce the current gain of the differential amplitude adjustment circuit 10, the second shunt current icq2 and the third shunt current icq3 should be increased and the first shunt current icq1 and the fourth shunt current icq4 should be decreased by decreasing the first control voltage Vgcp and increasing the second control voltage Vgcn. To increase the current gain of the differential amplitude adjustment circuit 10, the second shunt current icq2 and the third shunt current icq3 should be decreased and the first shunt current icq1 and the fourth shunt current icq4 should be increased by increasing the first control voltage Vgcp and decreasing the second control voltage Vgcn.

[0063] More precisely, the magnitudes of the first to fourth shunt currents, icq1 and icq4, are set according to the voltage difference between the first control voltage Vgcp and the second control voltage Vgcn. For example, if 3 / 4 of current iep is divided into the first shunt current icq1, the remaining 1 / 4 of current iep is divided into the second shunt current icq2, 3 / 4 of current ien is divided into the fourth shunt current icq4, and the remaining 1 / 4 of current ien is divided into the third shunt current icq3, then the amplitudes of the third differential current signals icbp and icbn will be 3 / 4 of the amplitudes of the second differential current signals iep and ien. For example, if half of the current iep is divided into the first shunt current icq1, the remaining half of current iep is divided into the second shunt current icq2, half of current ien is divided into the fourth shunt current icq4, and the remaining half of current ien is divided into the third shunt current icq3, then the amplitudes of the third differential current signals icbp and icbn will be half the amplitudes of the second differential current signals iep and ien. Note that the third differential current signals icbp and icbn are inverted signals of the second differential current signals iep and ien.

[0064] Thus, the differential amplitude adjustment circuit 10 varies the current gain using the first control voltage Vgcp and the second control voltage Vgcn input to the current shunt circuit 12. The current gain corresponds to the ratio of the magnitude (amplitude) of the third differential current signals icbp and icbn to the magnitude (amplitude) of the first differential current signals iinp and iinn. The current gain can be calculated, for example, by the formula (icbp-icbn) / (iinp-iinn). When the current gain is varied using the differential amplitude adjustment circuit 10 with such a configuration, the change in input impedance (as seen from the first input terminal INP and the second input terminal INN) associated with the change in current gain is small, thus suppressing the change in the frequency characteristics of the current gain.

[0065] In the differential amplitude adjustment circuit 10, the second differential current signals iep and ien are output from the constant current circuit 11 in accordance with the first differential current signals iinp and iinn. The shunt currents icq1 and icq4 flowing through transistors Q1 and Q4 from the second differential current signals iep and ien are input to the load resistors RL1 and RL2 and the next stage.

[0066] In this embodiment, a differential TIA circuit 20, which includes a differential amplifier and a first feedback resistor RF1 and a second feedback resistor RF2, is connected to the next stage of the differential amplitude adjustment circuit 10 (current shunt circuit 12). The differential TIA circuit 20 has an input impedance set lower than the resistance values ​​of the load resistors RL1 and RL2. Therefore, most of the shunt currents icq1 and icq4 flowing through transistors Q1 and Q4 of the second differential current signals iep and ien are input to the differential TIA circuit 20.

[0067] On the other hand, in the differential amplitude adjustment circuit 10, the shunt currents icq2 and icq3 flowing through transistors Q2 and Q3 are not output from the first output node OUT1 and the second output node OUT2, but become reactive currents (consumed as reactive power). The magnitude of the positive-sequence output current icbp changes according to the first control voltage Vgcp and the second control voltage Vgcn. The sign of the positive-sequence output current icbp is always non-inverted with respect to the sign of the first input current iinp. Similarly, the magnitude of the negative-sequence output current icbn changes according to the first control voltage Vgcp and the second control voltage Vgcn. The sign of the negative-sequence output current icbn is always non-inverted with respect to the sign of the second input current iinn. Therefore, when the first input current iinp is positive, the positive-sequence output current icbp is positive, and when the first input current iinp is negative, the positive-sequence output current icbp is negative. Similarly, when the second input current iinn is positive, the reverse-sequence output current icbn is positive, and when the second input current iinn is negative, the reverse-sequence output current icbn is negative. This type of operation is also called two-quadrant operation.

[0068] Since the input capacitance of the differential TIA circuit 20 is isolated from the outputs of the first photodetector PDP and the second photodetector PDN by the differential amplitude adjustment circuit 10, the first photodetector PDP and the second photodetector PDN can be operated over a wide bandwidth by reducing the input capacitance of the differential amplitude adjustment circuit 10.

[0069] The differential TIA circuit 20 converts amplitude-adjusted third differential current signals icbp and icbn into differential voltage signals voutp and voutn. The differential TIA circuit 20 comprises a third input node IN3 and a fourth input node IN4 to which the third differential current signals icbp and icbn are input, and a first output terminal OUTP and a second output terminal OUTN to which the differential voltage signals voutp and voutn are output. The third input node IN3 is connected to the first output node OUT1, and the fourth input node IN4 is connected to the second output node OUT2.

[0070] The differential TIA circuit 20 includes a transistor Q5 whose base is connected to the third input node IN3, and a transistor Q6 whose base is connected to the fourth input node IN4. The collector of transistor Q5 is connected to the second output terminal OUTN, and the collector of transistor Q6 is connected to the first output terminal OUTP. The emitters of transistor Q5 and transistor Q6 are connected to each other and connected to the third current source 9. It is preferable that transistors Q5 and Q6 have the same electrical characteristics.

[0071] The differential TIA circuit 20 includes a first feedback resistor RF1 connected between the third input node IN3 and the second output terminal OUTN, and a second feedback resistor RF2 connected between the fourth input node IN4 and the first output terminal OUTP. The first feedback resistor RF1 is connected between the base and collector of transistor Q5. The second feedback resistor RF2 is connected between the base and collector of transistor Q6. With this circuit configuration, the differential TIA circuit 20 generates differential voltage signals voutp and voutn in response to the third differential current signals icbp and icbn.

[0072] In a circuit where the differential TIA circuit 20 is connected to the differential amplitude adjustment circuit 10, the node voltages Va and Vb across the first feedback resistor RF1 and the node voltages Va' and Vb' across the second feedback resistor RF2 must be set to be equal to each other. Note that the node voltages Va, Vb, Va', and Vb' represent the average voltages (DC voltages) of the third input node IN3, the second output terminal OUTN, the fourth input node IN4, and the first output terminal OUTP, respectively. For example, if the node voltages Va and Vb are different, current will flow through the first feedback resistor RF1, causing the operating point of the differential TIA circuit 20 to deviate from the optimal value, which may lead to a deterioration of the frequency characteristics. Also, the difference between the node voltages Va and Va' corresponds to the input offset of the differential amplifier, thus narrowing the linear operating range of the differential TIA circuit 20.

[0073] Therefore, the receiving circuit 101 of this embodiment includes a voltage regulator circuit 80 that adjusts the gate voltage of transistor M1 to reduce the difference in average displacements of the first output node OUT1, the second output node OUT2, the first output terminal OUTP, and the second output terminal OUTN. This suppresses deviations from the optimal value of the operating point of the differential TIA circuit 20, thereby providing a receiving circuit 100 and an optical receiving circuit 200 that can suppress fluctuations in frequency characteristics when changing the current gain. Average displacement refers to the value obtained by averaging the instantaneous voltage values ​​of each node or terminal over a predetermined time (for example, a time between one period and several milliseconds). Note that here, the ground potential is considered as the reference potential, so the average potential may be considered as the average voltage.

[0074] The voltage regulator circuit 80 generates a DC voltage Vreg from the power supply voltage Vcc supplied by the power supply line VCC. The voltage regulator circuit 80 comprises, for example, resistors R1 through R4, an operational amplifier OPA1, and a transistor M1.

[0075] Resistor R1 is an example of a first input resistor. Resistor R1 is connected between the collector of transistor Q1 and the non-inverting input terminal of operational amplifier OPA1. Resistor R2 is an example of a second input resistor. Resistor R2 is connected between the collector of transistor Q4 and the non-inverting input terminal of operational amplifier OPA1. Resistor R3 is an example of a third input resistor. Resistor R3 is connected between the collector of transistor Q6 and the inverting input terminal of operational amplifier OPA1. Resistor R4 is an example of a fourth input resistor. Resistor R4 is connected between the collector of transistor Q5 and the inverting input terminal of operational amplifier OPA1.

[0076] Transistor M1 is a Field Effect Transistor (FET), for example, a P-channel MOSFET. Transistor M1 is connected between the power supply line VCC and the DC voltage node N1. Transistor M1 has a gate connected to the output of the operational amplifier OPA1, a source connected to the power supply line VCC, and a drain connected to the DC voltage node N1. The DC voltage node N1 is a node at a lower potential than the voltage Vcc of the power supply line VCC. The DC voltage Vreg of the DC voltage node N1 is lower than the power supply voltage Vcc supplied by the power supply line VCC.

[0077] The differential amplitude adjustment circuit 10 is connected to the power line VCC via transistor M1. Transistor M1 generates a DC voltage Vreg and supplies it to the differential amplitude adjustment circuit 10. The differential amplitude adjustment circuit 10 operates using the DC voltage Vreg as the power supply voltage.

[0078] The voltage regulator circuit 80 monitors the input voltages vcbp and vcbn and the output voltages voutp and voutn. The input voltages vcbp and vcbn correspond to the differential voltage signals input to the third input node IN3 and the fourth input node IN4 of the differential TIA circuit 20, or the differential voltage signals output from the first output node OUT1 and the second output node OUT2 of the differential amplitude adjustment circuit 10. The output voltages voutp and voutn correspond to the differential voltage signals output from the first output terminal OUTP and the second output terminal OUTN of the differential TIA circuit 20.

[0079] The voltage regulator circuit 80 amplifies the difference between the average values ​​of the input voltages vcbp and vcbn, monitored by resistors R1 and R2, and the average values ​​of the output voltages voutp and voutn, monitored by resistors R3 and R4, using the operational amplifier OPA1. The voltage regulator circuit 80 controls the gate of transistor M1 according to the amplified output of this difference by the operational amplifier OPA1. In this way, the voltage regulator circuit 80 can feedback control the DC voltage Vreg so that the average values ​​of the input voltages vcbp and vcbn match the average values ​​of the output voltages voutp and voutn (so that DC current does not flow through the first feedback resistor RF1 and the second feedback resistor RF2). This feedback control stabilizes the collector-base DC voltage of transistors Q1, Q4 and Q5, Q6, respectively, and suppresses fluctuations in the frequency characteristics of the current gain.

[0080] The operating point of the differential amplitude adjustment circuit 10, which operates in two quadrants, changes in accordance with the change in current gain due to the aforementioned function of the current shunt circuit 12. Therefore, the DC voltages of the input voltages vcbp and vcbn also change in accordance with the change in current gain. The voltage regulator circuit 80 performs feedback control, stabilizing the operating point of the differential amplitude adjustment circuit 10 in response to the change in current gain.

[0081] In the differential TIA circuit 20, if the average value of the input voltages vcbp and vcbn is greater (higher) than the average value of the output voltages voutp and voutn, the output voltage of the operational amplifier OPA1 will be higher. In this case, the gate-source voltage Vgs of transistor M1 will be lower, and the source-drain resistance Rds of transistor M1 will be higher. As a result, the source-drain voltage drop across transistor M1 will be larger, the DC voltage Vreg will be lower, and the average value of the input voltages vcbp and vcbn (in other words, the average value of the differential voltage signals output from the differential amplitude adjustment circuit 10) will be smaller. Consequently, the average value of node voltages Va and Va' will approach the average value of node voltages Vb and Vb'.

[0082] On the other hand, in the differential TIA circuit 20, if the average value of the input voltages vcbp and vcbn is smaller (lower) than the average value of the output voltages voutp and voutn, the output voltage of the operational amplifier OPA1 will be lower. In this case, the gate-source voltage Vgs of transistor M1 will be higher, and the source-drain resistance Rds of transistor M1 will be lower. As a result, the source-drain voltage drop across transistor M1 will be smaller, the DC voltage Vreg will be higher, and the average value of the input voltages vcbp and vcbn (in other words, the average value of the differential voltage signals output from the differential amplitude adjustment circuit 10) will be larger. Consequently, the average value of node voltages Va and Va' will approach the average value of node voltages Vb and Vb'.

[0083] The voltage regulator circuit 80 adjusts the DC voltage Vreg through this feedback operation so that the average value of the input voltages vcbp and vcbn is the same as the average value of the output voltages voutp and voutn. This suppresses the difference between the average values ​​of node voltages Va and Va' and node voltages Vb and Vb'.

[0084] The differential TIA circuit 20 further comprises a third current source 9, a third load resistor element RL3, and a fourth load resistor element RL4. The third current source 9 supplies a third constant current Ib3. The third current source 9 is connected between a common connection node, where the emitters of transistor Q5 and transistor Q6 are connected to each other, and the ground wire. Preferably, the fourth load resistor element RL4 has the same resistance value as the third load resistor element RL3. One end of the third load resistor element RL3 is connected to the collector of transistor Q5. One end of the fourth load resistor element RL4 is connected to the collector of transistor Q6. The other end of the third load resistor element RL3 is connected to the other end of the fourth load resistor element RL4. The pair of transistors Q5 and Q6, the pair of load resistor elements RL3 and RL4, and the third current source 9 constitute the differential amplifier described above.

[0085] The third constant current Ib3 is set to be equal to the sum of the average current flowing through the third load resistance element RL3 and the average current flowing through the fourth load resistance element RL4. This further suppresses the deviation of the operating point of the differential TIA circuit 20 from the optimal value, thereby further suppressing fluctuations in the frequency characteristics when changing the current gain. The average current is the value obtained by averaging the absolute value of the instantaneous AC current over a predetermined time (for example, a time between one period and several milliseconds).

[0086] The differential TIA circuit 20 further includes a fifth load resistor element RC. One end of the fifth load resistor element RC is connected to the third load resistor element RL3 and the fourth load resistor element RL4, and the other end is connected to the power line VCC. By adjusting the resistance value of the fifth load resistor element RC, the average current flowing through the third load resistor element RL3 and the average current flowing through the fourth load resistor element RL4 can be set to desired values.

[0087] To match the node voltages Va, Vb, Va', and Vb', the voltage drops due to the load resistance (from the first load resistance element RL1 to the fifth load resistance element RC) and the bias current (from the first constant current Ib1 to the third constant current Ib3) are made equal. First, to make node voltages Va and Va' match, RL1 × Ib1 = RL2 × Ib2 is satisfied, and to make node voltages Vb and Vb' match, RL3 × Ib3 / 2 = RL4 × Ib3 / 2 is satisfied. Furthermore, the reference potential of the voltages at the first output node OUT1 and the second output node OUT2 of the differential amplitude adjustment circuit 10 is the DC voltage Vreg at the DC voltage node N1, and the reference potential of the voltages at the first output terminal OUTP and the second output terminal OUTN of the differential TIA circuit 20 is the power supply voltage Vcc. Therefore, the resistance values ​​of the first to fifth load resistance elements RL1 to RC and the current values ​​of the first to third constant currents Ib1 to Ib3 are set with respect to the DC voltage Vreg and the power supply voltage Vcc such that Vreg - RL1 × Ib1 = Vreg - RL1 × Ib2 = Vcc - (RC × Ib3 + RL3 × Ib3 / 2) = Vcc - (RC × Ib3 + RL4 × Ib3 / 2). In the above equation, RL1 represents the resistance value of the first load resistance element RL1, and RL2, RL3, RL4, and RC represent the resistance values ​​of the load resistance elements RL2, RL3, RL4, and RC, respectively. Furthermore, in order to reduce the effects of temperature and power supply voltage fluctuations, it is preferable to have, for example, compensation functions for environmental fluctuations in the first constant current Ib1, second constant current Ib2, and third constant current Ib3.

[0088] Figure 3 shows the DC characteristics of a current shunt circuit 12 having transistors Q1 to Q4. Figure 3 shows the results of a circuit simulation. The horizontal axis represents the input current difference iep - ien. The vertical axis represents the positive-sequence output current icbp or negative-sequence output current icbn at high, medium, and low gain levels. Here, the second differential current signals iep and ien are complementary, and ien = -iep. Note that Iep represents the current when the positive-sequence component iep of the second differential current signals iep and ien is DC, and Ien represents the current when the negative-sequence component ien of the second differential current signals iep and ien is DC. Also, the positive-sequence output current Icbp and the negative-sequence output current Icbn each represent DC currents.

[0089] When the first control voltage Vgcp is relatively higher than the second control voltage Vgcn, the gain setting is high, and the change in the difference between the positive-sequence output current icbp and the negative-sequence output current icbn (Icbp-Icbn) in response to the change in the input current difference iep - ien is large, resulting in a high current gain. When the first control voltage Vgcp is relatively lower than the second control voltage Vgcn, the gain setting is low, and the change in the difference between the positive-sequence output current icbp and the negative-sequence output current icbn (Icbp-Icbn) in response to the change in the input current difference iep - ien is small, resulting in a low current gain. "Mid" is a gain setting between high and low.

[0090] Furthermore, when the first input current iinp increases, the current iep decreases. When the current iep decreases, the positive-sequence output current icbp increases. Therefore, when the first input current iinp increases, the positive-sequence output current icbp increases. Conversely, when the first input current iinp decreases, the positive-sequence output current icbp decreases.

[0091] Similarly, as the second input current iinn increases, the current ien decreases. As the current ien decreases, the reverse-sequence output current icbn increases. Therefore, as the second input current iinn increases, the reverse-sequence output current icbn increases. Conversely, as the second input current iinn decreases, the reverse-sequence output current icbn decreases.

[0092] Furthermore, as the input current difference iinp - iinn increases, the current difference iep - ien decreases. As the current difference iep - ien decreases, the output current difference icbp - icbn increases (see Figure 3. Figure 3 shows the DC characteristics, but the trend of increase and decrease is the same for the AC component). Therefore, as the input current difference iinp - iinn increases, the output current difference icbp - icbn increases. Conversely, as the input current difference iinp - iinn decreases, the output current difference icbp - icbn decreases. Therefore, the third differential current signals icbp, icbn are non-inverted with respect to the first differential current signals iinp, iinn. In this way, the differential amplitude adjustment circuit 10 adjusts the amplitude of differential signals without inversion. Generally, the polarity of a differential signal is reversed by swapping its positive-sequence and negative-sequence components. For example, the differential amplitude adjustment circuit 10 can also be made to perform inversion operation by swapping the first output node OUT1 and the second output node OUT2.

[0093] Figures 4 and 5 show the relationship between the control voltage difference Vgcp - Vgcn between the first control voltage Vgcp and the second control voltage Vgcn, the average value Vcb_ave of the input voltages vcbp and vcbn, and the average value Vout_ave of the output voltages voutp and voutn. For comparison, Figure 4 shows the characteristic diagram of a comparative receiver circuit without a voltage regulator circuit 80 (the differential amplitude adjustment circuit 10 is directly connected to the power line VCC), and Figure 5 shows the characteristic diagram of the receiver circuit 101 of this embodiment with a voltage regulator circuit 80.

[0094] In Figure 4, in the region where the control voltage difference Vgcp - Vgcn is relatively large (e.g., 130mV or more), the average values ​​Vcb_ave of the input voltages vcbp and vcbn, and Vout_ave of the output voltages voutp and voutn are approximately the same voltage. On the other hand, in the region where the control voltage difference Vgcp - Vgcn is relatively small (e.g., 50mV or less), the average value Vcb_ave of the input voltages vcbp and vcbn is higher than the average value Vout_ave of the output voltages voutp and voutn. The difference between the average value Vcb_ave and the average value Vout_ave corresponds to the voltage difference across the first feedback resistor RF1 and the second feedback resistor RF2, and is the base-collector voltage of transistors Q5 and Q6, respectively. Therefore, the bias voltage of transistors Q5 and Q6 changes significantly depending on the gain setting, affecting the frequency characteristics of the current gain.

[0095] On the other hand, in Figure 5, regardless of the magnitude of the control voltage difference Vgcp - Vgcn, the average values ​​Vcb_ave and Vout_ave are the same constant voltage value. Therefore, the bias voltages of transistors Q5 and Q6 are stabilized.

[0096] Figures 6 and 7 show the frequency characteristics of the O / E response obtained by circuit simulation (O / E: Optical signal / Electrical signal). In Figures 6 and 7, the horizontal axis represents the frequency of the complementary optical signals Lp and Ln. As described above, by adjusting the control voltage difference Vgcp - Vgcn, the current gain can be set to, for example, high gain high, medium gain mid, and low gain low.

[0097] The vertical axis in Figure 6 shows the gain of each level normalized by the gain value at 1 GHz when the gain setting is high. According to Figure 6, a variable range of more than 20 dB is obtained between the gain when the gain setting is high and the gain when the gain setting is low. The vertical axis in Figure 7 shows the gain of each level normalized by the gain value at 1 GHz for each of the high, mid, and low gain settings. According to Figure 7, the frequency characteristics of each stage with high, mid, and low gain settings almost overlap, indicating that the effect of changes in gain is small. In other words, the fluctuation of the frequency characteristics when changing the current gain is further suppressed.

[0098] Figure 8 shows the O / E response obtained by circuit simulation for a single comparison receiver circuit that does not have a voltage regulator circuit 80 (the differential amplitude adjustment circuit 10 is directly connected to the power line VCC). The vertical axis of Figure 8 represents the gain of each level normalized by the 1GHz gain value at each stage for gain settings high, mid, and low.

[0099] When the current gain is reduced, the current flowing through transistors Q1 and Q4 decreases, which reduces the voltage drop across load resistors RL1 and RL2, and increases the average values ​​of the input voltages vcbp and vcbn to the differential TIA circuit 20. As a result, DC current flows through the feedback resistors RF1 and RF2, lowering the output voltages voutp and voutn, and reducing the collector-base voltages of transistors Q5 and Q6. Consequently, the frequency characteristics of the O / E response change more significantly with respect to the change in current gain compared to Figure 7.

[0100] Figure 9 shows a control circuit for controlling the gain of the differential amplitude adjustment circuit 10. The control circuit 50, for example, detects the amplitudes of the differential voltage signals voutp and voutn, and generates a first control voltage Vgcp and a second control voltage Vgcn according to the detection results. The control circuit 50 may be a circuit provided inside the receiving circuit 100, or a circuit provided outside the receiving circuit 100.

[0101] Figure 10 shows an example of the configuration of a control circuit. The control circuit 50 includes a peak detection circuit 52, an average value detection circuit 53, an amplifier 54, and a differential amplifier circuit 55. The control circuit 50 includes nodes N2 and N3 for receiving differential voltage signals voutp and voutn. The peak detection circuit 52 has, for example, a non-inverting input terminal and an inverting input terminal. The average value detection circuit 53 has, for example, a non-inverting input terminal and an inverting input terminal. The non-inverting input terminal of the peak detection circuit 52 and the non-inverting input terminal of the average value detection circuit 53 are connected to node N2. The inverting input terminal of the peak detection circuit 52 and the inverting input terminal of the average value detection circuit 53 are connected to node N3. For example, a first voltage signal voutp is input to node N2 and a second voltage signal voutn is input to node N3.

[0102] The peak detection circuit 52 detects the peak values ​​of the first voltage signal voutp and the second voltage signal voutn, and outputs a voltage of a magnitude corresponding to the detected peak values. The average value detection circuit 53 detects the average value (magnitude of the DC component) of the first voltage signal voutp and the second voltage signal voutn, and outputs a voltage of a magnitude corresponding to the detected average value. The amplifier 54 outputs a voltage corresponding to the difference between the output voltage (peak voltage value) of the peak detection circuit 52 and the output voltage (average value) of the average value detection circuit 53 (corresponding to half the amplitude values ​​of the first voltage signal voutp and the second voltage signal voutn). The amplifier 54 is, for example, a differential amplifier circuit, and outputs one of the differential outputs (for example, the positive-sequence component). Therefore, the voltage output by the amplifier 54 is a voltage corresponding to the amplitude values ​​of the first voltage signal voutp and the second voltage signal voutn.

[0103] The differential amplifier circuit 55 compares the voltage output by amplifier 54 with a reference voltage Vagcref. When the voltage output by amplifier 54 is lower than the reference voltage Vagcref, the differential amplifier circuit 55 increases the first control voltage Vgcp and decreases the second control voltage Vgcn to increase the gain of the receiving circuit 101 (increases the amplitude of the difference between the positive-sequence output current icbp and the negative-sequence output current icbn). On the other hand, when the voltage output by amplifier 54 is higher than the reference voltage Vagcref, the differential amplifier circuit 55 decreases the first control voltage Vgcp and increases the second control voltage Vgcn to decrease the gain of the receiving circuit 101 (decreases the amplitude of the difference between the positive-sequence output current icbp and the negative-sequence output current icbn). As a result, the amplitudes of the differential voltage signals voutp and voutn are limited so as not to exceed the value set according to the reference voltage Vagcref. In other words, as the amplitudes of the differential voltage signals voutp and voutn approach the value set according to the reference voltage Vagcref, they are maintained within a predetermined control error range relative to the reference voltage Vagcref. Although referred to as "gain" above, the amplitudes of the third differential current signals icbp and icbn are set to be equal to or smaller than the amplitudes of the first differential current signals iinp and iinn. The amplitudes of the first differential current signals iinp and iinn correspond to the amplitude of the difference (differential current) between the first input current iinp and the second input current iinn. The amplitudes of the third differential current signals icbp and icbn correspond to the difference (differential current) between the positive-sequence output current icbp and the negative-sequence output current icpn.

[0104] Figure 11 shows an example of the configuration of a receiving circuit according to the second embodiment. In the second embodiment, the explanation of the configuration, operation, and effects similar to those of the first embodiment will be omitted or simplified by referring to the explanation above. The receiving circuit 102 shown in Figure 11 is an example of the receiving circuit 100 (Figure 1).

[0105] In Figure 11 (Second Embodiment), the first current source 7, the second current source 8, and the third current source 9 are shown as transistors and resistors, respectively, compared to Figure 2 (First Embodiment). A reference current circuit 40 is also shown, which supplies the base voltage (bias voltage Vbias) and base current to each transistor of the first current source 7, the second current source 8, and the third current source 9. Furthermore, the first feedback control voltage Vaocp and the second feedback control voltage Vaocn are shown. 、 An Automatic Offset Control (AOC) circuit 70 generated by two operational amplifiers 71 and 72 is shown. The AOC circuit 70 is an example of a feedback control circuit. A reference voltage circuit 60 that generates the reference voltage Vref for the AOC circuit 70 is also shown. The base voltage (input voltage) of transistor Q10 of the reference voltage circuit 60 is supplied from the reference current circuit 40. A fourth constant current Ib4 flows between the collector and emitter of transistor Q10.

[0106] The receiving circuit 102 further comprises a reference current circuit 40, a reference voltage circuit 60, a current extraction circuit 30, and an AOC circuit 70.

[0107] The reference current circuit 40 generates a reference current Iref. The reference current circuit 40 includes a series circuit of a current source 41, a transistor Q11, and a resistor RB5. The first current source 7 includes a first transistor Q7 that supplies a first constant current Ib1, and a resistor RB1 connected in series with the emitter of the first transistor Q7. The second current source 8 includes a second transistor Q8 that supplies a second constant current Ib2, and a resistor RB2 connected in series with the emitter of the second transistor Q8. Since the first current source 7 and the second current source 8 constitute a pair of current sources forming a differential circuit, it is preferable that, for example, the second transistor Q8 has the same electrical characteristics as the first transistor Q7. The third current source 9 includes a third transistor Q9 that supplies a third constant current Ib3, and a resistor RB3 connected in series with the emitter of the third transistor Q9. The resistors RB1, RB2, and RB3 are connected to the ground line. The reference current circuit 40 supplies a DC bias voltage Vbias (and DC bias current) to the bases of the first transistor Q7, the second transistor Q8, and the third transistor Q9 such that the first constant current Ib1, the second constant current Ib2, and the third constant current Ib3 are equal to the reference current Iref.

[0108] The current extraction circuit 30 receives a first current signal ipdp via the first input terminal INP and a second current signal ipdn via the second input terminal INN. The current extraction circuit 30 extracts a first DC current Iaocp (also called the first feedback current) from the first current signal ipdp and a second DC current Iaocn (also called the second feedback current) from the second current signal ipdn to generate first differential current signals iinp and iinn. The current extraction circuit 30 generates a first input current iinp, which is the positive-sequence component of the first differential current signals iinp and iinn, by extracting the first feedback current Iaocp from the first current signal ipdp. The current extraction circuit 30 generates a second input current iinn, which is the negative-sequence component of the first differential current signals iinp and iinn, by extracting the second feedback current Iaocn from the second current signal ipdn.

[0109] The first current signal ipdp includes an AC component that changes over time for information transmission and a DC component that corresponds to a time-averaged value. By making the magnitude of the first feedback current Iaocp the same as the magnitude of the DC component of the first current signal ipdp, the first input current iinp becomes equal to the AC component of the first current signal ipdp. Similarly, the second current signal ipdn includes an AC component that changes over time for information transmission and a DC component that corresponds to a time-averaged value. By making the magnitude of the second feedback current Iaocn the same as the magnitude of the DC component of the second current signal ipdn, the second input current iinn becomes equal to the AC component of the second current signal ipdn. In other words, the current extraction circuit 30 generates the first differential current signals iinp and iinn by removing their respective DC components from the first current signal ipdp and the second current signal ipdn.

[0110] The current extraction circuit 30 includes a first extraction current source 31 that generates a first feedback current Iaocp and a second extraction current source 32 that generates a second feedback current Iaocn. The first extraction current source 31 changes the value of the first feedback current Iaocp according to the value of the input first feedback control voltage Vaoccp. The second extraction current source 32 changes the value of the second feedback current Iaocn according to the value of the input second feedback control voltage Vaocn.

[0111] If the input signals (first differential current signals iinp, iinn) of the differential amplitude adjustment circuit 10 contain a DC component, the node voltages Va and Va' will deviate from their optimal values. The current extraction circuit 30 extracts the DC component in accordance with the first feedback control voltage Vaocp and the second feedback control voltage Vaocn, thereby suppressing the deviation of Va and Va' from their optimal values. This further suppresses fluctuations in the frequency characteristics when changing the current gain.

[0112] The AOC circuit 70 controls the extraction of the first feedback current Iaocp and the second feedback current Iaocn so that the DC voltage at the first input terminal INP (or the first input node IN1) (first DC voltage) and the DC voltage at the second input terminal INN (or the second input node IN2) (second DC voltage) are the same. In this example, the AOC circuit 70 controls the extraction of the first feedback current Iaocp and the second feedback current Iaocn so that each of the first DC voltage and the second DC voltage is equal to the voltage value of the reference voltage Vref. The AOC circuit 70 generates the first feedback control voltage Vaaocp and the second feedback control voltage Vaocn by negative feedback control according to the difference between each of the first DC voltage and the second DC voltage and the reference voltage Vref. As a result, the first DC voltage and the second DC voltage are maintained at the reference voltage Vref. The AOC circuit 70 and the current extraction circuit 30 control the DC current of the first photodetector PDP and the second photodetector PDN so that they are not input to the differential amplitude adjustment circuit 10, thereby suppressing deviations from the optimal operating point. This suppresses fluctuations in the frequency characteristics when changing the current gain.

[0113] In this example, the first extraction current source 31 is connected to the first input terminal INP (or the first input node IN1), and the second extraction current source 32 is connected to the second input terminal INN (or the second input node IN2). The first extraction current source 31 can divide the first feedback current Iaocp from the first current signal ipdp to ground, and the second extraction current source 32 can divide the second feedback current Iaocn from the second current signal ipdn to ground.

[0114] The AOC circuit 70 controls the DC flow rate from the first current signal ipdp by adjusting the first feedback control voltage Vaocp, and controls the DC flow rate from the second current signal ipdn by adjusting the second feedback control voltage Vaocn.

[0115] The AOC circuit 70 increases the first feedback control voltage Vaaocp and the first feedback current Iaocp when the first DC voltage at the first input terminal INP (or the first input node IN1) is higher than the reference voltage Vref. This reduces the DC component of the first input current iinp, resulting in feedback control that reduces the first DC voltage at the first input terminal INP (or the first input node IN1). On the other hand, for example, when the intensity of the first optical signal Lp and the second optical signal Ln decreases, the first DC voltage at the first input terminal INP (or the first input node IN1) becomes lower than the reference voltage Vref, so the AOC circuit 70 reduces the first feedback control voltage Vaaocp and the first feedback current Iaocp. This prevents excessive extraction of the first feedback current Iaocp from the first input current iinp, resulting in feedback control that increases the first DC voltage at the first input terminal INP (or the first input node IN1). As a result, feedback control is performed so that the first DC voltage is maintained at the reference voltage Vref. Similarly, feedback control is performed for the second DC voltage at the second input terminal INN (or the second input node IN2) so that the second DC voltage is maintained at the reference voltage Vref.

[0116] In this way, feedback control is performed so that the first DC voltage and the second DC voltage reach the same target value (reference voltage Vref). This makes it possible to perform amplification with a small output offset even if there is an imbalance (variation in characteristics) between the first photodetector PDP and the second photodetector PDN, or an imbalance between the pair of transistors Q7 and Q8 in the constant current circuit 11. The output offset is the difference between the DC component of the first voltage signal voutp and the DC component of the second voltage signal voutn.

[0117] The first extraction current source 31 and the second extraction current source 32 are circuits formed using, for example, n-type FETs. For example, the first extraction current source 31 has an n-type FET with its drain connected to the wiring connecting the first input terminal INP and the first input node IN1, and its source connected to ground. The gate of the n-type FET is connected to the output of an operational amplifier 71 to which the voltage of the first input node IN1 and a reference voltage Vref are input. Similarly, for example, the second extraction current source 32 has an n-type FET with its drain connected to the wiring connecting the second input terminal INN and the second input node IN2, and its source connected to ground. The gate of the n-type FET is connected to the output of an operational amplifier 72 to which the voltage of the second input node IN2 and a reference voltage Vref are input. The reference voltage Vref is set to, for example, the same value as the DC voltage of the first input node IN1 when the first feedback current Iaocp is zero.

[0118] The gain of op-amps 71 and 72 only needs to be a sufficiently large value; for example, a gain of several thousand, which is typical for op-amps, is sufficient.

[0119] Figure 12 shows an example of the configuration of a receiving circuit according to the third embodiment. In the third embodiment, the explanation of the configuration, operation, and effects similar to those of the first and second embodiments will be omitted or simplified by referring to the explanation above. The receiving circuit 102A shown in Figure 12 is an example of the receiving circuit 100 (Figure 1).

[0120] The reference voltage circuit 60 in Figure 12 (third embodiment) has a transistor Q12 added to the reference voltage circuit 60 in Figure 11 (second embodiment), to which the bias voltage VCS is input to the base. With the addition of transistor Q12, the connection configuration between the power line VCC and ground in the reference voltage circuit 60 matches the connection configuration between the power line VCC and ground in the differential amplitude adjustment circuit 10. That is, moving from the power line VCC toward the ground line, the load resistance element RL5 corresponds to the positions of the load resistance elements RL1 and RL2, the transistor Q12 corresponds to the positions of the transistors Q1, Q2, Q3, and Q4, the transistor Q10 corresponds to the positions of the transistors Q7 and Q8, and the resistance element RB4 corresponds to the positions of the resistance elements RB1 and RB2. By matching the configurations of both circuits in this way, the movement of the reference voltage Vref and the node voltages Va and Va' in response to temperature or power supply voltage fluctuations can be matched, so that accurate compensation operation can be performed. This makes it possible to further suppress fluctuations in the frequency characteristics when changing the gain.

[0121] In the configuration shown in Figure 12, the current shunt circuit 12 includes transistor Q1 connected between the first load resistance element RL1 and transistor Q7, and transistor Q4 connected between the second load resistance element RL2 and transistor Q8. On the other hand, the reference voltage circuit 60 includes transistor Q10, whose base is connected to the bases of transistors Q7, Q8, and Q9, and transistor Q12 connected between the load resistance element RL5 and transistor Q10. As a result, the reference voltage circuit 60 has the same connection configuration between the power line VCC and ground in the differential amplitude adjustment circuit 10 as the connection configuration between the power line VCC and ground in the power line VCC and ground wiring.

[0122] Furthermore, in the configuration shown in Figure 12, the load circuit 13 includes a first load resistance element RL1 connected between the power line VCC and transistor Q1, and a second load resistance element RL2 connected between the power line VCC and transistor Q4. The constant current circuit 11 includes a resistance element RB1 connected between the ground line and transistor Q7, and a resistance element RB2 connected between the ground line and transistor Q8. On the other hand, the reference voltage circuit 60 includes a load resistance element RL5 connected between the power line VCC and transistor Q12, and a resistance element RB4 connected between the ground line and transistor Q10. As a result, the reference voltage circuit 60 has the same connection configuration between the power line VCC and ground in the differential amplitude adjustment circuit 10 as the connection configuration between the power line VCC and ground in the power line VCC and ground.

[0123] Figure 13 shows an example of the configuration of a receiving circuit according to the fourth embodiment. In the fourth embodiment, the description of the configuration, operation, and effects similar to those of the embodiments described above will be omitted or simplified by referring to the description above. The receiving circuit 103 shown in Figure 13 is an example of the receiving circuit 100 (Figure 1).

[0124] The receiving circuit 103 includes a differential transimpedance amplifier 103a and a differential amplification circuit 103b.

[0125] The differential transimpedance amplifier 103a may be any one of the receiving circuits of the above-described embodiment, or a known configuration of a differential transimpedance amplifier may be used. The differential transimpedance amplifier 103a is a circuit that converts differential current to differential voltage. The differential amplifier circuit 103b is a circuit that amplifies the differential voltage output from the differential transimpedance amplifier 103a and outputs the amplified differential voltage as a differential voltage signal.

[0126] Figure 14 shows an example of a differential amplifier circuit 103b included in the receiving circuit according to the fourth embodiment. The differential amplifier circuit 103b comprises a differential OTA circuit 90, a differential TIA circuit 20, and a voltage regulator circuit 80. OTA is an abbreviation for Operational Transconductance Amplifier. The differential OTA circuit 90 generates differential current signals icbp and icbn according to differential voltage signals vinp and vinn. The differential TIA circuit 20 and voltage regulator circuit 80 in the third embodiment may have the same configuration as the differential TIA circuit 20 and voltage regulator circuit 80 in the first or second embodiment. The differential OTA circuit 90 in the fourth embodiment differs from the differential amplitude adjustment circuits 10 of each of the above embodiments in that it further comprises a differential pair circuit 14 composed of transistors Q12 and Q13 and a resistor RE.

[0127] The differential pair circuit 14 is connected between the constant current circuit 11 and the current shunt circuit 12. The differential pair circuit 14 converts the differential voltage signals vinp and vinn supplied from the differential transimpedance amplifier 103a into differential current signals iep and ien. The differential pair circuit 14 comprises a transistor Q12 located at the first input node, a transistor Q13 located at the second input node, and a resistor RE connected between the emitter of transistor Q12 and the emitter of transistor Q13.

[0128] Transistor Q12 has a base that receives the positive-sequence voltage vinp, which is the positive-sequence component of the differential voltage signals vinp and vinn, a collector connected to the emitter of transistor Q1, and an emitter connected to the collector of transistor Q7. Transistor Q13 has a base that receives the negative-sequence voltage vinn, which is the negative-sequence component of the differential voltage signals vinp and vinn, a collector connected to the emitter of transistor Q4, and an emitter connected to the collector of transistor Q8.

[0129] The differential OTA circuit 90, by incorporating the differential pair circuit 14, operates as a variable gain differential amplifier circuit with a wide bandwidth and small frequency response fluctuations. [Explanation of Symbols]

[0130] 10 Differential amplitude adjustment circuit 11 Constant current circuit 12 Current shunt circuit 13 Load circuit 14 Differential Pair Circuit 20 Differential TIA Circuit 30 Current extraction circuit 40 Reference current circuit 50 Control circuits 60 Reference Voltage Circuit 70 AOC circuit (feedback control circuit) 80 Voltage Regulator Circuit 90 Differential OTA Circuit 100, 101, 102, 102A, 103 Receiving Circuit 103b Differential amplifier circuit 200 Optical receiving circuit PDP, PDN photodetector

Claims

1. A constant current circuit comprising a first input node and a second input node to which a first differential current signal is input, a first current source connected to the first input node, and a second current source connected to the second input node, wherein the constant current circuit generates a second differential current signal in response to the first differential current signal, A current shunt circuit that generates a third differential current signal from the second differential current signal, comprising a first output node and a second output node that output the third differential current signal, and a current shunt circuit that sets the amplitude of the third differential current signal to be smaller than the amplitude of the second differential current signal in accordance with the first control signal and the second control signal, DC voltage node, A load circuit comprising a first load resistance element and a second load resistance element, wherein the first load resistance element is connected between the DC voltage node and the first output node, and the second load resistance element is connected between the DC voltage node and the second output node, A differential transimpedance amplifier circuit comprising: a third input node and a fourth input node to which the third differential current signal is input; a first output terminal and a second output terminal to which a differential voltage signal is output; a first feedback resistor element connected between the third input node and the second output terminal; and a second feedback resistor element connected between the fourth input node and the first output terminal, wherein the differential transimpedance amplifier circuit generates the differential voltage signal in accordance with the third differential current signal. A voltage regulator circuit comprising an FET connected between the power line and the DC voltage node, which adjusts the gate voltage of the FET to reduce the difference in average potential between the first output node, the second output node, the first output terminal, and the second output terminal, A receiving circuit equipped with the following features.

2. The first current source supplies a first current, The second current source supplies the second current, The second current has the same current value as the first current. The second load resistance element has the same resistance value as the first load resistance element. The differential transimpedance amplifier circuit further comprises a third current source, a third load resistance element, and a fourth load resistance element. The third current source supplies the third current, The fourth load resistance element has the same resistance value as the third load resistance element. The third current is equal to the sum of the average current flowing through the third load resistance element and the average current flowing through the fourth load resistance element. The receiving circuit according to claim 1.

3. The differential transimpedance amplifier circuit further comprises a fifth load resistance element, The receiving circuit according to claim 2, wherein one end of the fifth load resistance element is connected to the third load resistance element and the fourth load resistance element, and the other end is connected to the power line.

4. The first input node and The second input node and A constant current circuit comprising a first transistor and a second transistor, wherein the first input node is connected to the collector of the first transistor and the second input node is connected to the collector of the second transistor, DC voltage node, A current shunt circuit comprising a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein the emitter of the third transistor and the emitter of the fourth transistor are connected to the first input node, the emitter of the fifth transistor and the emitter of the sixth transistor are connected to the second input node, the collector of the fourth transistor and the collector of the fifth transistor are connected to the DC voltage node, the base of the third transistor and the base of the sixth transistor receive a first control signal, and the base of the fourth transistor and the base of the fifth transistor receive a second control signal. The load circuit comprises a first load resistor element and a second load resistor element, the first load resistor element being connected between the DC voltage node and the collector of the third transistor, and the second load resistor element being connected between the DC voltage node and the collector of the sixth transistor. A differential transimpedance amplifier circuit comprising a seventh transistor, an eighth transistor, a ninth transistor, a first feedback resistor, a second feedback resistor, a third load resistor, a fourth load resistor, and a fifth load resistor, wherein the base of the seventh transistor is connected to the first load resistor, the base of the eighth transistor is connected to the second load resistor, the emitter of the seventh transistor and the emitter of the eighth transistor are connected to the collector of the ninth transistor, the first feedback resistor is connected between the collector and base of the seventh transistor, the second feedback resistor is connected between the collector and base of the eighth transistor, the third load resistor is connected between the fifth load resistor and the seventh transistor, and the fourth load resistor is connected between the fifth load resistor and the eighth transistor. The first output terminal connected to the collector of the eighth transistor, The second output terminal connected to the collector of the seventh transistor, A voltage regulator circuit comprising an FET connected between the power line and the DC voltage node, which adjusts the gate voltage of the FET to reduce the difference in average potential between the collectors of the third transistor, the sixth transistor, the seventh transistor, and the eighth transistor, A receiving circuit equipped with the following features.

5. The voltage regulator circuit comprises a first input resistor element, a second input resistor element, a third input resistor element, a fourth input resistor element, and an operational amplifier. The first input resistor is connected between the collector of the third transistor and the non-inverting input terminal of the operational amplifier. The second input resistor is connected between the collector of the sixth transistor and the non-inverting input terminal of the operational amplifier. The third input resistor is connected between the collector of the eighth transistor and the inverting input terminal of the operational amplifier. The fourth input resistor is connected between the collector of the seventh transistor and the inverting input terminal of the operational amplifier. The receiving circuit according to claim 4, wherein the output of the operational amplifier is electrically connected to the gate of the FET.

6. The receiving circuit according to any one of claims 1 to 5, wherein the differential transimpedance amplifier circuit has an input impedance lower than the resistance values ​​of the first load resistance element and the second load resistance element.

7. A reference voltage circuit that generates a reference voltage, The system includes a first extraction current source connected to a first input terminal connected to the first input node and a second extraction current source connected to a second input terminal connected to the second input node, wherein the first extraction current source extracts a first feedback current from a first current signal input from the first input terminal, and the second extraction current source extracts a second feedback current from a second current signal input from the second input terminal, and The receiving circuit according to any one of claims 1 to 5, further comprising a feedback control circuit that controls the withdrawal of the first feedback current and the second feedback current so that the DC voltage of the first input terminal and the DC voltage of the second input terminal are the same as the reference voltage.

8. It further includes a reference current circuit that generates a reference current, The receiving circuit according to claim 4 or 5, wherein the reference current circuit supplies a bias voltage to the base of the first transistor, the base of the second transistor, and the base of the third transistor.

9. The aforementioned reference current circuit includes a tenth transistor, The collector of the 10th transistor is connected to the base of the 10th transistor. The receiving circuit according to claim 8, wherein the base of the tenth transistor is connected to the base of the first transistor, the base of the second transistor, and the base of the third transistor.

10. A reference voltage circuit that generates a reference voltage according to the bias voltage, The system includes a first extraction current source connected to a first input terminal connected to the first input node and a second extraction current source connected to a second input terminal connected to the second input node, wherein the first extraction current source extracts a first feedback current from a first current signal input from the first input terminal, and the second extraction current source extracts a second feedback current from a second current signal input from the second input terminal, and The receiving circuit according to claim 8, further comprising a feedback control circuit that controls the withdrawal of the first feedback current and the second feedback current so that the DC voltage of the first input terminal and the DC voltage of the second input terminal are equal to the reference voltage.

11. The reference voltage circuit comprises an eleventh transistor and a twelfth transistor, The base of the 11th transistor is connected to the base of the first transistor, the base of the second transistor, and the base of the third transistor. The receiving circuit according to claim 10, wherein the collector of the 11th transistor is connected to the emitter of the 12th transistor.

12. A differential transimpedance amplifier that converts differential current to differential voltage, The circuit comprises a differential amplifier circuit for amplifying the differential voltage, The differential amplifier circuit comprises the constant current circuit, the current shunt circuit, the DC voltage node, the load circuit, the differential transimpedance amplifier circuit, the voltage regulator circuit, and the differential pair circuit. The differential pair circuit comprises a 13th transistor located at the first input node, a 14th transistor located at the second input node, and a resistive element connected between the emitter of the 13th transistor and the emitter of the 14th transistor. The receiving circuit according to any one of claims 1 to 5, wherein the base of the 13th transistor and the base of the 14th transistor receive the differential voltage.

13. A first photodetector that generates a first current signal in response to a first optical signal, A second photodetector that generates a second current signal in response to a second optical signal, A receiving circuit according to any one of claims 1 to 5, An optical receiving circuit equipped with this.

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