semiconductor device, memory device

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. This semiconductor device has a first conductor, a first oxide and a second oxide which are electrically connected to the first conductor and have an opening, a second conductor electrically connected to the first oxide, a third conductor disposed inside the opening in the first oxide, a fourth conductor electrically connected to the third conductor, a fifth conductor electrically connected to the second oxide, a sixth conductor disposed inside the opening in the second oxide, a seventh conductor electrically connected to the sixth conductor, and an eighth conductor electrically connected to the second conductor and the seventh conductor. The fourth conductor is provided in the same layer as the seventh conductor, and the direction in which the fourth conductor extends is the same as the direction in which the fifth conductor extends.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device. Another aspect of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product, method, or method of manufacture. Another aspect of the present invention relates to a process, machine, manufacture, or composition of matter. [Background technology]

[0004] With the increasing integration of memory devices, there is a growing demand for reducing the memory's footprint. However, miniaturizing memory devices using Si transistors is becoming increasingly difficult from both a technical and cost perspective.

[0005] In recent years, oxide semiconductors have attracted attention as semiconductor materials that can form transistors during the BEOL (Back End of Line) process for forming wiring in semiconductor devices. The technique of directly forming OS transistors (transistors with metal oxide in the channel formation region) on top of conventional Si transistors (transistors with silicon in the channel formation region) (also known as BEOL-Tr technology) makes it possible to construct 3D functional circuits while maintaining design rules. Therefore, it is expected to be a technology that can realize high-performance memory devices with low power consumption and low cost.

[0006] Furthermore, if the OS transistor can be oriented vertically, the design rule can be changed to 6F. 2 (F is the minimum machining dimension) to 4F 2 This makes it possible to minimize the size. For example, Patent Document 1 discloses a vertical transistor in which the side surface of an oxide semiconductor is covered with a word line via a gate insulating layer. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2021-108331 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] One aspect of the present invention aims to provide a transistor that can be miniaturized or highly integrated. One aspect of the present invention aims to provide a transistor having good electrical characteristics. One aspect of the present invention aims to provide a transistor with little variation in electrical characteristics. One aspect of the present invention aims to provide a transistor with a large on-current. One aspect of the present invention aims to provide a transistor with good reliability. One aspect of the present invention aims to provide a novel transistor. One aspect of the present invention aims to provide a semiconductor device or memory device having said transistor. One aspect of the present invention aims to provide a semiconductor device or memory device with low power consumption. One aspect of the present invention aims to provide a semiconductor device or memory device with a high operating speed.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0010] One aspect of the present invention is a semiconductor device comprising: a first conductor; a first oxide and a second oxide electrically connected to the first conductor and having an opening; a second conductor electrically connected to the first oxide; a first insulator disposed inside the opening of the first oxide; a third conductor on the first insulator; a fourth conductor electrically connected to the third conductor; a fifth conductor electrically connected to the second oxide; a second insulator disposed inside the opening of the second oxide; a sixth conductor on the second insulator; a seventh conductor electrically connected to the sixth conductor; and an eighth conductor electrically connected to the second and seventh conductors. The fourth conductor is provided on the same layer as the seventh conductor, and the direction in which the fourth conductor extends is the same as the direction in which the fifth conductor extends.

[0011] In the semiconductor device described above, it is preferable that the first conductor extends in a direction perpendicular to the direction in which the fourth conductor extends.

[0012] Furthermore, it is preferable that the semiconductor device further comprises a ninth conductor and a tenth conductor, wherein the ninth conductor is provided between the first oxide and the second conductor, and the side surface of the ninth conductor coincides with the side surface of the first oxide, and the tenth conductor is provided between the second oxide and the fifth conductor, and the side surface of the tenth conductor coincides with the side surface of the second oxide. It is even more preferable that the second conductor has a convex shape, and that the convex shape contacts the ninth conductor.

[0013] Furthermore, in the semiconductor device described above, it is preferable that the side surface of the first oxide has a tapered shape when viewed in cross-section.

[0014] One aspect of the present invention is a semiconductor device comprising a first conductor and a second conductor; a first oxide electrically connected to the first conductor and having an opening; a third conductor electrically connected to the first oxide; a first insulator disposed inside the opening of the first oxide; a fourth conductor on the first insulator; a fifth conductor electrically connected to the fourth conductor; a second oxide electrically connected to the second conductor and having an opening; a sixth conductor electrically connected to the second oxide; a second insulator disposed inside the opening of the second oxide; a seventh conductor on the second insulator; an eighth conductor electrically connected to the seventh conductor; and a ninth conductor electrically connected to the third and eighth conductors. The fifth conductor is provided on the same layer as the eighth conductor, and the direction in which the fifth conductor extends is the same as the direction in which the sixth conductor extends.

[0015] In the semiconductor device described above, it is preferable that the first conductor extends in a direction perpendicular to the direction in which the fifth conductor extends, and the second conductor extends in a direction perpendicular to the direction in which the sixth conductor extends.

[0016] Furthermore, the semiconductor device further comprises a tenth conductor and an eleventh conductor, wherein the tenth conductor is provided between the first oxide and the third conductor, and the side surface of the tenth conductor coincides with the side surface of the first oxide; and the eleventh conductor is provided between the second oxide and the sixth conductor, and the side surface of the eleventh conductor coincides with the side surface of the second oxide.

[0017] Furthermore, in the semiconductor device described above, it is preferable that the side surface of the first oxide has a tapered shape when viewed in cross-section.

[0018] One aspect of the present invention is a memory device comprising the semiconductor device described above and a layer including peripheral circuits, wherein the layer is located below the semiconductor device, and the peripheral circuits have the function of writing data to the semiconductor device and reading data from the semiconductor device. [Effects of the Invention]

[0019] According to one aspect of the present invention, a transistor that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a transistor having favorable electrical characteristics can be provided. According to one aspect of the present invention, a transistor with little variation in electrical characteristics can be provided. According to one aspect of the present invention, a transistor with large on-current can be provided. According to one aspect of the present invention, a transistor with high reliability can be provided. According to one aspect of the present invention, a novel transistor can be provided. According to one aspect of the present invention, a semiconductor device or a memory device including the transistor can be provided. According to one aspect of the present invention, a semiconductor device or a memory device with low power consumption can be provided. A semiconductor device or a memory device with high operating speed can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not need to have all of these effects. Effects other than these will be readily apparent from the description in the specification, drawings, claims, etc., and effects other than these can be extracted from the description in the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG. 1A is a perspective view illustrating a configuration example of a semiconductor device. FIG. 1B is a top view illustrating a configuration example of the semiconductor device. FIG. 2A is a top view illustrating a configuration example of a semiconductor device. FIGS. 2B and 2C are cross-sectional views illustrating configuration examples of the semiconductor device. FIG. 2D is a perspective view illustrating a configuration example of the semiconductor device. FIG. 2E is a cross-sectional view illustrating a configuration example of the semiconductor device. FIGS. 3A to 3F are top views illustrating configuration examples of a semiconductor device. FIGS. 4A to 4E are top views illustrating configuration examples of a semiconductor device. FIGS. 5A and 5B are cross-sectional views illustrating configuration examples of a semiconductor device. FIG. 5C is a perspective view illustrating a configuration example of the semiconductor device. FIG. 6A is a top view illustrating a configuration example of a semiconductor device. FIG. 6B is a cross-sectional view illustrating a configuration example of the semiconductor device. FIG. 6C is a perspective view illustrating a configuration example of the semiconductor device. Figures 7A and 7B are top views showing examples of semiconductor device configurations. Figure 8A is a top view showing an example of the configuration of a semiconductor device. Figure 8B is a cross-sectional view showing an example of the configuration of a semiconductor device. Figure 8C is a perspective view showing an example of the configuration of a semiconductor device. Figures 9A and 9B are top views showing examples of semiconductor device configurations. Figures 10A and 10B are cross-sectional views showing an example of a semiconductor device configuration. Figure 10C is a perspective view showing an example of a semiconductor device configuration. Figures 11A and 11B are cross-sectional views showing examples of semiconductor device configurations. Figures 12A to 12C are cross-sectional views showing examples of semiconductor device configurations. Figures 13A and 13D are top views showing examples of semiconductor device configurations. Figures 13B and 13C are cross-sectional views showing examples of semiconductor device configurations. Figures 14A and 14B are cross-sectional views showing examples of semiconductor device configurations. Figures 15A1 and 15B1 are top views showing examples of semiconductor device fabrication methods. Figures 15A2 and 15B2 are cross-sectional views showing examples of semiconductor device fabrication methods. Figures 16A1 and 16B1 are top views showing examples of semiconductor device fabrication methods. Figures 16A2 and 16B2 are cross-sectional views showing examples of semiconductor device fabrication methods. Figures 17A1 and 17B1 are top views showing examples of semiconductor device fabrication methods. Figures 17A2 and 17B2 are cross-sectional views showing examples of semiconductor device fabrication methods. Figures 18A1 and 18B1 are top views showing examples of semiconductor device fabrication methods. Figures 18A2 and 18B2 are cross-sectional views showing examples of semiconductor device fabrication methods. Figures 19A1 and 19B1 are top views showing examples of semiconductor device fabrication methods. Figures 19A2 and 19B2 are cross-sectional views showing examples of semiconductor device fabrication methods. Figures 20A1 and 20B1 are top views showing examples of semiconductor device fabrication methods. Figures 20A2 and 20B2 are cross-sectional views showing examples of semiconductor device fabrication methods. Figures 21A1 and 21B1 are top views showing examples of semiconductor device fabrication methods. Figures 21A2 and 21B2 are cross-sectional views showing examples of semiconductor device fabrication methods. Figures 22A1 and 22B1 are top views showing examples of semiconductor device fabrication methods. Figures 22A2 and 22B2 are cross-sectional views showing examples of semiconductor device fabrication methods. Figure 23A is a block diagram showing an example of a storage device configuration. Figure 23B is a perspective view showing an example of a storage device configuration. Figures 24A and 24B are circuit diagrams showing example configurations of memory cells. Figures 24C and 24D are perspective views showing example configurations of storage devices. Figure 25 is a cross-sectional view showing an example of a storage device configuration. Figure 26 is a cross-sectional view showing an example of a storage device configuration. Figures 27A to 27E illustrate an example of a storage device. Figures 28A to 28G are diagrams illustrating an example of an electronic device. [Modes for carrying out the invention]

[0022] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be construed as being limited to the following embodiments.

[0023] Furthermore, in drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, the scale is not necessarily limited. Also, the drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown. For example, in actual manufacturing processes, layers, resist masks, etc., may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. Additionally, in drawings, the same reference numerals may be used across different drawings for identical parts or parts with similar functions, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and no specific reference numeral may be assigned.

[0024] Furthermore, in perspective views or top views (also called "plan views"), for example, the description of some components may be omitted to facilitate understanding of the invention. Also, the description of some hidden lines may be omitted. Additionally, the drawings may omit notations such as hatching patterns. Furthermore, the hatching pattern in the top view and the hatching pattern in the cross-sectional view may differ for the same component.

[0025] Furthermore, the ordinal numbers used in this specification, such as "first," "second," etc., are for convenience only and do not indicate the order of processes or stacking. Therefore, for example, "first" can be replaced with "second" or "third," etc., as appropriate in the explanation. Also, the ordinal numbers described in this specification may not be the same as the ordinal numbers used to specify an aspect of the present invention.

[0026] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation.

[0027] For example, where it is explicitly stated in this specification that X and Y are connected, this specification discloses the cases in which X and Y are electrically connected, functionally connected, and directly connected. Therefore, it is not limited to predetermined connection relationships, such as those shown in the figures or text, but also includes connection relationships other than those shown in the figures or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0028] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter also referred to as the channel-forming region), and current can flow between the source and the drain through the channel-forming region. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0029] Furthermore, the functions of the source or drain may be reversed when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably in this specification.

[0030] Impurities in semiconductors refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause problems such as an increase in the defect level density of the semiconductor and a decrease in crystallinity. In the case of oxide semiconductors, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O (Also known as an oxygen vacancy) may form.

[0031] In this specification, "oxide nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content.

[0032] Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer."

[0033] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0034] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0035] Furthermore, in this specification, normally off means that when no potential is applied to the gate, or when the gate is given a ground potential, the drain current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. -20 A or less, 1 × 10 at 85℃ -18 A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A.

[0036] In this specification, when the same symbol is used for multiple elements, and especially when it is necessary to distinguish them, an identifying symbol such as "[n]" or "[m,n]" may be added to the symbol.

[0037] In this specification, "matching heights" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, in the manufacturing process of semiconductor devices, the surfaces of one or more layers may be exposed by planarization (typically CMP (Chemical Mechanical Polishing)). In this case, the surfaces subjected to CMP treatment have a configuration in which the heights from the reference surface are equal. However, the heights of multiple layers may differ depending on the processing apparatus, processing method, or material of the surface subjected to CMP treatment. In this specification, this case is also treated as "matching heights." For example, if there are two layers with different heights (here referred to as a first layer and a second layer) with respect to a reference surface, and the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less, this is also referred to as "matching heights."

[0038] In this specification, "ends coincide" means that, when viewed from above, at least a portion of the contours of the stacked layers overlap. This includes, for example, cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer; in this case, too, it is referred to as "ends coincide".

[0039] In general, it is difficult to clearly distinguish between "exact match" and "approximate match." Therefore, in this specification, "match" includes both exact matches and approximate matches.

[0040] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention and a method for manufacturing such a semiconductor device will be described with reference to the drawings.

[0041] One aspect of the present invention relates to a semiconductor device having a memory layer on a substrate. The memory layer has first and second transistors, which together constitute a memory cell. Since the semiconductor device according to one aspect of the present invention has a memory cell, it has the function of storing data. Therefore, the semiconductor device according to one aspect of the present invention can be called a memory device.

[0042] When a memory cell is constructed using the first and second transistors, one of the first and second transistors functions as a writing transistor, and the other functions as a reading transistor.

[0043] A semiconductor device according to one aspect of the present invention preferably has a transistor (OS transistor) having a metal oxide in the channel formation region. OS transistors have a small off-current. Therefore, by using an OS transistor in a semiconductor device that can function as a memory device, the stored contents can be retained for a long period of time. In other words, refresh operations are not required, or the frequency of refresh operations is extremely low, so the power consumption of the semiconductor device can be significantly reduced. Therefore, a low-power semiconductor device can be provided. Furthermore, because OS transistors have high frequency characteristics, the semiconductor device can read and write data at high speed. Therefore, a semiconductor device with a high operating speed can be provided.

[0044] The first and second transistors have a configuration in which current flows vertically, with one source and drain located at the bottom and the other at the top. In other words, the channel length direction of the first and second transistors is vertical. That is, the first and second transistors are vertical transistors. Compared to so-called horizontal transistors in which current flows horizontally, vertical transistors can be miniaturized. Therefore, by making the structure of the first and second transistors vertical, the transistors can be arranged at high density, enabling high integration in semiconductor devices. Also, compared to horizontal transistors, vertical transistors can have a wider channel width per unit area. Therefore, the current density flowing through the transistors increases, the on-current of the transistors can be increased, and the frequency characteristics can be improved.

[0045] Furthermore, OS transistors are highly resistant to short-channel effects. Therefore, compared to transistors with silicon in the channel formation region (also called Si transistors), OS transistors are less susceptible to substrate stray effects even in a vertical structure, and the channel length can be easily shortened even with a thick gate insulating film. In other words, the gate leakage current can be reduced, which can improve the retention characteristics of memory devices.

[0046] Short-channel effects refer to the degradation of electrical characteristics that becomes apparent with the miniaturization of transistors (reduction of channel length). Short-channel effects include drain-induced barrier reduction, electron velocity saturation, and hot carrier degradation. Specific examples of short-channel effects include threshold voltage reduction, subthreshold swing value increase, and leakage current increase. Here, subthreshold swing value refers to the change in gate voltage in the subthreshold region where the drain current changes by one order of magnitude while the drain voltage remains constant.

[0047] Furthermore, in a semiconductor device according to one embodiment of the present invention, the vertical structure transistor can control the channel length by the thickness of the oxide semiconductor film, thus reducing variations in channel length due to manufacturing processes compared to a horizontal structure transistor. In other words, variations in the current density flowing through the transistor can be suppressed. Consequently, the frequency characteristics can be improved.

[0048] <Example of semiconductor device configuration> The following describes an example of the configuration of a semiconductor device according to one aspect of the present invention. Note that the components of the semiconductor device in this embodiment may each have a single-layer structure or a multilayer structure.

[0049] Figures 1A and 1B are a perspective view and a top view, respectively, showing an example configuration of a semiconductor device according to one embodiment of the present invention. Figure 1A is a perspective view of the semiconductor device 10. Figure 1B is a top view of the semiconductor device 10.

[0050] In the drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X-axis, and unless explicitly stated, forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are directions that intersect each other. More specifically, the X, Y, and Z directions are directions that are orthogonal to each other. In this specification, one of the X, Y, or Z directions may be referred to as the "first direction" or "first direction." Another may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0051] The semiconductor device 10 has multiple memory cells 100. Figure 1A shows an example in which the semiconductor device 10 has multiple memory cells 100 arranged in a matrix of m rows and n columns (where m and n are each independent integers of 2 or more). By arranging the memory cells 100 in a matrix, a memory cell array can be constructed.

[0052] Rows and columns extend in mutually orthogonal directions. In this embodiment, the X direction is defined as "rows" and the Y direction as "columns". Alternatively, the X direction may be defined as "columns" and the Y direction as "rows".

[0053] In Figure 1A, memory cell 100 in the first row and first column is shown as memory cell 100[1,1], memory cell 100 in the second row and first column is shown as memory cell 100[2,1], and memory cell 100 in the first row and second column is shown as memory cell 100[1,2]. Although not shown in Figure 1A, memory cell 100 in the mth row and nth column is denoted as memory cell 100[m,n].

[0054] In this embodiment, an arbitrary row may be referred to as row i, and an arbitrary column as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. In this embodiment, the memory cell 100 in row i and column j is referred to as memory cell 100[i,j]. In this embodiment, when "i+α" (where α is a positive or negative integer) is used, "i+α" is not less than 1 and not greater than m. Similarly, when "j+α" is used, "j+α" is not less than 1 and not greater than n.

[0055] Furthermore, the semiconductor device 10 has m conductors 262a extending in the row direction, m conductors 246b extending in the row direction, and n conductors 244 extending in the column direction. In this embodiment, the i-th conductor (i-th row) is denoted as conductor 262a[i], and the i-th conductor (i-th row) is denoted as conductor 246b[i]. Similarly, the j-th conductor (j-th column) is denoted as conductor 244[j].

[0056] Memory cell 100[i,j] is electrically connected to conductors 262a[i], 246b[i], and 244[j], respectively. In other words, conductor 262a[i] is electrically connected to n memory cells (memory cells 100[i,1] to 100[i,n]), conductor 246b[i] is electrically connected to n memory cells (memory cells 100[i,1] to 100[i,n]), and conductor 244[j] is electrically connected to m memory cells (memory cells 100[1,j] to 100[m,j]).

[0057] Hereafter, conductor 262a refers to one or more of conductors 262a[1] through conductor 262a[m], and conductor 246b refers to one or more of conductors 246b[1] through conductor 246b[m]. Similarly, conductor 244 refers to one or more of conductors 244[1] through conductor 244[n]. Similarly, memory cell 100 refers to one or more of memory cell 100[1,1] through memory cell 100[m,n].

[0058] Conductors 262a, 246b, and 244 function as wiring.

[0059] [Memory cell 100] Figures 2A to 2E are a top view, a cross-sectional view, and a perspective view illustrating an example of the configuration of a memory cell in a semiconductor device according to one embodiment of the present invention. Figure 2A is a top view of the memory cell 100. Figure 2B is a cross-sectional view of the memory cell 100, and is also a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 2A. Figure 2C is a cross-sectional view of the memory cell 100, and is also a cross-sectional view of the area indicated by the dashed line B1-B2 in Figure 2A. Figure 2D is a perspective view of the memory cell 100.

[0060] Since memory cells 100[1,1] through 100[m,n] have the same configuration, they are referred to as memory cell 100 in Figure 2, etc., and no identification code is added.

[0061] The memory cell 100 shown in Figure 2 has a transistor 200a and a transistor 200b. Note that transistor 200a is provided on the same layer as transistor 200b. Compared to a configuration where transistors 200a and 200b are provided on different layers, providing transistors 200a and 200b on the same layer allows for simultaneous fabrication of transistors 200a and 200b, thereby shortening the semiconductor device manufacturing process.

[0062] In the following sections, when describing common features of components distinguished by letters, the letters may be omitted and a code may be used. For example, when describing features common to transistors 200a and 200b, it may be written as transistor 200.

[0063] The transistor 200 comprises an oxide 230, a conductor 242a on the oxide 230, an insulator 250, and a conductor 260 on the insulator 250. As shown in Figures 2A to 2C, the side surface of the conductor 242a coincides with the side surface of the oxide 230. The oxide 230 and the conductor 242a have a cylindrical shape. The cylindrical shape of the oxide 230 and the conductor 242a extends in the Z direction. The oxide 230 and the conductor 242a also have openings. These openings may be referred to as openings, hollows, or hollow sections. The openings of the oxide 230 and the conductor 242a overlap. The top surface shape of the oxide 230 and the conductor 242a is a hollow circular shape. In other words, the oxide 230 and the conductor 242a have a cylindrical shape with a hollow portion. A cylindrical shape with a hollow portion is sometimes referred to as a hollow cylindrical shape.

[0064] In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0065] Figure 2A shows a configuration in which the top surfaces of the oxide 230 and the conductor 242a have a hollow circular shape, but the present invention is not limited to this. For example, the top surfaces of the oxide 230 and the conductor 242a may have a hollow elliptical shape, a hollow polygonal shape, or a hollow polygonal shape with rounded corners. Here, a polygonal shape refers to a triangle, quadrilateral, pentagon, hexagon, etc.

[0066] The insulator 250 and the conductor 260 are arranged inside the openings of the oxide 230 and the conductor 242a. The insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260.

[0067] Furthermore, the memory cell 100 has a conductor 244. The oxide 230 is electrically connected to the conductor 244. In the configuration shown in Figure 2B, the oxide 230 has a region that is in contact with at least a portion of the upper surface of the conductor 244.

[0068] The conductor 260 functions as the gate electrode of the transistor 200. The insulator 250 functions as the gate insulator of the transistor 200. Note that the gate insulator may also be called the gate insulating layer or gate insulating film. The conductor 244 has a region that functions as one of the source electrode and drain electrode of the transistor 200. The conductor 242a functions as the other of the source electrode and drain electrode of the transistor 200. At least a portion of the region of the oxide 230 that overlaps with the conductor 260 functions as the channel forming region of the transistor 200. Note that the region of the oxide 230 that overlaps with the conductor 260 can be rephrased as the region of the oxide 230 that faces the conductor 260. Alternatively, the region of the oxide 230 that overlaps with the conductor 260 can be rephrased as the region of the oxide 230 that faces the conductor 260 via the insulator 250. In other words, at least a portion of the region of the oxide 230 that faces the conductor 260 functions as the channel forming region of the transistor 200.

[0069] Transistor 200 is a so-called vertical transistor, in which current flows vertically because one of its source and drain electrodes is located below the channel formation region and the other is located above the channel formation region. Furthermore, transistor 200 has a structure in which the channel formation region surrounds the gate electrode. Therefore, transistor 200 can be described as a CAA (Channel-All-Around) structure transistor.

[0070] The channel length of transistor 200 is defined as the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap in a cross-sectional view, the length of the region where the semiconductor and the gate electrode face each other, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. In other words, the channel length of transistor 200 corresponds to the film thickness of oxide 230. Therefore, since the channel length of transistor 200 can be adjusted by the film thickness of oxide 230, a transistor 200 with a shorter channel length can be fabricated by reducing the film thickness of oxide 230. By forming the oxide 230 using a film formation method that allows for the formation of thin films, the channel length of transistor 200 can be set to, for example, 30 nm or less, 20 nm or less, 15 nm or less, 10 nm or less, 8 nm or less, or 5 nm or less. In other words, it is preferable to form the oxide 230 so that its film thickness is, for example, 3 nm or more and 30 nm or less. Because OS transistors have an extremely low off-current, the off-current of transistor 200 can be kept low even with the channel length described above. Figure 2B shows the channel length of transistor 200 with a dashed-dotted double arrow.

[0071] On the other hand, when operating a transistor in the saturation region, the channel length of the transistor may be increased to improve the electrical characteristics in the saturation region. Since transistor 200 is a vertical transistor, the area occupied by transistor 200 when viewed from above does not depend on the thickness of the oxide 230. Therefore, the thickness of the oxide 230 corresponding to the channel length may be thick. For example, the thickness of the oxide 230 may be greater than 30 nm and less than or equal to 100 nm.

[0072] Based on the above, the film thickness of oxide 230 is set to 3 nm or more and 100 nm or less, preferably 3 nm or more and 30 nm or less, more preferably 5 nm or more and 30 nm or less, and even more preferably 5 nm or more and 15 nm or less.

[0073] Furthermore, the channel width of transistor 200 is defined as the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, the length of the region where the semiconductor and the gate electrode face each other, or the length of the channel formation region perpendicular to the channel length direction in the channel formation region, as viewed from above. In other words, the channel width of transistor 200 corresponds to the circumference of the hollow area of ​​oxide 230. Note that the channel width is not necessarily the same in all regions of a single transistor. That is, the channel width of a single transistor may not be fixed to a single value. For example, as will be described later, this may occur when the side surface of the hollow area of ​​oxide 230 has a tapered shape in a cross-sectional view of the transistor. Therefore, in this specification, the channel width is defined as one value, the maximum value, the minimum value, or the average value in the channel formation region. Figure 2E shows the channel width of transistor 200 with a dashed double arrow. Figure 2E is a cross-sectional view in the XY plane including oxide 230.

[0074] The channel length and channel width can be determined, for example, by analyzing cross-sectional TEM images.

[0075] The memory cell 100 includes conductors 262a and 262c, conductors 246b and 246c, and conductor 256. Conductor 262a is provided in the same layer as conductor 262c. Conductor 246b is provided in the same layer as conductor 246c.

[0076] The conductor 262a is electrically connected to the conductor 260 of the transistor 200a. In the configuration shown in Figure 2B, the conductor 262a has a region that is in contact with the upper surface of the conductor 260 of the transistor 200a.

[0077] The conductor 262c is electrically connected to the conductor 260 of the transistor 200b. In the configuration shown in Figure 2B, the conductor 262c has a region that is in contact with the upper surface of the conductor 260 of the transistor 200b.

[0078] The conductor 246b is electrically connected to the conductor 242a of the transistor 200b. Furthermore, the conductor 246b is electrically connected to the oxide 230 of the transistor 200b via the conductor 242a of the transistor 200b. In other words, the conductor 242a of the transistor 200b is provided between the oxide 230 of the transistor 200b and the conductor 246b. In the configuration shown in Figure 2C, the conductor 246b has a region that is in contact with at least a portion of the upper surface of the conductor 242a of the transistor 200b.

[0079] The conductor 246c is electrically connected to the conductor 242a of the transistor 200a. Furthermore, the conductor 246c is electrically connected to the oxide 230 of the transistor 200a via the conductor 242a of the transistor 200a. In other words, the conductor 242a of the transistor 200a is provided between the oxide 230 of the transistor 200a and the conductor 246c. In the configuration shown in Figure 2B, the conductor 246c has a region that is in contact with at least a portion of the upper surface of the conductor 242a of the transistor 200a.

[0080] Conductor 256 is electrically connected to conductors 262c and 246c. In other words, conductor 246c is electrically connected to conductor 262c via conductor 256.

[0081] As shown in Figure 2A, the conductors 262a and 246b are provided extending in the X direction. That is, the direction in which conductor 262a extends is the same as the direction in which conductor 246b extends. In addition, the conductor 244 is provided extending in the Y direction. That is, the conductor 244 extends in a direction perpendicular to the direction in which conductor 262a extends. Furthermore, the conductor 244 extends in a direction perpendicular to the direction in which conductor 246b extends.

[0082] As described above, transistor 200 is a vertical transistor. Vertical transistors can be formed at cross points where the minimum pitch wiring intersects. Specifically, transistor 200a is formed between the regions where conductor 244 and conductor 262a intersect, and transistor 200b is formed between the regions where conductor 244 and conductor 246b intersect. Therefore, miniaturization or high integration of semiconductor devices can be achieved.

[0083] In transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor in the oxide 230 including the channel formation region.

[0084] Furthermore, the band gap of the metal oxide that functions as a semiconductor is preferably 2.0 eV or higher, and more preferably 2.5 eV or higher. By using a metal oxide with a large band gap, the off-current of the transistor can be reduced.

[0085] As oxide 230, it is preferable to use a metal oxide such as indium oxide, gallium oxide, and zinc oxide. Alternatively, as oxide 230, it is preferable to use a metal oxide having two or three elements selected from indium, element M, and zinc. Element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, antimony, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, it is preferable that element M is one or more selected from aluminum, gallium, yttrium, and tin. A metal oxide having indium, element M, and zinc may be referred to as In-M-Zn oxide.

[0086] Specifically, as oxide 230, metal oxides with compositions of In:M:Zn=4:2:3 [atomic ratio] or nearby, In:M:Zn=1:1:1 [atomic ratio] or nearby, In:M:Zn=1:1:1.2 [atomic ratio] or nearby, or In:M:Zn=1:1:2 [atomic ratio] or nearby can be used. Note that nearby compositions include a range of ±30% of the desired atomic ratio.

[0087] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also written as IGZO) as oxide 230. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also written as IAZO) may be used as oxide 230. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also written as IAGZO, IGAZO, or AGIZO) may be used as oxide 230.

[0088] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may be called metal oxynitrides.

[0089] When silicon is used in the channel formation region of a vertical transistor, the substrate levitation effect occurs, making the electrical properties of the vertical transistor unstable. On the other hand, metal oxides such as IGZO, IAZO, and IAGZO have a large effective hole mass. Therefore, by using these metal oxides in the channel formation region, the accumulation of holes in the channel formation region can be suppressed, and a vertical transistor with little or no effect from the substrate levitation effect can be fabricated. In other words, by using the above metal oxides for oxide 230, stable electrical properties can be imparted to the transistor 200. Therefore, a transistor with good electrical properties and a semiconductor device having such a transistor can be provided. Furthermore, a transistor with less variation in electrical properties and a semiconductor device having such a transistor can be provided.

[0090] For oxide 230, it is preferable to use a crystalline oxide semiconductor. Examples of crystalline oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductor, and single-crystal oxide semiconductor. For oxide 230, it is preferable to use CAAC-OS or nc-OS, and it is particularly preferable to use CAAC-OS.

[0091] CAAC-OS is a metal oxide with a highly crystalline, dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization of the metal oxide (e.g., between 400°C and 600°C), the CAAC-OS can be made to have an even more crystalline and dense structure. By increasing the density of CAAC-OS in this way, the diffusion of impurities or oxygen within the CAAC-OS can be further reduced.

[0092] Furthermore, because it is difficult to identify clear grain boundaries in CAAC-OS, a decrease in electron mobility due to grain boundary issues is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are highly heat-resistant and reliable.

[0093] Furthermore, by using a crystalline oxide such as CAAC-OS as oxide 230, the extraction of oxygen from oxide 230 by conductors 244 and 242a can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from oxide 230 is suppressed, making the transistor stable against high temperatures (so-called thermal budget) in the manufacturing process. In addition, a decrease in the conductivity of conductors 244 and 242a can be suppressed.

[0094] nc-OS exhibits periodicity in its atomic arrangement in minute regions (for example, regions between 1 nm and 10 nm, particularly regions between 1 nm and 3 nm). In other words, nc-OS contains minute crystals (also called nanocrystals). Furthermore, because nc-OS does not exhibit regularity in crystal orientation between different nanocrystals, the entire film is free from orientation. That is, when nc-OS is used as oxide 230, the film properties of oxide 230 remain constant regardless of the direction of carriers flowing through the oxide 230, thus stabilizing the electrical properties of the transistor.

[0095] Furthermore, oxide semiconductors can take on diverse structures, each possessing different properties. Oxide 230 may consist of two or more of the following: CAAC-OS, nc-OS, pseudo-amorphous oxide semiconductor (a-like OS), amorphous oxide semiconductor, polycrystalline oxide semiconductor, and CAC-OS (cloud-aligned composite oxide semiconductor).

[0096] Furthermore, when structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the peak indicating c-axis orientation (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS. In addition, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. Note that two spots are observed at point-symmetric positions with respect to the spot of the incident electron beam that passed through the sample (also called the direct spot).

[0097] Furthermore, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter equivalent to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0098] The oxide 230 can be rephrased as a semiconductor layer containing the channel formation region of the transistor 200. Note that the material applicable to this semiconductor layer is not limited to metal oxides (oxide semiconductors) that function as semiconductors. For example, single-crystal silicon, polycrystalline silicon, or amorphous silicon may be used as the semiconductor layer, or low-temperature polysilicon (LTPS) may be used.

[0099] Alternatively, a transition metal chalcogenide that functions as a semiconductor may be used as the semiconductor layer. For example, molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc., may be used.

[0100] The oxide 230 can be deposited using sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or atomic layer deposition (ALD). Sputtering is particularly preferred for depositing the oxide 230. Sputtering allows for the formation of crystalline metal oxides. Furthermore, because sputtering is a film deposition method capable of forming thin films, it is suitable for depositing oxide 230.

[0101] In a so-called gate-all-around transistor, where the sides of a semiconductor-functioning metal oxide are covered by a word line via a gate insulating layer, the metal oxide is provided inside an opening formed in the word line or gate insulating layer. To miniaturize such a transistor, the inner wall of the opening needs to be as perpendicular as possible to the substrate surface. In this case, high step coverage is required during the deposition of the metal oxide, which limits the flexibility of the deposition method for the metal oxide.

[0102] On the other hand, the transistor 200 is fabricated by forming an opening in a laminate of oxide 230 and conductor 242a, and forming an insulator 250 and conductor 260 inside the opening. In this case, the oxide 230 can be formed on the conductor 244, and high step coverage is not required when depositing the oxide 230. Therefore, the method for depositing the oxide 230 can be freely applied. For example, sputtering can be used to deposit the oxide 230, and a crystalline metal oxide can be formed.

[0103] Furthermore, to form openings or recesses, it is advisable to use double patterning techniques such as LELE (Litho-Etch-Litho-Etch) and SADP (Self-Aligned Double Patterning), quadruple patterning techniques such as SAQP (Self-Aligned Quadruple Patterning), and multi-patterning techniques such as octave patterning. By using multi-patterning techniques, it is possible to form fine openings or fine recesses.

[0104] Alternatively, the openings in the resist pattern may be reduced by using a shrinking agent on the resist pattern. For example, after applying the shrinking agent to the resist surface, a heat treatment is performed. This causes the resist to react with the shrinking agent, forming a reaction layer on the surface of the resist. At this time, the reaction layer is formed on the side of the openings in the resist pattern, thus reducing the size of the openings. By using a resist pattern with reduced openings, fine openings or fine recesses can be formed. The shrinking agent described above is sometimes called a pattern shrinking agent or a hole shrinking agent.

[0105] Alternatively, fine patterns may be directly formed by exposure using EUV (Extreme Ultraviolet) light or the like.

[0106] Alternatively, you can combine the above methods to perform patterning.

[0107] Based on the above, an oxide semiconductor with little or no substrate levitation effect is deposited by sputtering, and then a cylindrical channel with a hollow portion is formed using multi-patterning technology such as SAQP. By providing a vertical transistor with a gate electrode in the hollow portion, a transistor that can be miniaturized or highly integrated can be provided. Using this transistor, a memory cell with a minimum processing dimension (F) of, for example, 15 nm or less can be realized. Here, the minimum processing dimension (F) is, for example, the width of the conductor 244 in the X direction, the width of the conductor 262a in the Y direction, or the width of the conductor 246b in the Y direction.

[0108] As the conductor 242a, it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0109] Furthermore, hydrogen contained in oxide 230 and other materials may diffuse into the conductor 242a. In particular, by using a tantalum-containing nitride for the conductor 242a, hydrogen contained in oxide 230 and other materials diffuses easily into the conductor 242a, and the diffused hydrogen may combine with the nitrogen contained in the conductor 242a. In other words, hydrogen contained in oxide 230 and other materials may be absorbed by the conductor 242a.

[0110] Furthermore, since the conductor 242a has a region in contact with the oxide 230, it is preferable to use a conductive material containing oxygen. By using a conductive material containing oxygen as the conductor 242a, conductivity can be maintained even if the conductor 242a absorbs oxygen. Also, even when an insulator containing oxygen is used as the insulator 250, the conductor 242a can maintain conductivity, which is also preferable.

[0111] Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also known as ITO), indium tin oxide containing titanium oxide, silicon-added indium tin oxide (also known as ITSO), indium zinc oxide (also known as IZO®), and indium zinc oxide containing tungsten oxide. Furthermore, examples of oxygen-containing conductive materials include oxides containing ruthenium oxide, strontium, and ruthenium, or oxides containing lanthanum and nickel. In this specification, conductive films formed using oxygen-containing conductive materials are sometimes referred to as oxide conductive films.

[0112] It is preferable that the insulator 250 be formed using an insulator that has the function of suppressing oxygen diffusion. With this configuration, the diffusion of oxygen contained in the oxide 230 to the conductor 260 can be suppressed. In other words, the formation of oxygen vacancies in the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen contained in the oxide 230 can be suppressed. Therefore, the electrical characteristics of the transistor 200 can be improved and its reliability can be enhanced.

[0113] As the insulator 250, it is preferable to use an insulator containing an oxide of either or both aluminum and hafnium. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or an oxide containing hafnium and silicon (hafnium silicate) can be used.

[0114] Furthermore, the insulator 250 may be made of a high-dielectric constant (high-k) material. By using a high-dielectric constant material as the insulator 250, it becomes possible to reduce the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator. Therefore, the dielectric breakdown voltage of the insulator 250 can be increased.

[0115] Examples of high dielectric constant materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxide nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxide nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0116] Furthermore, the insulator 250 may be silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies.

[0117] Furthermore, the insulator 250 extends in the Z direction. Preferably, the upper surface of the insulator 250 of the transistor 200a is located above the upper surface of the conductor 246c. This prevents contact between the conductor 246c and the conductor 262a, thereby preventing leakage current and short circuits between the conductor 246c and the conductor 262a. If an insulator is provided between the conductor 246c and the conductor 260 of the transistor 200a, and the upper surface of the insulator is located above the upper surface of the conductor 246c, the upper surface of the insulator 250 of the transistor 200a may be located below the upper surface of the conductor 246c.

[0118] Similarly, it is preferable that the upper surface of the insulator 250 of transistor 200b is located above the upper surface of the conductor 246b. This prevents contact between the conductor 246b and the conductor 262c, thereby preventing leakage current and short circuits between the conductor 246b and the conductor 262c. If an insulator is provided between the conductor 246b and the conductor 260 of transistor 200b, and the upper surface of the insulator is located above the upper surface of the conductor 246b, the upper surface of the insulator 250 of transistor 200b may be located below the upper surface of the conductor 246b.

[0119] Figure 2B shows a configuration in which the insulator 250 is a single layer, but the present invention is not limited to this, and a laminated structure of two or more layers may be used. For example, when the insulator 250 is a two-layer laminated structure, the insulator provided on the oxide 230 side may be formed using an insulator that has the function of suppressing oxygen diffusion, and the insulator provided on the conductor 260 side may be formed using a high dielectric constant material.

[0120] As the conductor 260, it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or ruthenium nitride. Alternatively, for example, ruthenium oxide, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are conductive materials that are resistant to oxidation, or materials that maintain conductivity even when absorbing oxygen, and are therefore suitable when an insulating material containing oxygen is used as the insulator 250 that comes into contact with the conductor 260.

[0121] Furthermore, it is preferable to use a conductive material for the conductor 260 that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules) may be used. Examples of conductive materials that have the function of suppressing the diffusion of oxygen include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0122] Furthermore, because the conductor 260 has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260 by the oxygen contained in the insulator 250, which would reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0123] It is preferable that conductors 246b and 246c be conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, each of conductors 246b and 246c may also be in a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material.

[0124] It is preferable that the conductors 262a and 262c be conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, each of the conductors 262a and 262c may also have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material.

[0125] Here, Figure 3A shows a top view of the same configuration as in Figure 2A, including the conductor 242a, insulator 250, conductor 260, conductor 246b, and conductor 246c. For ease of understanding, the outlines of conductor 244 and conductor 262a are shown as dotted lines in Figure 3A. Furthermore, modified configurations of the one shown in Figure 3A are shown in Figures 3B to 3F. Figures 3A to 3F also serve as top views illustrating examples of semiconductor device configurations. In Figures 3D and 3F, the outline of conductor 262c is shown as a dotted line.

[0126] Region 264b shown in Figures 3A to 3F is the region where the conductor 246b and the conductor 242a located below the conductor 246b overlap. Region 264c shown in Figures 3A to 3F is the region where the conductor 246c and the conductor 242a located below the conductor 246c overlap.

[0127] As shown in Figure 3A, the conductor 246b has an opening. An insulator 250 and a conductor 260 are provided within this opening. In a top view, as shown in Figure 3A, if the width of the conductor 246b in the Y direction is equal to the outer diameter of the insulator 250, or as shown in Figure 3B, if the width of the conductor 246b in the Y direction is smaller than the outer diameter of the insulator 250, the conductor 246b is divided by the insulator 250. However, the divided conductors 246b are electrically connected via a conductor 242a provided below the conductor 246b. Therefore, since the conductor 246b extends in the X direction via the conductor 242a provided below the conductor 246b, the conductor 246b can be considered to extend in the X direction.

[0128] On the other hand, in a top view, as shown in Figure 3C, if the width of the conductor 246b in the Y direction is greater than the outer diameter of the insulator 250, the conductor 246b extends in the X direction as a continuous conductor.

[0129] Figures 3A to 3C show a configuration in which an insulator 250 and a conductor 260 are provided in an opening in the conductor 246b, but the present invention is not limited to this. The opening in the conductor 246b may be provided with a conductor 260 and an insulator covering the side surface of the conductor 260. The insulator may consist only of the insulator 250, or it may consist of the insulator 250 and an insulator provided on the insulator 250.

[0130] Furthermore, the conductor 246b only needs to extend in the X direction via the conductor 242a provided below the conductor 246b, and does not need to have the same contour as the outer circumference of the insulator 250 in a top view. For example, as shown in Figure 3D, in a top view, the end of the conductor 246b in the region overlapping with the conductor 242a provided below the conductor 246b may be straight. Figure 3D shows a configuration in which the conductor 246b does not overlap with the conductor 262c.

[0131] Furthermore, the shape of the region of conductor 246c that overlaps with conductor 242a of transistor 200a may have the same shape as conductor 246b.

[0132] In Figure 3A, the conductor 246c is provided on both the A1 and A2 sides with respect to the center of the conductor 260 of transistor 200a, but the present invention is not limited to this configuration. The conductor 246c only needs to be electrically connected to the conductor 242a of transistor 200a. For example, as shown in Figure 3E, the conductor 246c may be provided only on the A2 side with respect to the center of the conductor 260 of transistor 200a.

[0133] Similarly, in the configuration shown in Figure 3D, the conductor 246c may be provided only on the A2 side with respect to the center of the conductor 260 of the transistor 200a (see Figure 3F).

[0134] As shown in Figure 2A, in a top view, the conductor 244 coincides with the center of the hollow cylindrical shape of the oxide 230. However, the conductor 244 only needs to be in contact with at least a portion of the oxide 230 and does not need to coincide with the center of the hollow cylindrical shape of the oxide 230. For example, as shown in Figure 4A, in a top view, the conductor 244 may be positioned offset in the X direction from the center of the hollow cylindrical shape of the oxide 230. Figure 4A is a top view of the memory cell 100.

[0135] Figure 2A shows a configuration in which, in a top view, a line bisecting the width of the conductor 262a in the Y direction coincides with the center of the conductor 260 of the transistor 200a. Note that the conductor 262a only needs to be in contact with at least a portion of the conductor 260 of the transistor 200a. For example, as shown in Figure 4B, in a top view, the conductor 262a may be positioned such that the line bisecting the width of the conductor 262a in the Y direction (dotted line B3-B4) is offset in the Y direction from the center of the conductor 260. Note that Figure 4B is a top view of the memory cell 100.

[0136] Figure 2A shows a configuration in which, in a top view, the line that bisects the width of the conductor 246b in the Y direction coincides with the center of the conductor 260 of the transistor 200b. Note that the conductor 246b only needs to be in contact with at least a portion of the conductor 260 of the transistor 200b. For example, as shown in Figure 4C, in a top view, the conductor 246b may be positioned such that the line that bisects the width of the conductor 246b in the Y direction (dotted line B5-B6) is offset in the Y direction from the center of the conductor 260. Note that Figure 4C is a top view of the memory cell 100.

[0137] Furthermore, considering the configuration shown in Figure 4B, the center of the conductor 260 of transistor 200a may be located at a position shifted in the Y direction from the line that bisects the Y-direction width of conductor 262a. Also, considering the configuration shown in Figure 4C, the center of the conductor 260 of transistor 200b may be located at a position shifted in the Y direction from the line that bisects the Y-direction width of conductor 246b. For example, as shown in Figure 4D, the center of the conductor 260 of transistor 200b may be located on the A1 side of the line that bisects the Y-direction width of conductor 246b (dotted line B5-B6), and the center of the conductor 260 adjacent to the conductor 260 in the X direction may be located on the A2 side of the dashed line B5-B6. By adopting this configuration, the distance between transistor 200b and the transistor 200b adjacent to it in the X direction can be increased without changing the distance between conductors 244.

[0138] Furthermore, if transistor 200b is arranged as shown in Figure 4D, the distance between transistor 200b and transistor 200a in memory cell 100 adjacent to the memory cell 100 having transistor 200b in the Y direction may become small. Therefore, it is preferable to arrange transistor 200a in the same way as transistor 200b. For example, as shown in Figure 4D, the center of the conductor 260 of transistor 200a may be located on the A1 side of the line (dotted-dotted line B3-B4) that bisects the width of the conductor 262a in the Y direction, and the center of the conductor 260 adjacent to the conductor 260 in the X direction may be located on the A2 side of the dashed-dotted line B3-B4. This configuration can suppress the decrease in the distance between transistor 200a and transistor 200b.

[0139] By adopting the configuration shown in Figure 4D, the distance between transistors 200a, the distance between transistors 200b, and the distance between wirings can be reduced, making it possible to provide a semiconductor device with a high degree of memory cell integration.

[0140] Furthermore, by adopting the configuration shown in Figure 4D, the hollow circumference of the oxide 230 can be increased while maintaining the spacing between the conductors 246b and 262a. This increases the channel width of the transistor and increases the on-current. For example, as shown in Figure 4E, the hollow circumference of the oxide 230 of transistor 200b is made larger than the hollow circumference of the oxide 230 of transistor 200a. This configuration increases the channel width of transistor 200b. Therefore, the on-current of transistor 200b, which functions as a readout transistor, can be increased, and a semiconductor device with a fast readout speed can be provided.

[0141] Figures 2B and 2C show a configuration in which the lower surfaces of conductors 246b and 246c are flat, but the present invention is not limited to this. Conductors 246b and 246c only need to be in contact with at least a portion of the upper surface of conductor 242a of transistors 200b and 200a, respectively, and conductors 246b and 246c may have one or both of a convex portion and a concave portion.

[0142] For example, as shown in Figure 5A, the conductor 246c may have a convex-shaped portion 246c1. The convex-shaped portion 246c1 is provided in the region where the conductor 246c and the conductor 242a of the transistor 200a overlap. In this case, the upper surface shape of the convex-shaped portion 246c1 is the same as the shape of region 264c shown in any of Figures 3A to 3F. Also, the convex-shaped portion 246c1 is in contact with the conductor 242a of the transistor 200a.

[0143] Furthermore, as shown in Figure 5B, for example, the conductor 246b may have a convex-shaped portion 246b1. The convex-shaped portion 246b1 is provided in the region where the conductor 246b and the conductor 242a of the transistor 200b overlap. In this case, the upper surface shape of the convex-shaped portion 246b1 is the same as the shape of region 264b shown in any of Figures 3A to 3F. The convex-shaped portion 246b1 is in contact with the conductor 242a of the transistor 200a.

[0144] The method for forming the conductors 246b and 246c having a convex shape will be described later.

[0145] Figure 5C shows a perspective view of the memory cell 100 when the conductors 246b and 246c have a convex shape, and the upper surface shapes of the conductors 246b and 246c are as shown in Figure 3D.

[0146] [Memory cell 100A] Figures 6A to 6C show examples of configurations different from the memory cell 100 described above. In the memory cells shown below, structures having the same function as the structures constituting the memory cell 100 described above are denoted by the same reference numerals. Furthermore, the following explanation will mainly focus on the parts that differ from the memory cell 100 described above, and the explanation of overlapping parts will be omitted.

[0147] Figure 6A is a top view of memory cell 100A, Figure 6B is a cross-sectional view of memory cell 100A, and Figure 6C is a perspective view of memory cell 100A. Memory cell 100A differs from memory cell 100 shown in Figure 2 in that it has conductors 244a and 244b instead of conductor 244.

[0148] Conductor 244a is electrically connected to the oxide 230 of transistor 200a, and conductor 244b is electrically connected to the oxide 230 of transistor 200b. In Figure 6, conductors 244a and 244b are provided extending in the Y direction. That is, conductor 244a extends in a direction perpendicular to the direction in which conductor 262a extends. Conductor 244b extends in a direction perpendicular to the direction in which conductor 246b extends.

[0149] Conductor 244a functions as one of the source and drain electrodes of transistor 200a, and also functions as wiring. Conductor 244b functions as one of the source and drain electrodes of transistor 200b, and also functions as wiring.

[0150] The above configuration allows for the independence of the write bit line and read bit line of the memory cell. The configuration of the memory cell will be described in Embodiment 2.

[0151] Figure 7A is a top view of a memory cell array in which the memory cells 100A shown in Figure 6 are arranged in a matrix. In Figure 7A, conductors 262a and 246b extend in the X direction, conductor 244 extends in the Y direction, and the line segment connecting transistors 200a and 200b of the memory cell 100A is tilted in the X direction.

[0152] As shown in Figure 7A, one conductor 244 is electrically connected to the first memory cell and the second memory cell adjacent to the first memory cell in the X direction. For example, in the memory cell located in row i, conductor 244[j] is electrically connected to memory cell 100A[i,j-1] and memory cell 100A[i,j]. In other words, conductor 244[j] corresponds to conductor 244b of memory cell 100A[i,j-1] and conductor 244a of memory cell 100A[i,j].

[0153] However, the present invention is not limited to the above. For example, as shown in Figure 7B, the conductors 262a and 246b may extend in the X direction, the conductor 244 may extend at an angle in the X direction, and the line segment connecting transistors 200a and 200b of the memory cell 100A may be parallel to the Y direction. By adopting this configuration, the memory density of the semiconductor device may be increased.

[0154] [Memory cell 100B] Figures 8A to 8C show examples of configurations different from the memory cell 100 or memory cell 100A described above. In the memory cells shown below, structures having the same function as the structures constituting the memory cell 100 or memory cell 100A described above will be denoted by the same reference numerals. Furthermore, the following explanation will mainly focus on the parts that differ from the memory cell 100 or memory cell 100A described above, and the explanation of overlapping parts will be omitted.

[0155] Figure 8A is a top view of memory cell 100B, Figure 8B is a cross-sectional view of memory cell 100B, and Figure 8C is a perspective view of memory cell 100B.

[0156] The memory cell 100B includes transistors 200a and 200b, conductors 244b and 244c, conductors 246a and 246b, conductor 256, conductors 262a and 262c.

[0157] Conductor 244b is electrically connected to the oxide 230 of transistor 200b, and conductor 244c is electrically connected to the oxide 230 of transistor 200a.

[0158] Conductor 246a is electrically connected to conductor 242a of transistor 200a, and conductor 246b is electrically connected to conductor 242a of transistor 200b.

[0159] Conductor 256 is electrically connected to conductors 244c and 262c.

[0160] In Figure 8, conductors 262a and 244b extend in the X direction, conductors 246a and 246b extend in the Y direction, and the line segment connecting transistors 200a and 200b is inclined in the X direction.

[0161] By using the above configuration, the write bit lines and read bit lines for the memory cell can be made independent.

[0162] Figure 9A is a top view of a memory cell array in which the memory cells 100B shown in Figure 8 are arranged in a matrix. In Figure 9A, conductors 262a and 244b extend in the X direction, conductor 246 extends in the Y direction, and the line segment connecting transistors 200a and 200b of the memory cell 100B is tilted in the X direction.

[0163] As shown in Figure 9A, one conductor 246 is electrically connected to the first memory cell and to the second memory cell adjacent to the first memory cell in the X direction. For example, in the memory cell located in row i, conductor 246[j] is electrically connected to memory cell 100B[i,j-1] and memory cell 100B[i,j]. In other words, conductor 246[j] corresponds to conductor 246b of memory cell 100B[i,j-1] and conductor 246a of memory cell 100B[i,j].

[0164] However, the present invention is not limited to the above. For example, as shown in Figure 9B, the conductors 262a and 244b may extend in the X direction, the conductor 246 may extend at an angle in the X direction, and the line segment connecting transistors 200a and 200b of the memory cell 100B may be parallel to the Y direction. By adopting this configuration, the memory density of the semiconductor device may be further increased.

[0165] [Memory cell 100C] Figures 10C to 10B show examples of configurations different from the aforementioned memory cell 100, memory cell 100A, or memory cell 100B. In the memory cells shown below, structures having the same function as those constituting memory cell 100, memory cell 100A, or memory cell 100B will be denoted by the same reference numerals. Furthermore, the following explanation will mainly focus on the parts that differ from the aforementioned memory cell 100, memory cell 100A, or memory cell 100B, and the explanation of overlapping parts will be omitted.

[0166] Figures 10A and 10B are cross-sectional views of memory cell 100A, and Figure 10C is a perspective view of memory cell 100C. Memory cell 100C differs from the aforementioned memory cell 100, memory cell 100A, or memory cell 100B mainly in that transistors 200a and 200b are stacked on top of each other.

[0167] The memory cell 100C includes transistors 200a and 200b, conductors 244b and 244c, conductors 246a and 246b, and conductor 262a.

[0168] The conductor 244c is electrically connected to the oxide 230 of transistor 200a and the conductor 260 of transistor 200b. In other words, the oxide 230 of transistor 200a is electrically connected to the conductor 260 of transistor 200b via the conductor 244c.

[0169] In memory cell 100B, the oxide 230 of transistor 200a and the conductor 260 of transistor 200b are electrically connected via conductors 244c, 256, and 262c. However, in memory cell 100C, the oxide 230 of transistor 200a and the conductor 260 of transistor 200b are electrically connected only via conductor 244c. By adopting the configuration of memory cell 100C, the number of steps in the semiconductor device manufacturing process can be reduced, thereby improving productivity. Furthermore, the need to provide an area for arranging conductor 256 is eliminated, allowing for a higher memory density in the semiconductor device.

[0170] Furthermore, as shown in Figure 10, when transistors 200a and 200b are stacked, the film thickness of the oxide 230 in transistor 200a and the oxide 230 in transistor 200b can be made different. In other words, the channel lengths of transistors 200a and 200b can be made different.

[0171] By increasing the channel length of the transistor, variations in the transistor's Vth can be reduced. For example, the thickness of the oxide 230 in transistor 200b is made greater than the thickness of the oxide 230 in transistor 200a. In this case, the channel length of transistor 200b, which functions as a readout transistor, becomes larger, enabling the realization of a memory cell with high readout accuracy.

[0172] Furthermore, the smaller the channel length, the lower the on-resistance, resulting in a transistor capable of high-speed operation. For example, the thickness of the oxide 230 in transistor 200a is made smaller than that of transistor 200b. In this case, the channel length of transistor 200a, which functions as a writing transistor, becomes smaller, enabling the realization of a memory cell with a high writing speed. Moreover, by increasing the thickness of the oxide 230 in transistor 200b, the channel length of transistor 200b, which functions as a reading transistor, becomes larger, enabling the realization of a memory cell with a high writing speed and high reading accuracy.

[0173] In the configuration shown in Figure 10, transistors 200a and 200b are not located on the same layer, so their structures may be different. For example, one of transistors 200a and 200b may be a planar transistor, a staggered transistor, or an inverse staggered transistor. It may also be a top-gate or bottom-gate transistor structure. Furthermore, gates may be provided above and below the semiconductor layer in which the channel is formed.

[0174] Furthermore, in the configuration shown in Figure 10, the semiconductor layer of transistor 200a and the semiconductor layer of transistor 200b may be formed using the same material or different materials.

[0175] Other semiconductor materials that can be used in one of the semiconductor layers of transistor 200a and transistor 200b include, for example, semiconductors composed of elemental elements or compound semiconductors. Examples of semiconductors composed of elemental elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that the oxide semiconductors mentioned above are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0176] Examples of silicon that can be used in semiconductor layers include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

[0177] Transistors using amorphous silicon for the semiconductor layer can be formed on large glass substrates and manufactured at low cost. Transistors using polycrystalline silicon for the semiconductor layer have high field-effect mobility and can operate at high speeds. Furthermore, transistors using microcrystalline silicon for the semiconductor layer have even higher field-effect mobility than transistors using amorphous silicon and can operate at high speeds.

[0178] [Variations of Transistor 200] In the following section, we will describe configuration examples different from the transistor 200 described above, using Figures 11A to 12C. Note that this section describes a modified version of the transistor 200 in the memory cell 100 shown in Figure 2, but the configurations of the modified transistor 200 described below may also be applied to the memory cells (memory cells 100A to 100C) shown in Figures 6 to 10.

[0179] A modified example of the transistor 200 shown in Figure 2B is shown in Figure 11A. Figure 11A is a cross-sectional view of the memory cell 100. The transistor 200 shown in Figure 11A differs from the transistor 200 shown in Figure 2B in the shape of the oxide 230 and the conductor 242a. Specifically, the transistor 200 shown in Figure 11A differs from the transistor 200 shown in Figure 2B in that the sides of the oxide 230 and the conductor 242a each have a tapered shape.

[0180] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it refers to a shape having a region where the angle between the inclined side surface and the substrate surface or the surface to be formed (also called the taper angle) is less than 90 degrees. The side surface of the structure and the substrate surface do not necessarily have to be perfectly flat; they may be substantially planar with a fine curvature, or substantially planar with fine irregularities.

[0181] As shown in Figure 11A, in a cross-sectional view of the transistor 200, the side surface of the oxide 230 on the opening side (insulator 250 side) may have a tapered shape with a taper angle θ. Here, the taper angle θ is the angle between the side surface of the oxide 230 on the opening side and the substrate surface. However, one of the two sides extending from the vertex of the taper angle θ is not limited to the substrate surface, but may be the upper surface of the conductor 244 or the lower surface of the oxide 230, etc. In other words, the taper angle θ may be the angle between the side surface of the oxide 230 and the upper surface of the conductor 244 or the lower surface of the oxide 230. In this case, the outer side surface of the oxide 230 also has a tapered shape with a taper angle θ.

[0182] The tapered shape of the side surface on the opening side of the oxide 230 improves the coverage of the insulator 250 provided in the opening of the oxide 230, thereby reducing defects such as porosity. In addition, the area of ​​the lower bottom surface of the oxide 230 is increased, which increases the area of ​​contact between the conductor 244 and the oxide 230.

[0183] Furthermore, the closer the taper angle θ is to 90 degrees, the lower the conductor 260 can be positioned below the opening in the oxide 230. Therefore, the area of ​​the oxide 230 overlapping with the conductor 260 can be increased, stabilizing the electrical characteristics of the transistor. Additionally, the occupied area of ​​the transistor 200 can be reduced. For example, the taper angle θ may be 80 degrees or more, 85 degrees or more, or 87 degrees or more, and less than 90 degrees.

[0184] In the above configuration, the upper surface of the oxide 230 has a hollow circular shape. In other words, in the above configuration, the oxide 230 has a hollow frustoconical shape. That is, the area of ​​the upper base surface (the surface on the conductor 242a side) of the frustoconical shape of the oxide 230 is smaller than the area of ​​the lower base surface (the surface on the conductor 244 side) of the frustoconical shape of the oxide 230.

[0185] Similar to oxide 230, the side surface of the conductor 242a on the opening side (insulator 250 side) and the outer side surface of conductor 242a have a tapered shape. The angle between the opening side surface of conductor 242a and the substrate surface, and the angle between the outer side surface of conductor 242a and the substrate surface, coincide with or approximately coincide with the taper angle θ. However, depending on the combination of materials used for oxide 230 and conductor 242a, or the processing conditions of oxide 230 and conductor 242a, the angle between the opening side surface of conductor 242a and the substrate surface, and the angle between the outer side surface of conductor 242a and the substrate surface may not coincide with the taper angle θ.

[0186] Furthermore, the conductor 242a has a hollow frustoconical shape. In other words, the area of ​​the upper base surface (the surface on the conductor 246b or conductor 246c side) of the frustoconical shape of the conductor 242a is smaller than the area of ​​the lower base surface (the surface on the oxide 230 side) of the frustoconical shape of the conductor 242a.

[0187] A modified version of the transistor 200 shown in Figure 2B is shown in Figure 11B. Figure 11B is a cross-sectional view of the memory cell 100. The transistor 200 shown in Figure 11B differs from the transistor 200 shown in Figure 2B in that it has a conductor 242b.

[0188] The conductor 242b is provided between the oxide 230 and the conductor 244. In Figure 11B, the conductor 242b is provided in contact with the lower surface of the oxide 230. Also, the conductor 242b is provided in contact with at least a portion of the upper surface of the conductor 244.

[0189] The conductor 242b has a cylindrical shape (also called a cylindrical shape). The cylindrical shape of the conductor 242b extends in the Z direction. The conductor 242b also has an opening. Furthermore, the upper surface of the conductor 242b has a hollow circular shape. In other words, the conductor 242b has a cylindrical shape with a hollow portion. The conductor 242b functions as one of the source electrode and drain electrode of the transistor 200.

[0190] The insulator 250 and the conductor 260 are arranged inside the opening of the conductor 242b. This configuration allows the edges of the region where the oxide 230 and the conductor 260 overlap via the insulator 250 to be brought closer to the conductor 244. In other words, the region where the oxide 230 and the conductor 260 do not overlap via the insulator 250, the so-called Loff region, can be narrowed or eliminated. Therefore, the frequency characteristics of the transistor 200 can be improved. This makes it possible to improve the write speed and read speed of the memory cell 100, and the operating speed of the semiconductor device 10. Thus, a semiconductor device with a high operating speed can be provided.

[0191] The conductive film that becomes conductor 242a and the conductive film that becomes conductor 242b are formed by different processes. Therefore, conductor 242a and conductor 242b may be formed from different materials or from the same material.

[0192] Figure 2B shows a configuration in which oxide 230 is a single layer, but the present invention is not limited to this. For example, oxide 230 may be in a laminated structure of two or more layers.

[0193] A modified example of the transistor 200 shown in Figure 2B is shown in Figure 12A. Figure 12A is a cross-sectional view of the memory cell 100. The transistor 200 shown in Figure 12A differs from the transistor 200 shown in Figure 2B in that the oxide 230 has a three-layer stacked structure consisting of oxide 230_1, oxide 230_2, and oxide 230_3.

[0194] Oxide 230_2 functions as the channel formation region of transistor 200, oxide 230_1 functions as one of the source and drain regions of transistor 200, and oxide 230_3 functions as the other of the source and drain regions of transistor 200.

[0195] For oxide 230_2, any metal oxide that can be used for oxide 230 as described above may be used.

[0196] For oxides 230_1 and 230_3, it is preferable to use materials with higher conductivity compared to oxide 230_2. Furthermore, it is preferable to use degenerate oxide semiconductors for oxides 230_1 and 230_3.

[0197] For example, as oxide 230_1 and oxide 230_3, materials to which nitrogen has been added to a metal oxide that can be used for oxide 230_2 can be used. Specifically, it is preferable to use a metal oxide (also called a metal oxynitride) having indium, the aforementioned element M, zinc, and nitrogen. More specifically, oxides containing indium (In), gallium (Ga), zinc (Zn), and nitrogen (also called oxynitride having In, Ga, and Zn, or nitrogen-added IGZO), oxides containing indium (In), aluminum (Al), zinc (Zn), and nitrogen (also called oxynitride having In, Al, and Zn, or nitrogen-added IAZO), or oxides containing indium (In), aluminum (Al), gallium (Ga), zinc (Zn), and nitrogen (also called oxynitride having In, Al, Ga, and Zn, nitrogen-added IAGZO, nitrogen-added IGAZO, or nitrogen-added AGIZO) can be used.

[0198] For example, nitrogen-doped IGZO tends to have a wurtzite-type crystal structure. The wurtzite-type crystal structure has high lattice compatibility with the crystal structure of In-M-Zn oxide. Therefore, by using a metal oxynitride having a wurtzite-type crystal structure as oxide 230_1, the crystallinity of oxide 230_2 can be improved. In other words, it becomes easier to form a metal oxide having a CAAC structure as oxide 230_2.

[0199] Furthermore, as mentioned above, when CAAC-OS is used as oxide 230_2, the crystals of oxide 230_2 are oriented along the c axis with respect to the substrate surface. Note that impurities in CAAC-OS tend not to diffuse easily in the c-axis direction. In other words, by using CAAC-OS as oxide 230_2, the incorporation of impurities into oxide 230_2 can be suppressed. For example, the incorporation of nitrogen into oxide 230_2 can be suppressed. Therefore, the increased conductivity of oxide 230_2 can be suppressed.

[0200] In addition, the above description concerns a material in which nitrogen is added to a metal oxide that can be used in oxide 230_2. However, the element added to the metal oxide that can be used in oxide 230_2 can be any element that enhances the conductivity of the metal oxide. For example, one or more elements selected from hydrogen, group 15 elements (typically nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn) can be used.

[0201] Furthermore, the metal oxides used for oxides 230_1 and 230_3 only need to have higher conductivity than oxide 230_2. For example, oxides 230_1 and 230_3 may be metal oxides that have elements common to oxide 230_2 other than oxygen as their main components, but have different chemical compositions.

[0202] When oxides 230_1 and 230_3 and oxide 230_2 share a common element other than oxygen as a main component, it is preferable that oxide 230 has a layered structure of multiple oxide layers with different chemical compositions. For example, when In-M-Zn oxide is used as oxide 230_2, it is preferable that the ratio of the number of indium atoms to the sum of the number of atoms of the main metal element in the metal oxide used in oxide 230_1 or oxide 230_3 is greater than the ratio of the number of indium atoms to the sum of the number of atoms of the main metal element in the metal oxide used in oxide 230_2. Furthermore, it is preferable that the ratio of the number of indium atoms to element M in the metal oxide used in oxide 230_1 or oxide 230_3 is greater than the ratio of the number of indium atoms to element M in the metal oxide used in oxide 230_2.

[0203] Because oxides 230_1 and 230_3 and oxide 230_2 share a common element other than oxygen as their main component, the defect level density at the interface between oxide 230_1 or oxide 230_3 and oxide 230_2 can be reduced. Since the defect level density at the interface between oxide 230_1 or oxide 230_3 and oxide 230_2 can be reduced, the influence of interfacial scattering on carrier conduction is small, and a high on-current can be obtained.

[0204] Alternatively, titanium oxide, molybdenum oxide, zinc oxide, indium oxide, tungsten oxide, magnesium oxide, calcium oxide, tin oxide, indium zinc oxide, indium tin oxide, or silicon-containing indium tin oxide may be used as oxide 230_1 and oxide 230_3.

[0205] Furthermore, when the oxide 230 is configured in the three-layer laminated structure described above, it may be necessary to omit the conductor 242a, as shown in Figure 12B. In this case, the conductor 246b or conductor 246c also performs the function of the conductor 242a. That is, the conductor 246b or conductor 246c has the function of wiring and the function of the other of the source electrode and drain electrode. By omitting the conductor 242a, the number of steps in the semiconductor device manufacturing process can be reduced, thereby improving productivity.

[0206] A modified example of the transistor 200 shown in Figure 2B is shown in Figure 12C. Figure 12C is a cross-sectional view of the memory cell 100. The transistor 200 shown in Figure 12C differs from the transistor 200 shown in Figure 2B in that the oxide 230 has a two-layer stacked structure of oxide 230_1 and oxide 230_2.

[0207] When heat treatment is performed with the conductor 242a and oxide 230_2 in contact, the sheet resistance of the oxide 230_2 near the conductor 242a may decrease. Also, the carrier concentration may increase. Therefore, the oxide 230_2 near the conductor 242a can be made to have a self-aligned low resistance.

[0208] In the above case, for example, as shown in Figure 12C, region 230_22 is formed in oxide 230_2. Region 230_22 is a low-resistance region of oxide 230_2 near the conductor 242a. Region 230_22 functions as the other of the source region and drain region. Furthermore, the region of oxide 230_2 that functions as a channel-forming region is denoted as region 230_21. Note that it may be difficult to clearly detect the boundaries of each region in oxide 230_2.

[0209] Depending on the material used for the conductor 242a, region 230_22 may not be formed. In this case, the oxide 230_2 has region 230_21. Also, depending on the material used for the conductor 244, a low-resistance region may be formed near the conductor 244 of the oxide 230_1.

[0210] <Detailed example of semiconductor device configuration> In the following, a detailed example of the configuration of a semiconductor device according to one embodiment of the present invention will be described using Figures 13A to 13D. In the semiconductor device described below, structures having the same function as the structures constituting the semiconductor device shown in the previous <Example of Semiconductor Device Configuration> will be denoted by the same reference numerals. Furthermore, in the following, we will mainly describe the parts that differ from the semiconductor device shown in the previous <Example of Semiconductor Device Configuration>, and will omit the explanation of overlapping parts.

[0211] Figures 13A to 13D are top views and cross-sectional views of a semiconductor device including a memory cell 100. Figures 13A and 13D are top views of the semiconductor device. Figures 13B and 13C are cross-sectional views of the semiconductor device. Here, Figure 13B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 13A. Figure 13C is a cross-sectional view of the area indicated by the dashed line B1-B2 in Figure 13A. Figure 13D is a top view of the region enclosed by the double-dash line in Figure 13A, including the cross-section of the area indicated by the dashed line C1-C2 in Figure 13B. Note that some elements have been omitted from the top view of Figure 13A for clarity.

[0212] The semiconductor device shown in Figures 13A to 13D has a plurality of memory cells 100 arranged in a matrix. Figure 13A shows two of the plurality of memory cells 100 that the semiconductor device has.

[0213] The semiconductor device shown in Figures 13A to 13D includes an insulator 216 and a conductor 244 on a substrate (not shown), transistors 200a, 200b, insulators 275b, 250b, and 274 on the insulators 216 and 244, conductors 246b, 246c, 276, and 278 on the transistors 200a, 200b, 275b, 250b, and 274, insulator 277b on conductor 246b, insulator 277c and conductor 256 on conductor 246c, and conductors 262a, 262c, and 285 on insulators 276, 277b, 277c, 278, and conductor 256. Insulators 216, 274, 276, 277b, 277c, 278, and 285 function as interlayer films.

[0214] In the top view of the semiconductor device shown in Figures 13A to 13D, the conductor 262a does not overlap with the conductor 246c. Also, the conductor 262c does not overlap with the conductor 246b.

[0215] The memory cell 100 in the semiconductor device shown in Figures 13A to 13D is composed of transistor 200a and transistor 200b. Transistors 200a and 200b are electrically connected via conductors 262c, 256, and 246c. The memory cell 100 shown in Figures 13A to 13D is also a detailed configuration example of the memory cell 100 shown in Figures 3D, 5A, 5B, and 5C.

[0216] [Details of Memory Cell 100] As shown in Figures 13B and 13C, the transistor 200 includes a conductor 244 (conductor 244_1 and conductor 244_2) arranged to be embedded in the insulator 216, oxide 230_1 and insulator 275a on the insulator 216 and conductor 244, oxide 230_2 on oxide 230_1, oxide 230_3 on oxide 230_2, conductor 242a on oxide 230_3, insulator 250a on insulator 275a, and conductor 260 on insulator 250a.

[0217] In the following, oxides 230_1, 230_2, and 230_3 may be collectively referred to as oxide 230.

[0218] The insulators 275a, 250a, and 260 are provided inside the openings of the oxide 230 and conductor 242a. The insulator 250a has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. The insulator 275a has a region in contact with the side surface of the insulator 250a, a region in contact with the bottom surface of the insulator 250a, a region in contact with the side surface on the opening side of the oxide 230, a region in contact with the side surface on the opening side of the conductor 242a, and a region in contact with the top surface of the conductor 244. In this configuration, it can also be said that each of the insulators 275a and 250a has a recess. For example, as shown in Figure 4A, if the conductor 244 is positioned in a top view at a location offset in the X direction from the center of the hollow cylindrical shape of the oxide 230, the insulator 275a may have a region in contact with the insulator 216.

[0219] Figure 13D corresponds to the XY plane at or near the center of the oxide 230_2. In Figure 13D, when the upper surface of the oxide 230_2 has a hollow circular shape, the insulator 275a is provided concentrically inside the oxide 230_2, the insulator 250a is provided concentrically inside the insulator 275a, and the conductor 260 is provided concentrically inside the insulator 250a.

[0220] Here, width H1 is defined as the width of oxide 230_2 in the direction from the center of the hollow portion of oxide 230_2 toward the outer circumference of the cylindrical shape. In other words, width H1 is half the difference between the outer diameter and the inner diameter of the hollow cylindrical shape.

[0221] To prevent adjacent oxides 230_2 from touching each other, the width H1 must be smaller than half of the minimum processing dimension (F). On the other hand, to form a hollow cylindrical oxide 230_2, the width H1 must be of a certain size. If the minimum processing dimension (F) is, for example, 15 nm, the width H1 is preferably 1 nm to 7 nm, more preferably 1.5 nm to 6 nm, and even more preferably 2 nm to 5 nm. With this configuration, adjacent oxides 230_2 do not touch each other, and at least an insulator 275b can be provided between adjacent oxides 230_2. Note that the preferred range of width H1 is not limited to the above. The width H1 should be set appropriately considering the minimum processing dimension and the film thickness of the insulator 275b.

[0222] The oxide 230 has a region that overlaps with the conductor 244. More specifically, oxide 230_1 has a region that contacts at least a portion of the upper surface of the conductor 244. The oxide 230 also has a region that overlaps with the conductor 242a. More specifically, oxide 230_3 has a region that contacts at least a portion of the lower surface of the conductor 242a.

[0223] The top of insulator 250a is at the same height as the top of insulator 275a, the top of insulator 275b, the top of insulator 250b, and the top of insulator 274, respectively.

[0224] An insulator 276 is provided on insulators 275a and 250a. A conductor 262a or 262c is located on insulator 276. In other words, insulator 276 is provided between insulators 275a and 250a and conductor 262a or 262c. Insulator 276 has a region that overlaps with insulators 275a and 250a. Insulator 276 also has a region that is in contact with the lower surface of conductor 262a or 262c. In other words, at least a portion of the lower surface of conductor 262a or 262c is in contact with the upper surface of insulator 276.

[0225] The insulator 276 functions as an interlayer film. The insulator 276 has a cylindrical shape and an opening. In other words, the insulator 276 has a cylindrical shape with a hollow portion. To put it another way, the upper surface shape of the insulator 276 is a hollow circular shape. The conductor 260 is provided in the hollow portion of the insulator 276. Furthermore, if the cross-sectional shape of the conductor 260 is circular, the insulator 276 is provided concentrically on the outside of the conductor 260.

[0226] In a top view, it is preferable that the diameter of the hollow portion of the insulator 276 is the same as or larger than the inner diameter of the recess in the insulator 250a where the conductor 260 is provided. This configuration allows the conductor 260 to be more reliably embedded in the recess of the insulator 250a. For example, as shown in Figure 14A, a portion of the conductor 246c may be provided on the insulator 275a, or on both the insulator 275a and the insulator 250a. Even in such cases, the above configuration allows the conductor 260 to be embedded in the recess of the insulator 250a. The same applies when a portion of the conductor 246b is provided on the insulator 275a, or on both the insulator 275a and the insulator 250a.

[0227] Furthermore, it is preferable that the cylindrical contour of the insulator 276 matches the contour of the insulator 275a. With this configuration, the contact area between the conductor 242a and the conductor 246b or conductor 246c can be increased compared to a configuration in which the cylindrical contour of the insulator 276 is larger than the contour of the insulator 275a. Also, with this configuration, the distance between the conductor 262a and the conductor 246c, and the distance between the conductor 262c and the conductor 246b can be increased compared to a configuration in which the cylindrical contour of the insulator 276 is smaller than the contour of the insulator 275a. Therefore, leakage current and short circuits can be prevented between the conductor 262a and the conductor 246c, and between the conductor 262c and the conductor 246b.

[0228] Furthermore, it is preferable that the insulator 276 extends in the Z direction such that the upper surface of the conductor 246b or conductor 246c is located between the lower and upper surfaces of the insulator 276. In other words, it is preferable that the insulator 276 extends in the Z direction such that the upper surface of the conductor 246b or conductor 246c is located above the lower surface of the insulator 276 and below the upper surface of the insulator 276. This configuration prevents contact between the conductor 262a and the conductor 246c, and between the conductor 262c and the conductor 246b, thereby preventing leakage current and short circuits between the conductor 262a and the conductor 246c, and between the conductor 262c and the conductor 246b.

[0229] An insulator 277b is provided on the conductor 246b, and an insulator 277c is provided on the conductor 246c. As shown in Figure 13B, the insulator 277c and the conductor 246c have a region where their ends coincide. Although not shown, the insulator 277b and the conductor 246b also have a region where their ends coincide.

[0230] Conductor 260 functions as the gate electrode of transistor 200. Insulators 275a and 250a function as gate insulators of transistor 200. Conductor 244 functions as one of the source and drain electrodes of transistor 200, and conductor 242a functions as the other of the source and drain electrodes of transistor 200. At least a portion of the region of oxide 230 that overlaps with conductor 260 functions as the channel-forming region of transistor 200. For example, oxide 230_2 functions as the channel-forming region of transistor 200, oxide 230_1 functions as one of the source and drain regions of transistor 200, and oxide 230_3 functions as the other of the source and drain regions of transistor 200.

[0231] In transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230_2 which includes the channel formation region. In some cases, a portion of the region of oxide 230_1 and oxide 230_3 that overlaps with the conductor 260 may function as a channel formation region.

[0232] In the transistor 200 shown in Figure 13B, the oxide 230 is shown as a stacked structure of three layers: oxide 230_1, oxide 230_2, and oxide 230_3. However, the present invention is not limited to this. For example, the oxide 230 may be a single layer, or a stacked structure of two or four or more layers.

[0233] The materials and composition of oxide 230 (oxide 230_1, oxide 230_2, and oxide 230_3) can be found in the description of the above <Example of Semiconductor Device Configuration>.

[0234] Insulators 216, 274, 276, 277b, 277c, 278, and 285 preferably have a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, as insulators 216, 274, 276, 277b, 277c, 278, and 285, silicon oxide, silicon oxide-nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, or resin may be used as appropriate. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0235] The conductor 244 has a region that overlaps with the oxide 230. More specifically, the conductor 244 is positioned so as to be in contact with at least a portion of the lower surface of the oxide 230_1. Here, it is preferable that the conductor 244 is embedded in an opening in the insulator 216.

[0236] The conductor 244 has a two-layer structure consisting of conductor 244_1 and conductor 244_2. Conductor 244_1 is provided in contact with the bottom surface and side wall of the opening in the insulator 216. Conductor 244_2 is provided so as to be embedded in a recess formed in conductor 244_1. Here, the height of the upper surface of conductor 244_2 is the same as the height of the upper surfaces of conductor 244_1 and insulator 216, respectively.

[0237] Here, it is preferable that the conductor 244_1 is a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule). Alternatively, it is preferable that the conductor 244_1 is a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms.

[0238] By using a conductive material that has the function of suppressing oxygen diffusion for the conductor 244_1, oxidation of the conductor 244_2 and a decrease in conductivity can be suppressed. Preferably, the conductive material that has the function of suppressing oxygen diffusion is titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Therefore, the conductive material 244_1 can be a single layer or a laminate of the above-mentioned conductive material. For example, titanium nitride can be used for the conductor 244_1.

[0239] Furthermore, it is preferable that the conductor 244_2 be a conductive material mainly composed of tungsten, copper, or aluminum. For example, tungsten may be used for the conductor 244_2.

[0240] The electrical resistivity of the conductor 244 is designed considering the potential applied to the conductor 244, and the film thickness of the conductor 244 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 244. Here, it is preferable to make the film thicknesses of both the conductor 244 and the insulator 216 as thin as possible within the limits permitted by the design of the conductor 244. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby suppressing the diffusion of these impurities into the oxide 230.

[0241] Although Figure 13B shows a configuration in which the conductor 244 has a two-layer structure consisting of conductor 244_1 and conductor 244_2, the present invention is not limited to this. For example, the conductor 244 may be provided as a single layer or as a laminated structure of three or more layers.

[0242] The material and configuration of the conductor 244 can be found in the <Example of Semiconductor Device Configuration> section above. Furthermore, the conductor 244 may be made of a conductive material applicable to the conductor 242a.

[0243] The conductor 242a is superimposed on the oxide 230. More specifically, the conductor 242a is provided in contact with the upper surface of the oxide 230_3.

[0244] Although Figure 13B shows a configuration in which the conductor 242a is a single layer, the present invention is not limited to this, and the conductor 242a may be a laminated structure of two or more layers. For example, the conductor 242a may be a two-layer laminated structure consisting of a first conductor on the oxide 230_3 and a second conductor on the first conductor.

[0245] The first conductor of the conductor 242a is preferably composed of a conductive material that is resistant to oxidation. This prevents oxidation of the first conductor of the conductor 242a and a decrease in the conductivity of the conductor 242a. The first conductor of the conductor 242a may also have properties that easily absorb (extract) hydrogen. This allows hydrogen from the oxide 230 to diffuse into the first conductor of the conductor 242a, reducing the hydrogen concentration of the oxide 230. Thus, stable electrical characteristics can be imparted to the transistor 200.

[0246] Preferably, the second conductor of conductor 242a is composed of a conductive material with higher conductivity than the first conductor of conductor 242a. In this case, the second conductor of conductor 242a only needs to have a region with higher conductivity than the first conductor of conductor 242a in at least a portion of it. Furthermore, it is preferable that the second conductor of conductor 242a is composed of a conductive material with lower resistivity than the first conductor of conductor 242a. This makes it possible to manufacture a semiconductor device with suppressed wiring delay.

[0247] Furthermore, the second conductor of conductor 242a may have properties that readily absorb hydrogen. This allows hydrogen absorbed by the first conductor of conductor 242a to diffuse into the second conductor of conductor 242a, further reducing the hydrogen concentration in the oxide 230. Thus, stable electrical characteristics can be imparted to the transistor 200.

[0248] Here, it is preferable that the first and second conductors of the conductor 242a are conductive materials that have the same constituent elements but different chemical compositions. In this case, the first and second conductors of the conductor 242a can be continuously deposited without exposure to the atmospheric environment. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the surface of the first conductor of the conductor 242a, and to keep the vicinity of the interface between the first and second conductors of the conductor 242a clean.

[0249] Furthermore, it is preferable to use a tantalum-containing nitride with a high atomic ratio of nitrogen to tantalum as the first conductor of conductor 242a, and a tantalum-containing nitride with a low atomic ratio of nitrogen to tantalum as the second conductor of conductor 242a. For example, as the first conductor of conductor 242a, a tantalum-containing nitride with an atomic ratio of nitrogen to tantalum of 1.0 or more and 2.0 or less, preferably 1.1 or more and 1.8 or less, and more preferably 1.2 or more and 1.5 or less is used. Also, for example, as the second conductor of conductor 242a, a tantalum-containing nitride with an atomic ratio of nitrogen to tantalum of 0.3 or more and 1.5 or less, preferably 0.5 or more and 1.3 or less, and more preferably 0.6 or more and 1.0 or less is used.

[0250] In tantalum-containing nitrides, increasing the atomic ratio of nitrogen to tantalum can suppress oxidation of the tantalum-containing nitride. Furthermore, it can improve the oxidation resistance of the tantalum-containing nitride. Additionally, it can suppress the diffusion of oxygen into the tantalum-containing nitride. Therefore, it is preferable to use a tantalum-containing nitride with a high atomic ratio of nitrogen to tantalum as the first conductor of the conductor 242a. This prevents the formation of an oxide layer between the first conductor of the conductor 242a and the oxide 230, or reduces the thickness of the oxide layer.

[0251] Furthermore, in a tantalum-containing nitride, the resistivity of the nitride can be reduced by lowering the atomic ratio of nitrogen to tantalum. Therefore, it is preferable to use a tantalum-containing nitride with a low atomic ratio of nitrogen to tantalum as the second conductor of conductor 242a. This makes it possible to manufacture a semiconductor device with suppressed wiring delay.

[0252] Furthermore, in the conductor 242a, it may be difficult to clearly detect the boundary between the first conductor and the second conductor. When a nitride containing tantalum is used for the conductor 242a, the tantalum and nitrogen concentrations detected in each layer may not be limited to stepwise changes in each layer, but may also change continuously (also called a gradient) in the region between the first conductor and the second conductor. In other words, the closer the region of the conductor 242a is to the oxide 230, the higher the atomic ratio of nitrogen to tantalum should be. Therefore, it is preferable that the atomic ratio of nitrogen to tantalum in the region located below the conductor 242a is higher than the atomic ratio of nitrogen to tantalum in the region located above the conductor 242a.

[0253] The film thickness of the first conductive layer of conductor 242a is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, more preferably 1.0 nm or more and 3.0 nm or less. In this case, the first conductive layer of conductor 242a only needs to have a region with the above-mentioned film thickness in at least a part of it. Furthermore, it is preferable that the film thickness of the first conductive layer of conductor 242a is thinner than the film thickness of the second conductive layer of conductor 242a. In this case, the first conductive layer of conductor 242a only needs to have a region with a film thickness thinner than the second conductive layer of conductor 242a in at least a part of it.

[0254] Although the example shown uses conductive materials with the same constituent elements but different chemical compositions for the first and second conductors of conductor 242a, the example is not limited to this, and the first and second conductors of conductor 242a may be formed using different conductive materials. For example, a tantalum-containing nitride may be used as the first conductor of conductor 242a, and a titanium-containing nitride or tungsten may be used as the second conductor of conductor 242a.

[0255] The material and structure of the conductor 242a can be found in the description of the above-mentioned <Example of Semiconductor Device Configuration>.

[0256] In a top view, the insulator 275a is positioned inside the openings of the oxide 230 and conductor 242a (the hollow portion of the oxide 230 and conductor 242a). The insulator 275a functions as part of the gate insulator. The insulator 275b is positioned outside the cylindrical shape of the oxide 230 and conductor 242a in a top view.

[0257] As will be explained in detail later, insulators 275a and 275b are formed in the same process. Therefore, insulator 275a has the same insulating material as insulator 275b. Also, the film thickness of insulator 275b is equal to the film thickness of insulator 275a.

[0258] Furthermore, the insulator 275a is provided on the same layer as the insulator 275b. In Figure 13B, the insulators 275a and 275b are provided on the insulator 216 and the conductor 244.

[0259] It is preferable to use an oxygen barrier insulating film as insulator 275a and insulator 275b. For example, an insulator containing an oxide of one or both of aluminum and hafnium may be used as insulator 275a and insulator 275b. As such an insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc., can be used. In this embodiment, aluminum oxide is used as insulator 275a and insulator 275b. In this case, insulator 275a and insulator 275b contain at least oxygen and aluminum.

[0260] As shown in Figure 13B, the insulator 275a is provided in contact with the side surface of the opening of the oxide 230. The insulator 275b is provided in contact with the outer side surface of the oxide 230. In other words, the oxide 230 is covered by insulators 275a and 275b. This prevents oxygen from being released from the oxide 230 during heat treatment, etc., due to the oxygen barrier properties of insulators 275a and 275b. Therefore, the formation of oxygen vacancies in the oxide 230 can be suppressed. This prevents the formation of oxygen vacancies and V O This allows for a reduction in H. Therefore, the electrical characteristics of transistor 200 can be improved, and its reliability can be enhanced.

[0261] Furthermore, even if an excess amount of oxygen is present in the insulator 274 and insulator 250a, it is possible to suppress the excessive supply of oxygen to the oxide 230. Therefore, it is possible to suppress the excessive oxidation of oxide 230_1 and oxide 230_3, which would cause a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility.

[0262] Furthermore, as shown in Figure 13B, the insulator 275a is provided in contact with the open side surface of the conductor 242a, and the insulator 275b is provided in contact with the outer side surface of the conductor 242a. In other words, the conductor 242a is covered by the insulators 275a and 275b. This prevents oxidation of the side surface of the conductor 242a and the formation of an oxide film on that surface. This prevents a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility.

[0263] When aluminum oxide is used as insulators 275a and 275b, aluminum may be added to the region of oxide 230_2 that is in contact with insulator 275a and its vicinity, and to the region of oxide 230_2 that is in contact with insulator 275b and its vicinity. For example, when IGZO is used as oxide 230_2, the region of oxide 230_2 that is in contact with insulator 275a and its vicinity, and the region of oxide 230_2 that is in contact with insulator 275b and its vicinity, contains indium, gallium, aluminum, and zinc.

[0264] Furthermore, as shown in Figure 13B and other figures, by providing an insulator 275a made of aluminum oxide or the like in contact with the side surface of the opening of the oxide 230_2, the indium contained in the oxide 230_2 may be unevenly distributed at and near the interface between the oxide 230_2 and the insulator 275a. As a result, the atomic ratio near the surface on the opening side of the oxide 230_2 becomes close to that of indium oxide, or close to that of In-Zn oxide. By increasing the atomic ratio of indium in the oxide 230_2, especially near the surface on the opening side of the oxide 230_2, the field-effect mobility of the transistor 200 can be improved.

[0265] The insulator 275a, together with the insulator 250a and the conductor 260, must be provided within the openings of the conductor 242a and the oxide 230. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 275a be thin. The film thickness of the insulator 275a should be 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and less than 3.0 nm. In this case, it is sufficient that the insulator 275a has a region with the above-mentioned film thickness in at least a portion of it. Furthermore, it is preferable that the film thickness of the insulator 275a be thinner than that of the insulator 250a. In this case, it is sufficient that the insulator 275a has a region with a thinner film thickness than the insulator 250a in at least a portion of it.

[0266] To achieve the thin film thickness of insulator 275a as described above, it is preferable to deposit insulator 275a using the ALD method. ALD methods include thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. The PEALD method is preferable in some cases because the use of plasma allows for film deposition at lower temperatures.

[0267] The ALD method allows for the deposition of atoms layer by layer, resulting in several advantages: the ability to deposit extremely thin films, films on structures with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. Therefore, the insulator 275a can be deposited with good coverage on the sides of openings in the conductor 242a and oxide 230, with the thin film thickness described above.

[0268] Note that precursors used in the ALD method may contain carbon and other impurities. Therefore, films formed by the ALD method may contain more carbon and other impurities compared to films formed by other deposition methods. The quantity of impurities can be quantified using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0269] Insulator 250a is positioned in the recess of insulator 275a. Insulator 250a functions as part of the gate insulator. Insulator 250b is positioned in contact with the upper surface of insulator 275b.

[0270] As will be explained in detail later, insulators 250a and 250b are formed in the same process. Therefore, insulator 250a has the same insulating material as insulator 250b. Also, the film thickness of insulator 250b is equal to the film thickness of insulator 250a.

[0271] Furthermore, in Figure 13B, the insulator 250a is provided on the insulator 275a, and the insulator 250b is provided on the insulator 275b. As described above, since the insulator 275a is provided in the same layer as the insulator 275b, the insulator 250a can be considered to be provided in the same layer as the insulator 250b.

[0272] Note that for the materials, configurations, and the like of the insulator 250a and the insulator 250b, reference can be made to the content of the insulator 250 described in the foregoing <Configuration Example of Semiconductor Device>.

[0273] In the present embodiment, hafnium oxide is used as the insulator 250a and the insulator 250b. In this case, the insulator 250a and the insulator 250b contain at least oxygen and hafnium.

[0274] The conductor 260 is disposed in the recess of the insulator 250a. In the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening included in the oxide 230 and the conductor 242a.

[0275] Although FIG. 13B shows a configuration in which the conductor 260 is a single layer, the present invention is not limited thereto. For example, the conductor 260 may have a stacked structure of two or more layers.

[0276] Note that for the materials, configurations, and the like of the conductor 260, reference can be made to the content described in the foregoing <Configuration Example of Semiconductor Device>.

[0277] The conductor 246b is disposed on the conductor 242a included in the transistor 200b. Further, the conductor 246b is disposed in contact with at least a part of the upper surface of the conductor 242a included in the transistor 200b. Further, the conductor 246b has a convex-shaped portion in a region overlapping with the conductor 242a included in the transistor 200b. The conductor 246b functions as a wiring.

[0278] The conductor 246c is disposed on the conductor 242a included in the transistor 200a. Further, the conductor 246c is disposed in contact with at least a part of the upper surface of the conductor 242a included in the transistor 200a. Further, the conductor 246c has a convex-shaped portion in a region overlapping with the conductor 242a included in the transistor 200a.

[0279] Note that for the materials, configurations, and the like of the conductor 246b and the conductor 246c, reference can be made to the content described in the foregoing <Configuration Example of Semiconductor Device>.

[0280] The conductor 262a is disposed on the conductor 260 included in the transistor 200a. Further, the conductor 262a is disposed in contact with the top surface of the conductor 260 included in the transistor 200a. The conductor 262a functions as a wiring.

[0281] The conductor 262a preferably has a two-layer structure including a conductor 262a_1 and a conductor 262a_2 over the conductor 262a_1. For example, the conductor 262a_1 is preferably disposed so as to wrap the bottom surface and side surfaces of the conductor 262a_2. Note that in FIG. 13B, the conductor 262a is illustrated as a two-layer structure of the conductor 262a_1 and the conductor 262a_2, but it may have a single-layer structure or a stacked structure of three or more layers.

[0282] The conductor 262c is disposed on the conductor 260 included in the transistor 200b. Further, the conductor 262c is disposed in contact with the top surface of the conductor 260 included in the transistor 200b.

[0283] The conductor 262c preferably has a two-layer structure including a conductor 262c_1 and a conductor 262c_2 over the conductor 262c_1. For example, the conductor 262c_1 is preferably disposed so as to wrap the bottom surface and side surfaces of the conductor 262c_2. Note that in FIG. 13B, the conductor 262c is illustrated as a two-layer structure of the conductor 262c_1 and the conductor 262c_2, but it may have a single-layer structure or a stacked structure of three or more layers.

[0284] As illustrated in FIG. 13B, the height of the top surface of the conductor 262a matches that of the respective top surfaces of the conductor 262c and the insulator 285.

[0285] The conductor 262a_1 and the conductor 262c_1 are preferably formed using a conductive material having a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule, and a copper atom. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, and the like) is preferably used.

[0286] Furthermore, because conductors 262a_1 and 262c_1 have the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of conductors 262a_2 and 262c_2 by oxygen contained in the insulator 285, which would reduce their conductivity. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0287] Furthermore, since the conductor 262a functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 262a_2 can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 262a_2 may also be a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material. The same applies to the conductor 262c_2.

[0288] The materials and configurations of conductors 262a and 262c can be found in the description of the above-mentioned <Example of Semiconductor Device Configuration>.

[0289] [Materials used in semiconductor devices] The following describes the constituent materials that can be used in semiconductor devices.

[0290] Circuit board As the substrate for forming transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0291] Insulator Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0292] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0293] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0294] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0295] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used.

[0296] Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0297] ≪Conductors≫ As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0298] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0299] Note that in the case where an oxide is used for a channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the aforementioned metal element and a conductive material containing oxygen are combined for a conductor that functions as a gate electrode. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. Providing the conductive material containing oxygen on the channel formation region side facilitates supply of oxygen released from the conductive material to the channel formation region.

[0300] In particular, as the conductor that functions as a gate electrode, it is preferable to use a conductive material containing a metal element and oxygen that are included in a metal oxide where a channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide to which silicon is added, or indium gallium zinc oxide containing nitrogen may also be used. Use of such a material sometimes enables capture of hydrogen contained in the metal oxide where a channel is formed. Alternatively, it may sometimes be possible to capture hydrogen mixed in from an outer insulator or the like.

[0301] [Modification Example of Memory Cell 100] A configuration example different from that of the memory cell 100 illustrated in FIG. 13 is described below with reference to FIG. 14B.

[0302] A modification example of the memory cell 100 illustrated in FIG. 13 is illustrated in FIG. 14B. FIG. 14B is a cross-sectional view of a semiconductor device including the memory cell 100. The memory cell 100 illustrated in FIG. 14B differs from the transistor 200 illustrated in FIG. 13 in including an insulator 254a, an insulator 254b, an insulator 212, and an insulator 247.

[0303] The insulator 254a is located between the insulator 250a and the conductor 260. Specifically, the insulator 254a is provided in a recess of the insulator 250a. Furthermore, the insulator 254a is provided in contact with the side and bottom surfaces of the conductor 260. In this configuration, it can also be said that the insulator 254a has a recess. In addition, the uppermost part of the insulator 254a is at the same height as the uppermost parts of the insulators 275a and 250a, respectively.

[0304] The insulator 254a functions as part of the gate insulator. Preferably, a barrier insulating film against hydrogen is used as the insulator 254a. This suppresses the diffusion of impurities such as hydrogen contained in the conductor 260 into the oxide 230_2. For example, silicon nitride may be used as the insulator 254a. Alternatively, silicon nitride deposited by the PEALD method may be used as the insulator 254a. In this case, the insulator 254a contains at least nitrogen and silicon. Alternatively, for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, or silicon nitride may be used as the insulator 254a. The insulator 254a should be less permeable to hydrogen than, for example, the insulator 254a. Furthermore, the insulator 254a should be made of a material that is less permeable to hydrogen than, for example, the insulator 250a.

[0305] Furthermore, the insulator 254a may also have barrier properties against oxygen. This can suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260.

[0306] Furthermore, insulator 254a, along with insulator 275a, insulator 250a, and conductor 260, must be provided in the openings of oxide 230 and conductor 242a. In order to miniaturize the transistor, it is preferable that the film thickness of insulator 254a be thin. The film thickness of insulator 254a is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that insulator 254a has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of insulator 254a is thinner than the film thickness of insulator 250a. In this case, it is sufficient that insulator 254a has a region with a film thickness thinner than insulator 250a in at least a part of it.

[0307] In a top view, the insulator 254b is positioned outside the oxide 230 and conductor 242a (on the side of insulator 275b). Furthermore, the insulator 254b is located between the insulator 250b and the insulator 274. Specifically, the insulator 254b is provided in contact with the top surface of the insulator 250b. Additionally, the insulator 254b is provided in contact with the side and bottom surfaces of the insulator 274.

[0308] Insulators 254a and 254b are formed in the same process. Therefore, insulator 254a has the same insulating material as insulator 254b. Also, the film thickness of insulator 254a is equal to the film thickness of insulator 254b.

[0309] The insulator 247 is located between the conductor 262a and the insulators 277c, 278, and 285. Furthermore, the insulator 247 is located between the conductor 262c and the insulators 277b, 278, and 285. Additionally, the insulator 247 is provided in contact with the side surface of either the conductor 262a or the conductor 262c.

[0310] The insulator 247 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the conductor 262a or conductor 262c. This suppresses the diffusion of impurities such as hydrogen contained in the insulator 285 into the oxide 230_2 via the conductor 262a or conductor 262c. As the insulator 247, any insulator that can be used for the insulator 254a may be used. For example, silicon nitride deposited by the PEALD method may be used as the insulator 247. In this case, the insulator 247 has at least nitrogen and silicon.

[0311] In addition, an insulator made of the same material as the insulator 247 may be formed to cover the side surface of the region of the conductor 260 that is exposed from the insulator 276.

[0312] The insulator 212 is provided on a substrate (not shown) and is located below the insulator 216 and the conductor 244.

[0313] The insulator 212 functions as an interlayer film. Preferably, the insulator 212 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200. By providing the insulator 212, the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side can be suppressed.

[0314] As the insulator 212, any insulator that can be used for the insulator 254a described above may be used. For example, it is preferable to use a silicon-containing nitride such as silicon nitride or silicon nitride oxide as the insulator 212. Specifically, silicon nitride deposited by sputtering may be used as the insulator 212. By depositing the insulator 212 by sputtering, a high-density silicon nitride can be formed. Alternatively, as the insulator 212, silicon nitride deposited by the PEALD method or CVD method may be laminated on top of the silicon nitride deposited by sputtering.

[0315] <Method for fabricating semiconductor devices> Next, the method for fabricating the semiconductor device shown in Figures 13A to 13D will be explained using Figures 15A1 to 22B2.

[0316] In Figures 15A1 to 22B2, A1 and B1 in each figure show a top view. A2 and B2 in each figure are cross-sectional views corresponding to the areas indicated by the dashed line A1-A2 in A1 and B1 of each figure. Note that some elements have been omitted from the top views of A1 and B1 in each figure for clarity.

[0317] In the following, insulating materials for forming an insulator, conductive materials for forming a conductor, or semiconductor materials for forming a semiconductor can be deposited using methods such as plating, sputtering, CVD, MBE, PLD, or ALD as appropriate.

[0318] Sputtering methods include RF sputtering, which uses a high-frequency power supply, and DC sputtering, which uses a direct current power supply. DC sputtering further includes pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing conductive metal films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0319] Furthermore, CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) or metal-organic CVD (MOCVD) depending on the source gas used.

[0320] Plasma CVD (Chemical Vapor Deposition) allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (such as transistors and capacitive elements) contained in semiconductor devices can be charged up by receiving charge from the plasma. In this case, the accumulated charge can destroy the wiring, electrodes, and elements contained in the semiconductor device. In contrast, thermal CVD, which does not use plasma, does not cause such plasma damage, thus increasing the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0321] Furthermore, ALD methods that can be used include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants.

[0322] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and provide good step-level coating. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coating and uniform thickness. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other deposition methods that have a faster deposition rate, such as the CVD method.

[0323] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the raw material gases. For example, in the CVD method, films with continuously changing compositions can be deposited by changing the flow rate ratio of the raw material gases while the film is being deposited. When depositing films while changing the flow rate ratio of the raw material gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time spent on transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0324] Furthermore, the ALD method allows for the deposition of films with any desired composition by simultaneously introducing multiple different types of precursors. Alternatively, when introducing multiple different types of precursors, films with any desired composition can be deposited by controlling the number of cycles for each precursor.

[0325] First, a substrate (not shown) is prepared, and an insulator 216 (not shown) is deposited on the substrate. It is preferable to deposit the insulator 216 using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced.

[0326] In this embodiment, silicon oxide is deposited as the insulator 216 using a silicon target in an atmosphere containing oxygen gas by pulsed DC sputtering. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate, deposition rate, and film quality can be improved.

[0327] Furthermore, when providing the insulator 212 shown in Figure 14B, it is preferable to continuously deposit the insulator 212 and insulator 216 without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of the insulator 212 and insulator 216 with reduced hydrogen content in the film, and further suppresses the incorporation of hydrogen into the film between each deposition process.

[0328] Next, an opening is formed in the insulator 216. This opening includes, for example, grooves and slits. The term "opening" may also refer to the area where the opening is formed. While wet etching may be used to form the opening, dry etching is preferable for microfabrication.

[0329] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source may be, for example, an inductively coupled plasma (ICP) etching apparatus.

[0330] Furthermore, it is preferable to provide an insulator that functions as an etching stopper film when etching the insulator 216 to form an opening, in contact with the lower surface of the insulator 216. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the opening, the insulator may be silicon nitride, aluminum oxide, or hafnium oxide. For example, the insulator 212 shown in Figure 14B may be provided as the insulator. In other words, it is preferable that the insulator 212 has this function.

[0331] After the opening is formed, a conductive film that will become the conductor 244_1 is deposited. It is desirable that the conductive film contains a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, or titanium nitride can be used. Alternatively, a laminated film can be formed of a conductor that has the function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy.

[0332] In this embodiment, a titanium nitride film is formed as the conductive film that will become the conductor 244_1. By placing such a metal nitride below the conductor 244_2, oxidation of the conductor 244_2 by the insulator 216 and the like can be suppressed. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 244_2, it is possible to prevent the metal from diffusing out of the conductor 244_1.

[0333] Next, a conductive film to form the conductor 244_2 is deposited. As the conductive film, tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. In this embodiment, a tungsten film is deposited as the conductive film.

[0334] Next, by performing a CMP treatment, a portion of the conductive film that will become conductor 244_1 and the conductive film that will become conductor 244_2 is removed, exposing the insulator 216. As a result, conductor 244 (conductor 244_1 and conductor 244_2) is formed by leaving conductor 244_1 and conductor 244_2 only in the openings formed in the insulator 216. Note that a portion of the insulator 216 may be removed by this CMP treatment.

[0335] Next, oxide films 230_1A, 230_2A, and 230_3A are sequentially deposited on the insulator 216 and the conductor 244 (see Figures 15A1 and 15A2). It is preferable to deposit oxide films 230_1A, 230_2A, and 230_3A continuously without exposing them to the atmosphere. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230_1A and 230_2A, and to keep the interfaces between oxide films 230_1A and 230_2A and the vicinity thereof, as well as the interfaces between oxide films 230_2A and 230_3A and the vicinity thereof, clean.

[0336] For example, when depositing oxide films 230_1A, 230_2A, and 230_3A by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above oxide films by sputtering, targets such as the In-M-Zn oxide mentioned above can be used.

[0337] Furthermore, when depositing nitrogen-added metal oxide films as oxide film 230_1A and oxide film 230_3A by sputtering, by including nitrogen gas in the sputtering gas during film deposition, it is possible to deposit nitrogen-added metal oxide films even if the target does not contain nitrogen. When depositing metal oxide films with nitrogen gas, a higher nitrogen flow rate ratio can increase the carrier mobility of the metal oxide film.

[0338] The nitrogen flow rate ratio can be appropriately set within a range of 10% to 100% to match the desired characteristics of oxides 230_1 and 230_3. In this case, for example, the sputtering gas can be a mixture of nitrogen gas and argon gas. Alternatively, the sputtering gas may be a mixture of nitrogen gas and oxygen gas, or a mixture of nitrogen gas, oxygen gas, and argon gas.

[0339] Furthermore, when using a target containing nitrogen, it is possible to configure the system so that nitrogen is not used as the sputtering gas, even when depositing a nitrogen-doped metal oxide film.

[0340] If the sputtering gas for the oxide film 230_1A contains oxygen gas, some of the oxygen in the sputtering gas may be supplied to the insulator 216. Therefore, the proportion of oxygen in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

[0341] The sputtering gas described above is preferably highly purified. For example, by using oxygen, nitrogen, or argon gas as the sputtering gas, and purifying it to a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower, and more preferably -120°C or lower, it is possible to prevent moisture and other substances from being incorporated into the metal oxide film as much as possible.

[0342] When oxide film 230_2A is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be more than 30% and 100% or less, preferably 70% or more and 100% or less, an oxygen-rich oxide semiconductor is formed. Transistors using oxygen-rich oxide semiconductors in the channel formation region can achieve relatively high reliability. However, one aspect of the present invention is not limited to this. When oxide film 230_2A is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. Transistors using oxygen-deficient oxide semiconductors in the channel formation region can achieve relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate.

[0343] The method for depositing oxide film 230_3A can be found by referring to the method for depositing oxide film 230_1A.

[0344] Furthermore, it is preferable to deposit oxide films 230_1A, 230_2A, and 230_3A by sputtering without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This suppresses the incorporation of hydrogen into the films between each deposition process for oxide films 230_1A, 230_2A, and 230_3A.

[0345] Furthermore, when depositing metal oxide films with nitrogen added as oxide film 230_1A and oxide film 230_3A by sputtering, and depositing a metal oxide film as oxide film 230_2A by sputtering, oxide film 230_2A is deposited by switching the type of gas introduced into the sputtering apparatus after oxide film 230_1A is deposited, i.e., by stopping the introduction of nitrogen. After depositing oxide film 230_2A, oxide film 230_3A is deposited by switching the type of gas introduced into the sputtering apparatus, i.e., by introducing nitrogen. This makes it possible to continuously deposit oxide films 230_1A, 230_2A, and 230_3A, resulting in excellent mass productivity.

[0346] In this embodiment, nitrogen-added metal oxide films are deposited as oxide films 230_1A and 230_3A by sputtering. Furthermore, oxide film 230_2A is deposited by sputtering using an oxide target with an In:Ga:Zn ratio of 4:2:4.1, an In:Ga:Zn ratio of 1:1:1, an In:Ga:Zn ratio of 1:1:1.2, or an In:Ga:Zn ratio of 1:1:2. Each oxide film may be formed according to the desired properties of oxide films 230_1, 230_2, and 230_3 by appropriately selecting the deposition conditions and atomic ratios.

[0347] Next, it is preferable to perform a heat treatment. The heat treatment should be performed within a temperature range in which oxide films 230_1A, 230_2A, and 230_3A do not undergo polycrystallization, and should be performed between 250°C and 650°C, preferably between 400°C and 600°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0348] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into oxide films 230_1A, 230_2A, and 230_3A.

[0349] In this embodiment, the heat treatment involves a nitrogen gas to oxygen gas flow rate ratio of 4:1 and a treatment at a temperature of 400°C for 1 hour. This heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230_2A. By reducing impurities in the film in this way, the crystallinity of the oxide film 230_2A can be improved, resulting in a denser, more compact structure. This increases the crystalline region in the oxide film 230_2A and reduces in-plane variation of the crystalline region within the oxide film 230_2A. Therefore, in-plane variation in the electrical characteristics of the transistor 200 can be reduced.

[0350] Furthermore, by performing a heat treatment, the hydrogen concentration in the insulator 216 and the oxide film 230_2A can be reduced. In particular, the oxide 230_2 formed from the oxide film 230_2A functions as a channel formation region of the transistor 200. Therefore, a transistor 200 having oxide 230_2 with reduced hydrogen concentration is preferable because it has good reliability.

[0351] Next, a conductive film 242A is deposited on the oxide film 230_3A (see Figures 15A1 and 15A2). For example, a tantalum nitride film may be deposited as the conductive film 242A using the sputtering method. Note that a heat treatment may be performed before depositing the conductive film 242A. This heat treatment may be performed under reduced pressure, and the conductive film 242A may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230_3A can be removed, and the moisture and hydrogen concentrations in the oxide film 230_1A, oxide film 230_2A, and oxide film 230_3A can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C. In this embodiment, the temperature of the heat treatment is set to 200°C.

[0352] Next, an insulating film 291A is deposited on the conductive film 242A (see Figures 15A1 and 15A2). It is preferable to use an insulating film 291A that has the function of suppressing oxygen permeation. For example, an aluminum oxide film or a silicon nitride film may be deposited as the insulating film 291A by sputtering.

[0353] Furthermore, it is preferable to deposit the conductive film 242A and the insulating film 291A by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of the conductive film 242A and the insulating film 291A with reduced hydrogen content, and also suppresses the incorporation of hydrogen into the film between each deposition process. In addition, if a hard mask is provided on the insulating film 291A, the hard mask film can also be deposited continuously without exposure to the atmosphere.

[0354] Next, using lithography, oxide films 230_1A, 230_2A, 230_3A, conductive film 242A, and insulating film 291A are processed into a hollow cylindrical shape to form oxide 230 (oxide 230_1, oxide 230_2, and oxide 230_3), conductor 242a, and insulator 291. Here, oxides 230_1, 230_2, 230_3, conductor 242a, and insulator 291 are formed so that at least a portion of them overlaps with the conductor 244. The above processing can be performed using either a dry etching method or a wet etching method.

[0355] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV light, etc. Alternatively, immersion technology can be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0356] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material is formed on the conductive film 242A, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. Etching of the conductive film 242A, etc., may be performed after removing the resist mask, or it may be performed while the resist mask remains. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the conductive film 242A, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily required to remove the hard mask. In this embodiment, an insulator 291 is used as the hard mask.

[0357] In the following section, an example of a method for forming a hollow cylindrical oxide 230 (oxide 230_1, oxide 230_2, and oxide 230_3), a conductor 242a, and an insulator 291 using lithography will be described.

[0358] First, a resist mask 292 is formed on the insulating film 291A (see Figures 15A1 and 15A2). The resist mask 292 is provided in a region where at least a portion of the resist mask 292 overlaps with the conductor 244.

[0359] Although the top surface shape of the resist mask 292 is shown as circular, it is not limited to this. For example, the top surface may be elliptical, triangular, quadrilateral, or other polygonal shapes. Furthermore, if the top surface is polygonal, the corners of the polygon may be rounded.

[0360] The resist mask 292 can be formed, for example, by exposing the resist through the mask and then removing or leaving the exposed area using a developer. Alternatively, the resist mask 292 may be shrunk by isotropic etching with oxygen plasma. Shrinking the resist mask is sometimes called resist slimming or resist trimming. By shrinking the resist mask 292, the resist mask 292 can be miniaturized.

[0361] Alternatively, the resist mask 292 may be formed, for example, by exposing the resist through a mask on which a line pattern can be formed, exposing the resist again through the mask rotated 90 degrees on the Z axis, and then removing or leaving the exposed area using a developer. This process results in the upper surface of the resist mask 292 having a rounded corner or a circular shape.

[0362] Furthermore, the multi-patterning technique described above may be used to form the resist mask 292. For example, the resist mask 292 may be formed by using the multi-patterning technique to form a resist mask with a line pattern extending in the X direction, and then processing the resist mask with a line pattern extending in the Y direction using the same multi-patterning technique. As a result of this processing, the upper surface shape of the resist mask 292 will have rounded corners or be circular.

[0363] Next, an insulating film 293A is deposited on the resist mask 292 (see Figures 15A1 and 15A2). The thickness of the insulating film 293A corresponds to the width H1 shown in Figure 13D. Therefore, the thickness of the insulating film 293A can be set appropriately according to the design of the transistor 200.

[0364] Next, the insulating film 293A is anisotropically etched to form an insulator 293 (see Figures 15B1 and 15B2). For anisotropic etching of the insulating film 293A, for example, a dry etching method can be used. By anisotropically etching the insulating film 293A, an insulator 293 is formed on the side surface of the resist mask 292. In other words, the insulator 293 can be referred to as a sidewall.

[0365] Next, the resist mask 292 is removed (see Figures 15B1 and 15B2). By removing the resist mask 292, the insulator 293 remains on the insulating film 291A. The shape of the top surface of the opening in the insulator 293 corresponds to the shape of the top surface of the resist mask 292. For example, if the top surface of the resist mask 292 is circular, the top surface of the insulator 293 will be hollow cylindrical, as shown in Figure 15B1. Also, if the top surface of the resist mask 292 is elliptical as described above, the top surface of the insulator 293 will be hollow elliptical. Furthermore, if the top surface of the resist mask 292 is polygonal with rounded corners as described above, the top surface of the insulator 293 will be hollow polygonal with rounded corners.

[0366] Next, using the insulator 293 as a hard mask, a portion of the insulating film 291A, a portion of the conductive film 242A, a portion of the oxide film 230_3A, a portion of the oxide film 230_2A, and a portion of the oxide film 230_1A are processed until the upper surfaces of the insulator 216 and the conductor 244 are exposed (see Figures 16A1 and 16A2). The above processing can be performed using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. Furthermore, the processing of the insulating film 291A, the conductive film 242A, the oxide film 230_3A, the oxide film 230_2A, and the oxide film 230_1A may be carried out under different conditions.

[0367] As a result of the above processing, an insulator 291, a conductor 242a, and an oxide 230 (oxide 230_3, oxide 230_2, and oxide 230_1) are formed whose upper surface shape is the same as or approximately the same as the upper surface shape of the insulator 293 (see Figures 16A1 and 16A2). In other words, in a top view, the ends of the insulator 291, conductor 242a, and oxide 230 coincide. Also, each of the oxide 230, conductor 242a, and insulator 291 becomes a hollow cylindrical shape. As mentioned above, the upper surface shapes of the oxide 230, conductor 242a, and insulator 291 correspond to the upper surface shape of the resist mask 292. Therefore, the above hollow cylindrical shape can be appropriately rephrased to match the upper surface shape of the resist mask 292.

[0368] The above is an example of a method for forming an oxide 230, a conductor 242a, and an insulator 291 having a hollow cylindrical shape using lithography.

[0369] Furthermore, it is preferable that the sides of the oxide 230 and the conductor 242a are perpendicular to the upper surface of the insulator 216. This configuration makes it possible to reduce the area and increase the density when providing multiple transistors 200.

[0370] However, the configuration is not limited to the above, and as explained using Figure 11A, the sides of the oxide 230 and the conductor 242a may be tapered. By making the sides tapered, the coverage of the insulating film that will become the insulator 275a in subsequent processes is improved, and defects such as porosity can be reduced.

[0371] Next, remove the insulator 293 (see Figures 16B1 and 16B2).

[0372] During the process up to this point, impurities may adhere to the sides of the oxide 230, conductor 242a, and insulator 291, or diffuse into their interiors. A step may be taken to remove such impurities. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, or chlorine.

[0373] In order to remove impurities adhering to the side surface of oxide 230 during the etching process described above, a cleaning process is performed. Cleaning methods include wet cleaning using a cleaning solution (which can also be called wet etching), plasma treatment using plasma, and cleaning by heat treatment. These cleaning methods may be combined as appropriate. Note that the grooves may become deeper as a result of this cleaning process.

[0374] Wet cleaning may be performed using aqueous solutions of ammonia water, oxalic acid, phosphoric acid, or hydrofluoric acid diluted with carbonated water or distilled water, or distilled water or carbonated water. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0375] In this specification, an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as diluted ammonia water. The concentration and temperature of the aqueous solution may be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water should be 0.01% to 5%, preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid should be 0.01 ppm to 100 ppm, preferably 0.1 ppm to 10 ppm.

[0376] Furthermore, it is preferable to use a frequency of 200 kHz or higher, preferably 900 kHz or higher, for ultrasonic cleaning. Using this frequency can reduce damage to oxides 230 and other components.

[0377] Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0378] Heat treatment may be performed after the etching or cleaning described above. The heat treatment should be performed at a temperature of 100°C to 450°C, preferably 350°C to 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 230_2, thereby reducing oxygen deficiency. Furthermore, such heat treatment can improve the crystallinity of the oxide 230_2. The heat treatment may also be performed under reduced pressure. Alternatively, after heat treatment in an oxygen atmosphere, continuous heat treatment in a nitrogen atmosphere may be performed without exposure to the atmosphere.

[0379] The above cleaning and heating treatments may be performed before removing the insulator 293.

[0380] Next, an insulating film 275A is formed on the insulator 216, the conductor 244, and the insulator 291 (see Figures 16B1 and 16B2). In other words, the insulating film 275A is formed over the oxide 230, the conductor 242a, and the insulator 291.

[0381] The insulating film 275A is preferably deposited using the ALD method. As mentioned above, it is preferable to deposit the insulating film 275A with a thin film thickness, and it is necessary to minimize variations in film thickness. In this regard, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (e.g., an oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Furthermore, as shown in Figures 16B1 and 16B2, the insulating film 275A needs to be deposited with good coverage on the sides of the openings formed in the oxide 230, conductor 242a, and insulator 291, as well as on the upper surfaces of the conductor 244 and insulator 216. In particular, it is preferable to deposit the film with good coverage on the sides of the oxide 230 and the sides of the conductor 242a. Since the ALD method can deposit layers of atoms one by one on the bottom and sides of the openings, the insulating film 275A can be deposited with good coverage on the openings.

[0382] Furthermore, when the insulating film 275A is deposited by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidizing agents. By using hydrogen-free oxidizing agents such as ozone (O3) and oxygen (O2), the amount of hydrogen diffused into the oxide 230 can be reduced.

[0383] It is preferable to use an insulating film 275A that has the function of suppressing oxygen permeation. For example, an aluminum oxide film can be formed as the insulating film 275A using the ALD method. In this way, the oxide 230 and the conductor 242a can be covered with an insulating film 275A that has the function of suppressing oxygen diffusion. This makes it possible to suppress the direct diffusion of oxygen from the insulator 274, etc., into the oxide 230 and the conductor 242a in a later process.

[0384] Next, microwave processing may be performed in an oxygen-containing atmosphere. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0385] For microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating a high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus should be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. By using a high-density plasma, high-density oxygen radicals can be generated. The power of the power supply that applies microwaves to the microwave processing apparatus should be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the oxide 230_2.

[0386] Further, the microwave treatment described above is preferably performed under reduced pressure, and the pressure may be 10 Pa or more and 1000 Pa or less, preferably 300 Pa or more and 700 Pa or less. Further, the treatment temperature may be 750°C or lower, preferably 500°C or lower, for example, approximately 400°C. Further, after performing the oxygen plasma treatment, heat treatment may be continuously performed without exposure to open air. For example, the temperature may be 100°C or higher and 750°C or lower, preferably 300°C or higher and 500°C or lower.

[0387] Further, for example, the microwave treatment described above may be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) may be greater than 0% and 100% or less, preferably greater than 0% and 50% or less, more preferably 10% or more and 40% or less, and even more preferably 10% or more and 30% or less. As described above, performing the microwave treatment in an atmosphere containing oxygen can reduce the carrier concentration in the oxide 230_2. Further, in the microwave treatment, preventing an excessive amount of oxygen from being introduced into the chamber can suppress an excessive decrease in carrier concentration in the oxide 230_2 and the oxide 230_3.

[0388] Performing microwave treatment in an atmosphere containing oxygen allows oxygen gas to be turned into plasma using microwaves or high frequencies such as RF, and allows the oxygen plasma to act on the oxide 230_2. At this time, the oxide 230_2 can also be irradiated with high frequencies such as microwaves or RF. That is, high frequencies such as microwaves or RF, or oxygen plasma or the like can be allowed to act on the oxide 230_2. By the action of plasma, microwaves, or the like, V in the oxide 230_2 O H can be fragmented, and hydrogen can be removed from the oxide 230_2. That is, V contained in the oxide 230_2 O H can be reduced. Therefore, oxygen vacancies in the oxide 230_2, and V OThis reduces H and lowers the carrier concentration. Furthermore, by supplying oxygen radicals generated in the oxygen plasma or oxygen contained in the insulator 275a to the oxygen vacancies formed in oxide 230_2, the oxygen vacancies in oxide 230_2 can be further reduced, and the carrier concentration can be lowered.

[0389] Furthermore, an insulating film 275A, which has barrier properties against oxygen, is provided in contact with the side surface of the conductor 242a. This suppresses the formation of an oxide film on the side surface of the conductor 242a due to microwave processing.

[0390] Furthermore, since the film quality of the insulating film 275A can be improved, the reliability of the transistor 200 is enhanced.

[0391] Next, an insulating film 250A is deposited on the insulating film 275A (see Figures 16B1 and 16B2). It is preferable to form the insulating film 250A using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, oxidation of the conductor 260 by oxygen contained in the oxide 230 can be suppressed. For example, a hafnium oxide film can be deposited as the insulating film 250A using the thermal ALD method.

[0392] If the microwave treatment described above is not performed after the deposition of insulating film 275A, it is preferable to deposit insulating film 275A and insulating film 250A continuously without exposing them to the atmospheric environment. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to insulating film 275A, and to keep the interface between insulating film 275A and insulating film 250A and its vicinity clean.

[0393] Next, an insulating film 274A is deposited on the insulating film 250A (see Figures 16B1 and 16B2). For example, a silicon oxide film can be deposited as the insulating film 274A using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 274A can be reduced. Note that a heat treatment may be performed before depositing the insulating film 274A. In this embodiment, a silicon oxide film is deposited as the insulating film 274A by a CVD method.

[0394] Next, the insulating films 274A, 250A, and 275A are processed by CMP until the insulator 291 is exposed. Through this CMP process, insulators 274 and 274c are formed from the insulating film 274A, insulators 250a and 250b are formed from the insulating film 250A, and insulators 275a and 275b are formed from the insulating film 275A (see Figures 17A1 and 17A2).

[0395] As described above, the oxide 230, conductor 242a, and insulator 291 each have a hollow cylindrical shape. In other words, the laminate of oxide 230, conductor 242a, and insulator 291 has a hollow cylindrical shape. Insulator 275a is provided in contact with the inner wall of the hollow portion of the laminate, the upper surface of insulator 216, and the upper surface of conductor 244, insulator 250a is provided in contact with the inner wall and bottom surface of the recess formed in insulator 275a, and insulator 274c is provided so as to fill the recess formed in insulator 250a.

[0396] Furthermore, the insulator 275b is provided in contact with the outer side surface of the laminate, the upper surface of the insulator 216, and the upper surface of the conductor 244. In addition, the insulator 250b is provided in contact with the upper surface of the insulator 275b, and the insulator 274 is provided in contact with the upper surface of the insulator 250b.

[0397] The above CMP process may remove a portion of the upper surface of the insulator 291.

[0398] The top surface of insulator 274 is at the same height as the top surfaces of insulators 291 and 274c, respectively. Also, the top heights of insulators 250a, 250b, 275a, and 275b are the same.

[0399] Next, the insulator 291 is removed to expose the upper surface of the conductor 242a (see Figures 17B1 and 17B2). Dry etching or wet etching can be used to remove the insulator 291.

[0400] By removing the insulator 291, the upper surface of the conductor 242a can be exposed in a self-aligned manner. Therefore, the conductors 246b and 246c, which are formed later, can be reliably positioned to be in contact with the conductor 242a without the need for alignment. When removing the insulator 291 by etching, it is preferable to use etching conditions with a high selectivity ratio so that the insulator 274c is not removed by the etching. This allows the insulator 274c to remain after the insulator 291 has been removed.

[0401] Next, conductive films that will become conductors 246b and 246c, and insulating films that will become insulators 277b and 277c are deposited in sequence. Then, a portion of the conductive film and a portion of the insulating film are processed by lithography (Figures 18A1 and 18A2). This processing allows for the formation of conductors 246b, conductors 246c, insulators 277b, and insulators 277c. At this time, convex-shaped portions are formed in the region of conductor 246b that overlaps with conductor 242a, and in the region of conductor 246c that overlaps with conductor 242a. Although wet etching may be used for this processing, dry etching is preferable for fine processing.

[0402] Next, an insulating film that will become an insulating film 278 is formed on the insulating films 277b, 277c, and 274. This insulating film may be formed using the same material as the insulating films that will become insulating films 277b and 277c, or it may be formed using a different material.

[0403] Next, the insulating film that will become the insulator 278 is processed by CMP until the insulators 277b and 277c are exposed. This CMP process forms an insulator 278 with a flattened top surface. Note that this CMP process may remove a portion of the top surface of the insulators 277b and 277c.

[0404] Next, an opening is formed in the region of the insulator 278 that overlaps with insulators 274c, 250a, and 275a (see Figures 18B1 and 18B2). When the resist mask 292 is formed using the multi-patterning technique described above, the same multi-patterning technique is also used to form the opening in the insulator 278.

[0405] Next, insulating film 276A is deposited on insulators 274c, 250a, 275a, 277b, 277c, and 278 (see Figures 19A1 and 19A2). It is preferable to deposit insulating film 276A using the ALD method. The insulating film 276A needs to be deposited with good coverage on the bottom and side surfaces of the openings formed in insulator 278. The ALD method allows for the deposition of atomic layers one by one on the bottom and side surfaces of the openings, thus enabling the deposition of insulating film 276A with good coverage on the openings. In this embodiment, silicon nitride film is deposited as insulating film 276A using the PEALD method.

[0406] Next, the insulating film 276A is anisotropically etched to form an insulator 276 (see Figures 19B1 and 19B2). By forming the insulator 276, a portion of the upper surface of the insulator 250a and the upper surface of the insulator 274c are exposed.

[0407] For the anisotropic etching described above, a dry etching method may be used, for example. By providing an insulator 276 on the side wall of the opening, a physical distance can be maintained between the conductor 246b or conductor 246c and the conductor 260 that will be formed later. Therefore, it is possible to prevent electrical contact between the conductor 246b or conductor 246c and the conductor 260. In other words, it is possible to prevent electrical connection between the conductor 246b or conductor 246c and the conductor 260.

[0408] Next, remove the insulator 274c (see Figures 20A1 and 20A2). Dry etching or wet etching can be used to remove the insulator 274c.

[0409] Furthermore, when removing the insulator 274c by etching, it is preferable to use etching conditions with a high selectivity ratio so that the insulators 250a and 276 are not removed by the etching. This allows the insulators 250a and 276 to remain after the insulator 274c has been removed.

[0410] Next, conductive films 260_1A and 260_2A are deposited in sequence (see Figures 20B1 and 20B2). In this embodiment, a titanium nitride film is deposited as conductive film 260_1A using the ALD method, and a tungsten film is deposited as conductive film 260_2A using the CVD method.

[0411] Next, conductive films 260_1A and 260_2A are processed by CMP until insulators 277b, 277c, and 278 are exposed, thereby forming the conductor 260 (see Figures 21A1 and 21A2). As a result, the conductor 260 is positioned to fill the openings in insulator 276 and the recesses in insulator 250a. In other words, the conductor 260 is positioned to fill the openings formed in the oxide 230 via insulators 275a and 250a.

[0412] In Figure 21A2, the conductor 260 is formed by the remaining conductive film 260_1A in the openings of the insulator 276 and the recesses of the insulator 250a, but the present invention is not limited to this. Depending on the conditions of the CMP treatment described above, or the size or depth of the openings of the insulator 276, parts of the conductive film 260_1A and parts of the conductive film 260_2A may remain in the openings of the insulator 276 and the recesses of the insulator 250a. In this case, the conductor 260 has a laminated structure of a first conductor formed from the conductive film 260_1A and a second conductor formed from the conductive film 260_2A. Also, as shown in Figure 21A2, if only the conductive film 260_1A remains in the openings of the insulator 276 and the recesses of the insulator 250a, it is not necessary to deposit the conductive film 260_2A.

[0413] The above CMP process may remove a portion of insulator 277b, a portion of insulator 277c, and a portion of insulator 278.

[0414] Next, an opening is formed in the insulator 277c that reaches the conductor 246c. Then, a conductive film that will become the conductor 256 is deposited. Next, a CMP treatment is performed to remove a portion of the conductive film, exposing the insulators 277b, 277c, and 278. As a result, the conductor 256 is formed in the opening (see Figures 21B1 and 21B2). Note that the CMP treatment may remove a portion of the insulators 277b, 277c, and 278.

[0415] Next, an insulator 285 is formed on insulators 276, 277b, 277c, 278, conductor 260, and conductor 256 (see Figures 22A1 and 22A2). It is preferable to deposit the insulator 285 using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced. In this embodiment, silicon oxide is deposited as the insulator 285 by sputtering.

[0416] Next, an opening is formed in the insulator 285 (see Figures 22B1 and 22B2). By forming this opening, at least the upper surface of the insulator 276, the upper surface of the conductor 256, and the upper surface of the conductor 260 are exposed. Wet etching may be used to form the opening, but dry etching is preferable for microfabrication. Note that when forming the opening in the insulator 285, a portion of the insulator 276 may be removed.

[0417] Next, conductive films that will become conductors 262a_1 and 262c_1, and conductive films that will become conductors 262a_2 and 262c_2 are deposited in sequence. In this embodiment, titanium nitride films are deposited using the ALD method as conductive films that will become conductors 262a_1 and 262c_1, and tungsten films are deposited using the CVD method as conductive films that will become conductors 262a_2 and 262c_2.

[0418] Next, the conductive films that will become conductors 262a_1 and 262c_1, and the conductive films that will become conductors 262a_2 and 262c_2, are processed by CMP until the insulator 285 is exposed. This forms conductors 262a (conductors 262a_1 and 262a_2) and conductors 262c (conductors 262c_1 and 262c_2) (see Figures 22B1 and 22B2). Note that if conductor 260 and conductors 262a_1 and 262c_1 are formed from the same material, it may be difficult to clearly detect the boundary between conductor 260 and conductors 262a_1 and 262c_1.

[0419] Based on the above, a semiconductor device having the transistor 200 shown in Figures 13A to 13D can be fabricated. As shown in Figures 15A1 to 22B2, the transistor 200 can be fabricated using the semiconductor device fabrication method shown in this embodiment.

[0420] According to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device with less variation in the electrical characteristics of transistors can be provided. According to one aspect of the present invention, a semiconductor device with good reliability can be provided. According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device with a large on-current can be provided.

[0421] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0422] (Embodiment 2) In this embodiment, a memory device according to one aspect of the present invention will be described with reference to the drawings. The memory device according to one aspect of the present invention is a memory device (hereinafter sometimes referred to as an OS memory device) to which a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) is applied.

[0423] <Example of a storage device configuration> Figure 23A shows an example of the configuration of an OS memory device. The storage device 1400 has peripheral circuits 1411 and a memory cell array 1470. Peripheral circuits 1411 are circuits that have the function of writing data to the memory cells of the memory cell array 1470 and reading data from the memory cells of the memory cell array 1470. Peripheral circuits 1411 have row circuits 1420, column circuits 1430, output circuits 1440, and control logic circuits 1460.

[0424] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has the function of precharging the wiring. The sense amplifier has the function of amplifying the data signal read from the memory cell. The above wiring is connected to the memory cells of the memory cell array 1470, and will be described in more detail later. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to access.

[0425] The storage device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from an external source. The storage device 1400 also receives control signals (CE, WE, RES), an address signal ADDR, and a data signal WDATA from an external source. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0426] The control logic circuit 1460 processes externally input control signals (CE, WE, RES) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RES is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals may be input as needed.

[0427] The memory cell array 1470 has multiple memory cells MC arranged in a matrix and multiple wirings. The number of wirings connecting the memory cell array 1470 to the row circuit 1420 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row. Similarly, the number of wirings connecting the memory cell array 1470 to the column circuit 1430 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row.

[0428] Although Figure 23A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this. For example, as shown in Figure 23B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470.

[0429] Using Figures 24A and 24B, we will explain an example of a memory cell configuration that can be applied to the above-mentioned memory cell MC.

[0430] Figure 24A shows an example of a circuit configuration for a two-transistor gain cell type memory cell. The memory cell 1471 shown in Figure 24A has transistor M1 and transistor M2. Transistors M1 and M2 are single-gate transistors.

[0431] The first terminal of transistor M1 is connected to the gate of transistor M2, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The first terminal of transistor M2 is connected to wiring SL, and the second terminal of transistor M2 is connected to wiring BIL.

[0432] The BIL wiring functions as a bit line, and the WOL wiring functions as a word line.

[0433] In memory cell 1471, the gate capacitance of transistor M2 is used as the retention capacitance. In other words, memory cell 1471 can be called a capacitorless memory cell. Therefore, it can also be called a gain cell type memory cell with two transistors and zero capacitance.

[0434] By using an OS transistor as transistor M1, and turning transistor M1 off, it becomes possible to retain the charge of a node where one of the source and drain of transistor M1 is electrically connected to the gate of transistor M2 for an extremely long period of time. Therefore, it is possible to realize a non-volatile memory cell.

[0435] As the memory cell 1471 shown in Figure 24A, the memory cell 100 shown in Figure 2 or the memory cell 100 shown in Figure 13 can be used. In this case, transistor M1 corresponds to transistor 200a, and transistor M2 corresponds to transistor 200b. Also, wiring BIL corresponds to conductor 244, wiring WOL corresponds to conductor 262a, and wiring SL corresponds to conductor 246b.

[0436] Figure 24B shows another example of a two-transistor gain-cell type memory cell circuit configuration. The memory cell 1472 shown in Figure 24B has transistor M1 and transistor M2. Transistors M1 and M2 are single-gate transistors.

[0437] The first terminal of transistor M1 is connected to the gate of transistor M2, the second terminal of transistor M1 is connected to wire WBL, and the gate of transistor M1 is connected to wire WOL. The first terminal of transistor M2 is connected to wire SL, and the second terminal of transistor M2 is connected to wire RBL.

[0438] Wired WBL functions as a write bit line, wired RBL functions as a read bit line, and wired WOL functions as a word line.

[0439] Similar to memory cell 1471, memory cell 1472 uses the gate capacitance of transistor M2 as the retention capacitance. By using an OS transistor as transistor M1, and turning transistor M1 off, it becomes possible to retain the charge of a node where one of the source and drain of transistor M1 is electrically connected to the gate of transistor M2 for an extremely long period of time. Therefore, it is possible to realize a non-volatile memory cell.

[0440] The memory cell 100A shown in Figure 6 can be used as the memory cell 1472 shown in Figure 24B. In this case, transistor M1 corresponds to transistor 200a, and transistor M2 corresponds to transistor 200b. Also, wiring WBL corresponds to conductor 244a, wiring RBL corresponds to conductor 244b, wiring WOL corresponds to conductor 262a, and wiring SL corresponds to conductor 246b.

[0441] Alternatively, memory cell 100B shown in Figure 8 or memory cell 100C shown in Figure 10 can be used as memory cell 1472 shown in Figure 24B. In this case, transistor M1 corresponds to transistor 200a, and transistor M2 corresponds to transistor 200b. Also, wiring WBL corresponds to conductor 246a, wiring RBL corresponds to conductor 246b, wiring WOL corresponds to conductor 262a, and wiring SL corresponds to conductor 244b.

[0442] Furthermore, the memory cell MC is not limited to memory cells 1471 and 1472, and the circuit configuration can be changed.

[0443] By using an OS transistor as transistor M1, transistor M1 can be formed during the BEOL process, which forms the wiring of the memory device. Furthermore, if Si transistors are used in the peripheral circuit 1411 that overlaps the memory cell array 1470, BEOL-Tr technology can be applied. By using this technology, 3D functional circuits can be constructed while maintaining the design rules, enabling high functionality with low power consumption and low cost.

[0444] Figure 24C shows a perspective view of the storage device 1400. The storage device 1400 has layers 1480 and 1490. Figure 24D is a perspective view illustrating the configuration of the storage device 1400, showing layers 1480 and 1490 separately.

[0445] Layer 1480 is a layer containing a transistor. The semiconductor layer containing the channel formation region of the transistor may be formed using semiconductor materials such as single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors, either individually or in combination. Examples of such semiconductor materials include silicon or germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used. Furthermore, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, or silicon germanium, which are applicable to HEMTs (High Electron Mobility Transistors), may also be used.

[0446] Layer 1490 is a layer containing a transistor. The semiconductor layer containing the channel formation region of the transistor may be provided using an oxide semiconductor or a semiconductor material capable of forming a thin film, such as silicon. By using BEOL-Tr technology, layer 1490 can be provided on layer 1480. Thus, a miniaturized memory device 1400 can be realized.

[0447] For example, the transistors included in layer 1480 are Si transistors. In this case, a peripheral circuit 1411 can be provided in layer 1480. Alternatively, the transistors included in layer 1490 are OS transistors. In this case, a memory cell array 1470 can be provided in layer 1480.

[0448] Based on the above, the memory device 1400 can be manufactured using BEOL-Tr technology. Therefore, the occupied area of ​​the memory device 1400 can be reduced.

[0449] The configuration of the peripheral circuit 1411, memory cell array 1470, etc., as shown in this embodiment is not limited to the above. The arrangement or function of these circuits, and the wiring, circuit elements, etc. connected to them, may be changed, deleted, or added as necessary.

[0450] Figure 25 shows an example of the cross-sectional configuration of the storage device 1400 shown in Figure 23A. Figure 25 shows a part of the storage device 1400 shown in Figure 23A.

[0451] As shown in Figure 25, the memory device 1400 has a layer 1480 and a layer 1490 on top of layer 1480. Peripheral circuits 1411 are provided on layer 1480. In other words, layer 1480 can be said to be a layer that includes peripheral circuits 1411. A memory cell array 1470 is provided on layer 1490. The memory cells of the memory cell array 1470 can be the semiconductor device shown in the previous embodiment. In other words, layer 1480 is located below the semiconductor device shown in the previous embodiment.

[0452] Figure 25 shows the transistor 300 included in layer 1480. Transistor 300 functions as part of the sense amplifier described above. In this case, layer 1480 can be considered as a substrate on which a semiconductor circuit including the transistor is formed.

[0453] Furthermore, Figure 25 shows a portion of the memory cell array 1470 located in layer 1490. Specifically, Figure 25 illustrates one memory cell MC located in layer 1490.

[0454] Conductor 262a corresponds to WOL wiring. Conductor 244 corresponds to BIL wiring. Conductor 246b (not shown) corresponds to SL wiring.

[0455] Although Figure 25 shows a configuration in which one layer 1490 containing a memory cell array 1470 is provided, the present invention is not limited to this. For example, multiple layers containing memory cell arrays 1470 may be stacked and provided.

[0456] Figure 26 shows a configuration in which layer 1490_1 containing a memory cell array and layer 1490_2 containing a memory cell array are stacked. Note that the number of stacked layers may be three or more. In this way, by using OS transistors for the transistors that make up the memory cell 100, multiple memory cell arrays 1470 can be stacked. That is, the amount of data that can be stored per unit area can be increased.

[0457] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel or n-channel type.

[0458] In Figure 25, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the top of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0459] Note that the transistor 300 shown in Figure 25 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0460] <Wiring layer> A wiring layer containing interlayer films, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, a conductor functioning as a plug or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0461] For example, on the transistor 300, insulators 320, 322, 324, and 326 are layered in sequence as interlayer films. Insulators 320, 322, 324, and 326 also have conductors 328 and 330 embedded in them, which are electrically connected to the transistor 200. Conductors 328 and 330 function as plugs or wiring.

[0462] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0463] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 25, insulators 350, 352, and 354 are stacked in order. Furthermore, a conductor 356 is formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0464] Insulators that can be used as interlayer films include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0465] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0466] For example, it is preferable that insulators 322, 352, and 354 have an insulator with a low dielectric constant. For example, it is preferable that the insulator has fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or a resin. Alternatively, it is preferable that the insulator has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride, silicon oxide, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide, and a resin. Since silicon oxide and silicon oxynitride are thermally stable, combining them with a resin can create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0467] Furthermore, the electrical characteristics of a transistor using an oxide semiconductor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, the insulator 350, etc., should be an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0468] As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride or silicon nitride, etc., can be used.

[0469] Conductors that can be used for wiring and plugs may include materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0470] For example, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials can be used as conductors 328, conductor 330, and conductor 356, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, with tungsten being preferable. Alternatively, it is preferable to form them with low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0471] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0472] (Embodiment 3) This embodiment describes application examples of a semiconductor device using the storage device shown in the previous embodiment. The storage device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memory, and SSDs (solid-state drives). Figures 27A to 27E schematically show some configuration examples of removable storage devices. For example, the semiconductor device shown in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memory.

[0473] Figure 27A is a schematic diagram of a USB memory device. The USB memory device 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a circuit board 1104. The circuit board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the circuit board 1104. A storage device or semiconductor device as shown in the above embodiment can be incorporated into the memory chip 1105, etc.

[0474] Figure 27B is a schematic diagram of the external appearance of an SD card, and Figure 27C is a schematic diagram of the internal structure of an SD card. The SD card 1110 has a housing 1111, a connector 1112, and a circuit board 1113. The circuit board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the circuit board 1113. The capacity of the SD card 1110 can be increased by also providing a memory chip 1114 on the back side of the circuit board 1113. Alternatively, a wireless chip with wireless communication functionality may be provided on the circuit board 1113. This allows for reading and writing data to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The memory chip 1114 and other components can be incorporated into the storage device or semiconductor device shown in the above embodiment.

[0475] Figure 27D is a schematic diagram of the external appearance of the SSD, and Figure 27E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a circuit board 1153. The circuit board 1153 is housed in the housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are mounted on the circuit board 1153. Memory chip 1155 is the work memory for the controller chip 1156, and for example, a DOSRAM chip can be used. The capacity of the SSD 1150 can be increased by also providing memory chips 1154 on the back side of the circuit board 1153. The storage device or semiconductor device shown in the above embodiment can be incorporated into the memory chip 1154, etc.

[0476] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0477] (Embodiment 4) Figures 28A to 28G show specific examples of electronic devices equipped with a storage device or semiconductor device according to one aspect of the present invention.

[0478] <Electronic Equipment and Systems> A storage device or semiconductor device according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include, for example, information terminals, computers, smartphones, e-book readers, television equipment, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, recording and playback devices, navigation systems, and sound playback devices. Here, "computer" includes not only tablet computers, notebook computers, and desktop computers, but also large computers such as server systems.

[0479] An electronic device according to one aspect of the present invention may have an antenna. By receiving signals with the antenna, the display unit can display images and information. Furthermore, if the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0480] An electronic device according to one aspect of the present invention may have sensors (including those with the function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0481] An electronic device according to one aspect of the present invention can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0482] [Information terminal] A memory device or semiconductor device according to one aspect of the present invention can be used to form a memory device for holding the program of a microcontroller. Therefore, according to one aspect of the present invention, the microcontroller chip can be made smaller.

[0483] Figure 28A illustrates a mobile phone (smartphone), a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. A touch panel is provided on the display unit 5102 as an input interface, and buttons are provided on the housing 5101. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space inside the mobile phone can be effectively utilized. Furthermore, a storage device according to one aspect of the present invention may be used for the storage of the mobile phone. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0484] Figure 28B illustrates a notebook-type information terminal 5200. The notebook-type information terminal 5200 comprises a terminal body 5201, a display unit 5202, and a keyboard 5203. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space inside the notebook-type information terminal can be effectively utilized. Furthermore, a storage device according to one aspect of the present invention may be used for the storage of the notebook-type information terminal. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0485] In the above, smartphones and notebook computers were used as examples of electronic devices, illustrated in Figures 28A and 28B, respectively. However, other types of information terminals can also be used. Examples of other types of information terminals include PDAs (Personal Digital Assistants), desktop computers, and workstations.

[0486] [Game console] Figure 28C shows a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, etc. Housings 5302 and 5303 can be detached from housing 5301. By attaching the connection unit 5305 provided on housing 5301 to another housing (not shown), the video output from the display unit 5304 can be output to another video device (not shown). At this time, housings 5302 and 5303 can each function as operation units. This allows multiple players to play the game simultaneously. A memory device or semiconductor device according to one aspect of the present invention can be incorporated into chips or the like provided on the circuit boards of housings 5301, 5302, and 5303.

[0487] Figure 28D also shows a home console 5400, which is an example of a game console. A controller 5402 is connected to the home console 5400 either wirelessly or via a wired connection.

[0488] By using a miniaturized microcontroller according to one aspect of the present invention in game consoles such as the portable game console 5300 and the home game console 5400, the limited space inside the game console can be effectively utilized. Furthermore, a storage device or semiconductor device according to one aspect of the present invention may be used for the storage of the portable game console. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0489] Figures 28C and 28D illustrate a portable game console and a home game console as examples of game consoles, but the game consoles to which the microcontroller according to one aspect of the present invention is applied are not limited to these. Examples of game consoles to which the microcontroller according to one aspect of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0490] [Large computer] A storage device or semiconductor device according to one aspect of the present invention can be applied to a large-scale computer.

[0491] Figure 28E shows the supercomputer 5500, an example of a large-scale computer. Figure 28F shows the rack-mount computer 5502, which is part of the supercomputer 5500.

[0492] The supercomputer 5500 comprises a rack 5501 and a plurality of rack-mount type computers 5502. The plurality of computers 5502 are housed in the rack 5501. Furthermore, each computer 5502 is provided with a plurality of circuit boards 5504, on which a microcontroller according to one aspect of the present invention can be mounted. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space of the large computer can be effectively utilized. Additionally, a storage device or semiconductor device according to one aspect of the present invention may be used for the storage of the large computer. This increases the storage capacity per unit area of ​​the storage device.

[0493] Figures 28E and 28F illustrate a supercomputer as an example of a large computer, but the large computers to which the microcontroller according to one aspect of the present invention is applied are not limited to this. Examples of large computers to which the microcontroller according to one aspect of the present invention is applied include service-providing computers (servers) and large general-purpose computers (mainframes).

[0494] [electric appliances] Figure 28G shows an example of an electrical appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a casing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0495] A storage device or semiconductor device according to one aspect of the present invention can also be applied to an electric refrigerator 5800. For example, by applying a miniaturized microcontroller according to one aspect of the present invention to the electric refrigerator 5800, the limited space of the electric refrigerator can be effectively utilized.

[0496] While electric refrigerators and freezers were described as an example of electrical appliances, other examples of electrical appliances include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0497] The electronic devices described in this embodiment, their functions, and their effects can be appropriately combined with descriptions of other electronic devices.

[0498] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0499] [Explanation of symbols] 10 Semiconductor Devices 100A: Memory cell, 100B: Memory cell, 100C: Memory cell, 100: Memory cell, 200a: Transistor, 200b: Transistor, 200: Transistor, 212: Insulator, 216: Insulator, 230_1: Oxide, 230_1A: Oxide film, 230_2: Oxide, 230_21: Region, 230_22: Region, 230_2A: Oxide film, 230_3: Oxide, 230_3A: Oxide film, 230: Oxide, 242a: Conductor, 242A: Conductive film, 242b: Conductor, 244_1: Conductor, 244_2: Conductor, 244a: Conductor, 244b: Conductor Electrode, 244c: Conductor, 244: Conductor, 246a: Conductor, 246b: Conductor, 246b1: Convex shape part, 246c: Conductor, 246c1: Convex shape part, 246: Conductor, 247: Insulator, 250a: Insulator, 250A: Insulating film, 250b: Insulator, 250: Insulator, 254a: Insulator, 254b: Insulator, 256: Conductor, 260_1A: Conductive film, 260_2A: Conductive film, 260: Conductor, 262a: Conductor, 262a_1: Conductor, 262a_2: Conductor, 262c: Conductor, 262c_1: Conductor, 262c_2: Conductor, 264b: Region 313: Semiconductor region, 264c: region, 274A: insulating film, 274c: insulator, 274: insulator, 275a: insulator, 275A: insulating film, 275b: insulator, 276A: insulating film, 276: insulator, 277b: insulator, 277c: insulator, 278: insulator, 285: insulator, 291A: insulating film, 291: insulator, 292: resist mask, 293A: insulating film, 293: insulator, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator Edge body, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 1100: USB memory, 1101: housing, 1102: cap, 1103: USB connector, 1104: circuit board, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: circuit board, 1114: memory chip, 1115: controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: circuit board, 1154: memory chip,1155: Memory chip, 1156: Controller chip, 1400: Storage device, 1411: Peripheral circuit, 1420: Row circuit, 1430: Column circuit, 1440: Output circuit, 1460: Control logic circuit, 1470: Memory cell array, 1471: Memory cell, 1472: Memory cell, 1480: Layer, 1490_1: Layer, 1490_2: Layer, 1490: Layer, 5100: Information terminal, 5101: Enclosure, 5102: Display unit, 5200: Notebook-type information terminal, 5 201: Main unit, 5202: Display unit, 5203: Keyboard, 5300: Portable game console, 5301: Cabinet, 5302: Cabinet, 5303: Cabinet, 5304: Display unit, 5305: Connection unit, 5306: Operation keys, 5400: Home game console, 5402: Controller, 5500: Supercomputer, 5501: Rack, 5502: Calculator, 5504: Circuit board, 5800: Electric refrigerator / freezer, 5801: Cabinet, 5802: Door for refrigerator compartment, 5803: Door for freezer compartment,

Claims

1. A first conductor and A first oxide and a second oxide are electrically connected to the first conductor and have an opening, A second conductor electrically connected to the first oxide, A first insulator is disposed inside the opening in the first oxide, The third conductor on the first insulator, A fourth conductor electrically connected to the third conductor, A fifth conductor electrically connected to the second oxide, A second insulator is disposed inside the opening in the second oxide, The sixth conductor on the second insulator, A seventh conductor electrically connected to the sixth conductor, An eighth conductor electrically connected to the second conductor and the seventh conductor, It has, The fourth conductor is provided in the same layer as the seventh conductor, A semiconductor device in which the direction in which the fourth conductor extends is the same as the direction in which the fifth conductor extends.

2. In claim 1, A semiconductor device in which the first conductor extends in a direction perpendicular to the direction in which the fourth conductor extends.

3. In claim 1, The present invention further comprises a ninth conductor and a tenth conductor. The ninth conductor is provided between the first oxide and the second conductor. The side surface of the ninth conductor coincides with the side surface of the first oxide. The tenth conductor is provided between the second oxide and the fifth conductor. A semiconductor device wherein the side surface of the tenth conductor coincides with the side surface of the second oxide.

4. In claim 3, The second conductor has a convex-shaped portion, The convex-shaped portion is a semiconductor device that is in contact with the ninth conductor.

5. In claim 1, A semiconductor device wherein, in cross-sectional view, the side surface of the first oxide has a tapered shape.

6. A first conductor and a second conductor, A first oxide having an opening and electrically connected to the first conductor, A third conductor electrically connected to the first oxide, A first insulator is disposed inside the opening in the first oxide, The fourth conductor on the first insulator, A fifth conductor electrically connected to the fourth conductor, A second oxide having an opening and electrically connected to the second conductor, A sixth conductor electrically connected to the second oxide, A second insulator is disposed inside the opening in the second oxide, The seventh conductor on the second insulator, An eighth conductor electrically connected to the seventh conductor, A ninth conductor electrically connected to the third conductor and the eighth conductor, It has, The fifth conductor is provided in the same layer as the eighth conductor, A semiconductor device in which the direction in which the fifth conductor extends is the same as the direction in which the sixth conductor extends.

7. In claim 6, The first conductor extends in a direction perpendicular to the direction in which the fifth conductor extends, A semiconductor device in which the second conductor extends in a direction perpendicular to the direction in which the sixth conductor extends.

8. In claim 6, The present invention further comprises a tenth conductor and an eleventh conductor. The tenth conductor is provided between the first oxide and the third conductor. The side surface of the tenth conductor coincides with the side surface of the first oxide. The eleventh conductor is provided between the second oxide and the sixth conductor. A semiconductor device wherein the side surface of the eleventh conductor coincides with the side surface of the second oxide.

9. In claim 6, A semiconductor device wherein, in cross-sectional view, the side surface of the first oxide has a tapered shape.

10. A semiconductor device according to any one of claims 1 to 9, and a layer including peripheral circuits, The aforementioned layer is located below the semiconductor device, The peripheral circuit is a memory device having the function of writing data to the semiconductor device and reading data from the semiconductor device.

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