Power transistor with soft recovery body diode

Abstract

To provide a semiconductor device.SOLUTION: A semiconductor device comprises: a substrate; a drift layer on the substrate; one or more injection regions in the drift layer, configured to provide a vertical transistor device configured to direct current in a first direction and a body diode configured to direct current in a second direction opposite the first direction; and a recombination region that comes into contact with one or more injection regions of the drift layer and have a higher density of minority carrier recombination centers than the drift layer.SELECTED DRAWING: Figure 5A

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 110,027, filed on 2 December 2020, and U.S. Patent Application No. 17 / 208,271, filed on 22 March 2021, the entire disclosures of the said applications are incorporated herein by reference.

[0002] This disclosure relates to semiconductor devices, and more particularly to power transistors including body diodes having soft recovery characteristics, and methods for manufacturing power transistors. [Background technology]

[0003] Transistors have many applications in modern electronic devices. Power transistors, which are capable of handling high voltages and currents, are often used in switching circuits that deliver power to loads. Transistors used in power switching circuits generally need to be able to conduct current in both directions. Therefore, antiparallel diodes are provided in conjunction with transistors in power switching circuits. In the case of a metal-oxide-semiconductor field-effect transistor (MOSFET), the anode of the antiparallel diode is coupled to the drain of the MOSFET, and the cathode of the antiparallel diode is coupled to the source of the MOSFET. This allows current to flow from the drain to the source in the forward conduction mode of the MOSFET, and from the source to the drain via the antiparallel diode in the reverse conduction mode. When the antiparallel diode switches between conduction and blocking, the performance characteristics of the antiparallel diode determine the speed at which such transitions can occur and the resulting switching losses. It is generally desirable to minimize both the transition time between operating modes and the switching losses. Therefore, there is a current need for anti-parallel diodes, which are used in conjunction with transistors to improve switching speed and reduce switching losses. [Overview of the project] [Means for solving the problem]

[0004] In one embodiment, the transistor includes a substrate, a drift layer on the substrate, and a junction implant in the drift layer opposite the substrate. The junction implant includes a body well and a source well within the body well. The source contact electrically contacts the source well and the body well. The drain contact electrically contacts the substrate. An insulating layer is provided over the drift layer, extending over the body well and part of the source well. The gate contact is located on the insulating layer. The softness factor of the body diode between the source contact and the drain contact is greater than 0.5. By providing the transistor such that the softness factor of the body diode is greater than 0.5, the switching performance of the body diode, and therefore the switching loss of the transistor, is significantly reduced when used in bidirectional conduction applications.

[0005] In one embodiment, the transistor includes a substrate, a drift layer on the substrate, and a junction implant in the drift layer opposite the substrate. The junction implant includes a body well and a source well within the body well. The source contact electrically contacts the source well and the body well. The drain contact electrically contacts the substrate. An insulating layer is located on the drift layer, extending over a portion of the body well and the source well. A gate contact is located on the insulating layer. Between the source contact and the drain contact, the body well, the drift layer, and the substrate form a body diode. In the forward-biased operating mode of the body diode, the concentration of minority carriers at the interface between the body well and the drift layer is lower than the concentration of minority carriers at the interface between the drift layer and the substrate. By designing the transistor to produce the aforementioned minority carrier profile in the drift layer of the body diode, the snappiness of the body diode is significantly reduced, thereby improving the switching performance of the transistor when used in bidirectional conduction applications.

[0006] In one embodiment, the semiconductor device includes a substrate, a drift layer, and one or more injection regions in the drift layer. The drift layer has a carrier lifetime between 1 μs and 20 μs. One or more injection regions are configured to provide a vertical transistor device and a body diode. The vertical transistor device is configured to conduct current in a first direction, while the body diode is configured to conduct current in a second direction opposite to the first direction. By providing a drift layer with a carrier lifetime between 1 μs and 20 μs, the softness of the body diode can be increased, which in turn can reduce the switching losses associated with the semiconductor device.

[0007] In one embodiment, the softness factor of the body diode is between 0.5 and 10. As described above, this can reduce the switching losses associated with the semiconductor device. The semiconductor device may include a recombination region in the drift layer, which is 1 × 10⁻¹⁶. 13 cm -3 ~1 × 10 18 cm -3 This is an area with a density of minority carrier recombination centers, located between these points. The body diode may be configured to be a non-punch-through diode.

[0008] In one embodiment, the semiconductor device includes a substrate, a drift layer, one or more injection regions in the drift layer, and a recombination region in the drift layer. One or more injection regions are configured to provide a vertical transistor device and a body diode. The vertical transistor device is configured to conduct current in a first direction, while the body diode is configured to conduct current in a second direction opposite to the first direction. The recombination region is in contact with one or more injection regions in the drift layer and has a capacity of 1 × 10⁻⁶. 13 cm -3 ~1 × 10 18 cm -3It has a density of minority carrier recombination centers, which is between [a certain point]. The recombination region can increase the softness of the body diode, thereby reducing the switching losses associated with the semiconductor device.

[0009] In one embodiment, the softness factor of the body diode is between 0.5 and 10. The drift layer may have a carrier lifetime between 1 μs and 20 μs. The body diode may be configured to be a non-punch-through diode.

[0010] In certain embodiments, any of the embodiments described above may be combined for further advantages.

[0011] Those skilled in the art will understand the scope of this disclosure and, after reading the following detailed description of preferred embodiments in relation to the accompanying drawings, will be able to see further embodiments therefrom.

[0012] The accompanying drawings incorporated herein and forming part thereof illustrate several aspects of this disclosure and, together with the description, serve to illustrate the principles of this disclosure. [Brief explanation of the drawing]

[0013] [Figure 1] This is a cross-sectional view of a transistor according to one embodiment of the present disclosure. [Figure 2] This is a graph showing the reverse recovery of the body diode in a transistor according to one embodiment of the present disclosure. [Figure 3A] This figure shows the electric field in the drift layer of a punch-through diode according to one embodiment of the present disclosure. [Figure 3B] This figure shows the electric field in the drift layer of a non-punch-through diode according to one embodiment of the present disclosure. [Figure 4] This is a cross-sectional view of a transistor body diode according to one embodiment of the present disclosure. [Figure 5A] This is a cross-sectional view of a transistor according to one of the various embodiments of this disclosure. [Figure 5B] This is a cross-sectional view of a transistor according to one of the various embodiments of this disclosure. [Figure 5C] This is a cross-sectional view of a transistor according to one of the various embodiments of this disclosure. [Figure 5D] This is a cross-sectional view of a transistor according to one of the various embodiments of this disclosure. [Figure 5E] This is a cross-sectional view of a transistor according to one of the various embodiments of this disclosure. [Figure 6] This graph shows the doping profiles for multiple implants in a transistor according to one embodiment of the present disclosure. [Figure 7] This is a flowchart illustrating a method for manufacturing a transistor according to one embodiment of the present disclosure. [Figure 8] This graph shows the performance of a transistor body diode according to one embodiment of the present disclosure. [Figure 9] This figure shows a semiconductor device according to one embodiment of the present disclosure. [Figure 10] This figure shows a semiconductor device according to one embodiment of the present disclosure. [Figure 11] This figure shows a semiconductor device according to one embodiment of the present disclosure. [Figure 12] This figure shows a transistor according to one embodiment of the present disclosure. [Figure 13A] This figure shows a semiconductor device according to one embodiment of the present disclosure. [Figure 13B] Figure 13A is a graph showing the electric field in a vertical semiconductor device, illustrating the example. [Figure 13C] Figure 13A is a graph showing the electric field and drain-source current at the bottom of the drift layer when the drain-source voltage increases in the blocked state in the embodiment shown. [Figure 14A] This figure shows a semiconductor device according to one embodiment of the present disclosure. [Figure 14B] Figure 14A is a graph showing the electric field in a semiconductor device for the example shown. [Figure 14C]Figure 14A is a graph showing the electric field and drain-source current at the bottom of the drift layer when the drain-source voltage increases in the blocked state in the embodiment shown. [Figure 15A] This figure shows a semiconductor device according to one embodiment of the present disclosure. [Figure 15B] Figure 15A is a graph showing the electric field in a semiconductor device, illustrating the example. [Figure 15C] Figure 15A is a graph showing the electric field and drain-source current at the bottom of the drift layer when the drain-source voltage increases in the blocked state in the embodiment shown. [Figure 16A] This figure shows a semiconductor device according to one embodiment of the present disclosure. [Figure 16B] Figure 16A is a graph showing the electric field in a semiconductor device for the example shown. [Figure 16C] Figure 16A is a graph showing the electric field and drain-source current at the bottom of the drift layer when the drain-source voltage increases in the blocked state in the embodiment shown. [Figure 17A] This figure shows a semiconductor device according to one embodiment of the present disclosure. [Figure 17B] Figure 17A is a graph showing the relative stepwise doping concentration levels across various layers of a vertical semiconductor device in an example. [Figure 17C] Figure 17A is a graph showing the electric field and drain-source current at the bottom of the drift layer when the drain-source voltage increases in the blocked state in the embodiment shown. [Figure 18A] This figure shows a power device according to one embodiment of the present disclosure. [Figure 18B] Figure 18A is a graph showing the relative stepwise doping concentration levels across various layers of a vertical semiconductor device, illustrating the example shown. [Figure 19] This graph shows the response of the body diode in various embodiments of the present disclosure. [Figure 20] This graph shows the response of the body diode in various embodiments of the present disclosure. [Figure 21] This graph shows the response of the body diode in various embodiments of the present disclosure. [Modes for carrying out the invention]

[0014] The embodiments described below provide the information necessary to enable those skilled in the art to carry out the embodiments and to demonstrate the best mode for carrying them out. By reading the following description in reference to the figures in the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and recognize the applications of these concepts that are not specifically addressed herein. It should be understood that these concepts and applications are within the scope of this disclosure and the accompanying claims.

[0015] The terms "first," "second," etc., may be used herein to describe various elements, but it will be understood that these elements are not limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be called the second element, and similarly, the second element may be called the first element. Where used herein, the term "and / or" includes any and all combinations of one or more of the related enumerations.

[0016] When an element such as a layer, region, or substrate is said to be "on" another element or to extend "onto" another element, it will be understood that it can be directly on or extend directly onto another element, or that intervening elements may exist. In contrast, when an element is said to be "directly on" another element or to extend "directly onto" another element, there are no intervening elements. Similarly, when an element such as a layer, region, or substrate is said to be "over" another element or to extend "over" another element, it will be understood that it can be directly on or extend directly onto another element, or that intervening elements may exist. In contrast, when an element is said to be "directly over" another element or to extend "directly over" another element, there are no intervening elements. When an element is said to be "connected" or "coupled" to another element, it is understood that the element can be directly connected or coupled to the other element, or that there may be an intermediary element. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there is no intermediary element.

[0017] Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship between one element, layer, or region and another, as shown in the figure. It will be understood that these terms and the terms described above are intended to encompass various orientations of the device, in addition to the orientation shown in the figure.

[0018] The terminology used herein is intended to describe only specific embodiments and is not intended to limit the disclosure. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context explicitly states otherwise. Where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the described features, integers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as they would be generally understood by those skilled in the art to which this disclosure belongs. Terms used herein should be construed to have meanings consistent with their meanings in the context of this specification and in the relevant art, and it will be further understood that they should not be construed in an idealized or overly formal sense unless explicitly defined herein.

[0020] FIG. 1 is a cross-sectional view of a transistor 10 according to an embodiment of the present disclosure. The transistor 10 includes a substrate 12 and a drift layer 14 on the substrate 12. A body well 16 is provided on a surface of the drift layer 10 opposite to the substrate 12. A source well 18 is provided in the body well 16 so as to be within the body well 16. A contact well 19 is also provided in the body well 16 so as to be adjacent to the source well 18 in the body well 16. A junction field-effect transistor (JFET) region 20 is also provided on the surface of the drift layer 14 opposite to the substrate 12, adjacent to the body well 16. A source contact 22 is provided on the drift layer 14 on the side opposite to the substrate 12 so as to be in electrical contact with the source well 18 and the body well 16 via the contact well 19. A drain contact 24 is provided on the substrate 12 so as to be in electrical contact with the substrate 12. A gate insulator 26 is provided on the surface of the drift layer 14 opposite to the substrate 12 so as to be over the JFET region 20, a portion of the body well 16, and a portion of the source well 18. A gate contact 28 is provided on the gate insulator 26.

[0021] In one embodiment, the transistor 10 is an n-type device in which the substrate 12, the drift layer 14, the source well 18, and the JFET region 20 are n-type, whereas the body well 16 and the contact well 19 are p-type. The doping concentration of the substrate 12 is 1×10 18 cm -3 ~1×10 21 cm -3 can be between. The thickness of the substrate 12 can be between 10 μm and 360 μm. The doping concentration of the drift layer 14 is 1×10 17 cm -3 ~5×10 13 cm -3It may be between these ranges. The doping concentration of the drift layer 14 may be continuous along its thickness (from top to bottom as shown in Figure 1), or it may vary depending on the doping profile that changes along its thickness. The thickness of the drift layer 14 may be between 2 μm and 200 μm. The doping concentration of the drift layer 14 may be determined according to the thickness of the drift layer 14. In particular, the doping concentration may be inversely proportional to the thickness of the drift layer 14. The body well 16 is 1 × 10 16 cm -3 ~3×10 19 cm -3 The doping concentration may be between 0.2 μm and 4 μm. The source well 18 may have a thickness of 1 × 10 18 cm -3 ~1 × 10 21 cm -3 The doping concentration may be between 0.1 μm and 2 μm. The JFET region 20 is 1 × 10 16 cm -3 ~2×10 17 cm -3 The doping concentration may be between 1 × 10¹⁶. The JFET region 20 may have a thickness between 0.2 μm and 4 μm. Although the transistor 10 is described above as an n-type device, the principles of this disclosure are equally applicable to p-type devices. In one embodiment, the transistor 10 is a silicon carbide (SiC) device. However, the principles of this disclosure are equally applicable to any material system, in particular wide-bandgap material systems. With respect to either the doping concentration range or the thickness range described above, this disclosure intends to use any discrete point within that range or any subrange within a wider range. For example, this disclosure describes a doping concentration of the drift layer 14 where 1 × 10¹⁶ 17 cm -3 ~5×10 13 cm -3 During, 1 x 10 17 cm -3 Or nearby, 5x10 13 cm -3 Or nearby, 1 x 10 16 cm -3 ~5×10 13 cm-3 During, 1 x 10 17 cm -3 ~1 × 10 15 cm -3 It is intended to be a subrange between or within any other discrete point or broader exemplary range. The same applies to all ranges of doping concentrations and thickness ranges shown herein. Contact well 19 may have a thickness between 0.1 μm and 2 μm. The doping concentration of contact well 19 is 1 × 10⁻⁶. 16 cm -3 ~1 × 10 21 cm -3 It could be between these two points.

[0022] In one embodiment, the transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET). In such an embodiment, the gate insulator 26 may be an oxide layer. In another embodiment, the transistor is a metal-insulator-semiconductor field-effect transistor (MISFET).

[0023] Transistor 10 can be a power device capable of interrupting high voltages and conducting high currents. In particular, depending on the application, transistor 10 may have a breakdown voltage between 350V and 20kV. According to this range of breakdown voltage, the on-state resistance of transistor 10 is 0.3mΩ·cm. 2 ~100mΩ·cm 2 It can be between these values. That is, with respect to a breakdown voltage of 350V, the on-state resistance of transistor 10 is 0.3mΩ·cm. 2 It may be less than 20kV, while the on-state resistance of transistor 10 is 100mΩ·cm with respect to a breakdown voltage of 20kV. 2 It may be less than 90 mΩ·cm for a breakdown voltage of 15 kV. Another example is 90 mΩ·cm. 2 With an on-state resistance of less than 70 mΩ·cm and a breakdown voltage of 10 kV, the on-state resistance is less than 70 mΩ·cm. 2 With an on-state resistance of less than 10 mΩ·cm and a breakdown voltage of 3.3 kV, the on-state resistance is less than 10 mΩ·cm. 2Examples of on-state resistances include those less than a certain value. On-state resistances can vary between these minimum and maximum values ​​depending on their breakdown voltage.

[0024] As mentioned above, transistors used for power switching applications should conduct current in both directions. This can be achieved by an external diode antiparallel coupled between the source contact 22 and the drain contact 24 (anode to source, cathode to drain), but the same result can also be achieved using an internal body diode formed within the structure of the transistor 10. As shown in Figure 1, a body diode 30 is formed on the right side of the device between the source contact 22 and the drain contact 24. The body diode 30 is a PiN diode that includes the source contact 22 as the anode, a body well 16, a contact well 19, a drift layer 14, a substrate 12, and the drain contact 24 as the cathode. By using the body diode 30 to enable bidirectional current conduction, space is saved by eliminating the need for an external diode. However, the body diode 30 may not be optimized for switching. In particular, the body diode 30 may experience a high degree of snappiness, which can increase switching time and switching losses, as will be discussed in detail below.

[0025] The snappiness of a diode characterizes its reverse recovery. For illustrative purposes, Figure 2 is a graph showing the forward current and voltage across a diode when switching from forward conduction to reverse bias or blocking. Before time t0, the diode is forward biased, and therefore conducts current from the anode to the cathode. Thus, the voltage across the diode is approximately zero. When forward biased, excess minority carriers are injected into the drift region of the diode so that the drift region contains excess minority carriers. At time t0, the diode is switched from forward bias to reverse bias by changing the voltage supplied at its anode and cathode. Therefore, the current through the diode begins to decrease as the excess minority carriers decrease. Due to the current flow by the excess minority carriers, the voltage across the diode remains the same. At time t1, the current through the diode switches from positive current to negative current. The voltage across the diode remains the same. As the accumulated excess minority carriers in the drift region begin to decrease, the resistance of the region begins to increase. Therefore, at time t2, the voltage across the diode begins to decrease, while the current continues to decrease. At this point, a depletion region begins to form. At time t3, when there are almost no excess minority carriers left in the drift region, the reverse current through the diode reaches its maximum value. At time t4, the negative voltage across the diode reaches its peak value. The current through the diode and the voltage across the diode continue to increase until time t5, when they stabilize at zero and the reverse voltage, respectively.

[0026] During the reverse recovery process, the capacitance across the diode is determined by the diffusion and depletion capacitances of the diffusion and depletion regions within the diode, respectively. As the depletion region grows, the values ​​of the diffusion and depletion capacitances change. If the depletion region penetrates the diode to the point where the diffusion region no longer exists, the diffusion capacitance suddenly drops to zero, causing a large change in the overall capacitance of the diode, which can lead to ringing and distortion.

[0027] The time from when the current through the diode passes through zero (t1) until it reaches its negative peak value (t3) is t s It is shown that the current passing through the diode reaches its negative peak value (t3) when the current is 0.2·I RRM (t 5 The time until it recovers is t f It is shown as t f and t s The ratio (t) f / t s ) is defined herein as the softness factor S1 of the diode. The softness factor is inversely correlated with the snappiness of the diode. Therefore, a higher softness factor is desirable. A secondary softness factor S2 is defined herein.

number

[0028] Conventionally, those skilled in the art design transistors based on several desired characteristics of the transistor itself, such as breakdown voltage and on-state resistance. In other words, those skilled in the art generally do not design transistors with the performance of the body diode in mind. The inventors of this disclosure have found that one or more characteristics of the body diode of a transistor can be significantly improved with little or no impact on the performance of the transistor. In particular, the snappiness of the body diode in a transistor can be significantly reduced while maintaining the performance of the transistor.

[0029] Several adjustments are made to improve the snappiness of the body diode 30 within transistor 10. First, transistor 10 is designed so that the body diode 30 is a non-punch-through diode. As discussed herein, a non-punch-through diode is defined as a diode in which, at the diode's breakdown voltage, the depletion region formed in the diode's drift layer does not penetrate the substrate or adjacent n+ layers. In the case of the body diode 30, this means that, at its breakdown voltage, the depletion region remains within the drift layer 14 and does not penetrate the substrate 12. The body diode 30 may be designed to be non-punch-through by changing the doping concentration and / or thickness of the drift layer 14 compared to a conventional design in which these parameters are optimized for the desired breakdown voltage and on-state resistance of transistor 10. In particular, the thickness and doping concentration of the drift layer 14 may be increased compared to a conventional design to ensure that the depletion region of the body diode 30 remains within the drift layer 14 when reverse-biased. Therefore, with respect to a given breakdown voltage of transistor 10, the drift layer 14 is doped thicker and more densely than its conventional counterpart.

[0030] To provide a non-punch-through diode, the thickness of the drift layer 14 and the doping concentration can be determined using the following equation. Equation (1) is equal to the breakdown voltage BV diode and doping concentration N D The relationship is shown. Equation (2) is the maximum width W of the depletion region. d,max and doping concentration N D This shows the relationship.

number

[0031] Figures 3A and 3B show the electric fields within the drift layer 14 for a punch-through diode and a non-punch-through diode, respectively. In particular, Figure 3A shows a line representing the electric field within the drift layer 14 for a punch-through diode as described herein, and Figure 3B shows a line representing the electric field within the drift layer 14 for a non-punch-through diode. As shown, for a non-punch-through diode, the electric field drops to zero before reaching the interface between the drift layer 14 and the substrate 12. For a punch-through diode, the electric field remains at a significant level at the interface between the drift layer 14 and the substrate 12, and therefore "penetrates" the drift layer 14. As discussed herein, the transistor 10 can be designed to provide the body diode 30 as a non-punch-through diode, which can improve the snappiness of the body diode 30. As discussed herein, one way to achieve a non-punch-through-body diode 30 is to increase the thickness of the drift layer 14, which is why the drift layer 14 in Figure 3B is thicker than the drift layer 14 in Figure 3A. However, other design considerations also apply.

[0032] Applying conventional design rules to transistor 10 would affect the selection of the thickness and doping concentration of the drift layer 14 to minimize the on-state resistance for a given breakdown voltage. While this may lead to optimization of these features, it could result in the body diode 30 becoming a punch-through diode. The inventors of this disclosure have found that the thickness and doping concentration of the drift layer 14 can be selected such that the body diode 30 is a non-punch-through diode while maintaining the desirable, perhaps slightly higher, on-state resistance of transistor 10 at a given breakdown voltage. By providing the body diode 30 as a non-punch-through diode, carriers can remain in the drift layer 14 for a longer period because they are not rapidly cleared at the interface with the substrate 12 due to the decrease in the electric field in this area. Furthermore, by providing the body diode 30 as a non-punch-through diode, the diffusion capacitance does not abruptly drop to zero, thereby reducing ringing and distortion that would otherwise occur during reverse recovery due to large changes in the diffusion capacitance of the body diode 30.

[0033] In addition to or independently of providing the body diode 30 as a non-punch-through diode, the distribution profile of minority carriers within the body diode 30 is also altered when forward-biased. Therefore, Figure 4 shows a cross-section of the body diode 30 isolated from the transistor 10. The dashed line shows the distribution of minority carriers when forward-biased, when the body diode 30 is provided in a conventional manner without the improvements discussed herein. The solid line shows the distribution of minority carriers when forward-biased for the body diode 30 when the improvements discussed herein are made. As shown, without the improvements discussed herein, the concentration of minority carriers is higher at the interface between the body well 16 and the drift layer 14 than at the interface between the drift layer 14 and the substrate 12. This can lead to a decrease in the performance of the diode during reverse recovery. In particular, as the body diode 30 enters reverse bias, as shown by the dashed line, if there is a high concentration of minority carriers at the interface between the body well 16 and the drift layer 14, it takes longer to clear these minority carriers and begins to form a depletion region. This results in a situation like that shown in Figure 2. s This is extended, and as a result, snappiness increases (softness factor t f / t s (The concentration decreases) and performance deteriorates. Furthermore, as the depletion region grows, if there is a relatively low concentration of minority carriers at the interface between the drift layer 14 and the substrate 12, as shown by the dashed line, these carriers may be swept away from the drift layer 14 and thus penetrate the substrate 12 into the depletion region. As mentioned above, this also degrades performance due to the sudden disappearance of diffusion capacitance within the body diode 30. Furthermore, as shown in Figure 2, as the concentration of minority carriers near the interface between the drift layer 14 and the substrate 12 increases, t f This extends the softness factor, thereby reducing snappiness. f / t s(This increases). Therefore, as shown by the solid line, it is desirable to have a lower concentration of minority carriers at the interface between the body well 16 and the drift layer 14, and a higher concentration of minority carriers at the interface between the drift layer 14 and the substrate 12. Generally, it is desirable to have a minority carrier concentration with a positive gradient (on average) in the drift layer 14 between the body well 16 and the substrate 12.

[0034] There are several ways to achieve the desired minority carrier profile described above. In one embodiment, the carrier lifetime of the drift layer 14 is increased to increase the concentration of minority carriers at and near the interface between the drift layer 14 and the substrate 12. In SiC, carbon vacancies can shorten the carrier lifetime by forming recombination centers for minority carriers. To reduce carbon vacancies, high-temperature oxidation of the drift layer 14 is performed, as will be discussed in detail below, thereby increasing the carrier lifetime throughout the drift layer 14. In various embodiments, the minority carrier lifetime in the drift layer 14 may be intentionally increased to be between 0.5 μs and 20 μs. In particular, this disclosure intends to use any discrete value within the exemplary range of minority carrier lifetimes shown above, or within any sub-range of a broader range. For example, in various embodiments, the minority carrier lifetime of the drift layer 14 may be between 1 μs and 20 μs, 10 μs and 20 μs, between 1 μs and 5 μs, between 5 μs and 10 μs, between 15 μs and 20 μs, between 3 μs and 10 μs, or any other subrange or discrete point within a broader exemplary range. Those skilled in the art will understand Z 1 / 2 You will understand that trap density is inversely correlated with carrier lifetime in SiC. Therefore, increasing the carrier lifetime of drift layer 14 is Z 1 / 2 This may involve reducing the trap density. In various embodiments, the Z of the drift layer 14 1 / 2 The trap density is 5 × 10 13 cm -3 Less than 1 × 10 13 cm -3 Less than 5 x 10 12 cm -3 Less than 1 × 1012 cm -3 less than, and 1×10 10 cm -3 can be reduced to as low as approximately.

[0035] In addition to improving the carrier lifetime of the drift layer 14, a reduction in minority carriers at the interface between the body well 16 and the drift layer 14 is also desirable. This can be achieved by reducing the doping concentration of the body well 16 such that fewer minority carriers are injected from the body well 16 into the drift layer 14 during forward bias. In various embodiments, the doping concentration of the body well 16 near the interface between the body well 16 and the drift layer 14 is 1×10 16 cm -3 to 3×10 19 cm -3 which can be anywhere from about 5 to 15 times lower than conventional doping concentrations. More specifically, the doping concentration of the body well 16 within 0.2 μm of the interface between the body well 16 and the drift layer 14 is 1×10 16 cm -3 to 3×10 19 cm -3 In particular, the present disclosure intends that the doping concentration of the body well 16 may be any discrete value within any given exemplary range of doping concentrations, or any sub-range within the exemplary ranges.

[0036] In addition to or alternatively to reducing the doping concentration of the body well 16, as shown in FIG. 5A, a recombination region 32 may be provided in the drift region 14 at or near the interface between the body well 16 and the drift layer 14. The recombination region 32 is a region having a higher density of minority carrier recombination centers than the surrounding drift layer 14. This may be achieved by intentionally damaging the recombination region 32 via an implantation process, or by doping the recombination region 32. In one embodiment, the recombination region is implanted with argon to increase the density of minority carrier recombination centers in the recombination region. However, other implants such as hydrogen and helium may also be used in some embodiments. The density of minority carriers in the recombination region 32 may be between 5 to 10 times higher than that in the drift layer 14. In various embodiments, the density of minority carrier recombination centers in the recombination region 32 is 1×10 13 cm -3 ~1×10 18 cm -3 can be between In particular, the density of minority carrier recombination centers in the recombination region 32 may be any discrete point within this range, or any subrange within this range. For example, the density of minority carrier recombination centers in the recombination region 32 is 1×10 14 cm -3 ~1×10 18 cm -3 between 1×10 15 cm -3 ~1×10 18 cm -3 between 1×10 16 cm -3 ~1×10 18 cm -3 between 1×10 17 cm -3 ~1×10 18 cm -3 between 1×10 14 cm -3 ~1×10 17 cm -3 between 1×10 14 cm -3 ~1×10 16 cm -3 between 1×1014 cm -3 ~1 × 10 15 cm -3 During, 1 x 10 15 cm -3 ~1 × 10 17 cm -3 Between, and 1 × 10 17 cm -3 ~1 × 10 18 cm -3 The recombination region 32 may be between these ranges, or any discrete point within any of these ranges. The recombination region 32 is shown as a localized region of the body diode 30 at or near the interface between the body well 16 and the drift layer 14, but the recombination region 32 may be a blanket region over the entire transistor 10, or it may include multiple regions separated from each other. The density of minority carrier recombination centers in the recombination region 32 may be between 6 and 7 times greater than that of the drift layer 14, between 7 and 8 times greater than that of the drift layer 14, between 8 and 9 times greater than that of the drift layer 14, between 5 and 9 times greater than that of the drift layer 14, or it may be in any other subrange or discrete point within a broader exemplary range.

[0037] The thickness of body well 16 is T bw It is shown as follows. In various embodiments, T bw This can be between 0.1 μm and 2.0 μm. bw This may be any subrange within the larger range of 0.1 μm to 2.0 μm. For example, T bwThis includes the ranges between 0.25 μm and 0.5 μm, between 0.25 μm and 0.75 μm, between 0.25 μm and 1.0 μm, between 0.25 μm and 1.25 μm, between 0.25 μm and 1.5 μm, between 0.25 μm and 1.75 μm, between 0.5 μm and 0.75 μm, between 0.5 μm and 1.0 μm, between 0.5 μm and 1.25 μm, between 0.5 μm and 1.5 μm, between 0.5 μm and 1.75 μm, between 0.5 μm and 2.0 μm, between 0.75 μm and 1.0 μm, and between 0.75 μm and 1.25 μm. The width of the body well 16 may be between 0.75μm and 1.5μm, between 0.75μm and 1.75μm, between 0.75μm and 2.0μm, between 1.0μm and 1.25μm, between 1.0μm and 1.5μm, between 1.0μm and 1.75μm, between 1.0μm and 2.0μm, between 1.25μm and 1.5μm, between 1.25μm and 1.75μm, between 1.25μm and 2.0μm, between 1.5μm and 1.75μm, between 1.5μm and 2.0μm, and between 1.75μm and 2.0μm. bw It is shown as follows. In various embodiments, the width of the body well 16 may be between 1 μm and 10 μm. bw This may be any subrange within the larger range of 1 μm to 10 μm. For example, W bw is between 1μm~2μm, 1μm~3μm, 1μm~4μm, 1μm~5μm, 1μm~6μm, 1μm~7μm, 1μm~8μm, 1μm~9μm, 1μm~10μm, 2μm~3μm, 2μm ~4μm, 2μm~5μm, 2μm~6μm, 2μm~7μm, 2μm~8μm, 2μm~9μm, 2μm~10μm, 3μm~4μm, 3μm~5μm, 3μm~6μm, 3μm~7μm, 3μm The doping concentrations may be ~8μm, 3μm~9μm, 3μm~10μm, 4μm~5μm, 4μm~6μm, 4μm~7μm, 4μm~8μm, 4μm~9μm, 4μm~10μm, 5μm~6μm, 5μm~7μm, 5μm~8μm, 5μm~9μm, 5μm~10μm, 6μm~7μm, 6μm~8μm, 7μm~9μm, 7μm~10μm, 8μm~9μm, 8μm~10μm, and 9μm~10μm. The doping concentration in body well 16 is 1 × 10⁻¹⁶. 16 cm -3 ~3×10 19 cm -3It may be between or within any sub-range of this larger range. In various embodiments, the doping concentration in body well 16 is 5 × 10 16 cm -3 ~3×10 19 cm -3 During, 1 x 10 17 cm -3 ~3×10 19 cm -3 During 5 x 10 17 cm -3 ~3×10 19 cm -3 During, 1 x 10 18 cm -3 ~3×10 19 cm -3 During 5 x 10 18 cm -3 ~3×10 19 cm -3 During, 1 x 10 16 cm -3 ~1 × 10 19 cm -3 During, 1 x 10 16 cm -3 ~5×10 18 cm -3 During, 1 x 10 16 cm -3 ~1 × 10 18 cm -3 During, 1 x 10 16 cm -3 ~5×10 17 cm -3 During, 1 x 10 16 cm -3 ~1 × 10 17 cm -3 During, 1 x 10 16 cm -3 ~5×10 16 cm -3 During 5 x 10 16 cm -3 ~1 × 10 19 cm -3 During, 1 x 10 17 cm -3 ~5×10 18 cm -3 Between, and 5×10 17 ~1 × 10 18 cm -3It may be between. In some embodiments, the doping profile of the body well 16 has a thickness T bw It remains relatively constant along the line. In other embodiments, the doping concentration in body well 16 is the same as its thickness T. bw The doping profiles vary accordingly. For example, the doping profile of a body well can be linear (increasing from top to bottom or bottom to top), triangular (increasing and then decreasing from top to bottom), stepped (increasing or decreasing along a curve from top to bottom), or any other doping profile. In one embodiment, the doping profile of a body well 16 decreases proportionally to the distance from the surface of the drift layer 14 such that the injection of minority carriers from the body well 16 decreases at the junction between the body well 16 and the drift layer 14.

[0038] The thickness of the recombination region 32 is T rr It is shown as follows. In various embodiments, T rr This can range from 1 nm to the maximum thickness of the drift layer 14, which may be about 200 μm. rr This can be any subrange within the larger range of 1 nm to 200 μm. For example, T rr This may be any other subrange within the larger range of 1 nm to 200 μm, or between 1 nm and 100 μm, 1 nm to 1 μm, 1 nm to 5 μm, 1 nm to 10 μm, 10 nm to 1 μm, 10 nm to 5 μm, 10 nm to 10 μm, 1 μm to 5 μm, 1 μm to 10 μm, 5 μm to 10 μm, 5 μm to 50 μm, 10 μm to 50 μm, 10 μm to 100 μm, or between 1 nm to 200 μm. Width W of the recombination region 32 rr This can range in size from 0.25 μm to approximately the width of the active area of ​​transistor 10, which can be up to 15 mm. rr This can be any sub-range within the larger range of 0.25 μm to 15 mm. For example, W rrThis can be between 0.25 μm and 0.5 μm, between 0.25 μm and 0.75 μm, between 0.25 μm and 1.0 μm, between 0.25 μm and 1.25 μm, between 0.25 μm and 1.5 μm, between 0.25 μm and 1.75 μm, between 0.25 μm and 2.0 μm, between 0.25 μm and 2.5 μm, between 0.25 μm and 2.5 μm, between 0.5 μm and 1.0 μm, between 0.5 μm and 2.0 μm, between 1.0 μm and 5.0 μm, between 2.0 μm and 5.0 μm, between 2.0 μm and 10 μm, between 5.0 μm and 10 μm, or any other subrange of a larger range. In some embodiments, W rr The width may be at least as wide as the width of the contact region 19. As described above, the recombination region 32 may be located in a localized area below the body well 16, or below a portion of the body well 16, for example, in the area indicated as the body diode 30, or it may extend over a larger portion of the drift layer 14, such as below all or part of the JFET region 20 and / or below any other region not shown, such as the entire active area. In some embodiments, the density of minority carrier recombination centers in the recombination region 32 is such that the thickness T rr It may remain relatively constant along the line. In other embodiments, the density of minority carrier recombination centers in the recombination region 32 is such that its thickness T rr The desired profile can vary, including linear, triangular, or stepped shapes.

[0039] The recombination region 32 can be located directly below the body well 16 in the drift layer 14, as shown in Figure 5B, or it can overlap all or part of the thickness of the body well 16. Furthermore, the recombination region 32 can extend along only a portion of the width of the body well 16, as shown in Figure 5C. In some embodiments, the recombination region 32 may enclose the lower corner or the entire body well 16, as shown in Figure 5D. Finally, the recombination region 32 may be provided along the entire thickness of the drift layer 14 in any portion of the drift layer below the body well 16, as shown in Figure 5E. In short, the recombination region 32 can be provided in all or part of the area near the body well 16 to form a desired minority carrier profile and thus increase the softness of the body diode 30. The recombination region 32 can reduce minority carrier injection into the drift layer 14 by providing a recombination center for minority carriers below the body well 16. This increases the carrier lifetime of the drift layer 14, and therefore the softness of the body diode 30 can be further enhanced.

[0040] Figure 6 is a graph showing possible injection profiles for the body well 16 and recombination region 32 according to various embodiments of the present disclosure. On the left side of the graph, four different doping profiles for the body well 16 are shown. The first solid line represents a conventional doping profile for the body well 16. As mentioned above, this can result in undesirably high levels of minority carrier injection into the drift layer 14. Therefore, the three lines below this first solid line, shown as dashed, dotted, and dotted lines, represent doping profiles for the body well 16 according to various embodiments of the present disclosure. As shown, each doping profile peaks at approximately the same level, but the doping concentration decreases near the bottom of the body well 16 where the interface between the body well 16 and the drift layer 14 is located. In the center of the graph, three lines are shown representing various doping profiles for the recombination region 32. In particular, the solid line represents 1 × 10⁻⁶ 13 cm -3 The dashed line shows the recombination region 32 caused by the amount of argon injected, and the dashed line represents 5 × 10 13 cm -3 The dotted line shows the recombination region 32 caused by the amount of argon injected, and 2.5 × 10⁻⁶ 14 cm -3 This shows the recombination region 32 resulting from the amount of argon injected. As shown, the recombination region 32 overlaps with the body well 16 and may reach a peak at the interface between the body well 16 and the drift layer 14. In particular, the doping profiles for the body well 16 and recombination region 32 shown in Figure 6 are merely illustrative. Those skilled in the art will readily understand that there are various ways of configuring the body well 16 and recombination region 32 to achieve the aforementioned objectives, all of which are intended herein.

[0041] As described above, by providing the body diode 30 as a non-punch-through diode and / or redistributing minority carriers in the drift layer 14, it is possible to make the body diode 30 have a softness factor S1 greater than 0.5. In various embodiments, the improvements to the body diode 30 described above, either alone or in combination, may enable the body diode 30 to produce a softness factor S1 greater than 0.6, greater than 0.7, greater than 0.8, greater than 0.9, greater than 1.0, greater than 1.1, greater than 1.2, greater than 1.3, greater than 1.4, greater than 1.5, greater than 2.0, greater than 2.5, greater than 3.0, greater than 3.5, greater than 4.0, greater than 4.5, greater than 5.0, greater than 5.5, greater than 6.0, greater than 6.5, greater than 7.0, greater than 7.5, greater than 8.0, greater than 8.5, greater than 9.0, greater than 9.5, up to a maximum of 10. More broadly, this disclosure intends the softness factor S1 of the body diode 30 at any discrete point between 0.5 and 10, or at any subrange within 0.5 to 10.

[0042] Similarly, improvements to the body diode 30 may result in a secondary softness factor S2 greater than 0.5. In various embodiments, the improvements to the body diode 30 described above, either alone or in combination, may enable the body diode 30 to result in a secondary softness factor S2 greater than 0.6, greater than 0.7, greater than 0.8, greater than 0.9, greater than 1.0, greater than 1.1, greater than 1.2, greater than 1.3, greater than 1.4, greater than 1.5, greater than 2.0, greater than 2.5, greater than 3.0, greater than 3.5, greater than 4.0, greater than 4.5, greater than 5.0, greater than 5.5, greater than 6.0, greater than 6.5, greater than 7.0, greater than 7.5, greater than 8.0, greater than 8.5, greater than 9.0, greater than 9.5, up to a maximum of 10. More broadly, this disclosure intends the secondary softness factor S2 of the body diode 30 at any discrete point between 0.5 and 10, or at any subrange within 0.5 to 10.

[0043] Figure 7 is a flowchart showing a method for manufacturing a transistor according to one embodiment of the present disclosure. First, a substrate is prepared (step 100). A drift layer is provided on the substrate (step 102). As described above, the thickness and doping concentration of the drift layer are selected to make the body diode in the finished transistor a non-punch-through diode. In particular, the thickness and / or doping concentration of the drift layer are increased compared to conventional designs with respect to a given breakdown voltage in order to provide the body diode as a non-punch-through diode. A carrier lifetime enhancement process is performed on the drift layer (step 104). In one embodiment, the carrier lifetime enhancement process is high-temperature oxidation of the drift layer. In particular, the drift layer may be oxidized at a temperature between 1300°C and 1500°C for a time period between 30 minutes and 5 hours to reduce carbon vacancies that, if not reduced, could shorten the minority carrier lifetime in the drift layer. In particular, the present disclosure is intended to be any currently existing method of enhancing carrier lifetime, rather than being limited to a specific carrier lifetime enhancement process.

[0044] A recombination region is provided in the drift layer (step 106). In one embodiment, providing the recombination region includes damaging a region of the drift layer by ion implantation. In another embodiment, providing the recombination region includes implanting argon into a region of the drift layer. The recombination region may be provided as a blanket region or may be localized to a specific region within the drift layer. Generally, the recombination region is provided to be localized to a specific depth in the drift layer to provide an increased recombination center near the interface between the body well and the drift layer. A bonding implant including a body well and a source well is provided on the surface of the drift layer opposite to the substrate (step 108). In particular, the body well is supplied with a doping concentration lower than that determined by conventional design processes, near the interface between the body well and the drift layer. The source well is provided within the body well on the surface of the drift layer. A contact well is also provided within the body well adjacent to the source well. Both the source well and the body well can be provided by an ion implantation process. A JFET region can also be provided in some embodiments. The JFET region is an area of ​​increased carrier concentration adjacent to the body well and can also be provided by an ion implantation process.

[0045] Finally, a source contact, a drain contact, a gate insulator, and a gate contact are provided (step 110). The source contact is provided on the surface of the drift layer opposite to the substrate and electrically contacts the source well and the body well via a contact well. The drain contact is provided on the surface of the substrate opposite to the drift layer and electrically contacts the substrate. The gate oxide film is provided on the surface of the drift layer opposite to the substrate, extending over the JFET region, a portion of the body well, and a portion of the source well. The gate contact is provided in the gate oxide film.

[0046] Figure 8 is a graph comparing the reverse recovery of a conventional body diode in a transistor with a body diode that includes the improvements discussed herein to reduce snappiness. In detail, the solid line shows the current through the body diode and the voltage across that body diode (each appended to the graph), while the dashed line shows the current through the body diode and the voltage across that body diode in a conventional transistor. As shown, the improved body diode takes less time to reach its maximum reverse recovery current, and the maximum reverse recovery current is significantly less than that of the conventional body diode. The improved body diode also shows an extended time from the maximum reverse recovery current to 0.2 times the maximum reverse recovery time compared to the conventional body diode, and the slope of the current is shallower than that of the conventional diode as the current increases between these values. The current through the improved body diode also shows significantly less ringing than that of the conventional body diode. All of the above is due to the improved body diode's softness factor S1 (as described above). s / t f This shows a significant improvement in the improved body diode. Furthermore, the secondary softness factor S2 is also improved in relation to the slope of the reverse recovery current, and the total area between the x-axis and the reverse recovery current curve is reduced. In short, the improved body diode is significantly less snappy than the conventional body diode. As mentioned above, the reduced snappiness means that the improved body diode can switch faster and with less switching loss compared to the conventional body diode.

[0047] As described above, the doping concentration of the drift layer 14 may be continuous along its thickness (from top to bottom as shown in Figure 1), or it may vary depending on the doping profile that changes along its thickness. Furthermore, in some embodiments, the drift layer 14 may include several different layers, each having a different doping concentration and / or doping profile. In other embodiments, the transistor 10 may include a buffer layer within the drift layer 14, which is a layer having a specific doping profile. In some embodiments, the buffer layer may be positioned between the drift layer 14 and the substrate 12. Providing multiple drift layers and / or buffer layers can increase the durability of the transistor, particularly by lowering its second breakdown voltage, and can also be used to design the body diode 30 to be a non-punch-through diode, or to change the distribution of minority carriers within the body diode 30 to reduce the snappiness described above.

[0048] Figure 9 shows a simplified version of a transistor 10 according to one embodiment of the present disclosure. The transistor 10 includes a substrate 12, a buffer layer 34 on the substrate 12, and a drift layer 14 on the buffer layer 34. The graph shows the relative doping concentrations of the substrate 12, the buffer layer 34, and the drift layer 14. As shown, the substrate 12 is doped to a higher concentration than the buffer layer 34, and the buffer layer 34 is also doped to a higher concentration than the drift layer 14. In particular, the substrate 12, the buffer layer 34, and the drift layer 14 are all doped in a relatively constant manner, and thus form a step-doping profile as shown. By providing the buffer layer 34 having a doping concentration higher than the drift layer 14 but lower than that of the substrate 12, a buffer for charged particles that can be accelerated by collisions with radiating particles is formed, allowing these accelerated charged particles to recombine rather than pass through the transistor 10. This can increase the durability of transistor 10, and furthermore, such a modified doping profile can be used to configure a desired minority carrier profile in the device in order to reduce the snappiness of body diode 30 and thus improve its performance.

[0049] In particular, the thicknesses and doping concentrations of the substrate 12, buffer layer 34, and drift layer 14 are merely illustrative. In detail, these thicknesses and doping concentrations are given for a device rated at 1200V. Those skilled in the art will readily understand that higher blocking voltages may result in thicker thicknesses for the drift layer 14 and, in some embodiments, the buffer layer 34, and / or lower doping concentrations for these layers. However, the relationship between the thickness of these layers and the doping concentration remains relatively constant. In one embodiment, the thickness of the buffer layer 34 may be between 5% and 35% of the thickness of the drift layer 14. In certain embodiments, the thickness of the buffer layer 34 may be between 5% and 10% of the thickness of the drift layer 14, between 10% and 15% of the thickness of the drift layer 14, between 15% and 20% of the thickness of the drift layer 14, between 20% and 25% of the thickness of the drift layer 14, between 25% and 30% of the thickness of the drift layer 14, between 30% and 35% of the thickness of the drift layer 14, between 15% and 25% of the thickness of the drift layer 14, or between 25% and 35% of the thickness of the drift layer 14. Furthermore, the doping concentration of the buffer layer 34 may vary between 20% and 90% of the doping concentration of the substrate 12, while remaining at least 20% greater than the doping concentration of the drift layer 14. In certain embodiments, the doping concentration of the buffer layer 34 may be between 20% and 30% of the doping concentration of the substrate 12, between 30% and 40% of the doping concentration of the substrate 12, between 40% and 50% of the doping concentration of the substrate 12, between 50% and 60% of the doping concentration of the substrate 12, between 60% and 70% of the doping concentration of the substrate 12, between 70% and 80% of the doping concentration of the substrate 12, or between 80% and 90% of the doping concentration of the substrate 12.

[0050] In one embodiment, the substrate 12, buffer layer 34, and drift layer 14 are silicon carbide (SiC). Thus, the buffer layer 34 may be an epitaxial layer grown on the substrate 12 before the drift layer 14. The drift layer 14 may then be grown on top of the buffer layer 34. The buffer layer 34 may be grown in an environment where a dopant is used to bring about a desired doping concentration, or it may be grown and then implanted (e.g., via ion implantation) to the desired doping concentration. In another embodiment, the buffer layer 34 may be an implantation region on the surface of the substrate 12. Since the substrate 12 is doped to a higher concentration than the desired doping level for the buffer layer 34, it may be doped with the opposite doping type to reduce its net doping concentration (e.g., if the substrate 12 is an n-type substrate, it may be doped with a p-dopant). In particular, the principles of this disclosure apply equally to n-type or p-type substrates, buffer layers, and drift layers. In other words, the principles of this disclosure may apply equally to n-type and p-type devices.

[0051] Figure 10 shows a simplified version of transistor 10 according to a further embodiment of the present disclosure. The transistor 10 shown in Figure 10 is substantially the same as that shown in Figure 9, except for the device's doping profile and the relative thickness of the layers. In particular, the buffer layer 34 exhibits a linearly stepped doping concentration that decreases in proportion to the distance from the drift layer 14, such that the entire doping profile of the device includes a step between the drift layer 14 and the buffer layer 34 and another step between the buffer layer 34 and the substrate 12. In this embodiment, the buffer layer 34 may be thicker to allow a linear transition in its doping profile. Such a doping profile may be formed by first growing the buffer layer 34 and then ion implanting it, or by growing the buffer layer 34 in an environment in which the dopant concentration is controlled throughout the growth process. In particular, this doping profile is merely illustrative, and any linearly stepped doping concentration may be replaced with that shown in Figure 10 without departing from the principles of the present disclosure.

[0052] Figure 11 shows a simplified version of transistor 10 according to a further embodiment of the present disclosure. The transistor 10 shown in Figure 11 is substantially the same as that shown in Figure 9, except for the doping profile of the device and the relative thickness of the layers. In particular, the buffer layer 34 provides a substantially smooth transition between the doping concentration of the drift layer 14 and the doping concentration of the substrate 12. In this embodiment, the buffer layer 34 may be substantially thicker to enable the transition in its doping profile. Such a doping profile may be formed by first growing the buffer layer 34 and then ion implanting it, or by growing the buffer layer 34 in an environment in which the dopant concentration is controlled throughout the growth process. In particular, this doping profile is merely illustrative, and any stepwise doping concentration, linear or other form may be replaced with that shown in Figure 11 without departing from the principles of the present disclosure.

[0053] Figure 12 shows a simplified version of transistor 10 according to a further embodiment of the present disclosure. The transistor 10 shown in Figure 12 is substantially the same as that shown in Figure 9, except for the doping profile of the device and the relative thickness of the layers. In particular, the buffer layer 34 is provided as a doping “spike” and is not directly on the substrate 12. In this embodiment, the thickness of the buffer layer 34 may be reduced. Such a doping profile may be formed through separate growth on a small portion of the drift layer 14, or by growing a small portion of the drift layer 14, performing ion implantation to generate the buffer layer 34, and then growing the rest of the drift layer 14. In particular, this doping profile is merely illustrative, and any “spike” doping profile may be replaced with that shown in Figure 12 without departing from the principles of the present disclosure.

[0054] As shown in Figure 13A, in certain cases, a relatively thin but more highly doped diffusion layer 36 is provided above the drift layer 14 to aid current diffusion before reaching the less highly doped drift layer 14. Thus, a typical SiC or other wide-bandgap transistor 10 may have a thin, more highly doped upper region as the diffusion layer 36, a thicker, less highly doped drift layer 14, and a relatively thin substrate 12, thinly shown in Figure 13A to save space. Figure 13B is a graph of the distance from the top of the field pair transistor 10 in a vertical semiconductor. In the avalanche, the electric field is highest at the top surface of the diffusion layer 36 and decreases in intensity in the diffusion layer 36 and the drift layer 14, but at varying ratios. In particular, the electric field remains at a significant level at the interface between the drift layer 14 and the substrate 12 (i.e., the top surface of the substrate 12). Thus, as shown in Figure 13B, the electric field effectively penetrates the entire drift layer 14 (PT). Figure 13C shows that this type of breakthrough can occur sufficiently before avalanche breakdown, and that a second breakdown can occur for such a structure even at voltages lower than the avalanche. In particular, Figure 13C is a graph showing the electric field and drain-source current (lds) at the bottom of the drift layer 14 as the drain-source voltage (Vds) increases in blocking mode for the FET or diode configuration of transistor 10. Not only the voltages of the second breakdown and avalanche breakdown, but also the punch-through voltage V(PT) is observed.

[0055] To avoid or mitigate the penetration of the electric field into the substrate, a buffer layer 34 may be used together with a diffusion layer 36, as shown in Figure 14A. The doping concentration of the buffer layer 34 may be between the doping concentration of the drift layer 20 and the doping concentration of the substrate 12. By including the buffer layer 34, the electric field is moved away from the upper surface of the substrate 12, and the second breakdown voltage increases. In the exemplary embodiment, as shown in Figure 14B, the electric field at the avalanche voltage penetrates the drift layer 14 but is stopped at the buffer layer 34 and therefore does not penetrate into the substrate 12. By including the buffer layer 34, the second breakdown voltage increases, thereby increasing durability under high-electric-field bipolar conditions and moving the electric field away from the substrate 12. By moving the electric field away from the substrate, the effect of basal plane dislocation movement from the substrate 12 to the drift layer 14 is minimized. Figure 14C shows the electric field and drain-source current (lds) at the bottom of the drift layer 14 when the drain-source voltage (Vds) increases in the blocking mode for the diode configuration FET of transistor 10. When a buffer layer 34 is present, the avalanche (Vaval) and punch-through voltage V (PT) remain unchanged, but the second breakdown voltage is significantly increased. Furthermore, for the reasons mentioned above, the buffer layer 34 can prevent the electric field from penetrating, thereby increasing the softness of the body diode 30.

[0056] In a particular embodiment, the diffusion layer 36 generally has a doping level of 1 × 10⁻¹⁶ depending on the desired current and voltage ratings. 16 cm -3 ~1 × 10 17 cm -3 The range is between 1 μm and 4 μm in thickness. The doping for the drift layer 14 is determined according to the voltage rating of the device, and for devices rated at 300 V to 300 kV, 1 × 10 13 ~1 × 10 17 cm -3 The doping range and thickness can vary from 2 μm to 300 μm. The buffer layer 34 is generally doped less than the substrate 12, and in many cases, 1 × 10⁻⁶ 18 cm -3The doping is sufficiently high that the doping does not significantly deplete the inhibitory effect. Therefore, the buffer layer 34 functions as needed, depending on the doping level, at 1 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 The thickness can range from 0.5 μm to 5 μm. The thickness of the substrate 12 can range from 50 to 500 μm. The concept associated with the embodiment in Figure 14A adds little resistance to the structure, but may, in some cases, contribute to the durability and snappiness of the body diode 30.

[0057] The alternative doping concentration range for the example in Figure 14A is: 1 × 10 for the diffusion layer 36 16 ~5×10 16 cm -3 ; 1 × 10 for drift layer 14 13 ~1 × 10 17 cm -3 ; 5 × 10 for buffer layer 34 16 ~5×10 18 cm -3 and 5 × 10 for circuit board 12 17 ~1 × 10 20 cm -3 Includes.

[0058] In the embodiment shown in Figure 15A, multiple drift layers are provided on the transistor 10, referred to as the upper first drift layer 14A and the lower second drift layer 14B. The buffer layer 34 is not included. The first drift layer 14A is located between the diffusion layer 36 and the second drift layer 14B. The second drift layer 14B is located between the first drift layer 14A and the substrate 12.

[0059] The lower second drift layer 14B may have a slightly higher doping level than the upper first drift layer 14A to increase the drift compared to the previous embodiment. Furthermore, the first drift layer 14A may be thinner than the drift layer 14 in the embodiment in Figure 14A, while having a slightly higher doping level to keep the overall drift resistance low. Compared to the previous embodiment, these modifications increase both the punch-through voltage (V(PT)) and the second breakdown voltage.

[0060] In certain embodiments, the second drift layer 14B may have any thickness that is close to or thinner than the thickness of the first drift layer 14A, while having a doping level that is 1 to 3 times that of the first drift layer 14A. This embodiment results in increased durability by not applying an electric field high enough to penetrate the substrate 12. In selected embodiments, the first drift layer 14A and the second drift layer 14B of the transistor 10 can be designed to prevent any electric field from penetrating the second drift layer 14B and reaching the substrate 12, as shown in Figure 15B. Figure 15B shows the electric field in the transistor 10 at an avalanche voltage. In particular, the electric field is stopped at the second drift layer 14B just before reaching the substrate 12.

[0061] Figure 15C shows the electric field and drain-source current (lds) at the bottom of the second drift layer 14B as the drain-source voltage (Vds) increases in the blocking mode for the FET or diode configuration of transistor 10. By adding the lower second drift layer 14B, the avalanche voltage (Vaval) can remain constant, while both the punch-through voltage V (PT) and the second breakdown voltage increase beyond the avalanche voltage (Vaval).

[0062] The use of multiple drift layers, such as a first drift layer 14A and a second drift layer 14B, can contribute to the overall device durability under high electric field, high current, and high-speed switching conditions. Snappiness during switching is reduced, preventing the electric field from approaching the substrate 12, and thus preventing basal plane dislocations from moving to the first drift layer 14A or the second drift layer 14B. More than two drift layers may be used to achieve similar results.

[0063] The exemplary doping concentration range for the example in Figure 15A is: 1 × 10 for the diffusion layer 36 16 ~5×10 16 cm -3 ; For the first drift layer 14A, 1 × 10 13 ~4×10 16 cm -3 ; For the second drift layer 14B, 2 × 10 13 ~8×10 16 cm -3 and 5 × 10 for circuit board 12 17 ~1 × 10 20 cm -3 Includes. An alternative set of ranges is, 1 × 10 for the diffusion layer 36 16 ~5×10 16 cm -3 ; For the first drift layer 14A, 1 × 10 15 ~2×10 16 cm -3 ; For the second drift layer 14B, 2 × 10 15 ~3×10 16 cm -3 and 1 × 10 18 ~1 × 10 20 cm -3 Includes. An example thickness range is, Diffusion layer 36: 1-4 μm; For the first drift layer 14A, 2-50 μm; For the second drift layer 14B, 1-30 μm; and The substrate 12 contains 50 to 500 μm.

[0064] The embodiment shown in Figure 16A is built upon the embodiment in Figure 15A by adding a buffer layer 34 between the second drift layer 14B and the substrate 12. As in the previous embodiment, the electric field at the avalanche voltage does not penetrate the second drift layer 14B, as shown in Figure 16B, and is therefore stopped just before the buffer layer 34. Further advantages of this embodiment become more readily apparent in Figure 16C. Figure 16C shows the electric field and lds current at the bottom of the drift layer 14B when the drain-source voltage (Vds) increases in blocking mode, when the transistor 10 is configured as an FET or diode. By adding the buffer layer 34, the avalanche voltage (Vaval) and punch-through voltage (V(PT)) are kept relatively constant, while the second breakdown voltage is further increased, resulting in a further electric field drop under high electric field, high current discharge conditions.

[0065] The exemplary doping concentration range for the example in Figure 16A is: 1 × 10 for the diffusion layer 36 16 ~5×10 16 cm -3 ; For the first drift layer 14A, 1 × 10 13 ~5×10 16 cm -3 ; For the second drift layer 14B, 2 × 10 13 ~1 × 10 17 cm -3 ; 5 × 10 for buffer layer 34 16 ~5×10 18 cm -3 and 1 × 10 18 ~1 × 10 20 cm -3 Includes. An alternative set of ranges is, 1 × 10 for the diffusion layer 3616 ~5×10 16 cm -3 ; For the first drift layer 14A, 1 × 10 15 ~2×10 16 cm -3 ; For the second drift layer 14B, 2 × 10 15 ~3×10 16 cm -3 ; 1 × 10 for buffer layer 34 17 ~1 × 10 18 cm -3 and 1 × 10 18 ~1 × 10 20 cm -3 Includes. An example thickness range is, Diffusion layer 36: 1-5 μm; For the first drift layer 14A, 2-50 μm; For the second drift layer 14B, 1-30 μm; Buffer layer 34: 1-20 μm; and The substrate 12 contains 50 to 500 μm. The first drift layer 14A and the second drift layer 14B may have the same or different doping concentrations and the same or different doping profiles. For example, both the first drift layer 14A and the second drift layer 14B may have the same or different stepped or constant doping concentrations. Furthermore, either the first drift layer 14A or the second drift layer 14B may have a stepped doping profile, while the other drift layer is constant. In certain embodiments, the diffusion layer 36 has a higher doping concentration than at least one of the first and second drift layers, if not both of them.

[0066] The embodiment in Figure 17A provides a drift layer 14 with stepwise doping on the transistor 10. In the exemplary embodiment, there is only one drift layer 14 and no buffer layer 34. The doping concentration increases in the drift layer 14 from the bottom (i.e., the substrate interface) to the top (i.e., the interface with the diffusion layer 36). Therefore, the doping concentration is slightly higher at the bottom of the drift layer 14 and lower near the top of the drift layer 14. As shown in Figure 17B, the doping concentration is a relative level through the diffusion layer 36, decreasing to a first level at the top of the drift layer 14, continuously increasing in the drift layer 14 to a level below the diffusion layer 36, and then surging to a much higher, relatively constant level at the substrate 12. The doping concentrations in Figure 17B are shown on a logarithmic scale.

[0067] With appropriate doping concentration, profile, and thickness, an increase is observed in both the punch-through voltage (V(PT)) and the second breakdown voltage, as shown in Figure 17C. In the case of the stepped drift layer 14, the avalanche voltage (Vaval) can remain constant, while the second breakdown voltage and punch-through voltage V(PT) are increased beyond the avalanche voltage (Vaval) limit. This results in a further electric field drop under high electric field, high current discharge conditions.

[0068] By preventing any electric field from penetrating the substrate 12, or by not applying an electric field high enough to penetrate it, durability is increased under high electric field, high current, and high-speed switching conditions. The snappiness of the bipolar device during switching is also reduced. As in other embodiments, by keeping the electric field away from the substrate 12, basal plane dislocations are prevented from moving to the drift layer 14.

[0069] The exemplary doping concentration ranges for the examples in Figures 17A and 17B are: 1 × 10 for the diffusion layer 36 16 ~5×10 16 cm -3 ; 1 × 10 for drift layer 14 13~5×10 18 cm -3 1 x 10 15 ~5×10 17 cm -3 During; and 1 × 10 18 ~1 × 10 20 cm -3 Includes. An alternative set of ranges is, 1 × 10 for the diffusion layer 36 16 ~5×10 16 cm -3 ; 5x10 for drift layer 14 15 ~5×10 17 cm -3 1 x 10 16 ~1 × 10 17 cm -3 During; and 1 × 10 18 ~5×10 19 cm -3 Includes. An example thickness range is, Diffusion layer 36: 1-5 μm; For the drift layer 14, 3 to 200 μm; and The substrate 12 contains 50 to 500 μm.

[0070] Referring now to Figure 18, a buffer layer 34 and a stepped drift layer 14 are provided between the diffusion layer 36 and the substrate 12. In this embodiment, the diffusion layer 36 and the buffer layer 34 are uniformly doped, and the drift layer 14 is stepped as described above. In other embodiments, the doping of the diffusion layer 36 and / or the buffer layer 34 is stepped. The graph in Figure 18B presents an exemplary doping profile on a log scale. As shown in Figure 18B, the doping concentration decreases continuously from a first level at the top of the diffusion layer 36 to a second level at the bottom of the diffusion layer 36, increases continuously from a second level at the top of the drift layer 14 to a third level lower than the first level at the bottom of the drift layer 14, and increases continuously from a second level to a fourth level in the buffer layer 34. The doping in the substrate 12 is shown to be constant at the fourth level. In the exemplary embodiment, the doping level in the exemplary layer is continuous in that there is no abrupt change in doping concentration within a given layer or at the junction of layers.

[0071] The exemplary doping concentration range for the entire stepwise implementation is: 5 × 10 for the diffusion layer 36 16 ~1 × 10 14 cm -3 3 x 10 16 ~5×10 15 cm -3 Between; 1 × 10 for drift layer 14 13 ~1 × 10 17 cm -3 5x10 15 ~5×10 16 cm -3 Between; 5 × 10 for buffer layer 34 16 ~1 × 10 20 cm -3 1 x 10 17 ~1 × 10 20 cm -3 During; and 1 × 10 18 ~1 × 10 20 cm -3 Includes. An example thickness range is, Diffusion layer 36: 1-5 μm; Drift layer 14: 3-200 μm; Buffer layer 34: 1-20 μm; and The substrate 12 contains 50 to 500 μm. Regarding the embodiments shown in Figures 9 to 12, the characteristics, thickness, doping concentration, and / or doping concentration relationships of the substrate 12, buffer layer 34, and drift layer 14 can be applied to any of the embodiments shown in Figures 13 to 18, but this is not necessary, and the same applies in reverse.

[0072] The use of multiple drift layers, buffer layers 34, and diffusion layers 36 as described above in Figures 9 to 18 not only increases the durability of the transistor 10 but can also reduce the snappiness of the body diode 30. First, various configurations of the drift layer 14, buffer layer 34, and diffusion layer 36 can prevent penetration and thus improve the performance of the body diode 30, as described above. Furthermore, various configurations of the drift layer 14, buffer layer 34, and diffusion layer 36 can be designed to bring about a desired distribution of minority carriers in order to reduce snappiness, as described above in Figure 4.

[0073] Figure 19 is a graph showing the effect of providing the body diode 30 as a non-punch-through diode according to one embodiment of the present disclosure. In particular, the graph shows some portions of the voltage and current transient responses of the body diode 30 when provided as a punch-through diode and a non-punch-through diode. The dashed line shows the response of the body diode 30 at 25°C when provided as a punch-through diode. The dotted line shows the response of the body diode 30 at 175°C when provided as a punch-through diode. The solid line shows the response of the body diode 30 at 25°C when provided as a non-punch-through diode. As mentioned above, this can be achieved, for example, by changing the thickness and doping concentration of the drift layer 14. The dashed line shows the response of the body diode 30 at 175°C when provided as a non-punch-through diode. As shown, the response of the body diode 30 is more gradual at both 25°C and 175°C when it is provided as a non-punch-through diode.

[0074] Figure 20 is a graph showing the effect of the carrier lifetime of the drift layer 14 in the body diode 30. In particular, the graph shows several parts of the voltage and current transient response of the body diode 30 when various carrier lifetimes are given in the drift layer 14. The dashed line, which is mostly hidden by the solid line discussed below, shows the response of the body diode 30 without carrier lifetime improvement. The dotted line shows the Z in the drift layer 14. 1 / 2 Trap density is 1 x 10 15 cm -3 The response of the body diode 30 with improved carrier lifetime is shown below. The solid line represents the Z in the drift layer 14. 1 / 2 Trap density 5x10 13 cm -3 The response of the body diode 30, which has improved carrier lifetime, is shown below. The dashed line represents the Z in the drift layer 14. 1 / 2 Trap density is 1 x 10 12 cm -3The response of the body diode 30, which has improved carrier lifetime, is shown below. The carrier lifetime is Z 1 / 2 This relates to trap density, because these traps act as recombination centers for carriers. For example, as mentioned above, thermal oxidation causes Z 1 / 2 By reducing the trap density, the carrier lifetime can be increased, which reduces snappiness and therefore can increase the softness of the body diode 30. In particular, the graph in Figure 20 shows the response of the body diode 30 as a punch-through diode.

[0075] Figure 21 is a graph showing the effect of the recombination region 32 in the body diode 30. In particular, the graph shows several portions of the voltage and current transient response for the body diode 30 with and without the recombination region 32. The dashed line shows the response of the body diode 30 without the recombination region 32, while the solid line shows the response of the body diode 30 with the recombination region 32. In particular, the graph shows the response of the body diode 30 as a non-punch-through diode, and the drift layer 14 has an improved carrier lifetime. As shown, providing the recombination region 32 increases the softness of the body diode 30.

[0076] Those skilled in the art will recognize improvements and modifications to preferred embodiments of this disclosure. All such improvements and modifications are considered to fall within the scope of the concepts disclosed herein and the appended claims.

Claims

1. circuit board and The drift layer on the aforementioned substrate, One or more injection regions in the drift layer, A vertical transistor device is provided that is configured to conduct current in a first direction, One or more injection regions are configured to provide a body diode configured to conduct current in a second direction opposite to the first direction, A recombination region adjacent to one or more injection regions of the drift layer, having a higher density of minority carrier recombination centers than the drift layer, Equipped with, A semiconductor device wherein the density of minority carrier recombination centers in the recombination region is 5 to 10 times higher than the density of minority carrier recombination centers in the drift layer.

2. The density of minority carrier recombination centers in the recombination region is 1 × 10 １３ cm －３ ~1 x 10 １８ cm －３ A semiconductor device according to claim 1, which is between [a certain range].

3. The semiconductor device according to claim 1, wherein the minority carrier lifetime in the drift layer is between 1 μs and 20 μs.

4. Z in the drift layer １／２ The trap density is 5 x 10 １３ cm －３ A semiconductor device according to claim 1, wherein the value is less than [value missing].

5. The drift layer has a first doping type, The one or more injection regions include a body well having a second doping type, The semiconductor device according to claim 1, wherein at least a portion of the recombination region is located between the lower part of the body well and the substrate.

6. The semiconductor device according to claim 5, wherein the recombination region overlaps with at least a portion of the thickness of the body well.

7. The semiconductor device according to claim 5, wherein the width of the recombination region is narrower than the width of the body well in a direction parallel to the upper surface of the substrate.

8. The semiconductor device according to claim 5, wherein the width of the recombination region is equal to or wider than the width of the body well in a direction parallel to the upper surface of the substrate.

9. A substrate and The drift layer on the aforementioned substrate, One or more injection regions in the drift layer, A vertical transistor device is provided that is configured to conduct current in a first direction, One or more injection regions are configured to provide a body diode configured to conduct current in a second direction opposite to the first direction, A recombination region adjacent to one or more injection regions of the drift layer, having a higher density of minority carrier recombination centers than the drift layer, Equipped with, The drift layer has a first doping type, The one or more injection regions include a body well having a second doping type, At least a portion of the recombination region is located between the lower part of the body well and the substrate, A semiconductor device in which the density of minority carrier recombination centers in the recombination region reaches a peak value at the interface between the drift layer and the body well.

10. The doping concentration of the body well is 1×10 １６ / cm －３ to 3×10 １９ / cm －３ , and is within the range of The semiconductor device according to claim 5, wherein the doping concentration in the body well decreases toward the drift layer.

11. The semiconductor device according to claim 1, wherein the recombination region extends along the entire thickness of at least a portion of the drift layer in a direction perpendicular to the upper surface of the substrate.

12. A substrate and The drift layer on the aforementioned substrate, One or more injection regions in the drift layer, A vertical transistor device is provided that is configured to conduct current in a first direction, One or more injection regions are configured to provide a body diode configured to conduct current in a second direction opposite to the first direction, A recombination region adjacent to one or more injection regions of the drift layer, having a higher density of minority carrier recombination centers than the drift layer, Equipped with, A semiconductor device in which the body diode is a non-punch-through diode.

13. circuit board and A drift layer on the substrate having a minority carrier lifetime between 1 μs and 20 μs, One or more injection regions of the drift layer, A vertical transistor device is provided that is configured to allow current to flow in a first direction. One or more injection regions are configured to provide a body diode configured to allow current to flow in a second direction opposite to the first direction, Equipped with, A semiconductor device in which the softness factor of the body diode is between 0.5 and 10.

14. The Z layer of the aforementioned drift １／２ Trap density 5 x 10 １３ cm －３ The semiconductor device according to claim 13, wherein the value is less than [value missing].

15. The drift layer further includes a recombination region, and the density of minority carrier recombination centers in the recombination region is 1 × 10⁻⁶ １３ cm －３ and 1 x 10 １８ cm －３ A semiconductor device according to claim 13, which is between the above.

16. The aforementioned drift layer is A first drift layer having a first doping type and a first doping profile, A second drift layer having a second doping profile different from the first doping type and the first doping profile, The semiconductor device according to claim 13, comprising:

Images