System and method for implementing a micropulsation scheme using dual individual pulsers

Abstract

[0006] Embodiments of the present disclosure presented herein include an apparatus and method for processing a substrate in a plasma processing system. The apparatus includes a pulsed voltage (PV) waveform generator, the PV waveform generator comprising at least one synchronization signal and a plurality of pulsers for providing a plurality of TTL inputs. The PV waveform generator generates a waveform including pulses or bursts containing micropulses corresponding to the plurality of TTL input signals and the at least one synchronization signal. The method includes receiving, from a controller, a first TTL input signal and a synchronization signal; providing a first micropulse to an electrode assembly after receiving the first TTL input signal and synchronization signal; and providing a second micropulse to the electrode assembly after receiving a second TTL input signal and synchronization signal.

Description

[Background technology]

[0001] Technical field

[0001] Embodiments of the present invention generally relate to systems and methods for controlling the supply of power to a plasma formed in a plasma processing chamber used in semiconductor manufacturing.

[0002] Description of related technologies

[0002] Manufacturing high aspect ratio features with high reliability is one of the most important technical challenges for next-generation semiconductor devices. One method for forming high aspect ratio features involves using a plasma-assisted etching process to bombard the material formed on the substrate surface through openings formed in a patterned mask layer formed on the substrate surface.

[0003]

[0003] As technology nodes advance toward 2nm, microscopic precision is required in plasma processing to fabricate smaller features with higher aspect ratios. In the semiconductor equipment industry, where plasma ions play a major role in etching processes, controlling ion energy has always been an obstacle to the progress of reliable and repeatable device fabrication processes. In a typical plasma-assisted etching process, the substrate is placed on an electrostatic chuck (ESC) located in a processing chamber, and plasma is formed above this substrate. Ions from the plasma are accelerated toward the substrate, passing through the plasma sheath (i.e., the electron-depleted region) formed between the plasma and the substrate surface.

[0004]

[0004] Conventionally, in order to form the miniaturized device features described above as desired, a high-frequency (RF) substrate biasing method can be used, which uses a sinusoidal RF waveform to excite a plasma and form a plasma sheath. Recently, it has been found that supplying high-voltage pulses to one or more electrodes in a processing chamber can be useful in controlling the plasma sheath formed on the surface of the substrate as desired. However, generating medium to high-frequency high-voltage pulses is difficult. Such pulses can be particularly difficult to generate using standard electronic components because the switch components used to form the high-voltage pulses are heated.

[0005]

[0005] Therefore, in the art, there is a need for a pulsed voltage source and a biasing method that can enable the completion of a desirable plasma-assisted process on a substrate. [Overview of the project]

[0006]

[0006] The embodiments described herein generally relate to systems and methods used to control the supply of power to a plasma formed in a plasma processing chamber used in semiconductor manufacturing. More specifically, the embodiments described herein provide pulsed voltage sources and biasing methods that can enable the completion of a desired plasma-assisted process on a substrate.

[0007]

[0007] In one embodiment, a substrate processing system is provided. In this embodiment, the substrate processing system includes a substrate support assembly disposed in a processing chamber, electrodes disposed in the substrate support assembly, a pulse voltage waveform generator configured to supply pulse voltage waveforms to the electrodes, and a controller connected to the pulse voltage waveform generator. The controller comprises a plurality of pulsers and at least one synchronous pulser configured to transmit a synchronous signal. The plurality of pulsers include a first pulser configured to provide a first TTL input signal and a second pulser configured to provide a second TTL input signal, and the pulse voltage waveform includes a plurality of pulse voltage micropulses.

[0008]

[0008] In another embodiment, a method for processing a substrate in a plasma processing system is provided. In this embodiment, the method includes receiving a first TTL input signal and a synchronization signal from a first pulser of a plurality of pulsers via a waveform generator from a controller, and then, after receiving the first TTL input signal and the synchronization signal, supplying a first pulse voltage micropulse to an electrode located in a substrate support assembly in the plasma processing system via the waveform generator. The method further includes receiving a second TTL input signal and a synchronization signal from a second pulser of a plurality of pulsers via a waveform generator from a controller, before supplying a second pulse voltage micropulse to an electrode located in a substrate support assembly in the plasma processing system via the waveform generator after receiving a second TTL input signal and the synchronization signal. A first pulsed voltage micropulse comprises a plurality of first pulsed voltage micropulses, a second pulsed voltage micropulse comprises a plurality of second pulsed voltage micropulses, each of the plurality of second pulsed voltage micropulses is interleaved between each of the plurality of first pulsed voltage micropulses.

[0009]

[0009] In yet another embodiment, a processing system is provided. In this embodiment, the processing system includes a processing chamber, a voltage waveform generator configured to supply pulse voltage waveforms to an electrode assembly located within the processing chamber, a controller, and a memory for storing a program to be executed by the controller. The program includes instructions which cause the voltage waveform generator to receive a first TTL input signal and a synchronization signal from the controller to a first pulser among a plurality of pulsers, and, after receiving the first TTL input signal and the synchronization signal, to supply a first micropulse to an electrode located within a substrate support assembly in the plasma processing system.

[0010]

[0010] A more detailed description of the Disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings, so that the above-mentioned features of the Disclosure may be understood in more detail. However, it should be noted that the accompanying drawings show only exemplary embodiments, and should therefore not be considered to limit the scope of the Disclosure, as the Disclosure may also permit other equally valid embodiments. [Brief explanation of the drawing]

[0011] [Figure 1]

[0011] A schematic cross-sectional view of a processing chamber according to one embodiment is shown. [Figure 2]

[0012] An example of a pulsed voltage waveform is shown, which includes a voltage pulse provided in a pulsed voltage waveform established on a substrate by supplying a voltage pulse to a bias electrode during plasma processing using a PV waveform generation device according to a certain embodiment. [Figure 3A]

[0013] A voltage pulse waveform according to a certain embodiment is shown. [Figure 3B]

[0014] A voltage pulse waveform according to a certain embodiment is shown. [Figure 4]

[0015] This is a schematic diagram of a connection according to a certain embodiment. [Figure 5]

[0016] A method of using a plasma processing chamber according to certain embodiments is shown. [Modes for carrying out the invention]

[0012]

[0017] To facilitate understanding, the same reference numerals were used whenever possible to indicate identical elements common to multiple figures. It is assumed that elements and features of one embodiment can be usefully incorporated into other embodiments without further description.

[0013]

[0018] The embodiments of the disclosure presented in this book include apparatus and methods for plasma processing a substrate in a processing chamber. More specifically, embodiments of the disclosure describe a bias scheme configured to provide RF-generated RF waveforms from a radio frequency (RF) generator to one or more electrodes in a processing chamber, and pulse voltage (PV) waveforms supplied from one or more pulse voltage (PV) generators to one or more electrodes in a processing chamber.

[0014]

[0019] Generally, the generated RF waveform is configured to establish and maintain plasma within the processing chamber, and the supplied PV waveform is configured to establish a desired sheath voltage across the entire surface of the substrate during one or more phases of the plasma process, thereby creating a desired ion energy distribution function (IEDF) and electron energy distribution function (EEDF) on the substrate surface while one or more plasma processing phases are performed on the substrate within the processing chamber. The plasma processes disclosed herein can be used to control the shape of the IEDF and EEDF, and consequently, the interaction between the plasma and the substrate surface during processing. In some configurations, the plasma processes disclosed herein are used to control the profile of features formed on the substrate surface during processing. In some embodiments, the pulsed voltage waveform is established by a PV generator that is electrically coupled to a bias electrode located in a substrate support assembly positioned within the plasma processing chamber.

[0015]

[0020] Figure 1 shows a plasma processing system 100 according to one embodiment. The processing system 100 typically includes a processing chamber 113, which has a chamber lid 123, a chamber base 124, and a chamber wall 122 surrounding a processing space 129. A substrate support assembly 136 is located within the processing space 129 and is configured to receive and support a substrate 103 placed on the substrate support assembly 136. As shown in Figure 1, in some semiconductor plasma processes, ions are intentionally accelerated toward the substrate 103 by a voltage drop in an electron repulsion sheath formed above the substrate 103 placed on the substrate support assembly 136 located within the processing space 129 of the processing chamber 113. Without intending to limit the scope of the disclosures presented herein, the substrate support assembly 136 is often referred to herein as the “cathode assembly” or “cathode.” In some embodiments, the substrate support assembly 136 includes a substrate support 105 and a support base 107. The substrate support 105 may include an electrostatic chuck (ESC) assembly configured to chuck (e.g., hold) the substrate on the substrate receiving surface 105A.

[0016]

[0021] In some embodiments of the present disclosure presented herein, the processing chamber 113 is configured to provide a capacitively coupled gas discharge so that plasma 101 is generated by using an RF generator 118 connected to an RF electrode (e.g., a support base 107) via an RF matching network 162. The RF matching network 162 is configured to fine-tune the apparent load to minimize reflected power and maximize power supply efficiency. In some embodiments, the RF electrode includes a metal plate (not shown) positioned parallel to the surface of a substrate facing the plasma.

[0017]

[0022] In addition, in the plasma processing method disclosed herein, an ion acceleration cathode sheath is formed during plasma processing by using a pulsed voltage waveform generator 150 configured to establish a pulsed voltage (PV) waveform at one or more bias electrodes 104 normally disposed within a substrate support assembly 136. In some embodiments, the one or more bias electrodes 104 are separated from the substrate 103 by a thin layer of dielectric material formed within the substrate support assembly 136 (e.g., an electrostatic chuck (ESC) assembly), and optionally include an edge control electrode 115, the edge control electrode 115 being disposed inside or below an edge ring 114 that surrounds the substrate 103 when the substrate 103 is placed on the substrate support surface 105A of the substrate support assembly 136. In some embodiments, the bias electrode 104 is electrically coupled to a bias compensation module 116, which provides a chucking voltage (e.g., a static DC voltage between about -5000V and about 5000V) to the bias electrode 104 using an electrical conductor such as a coaxial transmission line 106 (e.g., a coaxial cable). The high voltage module 116 includes a bias compensation circuit element 116a, a DC power supply 155, and a blocking capacitor 153. The blocking capacitor of the bias compensation module (also referred to herein as blocking capacitor 153) is disposed between the output of the PV waveform generator 150 and the bias electrode 104.

[0018]

[0023] The edge control electrode 115 may be biased by using a PV waveform generator 150, which may be different from the PV waveform generator 150 used to bias the bias electrode 104. In one configuration, a first PV waveform generator 150 of a first PV source assembly 196 is configured to bias the bias electrode 104, and a second PV waveform generator 150 of a second PV source assembly 197 is configured to bias the edge control electrode 115.

[0019]

[0024] As mentioned above, in some embodiments, the RF generator 118 and the RF generator assembly 160 are generally configured to supply a desired amount of continuous wave (CW) or pulsed RF power to a support base 107 of a substrate support assembly 136 at a substantially constant desired sine wave frequency based on a control signal provided from a system controller 126.

[0020]

[0025] The controller 126 herein includes a central processing unit (CPU) 133, a memory 134, and a support circuit 135. The controller 126 is used to control process sequences used to process a substrate 103, including the substrate biasing method described herein. The CPU 133 is a general-purpose computer processor configured for use in an industrial environment for controlling a processing chamber and associated subprocessors thereof. The memory 134 described herein is generally non-volatile memory, and may include random access memory, read only memory, a floppy or hard disk drive, or other suitable forms of digital storage, local or remote. The support circuit 135 is conventionally coupled to the CPU 133, and includes cache, clock circuits, input / output subsystems, power supply sources, etc., and combinations thereof. Software instructions (programs) and data may be encoded and stored in the memory 134 to instruct the processor within the CPU 133. A software program (or computer instructions) readable by the CPU 133 in the controller 126 determines which tasks can be performed by components within the plasma processing chamber 100. Preferably, the program readable by the CPU 133 in the controller 126 includes code that, when executed by the processor (CPU 133), performs tasks relating to monitoring and executing the electrode biasing scheme described herein. The program includes instructions that are used to control various hardware and electronic components within the plasma processing chamber 100 to perform various process tasks and process sequences used to implement the electrode biasing scheme described herein.

[0021]

[0026] During processing, the RF generator 118 and the RF generator assembly 160 are configured to supply RF power (e.g., an RF signal) to a support base 107 located in close proximity to the substrate support 105 within the substrate support assembly 136. The RF power supplied to the support base 107 is configured to ignite and maintain the processing plasma 101 of the processing gas located within the processing space 129. In some embodiments, the RF generator 118 is configured to supply an RF signal having a frequency of 1 MHz or higher or about 2 MHz or higher (e.g., about 13.56 MHz or higher).

[0022]

[0027] In some embodiments, the support base 107 is an RF electrode electrically connected to the RF generator 118 via an RF power supply line 167, an RF matching circuit 162, and a first filter assembly 161 (both the RF matching circuit 162 and the first filter assembly 161 are located within the RF generator assembly 160). The first filter assembly 161 includes one or more electrical elements configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF power supply line 167 and damaging the RF generator 118. The first filter assembly 161 acts as a high impedance to the PV signal generated from the PV pulse generator P1 within the PV waveform generator 150, thereby suppressing the flow of current to the RF matching circuit 162 and the RF generator 118.

[0023]

[0028] In some embodiments, an RF generator assembly 160 and an RF generator 118 are used to ignite and maintain a processing plasma 101 using a field generated by a processing gas supplied into the processing space 129 and RF power (RF signal) supplied to the support base 107 by the RF generator 118. The processing space 129 is fluidly connected to one or more dedicated vacuum pumps through a vacuum outlet 120. These vacuum pumps maintain the processing space 129 at sub-atmospheric pressure conditions and discharge the processing gas or other gases through the vacuum outlet 120. In some embodiments, a substrate support assembly 136 located within the processing space 129 is positioned on a support shaft 138, which is grounded and extends through a chamber base 124. However, in some embodiments, the RF generator assembly 160 is configured to supply RF power to a bias electrode 104 located on the substrate support 105 and directed to the support base 107.

[0024]

[0029] As briefly described above, the substrate support assembly 136 typically includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may also include an insulating plate 111 and a grounding plate 112, as detailed below. The support base 107 is electrically insulated from the chamber base 124 by the insulating plate 111, with the grounding plate 112 interposed between the insulating plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to and positioned on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 positioned on the substrate support 105 during substrate processing.

[0025]

[0030]

[0031] Figure 2 shows an example of a pulsed voltage waveform, including a voltage pulse provided in the pulsed voltage waveform established on the substrate by supplying a voltage pulse to the bias electrode 104 during plasma processing using a PV waveform generator 105 according to one embodiment. It has been found that the establishment of a PV waveform on the substrate during plasma processing can be advantageously used to control the characteristics of the plasma sheath formed above the substrate surface during plasma processing. By controlling the magnitude and shape of the plasma sheath formed above the substrate surface, it becomes possible to control the interaction between ions and the substrate surface during processing, such as controlling the ion energy distribution function (IEDF), electron energy distribution function (EEDF), ion directivity, and other plasma-related properties.

[0026]

[0032] In Figure 2, waveform 225 includes two main stages: an ion current stage and a sheath collapse stage. Both the ion current stage and the sheath collapse stage of waveform 225 can be established on the substrate 103 during plasma processing. At the start of the ion current stage, a voltage drop occurs on the substrate 103 by supplying the negative portion (e.g., the ion current portion) of the PV waveform supplied to the bias electrode 104 by the PV waveform generator 150, thereby forming a high-voltage sheath on the substrate 103. This high-voltage sheath allows the positive ions generated by the plasma to be accelerated toward the biased substrate during the ion current stage, and consequently, allows control over the amount and characteristics of the etching process performed on the substrate surface during plasma processing in the reactive ion etching (RIE) process. In some embodiments, it is generally desirable that the ion current stage includes a region of pulsed voltage waveform that achieves a stable or minimally fluctuating voltage on the substrate throughout this stage. Significant voltage fluctuations established in the substrate during the ion current stage, as indicated by the positive slope in waveform 225, can lead to undesirable fluctuations in IEDF or EEDF, and consequently, undesirable characteristics of the etching features formed on the substrate during the RIE process.

[0027]

[0033] In some implementations, due to system complexity and equipment cost issues, positive ion currents are not compensated in the ion current stage of the voltage waveform, and therefore, the negative voltage on the substrate decays over time (e.g., becomes less negative). Waveform 225 is an example of an uncompensated pulsed PV waveform established on the substrate 103 during plasma processing by supplying a PV waveform to the bias electrode 104. Without compensation, the substrate voltage rises in the ion current stage (also referred to as voltage droop in this document). Voltage droop worsens with increasing plasma density (e.g., increased ion current), which leads to an expansion of the ion energy distribution (IED) toward the lower energy region.

[0028]

[0034] In some cases, a ramp voltage is generated to compensate for this voltage rise in part of the ion current stage by using a current source or multiple voltage sources connected to an electrode (e.g., electrode 104). Alternatively, the compensated PV waveform observed on the substrate can be established by applying a negative voltage ramp to the PV waveform provided to the bias electrode 104 by the PV waveform generator 150 in the ion current stage of a pulsed voltage waveform. However, at higher voltages (e.g., above 5kV), it is difficult to generate a customized waveform with a ramp to compensate for this voltage rise.

[0029]

[0035] In some embodiments, high-frequency voltage waveforms may be used to mitigate the effects of this voltage rise (i.e., droop) that occurs during the ion current stage. Generating high-frequency voltage pulse trains at pulse repetition frequencies or pulse switching frequencies above 400 kHz is problematic due to physical and practical device constraints. Therefore, the switching speed of conventional high-voltage switching is limited to a practical maximum switching speed to avoid thermal damage that occurs when used at medium-to-high frequencies. In certain embodiments of this disclosure, alternating arrangements of voltage pulses are used to generate a waveform supplied to a composite load (such as an electrostatic chuck and plasma 101) so that the load receives pulses at a higher frequency and the effects of voltage droop on the substrate surface are mitigated. For example, positive voltage pulses with a frequency of about 400 kHz may be used to obtain an IED with a single energy peak by periodically establishing a negative direct current (DC) bias on the substrate. As detailed in this book, in the ion current stage of the first voltage waveform pulse, when the voltage on the substrate surface rises to a certain threshold, a second voltage waveform pulse may be applied (e.g., from a different source or switch) to reset the voltage on the substrate surface during the subsequent pulse cycle.

[0030]

[0036] The PV waveform generated by the PV waveform generator 150 may include multiple bursts (not shown). Each burst consists of a pulse voltage waveform containing multiple asymmetric voltage pulses. In some embodiments, a bias voltage is applied to each of the asymmetric voltage pulses in the ion current stage. In other words, the off-time T of each voltage pulse off This occurs during the sheath collapse stage, and the application of the bias voltage occurs during the on-time T in the ion current stage. on It will be held at [location]. On time T on and off-time T off This is the duration T of each voltage pulse. P It is set as a percentage. The frequency of each voltage pulse is T P This can be adjusted by increasing or decreasing the on-time T, while the on-time T on and off-time Toff , T P can be adjusted by changing these percentages of . Further, the voltage pulse has an applied voltage V, and the applied voltage V is defined as the peak voltage in the sheath collapse stage.

[0031]

[0037] FIG. 3A shows pulses of a PV waveform generated by PV waveform generator 150 and supplied to bias electrode 104, according to certain embodiments. PV waveform generator 150 is configured to generate a PV waveform 310 comprising a plurality of bursts of voltage pulses (e.g., 310a) based on information provided in parameters of a synchronization signal 320 provided by controller 126, a first transistor-transistor logic (TTL) input signal 330, and a second TTL 340 input signal. Characteristics of voltage pulses within the bursts of voltage pulses generated by PV waveform generator 150 are controlled by synchronization signal 320 and first and second TTL input signals 330 and 340 (FIG. 4) from pulser 470. In some embodiments, at least one parameter of voltage pulses within a burst is based on a parameter of synchronization signal 320. In one example, burst 310a may include a plurality of micro-pulses 312 (e.g., 312a and 312b) corresponding to first and second TTL input signals 330 and 340. For clarity, in FIGS. 3A and 3B, the characteristics of the first TTL input signal 330 and the corresponding micro-pulse 312a are labeled S1, and the characteristics of the second TTL input signal 340 and the corresponding micro-pulse 312b are labeled S2.

[0032]

[0038] In some embodiments, bursts are transmitted between each waveform pulse of the synchronization signal 320. At least one parameter of the asymmetric voltage pulse constituting each burst (such as burst frequency, pulse-on time, pulse voltage, and combinations thereof) may be based on the parameters of each waveform pulse of the synchronization signal 320. In some embodiments, the PV waveform generator 150 may be configured to supply bursts with various parameters based on one or more characteristics of the synchronization signal 320 from the controller 126 received by the PV waveform generator 150 in order to adapt to variations in IEDF, EEDF, and undesirable characteristics (such as non-uniformity of etched features). Advantageously, it is possible to improve etched features formed across the entire surface of the substrate 103 by controlling the partial characteristics of the pulse voltage waveform during various phases of the plasma process performed on the substrate 103. For example, a higher voltage pulse frequency in a burst may result in higher etching uniformity in the central portion 170 (Figure 1) of the substrate 103, while a lower voltage pulse frequency in a burst may result in lower etching uniformity in the edge portions 172 of the substrate 103. In another example, a longer pulse-on time relative to the pulse-off time may result in a faster etching rate at the edges 172 of the substrate 103, while a shorter pulse-on time may result in a slower etching rate at the central portion 170 of the substrate 103. It has been found that pulse frequency can also affect other important plasma processing parameters (such as etching selectivity). In another example, controlling the pulse voltage level, such as making the voltage level of one phase of the plasma process higher than that of another, may improve the ability to etch deep features on the substrate surface, increase the etching rate, and increase the plasma sheath (and vice versa for pulse rate), while decreasing the voltage level may be beneficially used to form specific types of etched features. In yet another example, adjusting the pause time between bursts of voltage pulses may be used to provide extra time for etching byproducts to pump out of the processing space 129, which may improve etching uniformity, while shortening the pause time between bursts may improve substrate throughput during plasma processing.Therefore, in each of the methods described later, at least one parameter of the voltage pulses in various bursts of the PV waveform may be adjusted during processing to achieve the desired plasma processing result. To fine-tune the plasma processing result observed on the substrate, a combination of separate bursts having voltage pulses with various characteristics may be used.

[0033]

[0039] At least one parameter of each voltage waveform during a burst may be based on the parameters of each waveform pulse of the synchronization signal 320. The parameters of each waveform pulse of the synchronization signal 320 may correspond to one, all, or a combination of such parameters applied to the voltage pulses during the burst. Furthermore, multiple synchronization signals corresponding to various parameters of each burst may also be used to distinguish between the characteristics applied to each voltage pulse during the burst.

[0034]

[0040] In some embodiments, the synchronization signal 320 includes a pulse-on delay (POD) 322, a pulse-end delay (PED) 324, or both. The POD 322 allows the diode generator to ramp up before processing. The PED 324 allows other substrate processing operations to be performed during the burst 310.

[0035]

[0041] In some embodiments, the first TTL input signal 330 and the second TTL input signal 340 correspond to the first pulser 470a and the second pulser 470b (Figure 4), respectively. The first TTL input signal 330 and the second TTL input signal 340 have separate amplitudes and durations (e.g., T) for each signal. p1 and T p2 The first TTL input signal 330 and the second TTL input signal 340 enable the signals from the first pulser 470a and the second pulser 470b to produce a specific off-time or "dead time" (T) in each burst 310, which generates multiple micropulses 312 with different amplitudes and durations. DWith this, the pulses can be received sequentially or alternately between each other. By alternately arranging the micropulses 312 from separate pulsers (e.g., a first pulser 470a and a second pulser 470b), a switching frequency faster than the switching frequency limit of the individual pulsers can be obtained (e.g., a frequency above 400 kHz in the case of a MOSFET-based pulser).

[0036]

[0042] By combining alternating TTL input signals (e.g., 330 and 340) with a synchronization signal (e.g., 320), the PV waveform 310 will have multiple fine-tuning elements (knobs) for substrate processing.

[0037]

[0043] Advantageously, to achieve a desired etching profile across the entire substrate 103, the synchronization signal 320 may be configured to change the parameters of the PV waveform 310 during processing, based on the etching recipe and the desired etched features formed on the substrate 103. In other words, the synchronization signal 320 may be configured to control the supply of voltage pulses in each burst in any preferred order or arrangement to achieve a desired etching profile, although the waveform pulses are arranged alternately in Figure 3A.

[0038]

[0044] Furthermore, the pause time between bursts of the PV waveform 310 may correspond to the pause time between waveform pulses of the synchronization signal 320, the first TTL input signal 330, and the second TTL input signal 340. For example, the PV waveform will not output bursts without the TTL input signals (e.g., 330 or 340) and the synchronization signal 320. Moreover, the PV waveform will not output pulses in the POD 322 or PED 324 of the synchronization signal 320.

[0039]

[0045] Figure 3A shows a burst generated based on two different pulsers, but the number of pulsers that generate separate TTL input signals is not intended to be limited by this disclosure. Each characteristic of each voltage waveform in the burst can be controlled by using one or more synchronization signals.

[0040]

[0046] Figure 3B shows an embodiment of the present disclosure with two synchronization signals (e.g., a first synchronization signal 360 and a second synchronization signal 390). The PV waveform 350 is configured similarly to the PV waveform 310 and includes a plurality of voltage pulse bursts (e.g., 350a) having a plurality of micropulses 352 (e.g., 352a and 352b) corresponding to a first TTL input signal 370 and a second TTL input signal 380. The first synchronization signal 360 includes POD 362 and PED 364. In Figure 3B, the second synchronization signal 390 does not include a POD or PED, but may optionally include a POD, a PED, or both. As shown in Figure 3B, burst 350a is transmitted in each waveform pulse of the first synchronization signal 360 (excluding POD 362 and PED 364) that overlaps with the waveform pulse of the second synchronization signal 390.

[0041]

[0047] Figure 4 shows a connection diagram of the controller 126. As shown, the controller 126 may include a software interface 410 connected to the logic board 440 through pulsers 420, 430, and 432. The logic board 440 is configured to supply a synchronous pulse 450 (320 in Figure 3A) to the RF generator 118. The logic board 440 is connected to a Dante match 480 and to a plurality of pulsers 470 (e.g., a first pulser 470a and a second pulser 470b) configured to supply a plurality of TTL input signals (e.g., a first TTL input signal 330 and a second TTL input signal 340). The pulsers 470 are then connected to a bias electrode 104.

[0042]

[0048] Figure 5 is a process flow diagram showing method 500 for waveform generation. Method 500 may be performed by a waveform generation system including a waveform generator (e.g., waveform generator 150) and a system controller (e.g., system controller 126).

[0043]

[0049] Method 500 begins in activity 502 by the PV waveform generator receiving a first TTL input signal (e.g., first TTL input signal 330) and a synchronization signal (e.g., synchronization signal 320) from the controller (e.g., controller 126) of the plasma processing chamber (e.g., plasma processing chamber 100). In activity 504, the PV waveform generator supplies a first PV micropulse (e.g., 312a) having a duration and amplitude.

[0044]

[0050] In activity 506, the PV waveform generator receives a second TTL input signal (e.g., second TTL input signal 340) and a synchronization signal (e.g., synchronization signal 320) from the controller.

[0045]

[0051] In activity 508, the PV waveform generator supplies a second PV micropulse (e.g., 312b) having duration and amplitude. The duration, amplitude, or both of the second PV micropulse may be equal to the duration, amplitude, or both of the first PV micropulse. Alternatively, the duration, amplitude, or both of the first and second PV micropulses may be different. For example, the duration of the first PV micropulse may be equal to the duration of the second PV micropulse, but their amplitudes may be different.

[0046]

[0052] The first PV micropulse may be a plurality of first PV micropulses, and the second PV micropulse may be a plurality of second PV micropulses. Each of the plurality of second PV micropulses may sequentially follow each of the plurality of first PV micropulses (i.e., they may be arranged alternately). This makes it possible to overcome the switching frequency limits of individual pulsers by supplying micropulses from an alternately arranged TTL input signal.

[0047]

[0053] In this book, the term "coupled" is used to refer to a direct or indirect connection between two objects. For example, if object A is physically touching object B, and object B is touching object C, then objects A and C can be considered coupled, even if they are not directly physically touching each other. For example, object 1 can be coupled to object 2 even if it is not directly physically touching object 2.

[0048]

[0054] While the foregoing description applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A substrate processing system A substrate support assembly placed inside the processing chamber, A bias electrode disposed within the substrate support assembly, A pulse voltage waveform generator configured to supply a pulse voltage waveform to the bias electrode, A support base that acts as a radio frequency (RF) electrode, An RF generation device assembly electrically connected to the support base, A controller connected to the pulse voltage waveform generator and the RF generator assembly, comprising a plurality of pulsers configured to provide a plurality of transistor-transistor logic (TTL) input signals, and at least one synchronous pulser configured to transmit a synchronous signal, A memory for storing a program that, when executed by the controller, is configured to provide instructions for generating a pulse voltage waveform which alternately includes a plurality of voltage pulses corresponding to the plurality of TTL input signals, and A substrate processing system comprising:

2. The substrate processing system according to claim 1, wherein the plurality of pulsers include a first pulser configured to provide a first transistor-transistor logic (TTL) input signal and a second pulser configured to provide a second TTL input signal.

3. The substrate processing system according to claim 1, wherein the program is configured to provide a command to generate the pulse voltage waveform, which includes a plurality of pulse voltage micropulses, when executed by the controller.

4. The substrate processing system according to claim 3, wherein the plurality of pulse voltage micropulses correspond to the plurality of pulsers.

5. The substrate processing system according to claim 1, wherein the program, when executed by the controller, is configured to provide a command to the synchronous pulser to generate the synchronous signal, the synchronous signal includes a pulse-on delay, and no pulse is supplied to the bias electrode during the pulse-on delay.

6. The substrate processing system according to claim 1, wherein the program, when executed by the controller, is configured to provide a command to the synchronous pulser to generate the synchronization signal, the synchronization signal includes a pulse termination delay, and during the pulse termination delay, no pulse is supplied to the bias electrode.

7. The substrate processing system according to claim 1, wherein the program, when executed by the controller, is configured to provide instructions to operate a plurality of pulsers, including a first pulser configured to provide a first transistor-transistor logic (TTL) input signal and a second pulser configured to provide a second TTL input signal, wherein the pulse voltage waveform includes a plurality of pulse voltage micropulses, the plurality of pulse voltage micropulses includes a plurality of first pulse voltage micropulses corresponding to the first TTL input signal and a plurality of second pulse voltage micropulses corresponding to the second TTL input signal, and the plurality of pulse voltage micropulses are supplied to the bias electrode according to the synchronization signal.

8. The substrate processing system according to claim 7, wherein the program, when executed by the controller, is configured to provide a command to the synchronous pulser to generate the synchronization signal, the synchronization signal includes a pulse-on delay and a pulse-end delay, and no pulse voltage micropulse is supplied to the bias electrode.

9. The substrate processing system according to claim 7, wherein each of the plurality of second pulse voltage micropulses is alternately arranged between each of the plurality of first pulse voltage micropulses.

10. A processing system, Processing chamber and A pulse voltage waveform generator configured to supply a pulse voltage waveform containing multiple voltage pulses to a bias electrode placed in the processing chamber, An RF generator configured to supply radio frequency (RF) to a support base, Controller and A memory for storing the program executed by the controller, The program includes instructions, and the instructions are given to the pulse voltage waveform generator. The waveform generator receives from the controller a first transistor-to-transistor logic (TTL) input signal from a first pulser among the plurality of pulsers, a second transistor-to-transistor logic (TTL) input signal from a second pulser among the plurality of pulsers, and a synchronization signal. After receiving the first TTL input signal, the second TTL input signal, and the synchronization signal, the waveform generation device alternately supplies a first pulse voltage micropulse corresponding to the first TTL input signal and a second pulse voltage micropulse corresponding to the second TTL input signal to the bias electrode located in the substrate support assembly within the processing system. To execute Processing system.

11. The command is given to the pulse voltage waveform generator, The waveform generation device receives from the controller a second TTL input signal from the second pulser among the plurality of pulsers and the synchronization signal, After receiving the second TTL input signal and the synchronization signal, the waveform generation device supplies a second pulse voltage micropulse to the bias electrode located in the substrate support assembly within the processing system. The processing system according to claim 10, configured to further perform the following.

12. The processing system according to claim 11, wherein the first pulse voltage micropulse comprises a plurality of first pulse voltage micropulses, the second pulse voltage micropulse comprises a plurality of second pulse voltage micropulses, and each of the plurality of second pulse voltage micropulses is alternately arranged between each of the plurality of first pulse voltage micropulses.

13. The processing system according to claim 11, wherein the command is configured to cause the waveform generator to supply the first pulse voltage micropulse and the second pulse voltage micropulse when a plurality of synchronization signals overlap.

14. The processing system according to claim 11, wherein the first pulse voltage micropulse includes a plurality of first pulse voltage micropulses, and the second pulse voltage micropulse includes a plurality of second pulse voltage micropulses.

15. The processing system according to claim 14, wherein each of the plurality of second pulse voltage micropulses is alternately arranged between each of the plurality of first pulse voltage micropulses.

16. An edge control electrode is located within a substrate support assembly located within an edge ring, A second pulse voltage waveform generator configured to supply a second pulse voltage waveform to the edge control electrode, The substrate processing system according to claim 1, further comprising:

17. An edge control electrode is located within a substrate support assembly located within an edge ring, A second pulse voltage waveform generator configured to supply a second pulse voltage waveform to the edge control electrode, The processing system according to claim 10, further comprising:

18. The substrate processing system according to claim 1, further comprising a DC power supply source electrically connected to the bias electrode.

19. The processing system according to claim 10, further comprising a DC power supply source electrically connected to the bias electrode.

20. The substrate processing system according to claim 1, wherein the plurality of TTL input signals have different characteristics from each other.

21. The processing system according to claim 10, wherein the first TTL input signal and the second TTL input signal have different characteristics from each other.

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