A calculation system, calculation method, and calculation program that include exception state retention and control.

Abstract

This technology provides a method for maintaining the continuity and safety of calculations even when unusual calculation conditions occur during the calculation process. [Solution] The arithmetic processing system 1 of this disclosure comprises a value register 102, a state register 105, an arithmetic logic circuit 101, an anomaly detection circuit 103, a write-back control circuit 104 that maintains the immediately preceding valid value held in the value register 102, a state transition circuit 106 that updates the state index stored in the state register 105, and a recursive data path 107 that feeds the state index back to the input side of the arithmetic logic circuit 101. Furthermore, the anomaly detection signal output by the anomaly detection circuit 103 is supplied only as input to the write-back control circuit 104 and the state transition circuit 106, and even if a unique calculation state occurs, the control flow is not changed and calculations by the arithmetic logic circuit 101 continue.

Description

[Technical Field]

[0001] The present invention relates to an arithmetic processing system, an arithmetic processing method, and an arithmetic processing program that include exception state holding and control for exceptional calculations that may occur during an arithmetic process. [Background Art]

[0002] In conventional arithmetic processing devices, the following methods are mainly known as coping methods when an exceptional calculation state occurs during an arithmetic process.

[0003] The first method is called the exception trap method, which rewrites a program counter when detecting the occurrence of an exceptional calculation state (exceptional state) that may occur during an arithmetic process, and transfers the control flow to an exception handler (exception processing routine). This method is the most common form of exception handling in microprocessors, but since it involves pipeline stoppage or flushing, the arithmetic execution time dynamically fluctuates, making it difficult to guarantee the worst-case execution time (WCET). In addition, register saving, context switching, cache state changes, and the like occur along with the control flow transition, which reduces processing throughput and can form a side channel where fluctuations in power consumption and timing can be observed from the outside.

[0004] The second method outputs a special value such as Not a Number (NaN) conforming to the IEEE754 standard or the like as an arithmetic result in the event of an exception, and allows software to subsequently refer to a status flag to branch processing. In this method, since the NaN value is written back to the register file, the NaN value propagates in subsequent operations, destroying the previous normal arithmetic result. In addition, since flag reference and branching processing by software are required, this can cause response delay in applications that require real-time performance.

[0005] A third method is known to avoid register hazards by selecting a pre-prepared fixed value on the input side using a selector when an exception occurs, thereby preventing pipeline shutdown (see, for example, Patent Document 1). However, this method involves substitution with a fixed value and does not retain the normal calculation result immediately before the exception occurred. Furthermore, it does not have a mechanism for structurally accumulating the history of exception occurrences, nor does it have a configuration that controls the input of subsequent calculations based on accumulated information of exception occurrences. Moreover, depending on the setting of the exception enable flag, exception processing (control flow change) may still occur, and it does not structurally guarantee that the control flow will not change.

[0006] A fourth method has been proposed in which, when an abnormal value occurs in the calculation result, the cause is sequentially identified by software processing, and depending on the cause, a transition to fail-safe processing or continuation of calculation using simplified control logic is selected (see, for example, Patent Document 2). However, this method is based on post-event software processing via an interrupt controller, and a change in the control flow (activation of interrupt processing) and a halt in the pipeline inevitably occur between anomaly detection and resolution. Furthermore, since the configuration involves writing the abnormal value to a register before the cause identification processing, the retention of the immediately preceding normal value is not guaranteed. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2000-305782 [Patent Document 2] Japanese Patent Publication No. 2019-106042 [Overview of the project] [Problems that the invention aims to solve]

[0008] The conventional technologies described above have the following problems. Specifically, in conventional technologies, exceptions, which are unique computational states that occur during the computation process, are treated as "events that should be handled by changing the control flow," and the occurrence of an exception inevitably accompanies a transition in the control flow (rewriting the program counter, branching to an exception handler, or initiating an interrupt handler). This structure leads to the following technical problems.

[0009] Firstly, there is the challenge of temporal indeterminacy. When an exception occurs and the control flow changes, pipeline stoppage or flushing, branch prediction recalculation, cache state changes, etc., occur dynamically, causing the computation execution time to fluctuate. In real-time control fields such as autonomous driving, aerospace control, and robotics, deterministic guarantee of execution time is a prerequisite for safety, and this challenge becomes an essential constraint.

[0010] Secondly, there is the issue of contamination of the computation context. In conventional methods, when an exception occurs, an abnormal value (NaN, fixed value, etc.) is written back to the register file, so the normal calculation value (previous valid value) that was held immediately before the exception occurs is destroyed, making it difficult to return to a safe calculation state. In this regard, Patent Document 1 discloses a configuration in which a selector selects a pre-prepared fixed value as the input for the subsequent instruction when an exception is detected, but this does not block writing to the value register itself and retain the previous normal calculation result as is. That is, the value held in the value register when an exception occurs is a fixed value predetermined independently of the calculation context, and is not the normal calculation result immediately before the exception occurred. Furthermore, in the configuration of Patent Document 1, if the exception enable flag is set to 1, exception processing (control flow change) is still executed. And when the control flow is changed when an exception occurs, patterns different from normal occur in processing time and power consumption, which may create vulnerabilities to external power analysis and timing analysis.

[0011] Thirdly, there is the issue of loss of throughput. If the pipeline stops or flushes every time an exception occurs, processing efficiency is significantly reduced in continuous data stream processing and high-frequency computing environments. In this regard, Patent Document 2 discloses a configuration in which the cause is identified when the calculation result of a floating-point arithmetic unit is NOT a number, and the system selects whether to transition to fail-safe processing or continue calculation control depending on the identified cause. However, this method detects the occurrence of NOT a number via an interrupt controller and invokes error processing as an interrupt. Therefore, between the detection of an anomaly and the start of countermeasures, the interrupt controller inevitably invokes an interrupt, the program counter is rewritten, and the pipeline stops, thus not achieving anomaly handling without changing the control flow. Furthermore, the configuration in Patent Document 2 does not physically maintain the immediately preceding valid value because the immediately preceding normal calculation result is overwritten by the NOT a number.

[0012] The purpose of this disclosure is to provide a technology that can maintain the continuity and security of calculations even when unusual calculation conditions occur during the calculation process. [Means for solving the problem]

[0013] An arithmetic processing system equipped with exception state retention and control according to a first aspect of the present disclosure includes: a value register for holding a value to be calculated; a state register configured as a memory element independent of the value register and storing a state index indicating the history of occurrence of a unique calculation state that occurred during the calculation process; an arithmetic logic circuit that performs calculations based on the value held in the value register; an abnormality determination circuit that determines whether a predetermined abnormal condition defined as the unique calculation state has been met based on the process or result of the calculation in the arithmetic logic circuit; a write-back control circuit that, based on an abnormality detection signal output by the abnormality determination circuit, hardware-wise suppresses the writing of the calculation result from the arithmetic logic circuit to the value register and maintains the immediately preceding valid value held in the value register; a state transition circuit that updates the state index stored in the state register based on the abnormality detection signal; and a recursive data path that feeds back the state index output from the state register to the input side of the arithmetic logic circuit and hardware-wise switches the input data in subsequent calculations based on the state index. Furthermore, the abnormality detection signal is supplied only as an input to the write-back control circuit and the state transition circuit, and does not have an electrical connection to any of the inputs of the circuit that controls the update of the program counter, the exception transition circuit that controls branching to the exception handler, and the circuit that controls interrupt requests. As a result, even when the unusual calculation state occurs, the control flow is not changed and the calculation by the arithmetic logic circuit continues.

[0014] In the above arithmetic processing system, exception signals related to exceptions, which are unique computational states that occur during the calculation process, are physically isolated from the control flow change system. This prevents pipeline stoppages and control flow transitions, thus achieving deterministic guarantee of calculation execution time. In other words, the calculation execution time does not fluctuate regardless of whether or not unique computational states (singular states) occur during the calculation process. This enables constant-time execution and guarantees the worst-case execution time. Furthermore, the write-back control circuit physically retains the immediately preceding valid value, the occurrence history is accumulated in the state register, and the input to subsequent calculations is autonomously switched by the recursive data path. In other words, unlike conventional fixed-value substitution methods and NaN output methods, it is possible to retain meaningful values ​​that are in line with the calculation context. Moreover, by managing exceptions, which are unique computational states that occur during the calculation process, as "evaluable state information," it becomes possible to achieve stepwise control according to severity.

[0015] Furthermore, in the arithmetic processing system of the first aspect of this disclosure, the state register may be a memory element having a bit width independent of the value register and assigned to a unique register identification space selected by an independent address decoding circuit. This physically separates the update control of the value and the state, enabling parallel operation.

[0016] Furthermore, in the arithmetic processing system in the first aspect of this disclosure, the state index may be structured data including a depth region that holds depth information for recording the cumulative number of occurrences of the unique computation state, and an attribute region that holds attribute information indicating the source type or computation type of the unique computation state. This makes it possible to obtain both the cumulative severity and source of the exception with a single reference. In this case, the state transition circuit may have a configuration that cumulatively increments the depth information using a hardware counter, or stores the attribute information by non-destructively superimposing or concatenating it with an existing bit sequence using at least one of a logical OR circuit, an exclusive OR circuit, or a bit shift coupling circuit. This ensures that past occurrence history is retained without being erased.

[0017] Furthermore, in the arithmetic processing system according to the first aspect of this disclosure, the write-back control circuit may be configured to mask the write-enable signal input to the write port of the value register with a logic gate based on the anomaly detection signal without stopping the clock signal of the arithmetic logic circuit, thereby selectively suppressing only writes to the value register while the arithmetic logic circuit continues to operate. This does not affect the timing design of the pipeline and does not cause fluctuations in the number of execution cycles. In other words, since the occurrence or absence of a singular state is not reflected in the execution path or execution time, security resistance against side-channel attacks and the like is improved. In addition, since calculations continue without stopping or flushing the pipeline, a decrease in processing efficiency is suppressed even under high-load environments.

[0018] Furthermore, in the arithmetic processing system according to the first aspect of this disclosure, the recursive data path may include a selector that takes a signal obtained by decoding at least a portion of the state indicator as input, and the selector may be configured to physically switch the operand supplied to the next stage of the arithmetic logic circuit to a predetermined bitmask value, shift amount, or alternative constant without changing the control flow, even during the period when the anomaly detection signal is asserted. This enables hardware-level arithmetic transformation without the need for software instructions.

[0019] Furthermore, in the arithmetic processing system according to the first aspect of this disclosure, the most recent valid value held in the value register is a normal calculation result in which the anomaly detection circuit did not detect the unusual calculation state in past calculation cycles, and the write-back control circuit may have a configuration that maintains the last confirmed safe value as the valid value when an anomaly occurs by performing latch control that permits updating the value register only when the anomaly detection circuit determines that it is normal. This ensures that a safe value is always held in the value register.

[0020] Furthermore, in the arithmetic processing system according to the first aspect of this disclosure, the arithmetic logic circuit may have a pipeline structure that advances a plurality of arithmetic stages in synchronization with a clock signal, the abnormality determination circuit may determine whether the abnormality condition is met at a predetermined stage in the pipeline structure, and the state index updated by the state transition circuit may be propagated to the next stage in synchronization with a data path that goes to the value register via an interstage register of the pipeline structure. This ensures consistency between values ​​and states at the hardware level.

[0021] Furthermore, in the arithmetic processing system according to the first aspect of this disclosure, the anomaly detection circuit may have a configuration that determines the occurrence of the unusual calculation state by detecting a signal change corresponding to at least one of division by zero, overflow, underflow, undefined operation, or predetermined reserved bit pattern at a predetermined bit position or calculation status flag line of the arithmetic logic circuit. This improves the comprehensiveness of the anomaly detection.

[0022] Furthermore, in the arithmetic processing system in the first aspect of this disclosure, the system may further include a state evaluation circuit that compares the state index with a predetermined determination condition, and an output control gate circuit that, based on a determination signal from the state evaluation circuit, physically performs either allowing, blocking, or switching to an alternative signal the output of a value held in a value register to the outside, wherein the output data path from the value register to the outside is connected only through the output control gate circuit. This enables hardware-driven fail-safe operation. In other words, this is hardware-driven safety governance (output governance), where the governance control of the external output is realized by the output control gate circuit. In this case, the system may further include a policy memory that holds the determination condition referenced by the state evaluation circuit, the policy memory consisting of hardware memory elements and configured to be writable via an update path independent of the data path of the arithmetic logic circuit. This enables dynamic changes to the policy without stopping the calculation. Furthermore, the policy memory may be configured to dynamically switch the threshold or determination table referenced by the state evaluation circuit in hardware in response to an external context signal indicating the safety requirement level or task priority. This allows the same hardware to support multiple safety levels.

[0023] Furthermore, in the above configuration, the state evaluation circuit and the output control gate circuit may be driven by an independent control clock having a different frequency or phase from the clock of the arithmetic logic circuit. This ensures stable output control timing. The output control gate circuit may also be configured to output to the outside, via a hardware multiplexer, one of the following processes depending on the state index: masking the output value of the value register, fixing it to a predetermined saturation value, or replacing it with a system-defined default value. This enables a gradual reduction in accuracy according to the severity of the anomaly.

[0024] Furthermore, in the arithmetic processing system according to the first aspect of the present disclosure, the state transition circuit may be configured to receive a signal from an external sensor provided outside the arithmetic logic circuit for detecting a physical abnormality, and store abnormality information based on the signal in the same status register that stores abnormality information resulting from an operation. This enables unified management of arithmetic abnormalities and physical abnormalities.

[0025] Furthermore, the arithmetic processing system according to the first aspect of the present disclosure may be implemented as an extension module or an IP core disposed adjacently to an arithmetic operation unit of an existing processor, and configured to execute operations while being physically separated from an interrupt request signal line and a program counter update logic of the processor. This enables retrofitting and integration into an existing processor.

[0026] Furthermore, in the arithmetic processing system according to the first aspect of the present disclosure, in a configuration in which a plurality of said arithmetic logic circuits are arranged in parallel, each arithmetic logic circuit has said independent status register and said state transition circuit exclusively owned by itself, and may be configured to isolate, at a hardware level, the occurrence of said peculiar computation state in one arithmetic logic circuit from the operation progress and control flow of other arithmetic logic circuits. This enables fault localization in a multi-core environment.

[0027] Furthermore, in the arithmetic processing system according to the first aspect of the present disclosure, operation data output to the outside may be configured such that at least a part of the status indicator is physically or structurally attached thereto as a sideband signal or a predetermined field in a packet header, so that the status indicator can be captured by another arithmetic processing system on the receiving side. This enables state tracking in a distributed system.

[0028] A second aspect of the present disclosure relates to an arithmetic processing method for which an exception state is maintained and controlled, comprising an arithmetic processing system having a value register for holding a value to be calculated and a state register independent of the value register, the method comprising: a step in which an abnormality determination circuit determines that a predetermined abnormal condition defined as a unique calculation state has been met based on the process or result of calculation in an arithmetic logic circuit, and outputs an abnormality detection signal; a step in which, based on the abnormality detection signal, the writing of the calculation result from the arithmetic logic circuit to the value register is suppressed in hardware and the immediately preceding valid value held in the value register is maintained; a step in which, based on the abnormality detection signal, a state index stored in the state register is updated; and a step in which the updated state index is fed back to the input side of the arithmetic logic circuit and the input data for subsequent calculations is switched in hardware based on the state index. The abnormality detection signal is used only for suppressing writing to the value register and controlling the update of the state index, and is not used for updating the program counter, branching to an exception handler, or controlling interrupt requests, so that even when the unique calculation state occurs, the control flow is not changed and calculations by the arithmetic logic circuit continue.

[0029] Furthermore, in addition to the hardware-based aspects described above, this disclosure also includes aspects that achieve equivalent functionality using software without changing the hardware configuration of an existing processor. The software-based aspects configure all processing as instruction sequences that do not include conditional branch instructions (branchless instruction sequences), thereby avoiding conditional changes (branching) to the program counter and maintaining the same instruction execution path regardless of whether a singular state occurs or not.

[0030] In hardware form, the function of the write-back control circuit is implemented in software form as a process that selects either the calculation result or the immediately preceding valid value without branching, based on an abnormality determination value, using conditional selection operations (conditional move instructions, predicate execution instructions, or SIMD selection instructions, etc.) or bitmask operations. In hardware form, the functions of the state register and state transition circuit are implemented as addition and logical OR operations on state data structures located in memory. In hardware form, the function of the recursive data path is implemented as a process that switches the input to the subsequent operation without branching, based on a conditional selection operation using a state index.

[0031] Furthermore, the arithmetic processing system comprising exception state retention and control according to a third aspect of the present disclosure is an arithmetic processing system comprising a processor and a memory connected to the processor, wherein the memory is provided with a value retention area for holding values ​​to be calculated and a state retention area configured as a storage area independent of the value retention area for storing state indicators that show the history of occurrence of unique calculation states that occurred during the calculation process, and the processor performs an abnormality determination process to calculate an abnormality determination value as an arithmetic or logical operation without using conditional branch instructions to determine whether a predetermined abnormal condition defined as the unique calculation state has been met with respect to the result of the calculation, and based on the abnormality determination value, the result of the calculation and The system performs a write-back control process that updates the value in the value storage area by selecting either the most recent valid value held in the value storage area or the current value using a conditional selection operation or bitmask operation without using a conditional branch instruction; a state update process that cumulatively updates the depth information in the state index held in the state storage area by an addition operation, or combines and updates the attribute information by a logical OR operation or exclusive OR operation, based on the abnormality determination value; and a feedback control process that switches the input data in subsequent calculations to a predetermined mask value, saturation value, or alternative value using a conditional selection operation or bitmask operation without using a conditional branch instruction, based on the state index held in the state storage area. The abnormality determination value is used only for controlling the write-back control process and the state update process, and is not used as an operand in a conditional branch instruction. As a result, the abnormality determination process, the write-back control process, the state update process, and the feedback control process are all executed as an instruction sequence that does not include a conditional branch instruction, and the same instruction execution path is maintained regardless of whether the unusual calculation state occurs or not.

[0032] Thus, in the arithmetic processing system according to the third aspect of this disclosure, the processor maintains the same instruction execution path regardless of whether a unique computation state occurs, by executing the abnormality detection process, write-back control process, state update process, and feedback control process as instruction sequences that do not include conditional branch instructions. As a result, the basic functions of this disclosure can be realized with software alone without changing the hardware of the existing processor. Because conditional branch instructions are not used, branch prediction errors and pipeline flushes do not occur, and it is guaranteed at the instruction sequence level that no conditional changes to the program counter occur. This achieves invariance of the instruction execution path, which is functionally equivalent to "control flow disconnection" in the hardware-based aspect. The maintenance of the immediately preceding valid value is realized by conditional selection calculations based on the abnormality detection value, cumulative state accumulation is realized by arithmetic operations on the state data structure in memory, and input switching for subsequent calculations is realized by conditional selection calculations based on the state index.

[0033] Furthermore, in the arithmetic processing system of the third aspect of this disclosure, the conditional selection operation in the write-back control process may be executed using any of the conditional move instruction, predicate execution instruction, or SIMD selection instruction provided by the processor. This enables efficient implementation according to the processor architecture.

[0034] Furthermore, in the arithmetic processing system of the third aspect of this disclosure, the state index may be placed in memory as a fixed-length bit field structure including a depth field indicating the cumulative number of occurrences of the singular computation state and an attribute field indicating the type of singular computation state that has occurred. This enables structured state management at the software level equivalent to that of a state register in a hardware embodiment.

[0035] Furthermore, in the arithmetic processing system of the third aspect of this disclosure, the feedback control processing may calculate the result of comparing the depth information of the state index with a predetermined threshold value as a selected value of 0 or 1 by arithmetic operation without using a conditional branch instruction, and use this selected value as a multiplication coefficient or bit mask to perform a selection between a normal operand and an alternative value. This enables threshold-based stepwise input switching without using conditional branching.

[0036] Furthermore, in the arithmetic processing system of a third aspect of this disclosure, the processor may further perform output control processing that compares the state index with predetermined policy data held in the memory, and based on the comparison result, permits, prohibits, or replaces the sending of the value held in the value holding area to an external output destination with an alternative value, without using conditional branch instructions. This enables output governance at the software level equivalent to that of an output control gate circuit in a hardware-based approach.

[0037] Furthermore, the arithmetic processing method comprising exception state retention and control according to the fourth aspect of the present disclosure is an arithmetic processing method executed by a processor in an arithmetic processing system comprising a processor and memory, comprising: a step of calculating an abnormality determination value by arithmetic or logical operation, without using a conditional branch instruction, whether or not a predetermined abnormal condition defined as a unique calculation state has been met with respect to the result of the calculation; a step of selecting either the result of the calculation or the immediately preceding valid value held in the memory, without using a conditional branch instruction, by a conditional selection operation or a bitmask operation, and updating the value in the memory, based on the abnormality determination value; a step of cumulatively updating depth information and attribute information in a state index held in the memory, based on the abnormality determination value; and a step of switching the input data for subsequent calculations by conditional selection operation or a bitmask operation, without using a conditional branch instruction, based on the updated state index. Furthermore, the abnormality determination value is used only to control the updating of the value in memory and the updating of the state indicator, and is not used as an operand of a conditional branch instruction. As a result, all of the steps are executed as an instruction sequence that does not include a conditional branch instruction, and the same instruction execution path is maintained regardless of whether or not the unusual calculation state occurs.

[0038] Furthermore, the arithmetic processing program comprising exception state retention and control according to the fifth aspect of this disclosure is a program executed by the arithmetic processing system according to the third aspect described above. [Effects of the Invention]

[0039] According to this disclosure, it is possible to provide a technology that can maintain the continuity and safety of calculations even when an unusual calculation state occurs during the calculation process. [Brief explanation of the drawing]

[0040] [Figure 1] This is a block diagram showing the overall configuration of the arithmetic processing system in the first embodiment. [Figure 2]This block diagram shows the arrangement of the processing system within the CPU pipeline, in comparison to the configuration of a conventional CPU. [Figure 3] This block diagram shows the internal structure of the ESRCS module as a structure that separates value paths and state paths. [Figure 4] This block diagram shows the signal path of the output signal of the abnormality detection circuit, in comparison to the configuration of a conventional CPU. [Figure 5] This diagram shows the timing relationships of the pipeline clock, calculation result, anomaly detection signal, post-mask write enable signal, value register update, state register update, and feedback signal over cycles N-2 to N+5. [Figure 6] This is a configuration diagram showing the overall configuration of the arithmetic processing system according to the second embodiment. [Figure 7] This is a flowchart showing the processing flow in the second embodiment. [Modes for carrying out the invention]

[0041] This disclosure relates to the retention and control of singular computation states that may occur during computation in an arithmetic processing unit. More specifically, this disclosure relates to an arithmetic processing system, an arithmetic processing method, and a program that, when a singular state such as division by zero, overflow, underflow, undefined operation, or a predetermined reserved bit pattern output as a computation result occurs, retains the singular state in the data path without changing the control flow, cumulatively evaluates it, and performs feedback to subsequent calculations and output control.

[0042] This disclosure relates to an arithmetic processing system equipped with a dedicated circuit configuration (an error detection circuit, a write-back control circuit, a state register, a state transition circuit, and a recursive data path) as a hardware embodiment, and to an arithmetic processing system, method, and program that achieve equivalent functionality using branchless instruction sequences without conditional branch instructions, without changing the hardware configuration of an existing processor.

[0043] This disclosure is applicable to various computing infrastructures, including processors, microcontrollers (MCUs), system-on-a-chip (SoCs), accelerators, programmable logic devices (FPGAs, etc.), chiplets, or three-dimensional stacked elements, and can be used in various data paths such as integer operations, floating-point operations, vector operations, matrix operations, approximation operations, or inference operations.

[0044] Embodiments of this disclosure will be described below with reference to the drawings. The configurations of the following embodiments are illustrative, and this disclosure is not limited to the configurations of these embodiments.

[0045] <Term definition> First, we define the terms used in the following embodiments. (1) A "singular calculation state" refers to a state detected in an arithmetic logic circuit, such as division by zero, overflow, underflow, undefined operation, output of a reserved bit pattern, or a similar state. Singular calculation states do not force the cessation of operations or changes in the control flow, but are defined as "state information" that is retained as the basis for decisions regarding input selection and output control of subsequent operations. (2) A "value register" is a physical memory element that holds data that is written back from the output of an arithmetic logic circuit and forms the basis for subsequent calculations or external outputs. In hardware embodiments, this may include general-purpose registers or floating-point registers in the register file of an existing processor. (3) A "state register" is a physical memory element that stores state indicators and has a physically or logically independent identification space, update control system, and read path from a value register. In hardware embodiments, it is implemented as a newly added dedicated register that is not included in the existing processor's register file. (4) An "independent address decoding circuit" refers to a decoding circuit that is provided separately from the address decoding circuit used for register selection of a value register (general-purpose register file) and does not share an input address bus with the address decoding circuit for that value register. In a typical processor, each register in the register file is selected by inputting the register specification field in the instruction (for example, the ModR / M field in the x86 architecture, or the Rn / Rd field in the ARM architecture) into the address decoding circuit. (5) The “unique register identification space” refers to a space of identifiers specifically assigned to state registers that does not overlap with the set of register numbers assigned to value registers (general-purpose register files) (for example, the register numbers RAX, RBX, ... in the x86 architecture, or the register numbers X0, X1, ... in the ARM architecture). “Unique” means that the identifiers (addresses or chip select signals) belonging to the identification space do not have a one-to-one correspondence with the identifiers used for selecting value registers (i.e., both value registers and state registers cannot be selected simultaneously with the same identifier). This assignment is a structural property that is statically determined at the time of hardware design and is not dynamically changed at runtime. (6) A "state index" refers to digital data that structures the history of occurrences of unique computational states as multidimensional information of depth (cumulative count) and attribute (type of occurrence). A state index is a hardware control parameter that is supplied directly without instruction execution as an input selection signal for an arithmetic logic circuit or a decision input for an output control gate circuit. (7) "Source type" refers to classification information that indicates the type of abnormal condition that caused the occurrence of the unusual computation state. The source type is information used to identify what abnormal condition in the arithmetic logic circuit caused the detected unusual computation state, and may specifically include the following classifications. (a) Division by Zero: An abnormal condition detected when the divisor is zero in a division operation. (b) Overflow: An abnormal condition detected when the result of an operation exceeds the representable range of the value register. (c) Underflow: An abnormal condition detected when the result of an operation falls below the minimum precision that can be represented in a value register. (d) Invalid Operation: An abnormal condition detected when an operation is attempted on an undefined combination of operands (e.g., the square root of a negative number, subtraction of infinity, etc.). (e) Reserved bit pattern detection: An abnormal condition that occurs when a predetermined bit pattern that is not used as a normal calculation value (for example, the signaling NaN bit pattern in the IEEE 754 standard, or a specific reserved pattern defined by the designer) is detected on the output bus of the calculation result. The above (a) through (e) are examples of source types, and other abnormal conditions (e.g., inexact results, denormal input, etc.) may be defined as source types depending on the type of arithmetic logic circuit to be implemented and its design specifications. (8) "Operation type" refers to classification information that indicates the type of operation the arithmetic logic circuit was performing when a unique calculation state occurred. The operation type is information that identifies the context of the operation, such as whether it occurred during an addition operation, a multiplication operation, or a floating-point operation, even if the source type is the same (e.g., overflow). Specifically, it may include the following classifications: (a) Integer addition / subtraction (b) Integer multiplication / division (c) Floating-point addition / subtraction (d) Floating-point multiplication / division (e) Vector operations or matrix operations (f) Approximation or inference operation The source type indicates "what kind of anomaly occurred," while the operation type indicates "which operation caused it." These are independent classification axes, and the attribute area may hold one or both depending on the implementation. (9) The "or" in "attribute information indicating source type or operation type" is intended to encompass all configurations in which the attribute area holds only source type, only operation type, and both source type and operation type. The number of bits and bit assignment of the attribute area are determined according to the implementation. For example, in a configuration where the attribute area consists of 8 bits, the lower 4 bits can be assigned to source type (bits for division by zero, overflow, underflow, and undefined operation), and the upper 4 bits can be assigned to operation type (bits for integer operation, floating-point operation, vector operation, etc.). Alternatively, a configuration in which all bits of the attribute area are assigned only to source type is also possible. (10) An “abnormality detection circuit” refers to a hardware circuit that monitors the output bus or status signal line of an arithmetic logic circuit and detects the occurrence of a specific calculation state based on a predetermined bit pattern or change in signal level. In a hardware embodiment, output signals such as an overflow flag generation circuit or division by zero detection circuit provided by the ALU / FPU of an existing processor can be used. (11) A “write-back control circuit” refers to a configuration that, based on an anomaly detection signal, physically disables the write enable signal (write enable) or the write data path from the arithmetic logic circuit to the value register using a logic gate. This configuration selectively masks only the write signal, rather than using clock gating. (12) A "state transition circuit" refers to a logic circuit that cumulatively or coupledly updates the depth information and attribute information of a state index based on an anomaly detection signal. It may include a structure that does not rely on a reset signal and enables non-destructive updating. (13) A "recursive data path" refers to a wiring structure that physically returns a state indicator to the input side of an arithmetic logic circuit (such as an operand selector). This enables arithmetic transformations that hardware-wise switch input data to masks, saturation, alternative constants, etc., based on the state indicator, without going through branching. (14) "Control flow disconnection" means a structure in which the signal path related to the output of the abnormality detection circuit or the update of the state indicator does not have a direct electrical connection to the input terminals of the program counter update control circuit, the exception vector generation circuit, and the interrupt controller, etc., which modify the control flow. (15) The “circuit that controls the update of the program counter” refers to a circuit provided within the processor’s control unit that determines the value of the program counter (PC) in the next cycle. In a typical processor, this circuit has the function of incrementing the PC by the length of the instruction during normal sequential execution, writing the branch destination address to the PC when a branch instruction is executed, and writing the exception vector address to the PC when an exception occurs. (16) The "exception vector generation circuit (exception transition circuit that controls branching to an exception handler)" refers to a circuit that generates the starting address (exception vector) of an exception handler (exception handling routine) when an arithmetic exception occurs and supplies that address to the program counter. In a typical processor, this circuit receives an exception detection signal, generates a reference address for the exception vector table according to the type of exception, and supplies that address to the PC update circuit. (17) An "interrupt controller (circuit that controls interrupt requests)" refers to a circuit (interrupt controller) that receives interrupt request signals generated from outside or inside the processor, and performs interrupt priority determination, masking, and transition control to the interrupt handler. In a typical processor, arithmetic exceptions (division by zero, overflow, etc.) are notified to the interrupt controller as a type of internal interrupt (synchronous exception), and the interrupt controller works in cooperation with the PC update circuit and the exception transition circuit to transition the control flow to the interrupt handler. (18) The “previous valid value” refers to the value that was successfully determined and held in the value register during the calculation cycle immediately preceding the detection of an unusual calculation state. This value, whose safety has been confirmed, is maintained during the period in which write-back blocking is effective. (19) "Output governance" refers to a hardware function in which an output control gate circuit determines whether or not the calculation result can be output externally, or what its content is, based on state indicators and policy information. This is done independently of output instructions by the program, by physically opening and closing a gate or by signal substitution. (20) "Arithmetic logic circuit" means a group of hardware circuits that perform digital operations, including an ALU (Arithmetic Logic Unit), an FPU (Floating Point Unit), a vector unit, a matrix unit, or a data path processing circuit that combines these. In hardware embodiments, the arithmetic units provided in existing processors can be used as is. (21) "Hardware-based suppression of writing calculation results from arithmetic logic circuits to value registers" means an operation in which a logic gate or equivalent circuit element placed on the physical data path through which the calculation results output by the arithmetic logic circuit reach the write port of the value register electrically blocks or disables signal transmission on the data path based on an abnormality detection signal, rather than control by the execution of software instructions (for example, conditional skipping of write instructions or conditional modification of the write address). (22) The "input side of the arithmetic logic circuit" refers to the data path located upstream of the input port for the arithmetic logic circuit to receive operands (data to be processed). Specifically, if the arithmetic logic circuit has a first operand input port and a second operand input port, the input stage of the operand selector (multiplexer) located upstream of at least one of these input ports corresponds to the "input side". In existing processors, the operand selector is generally provided as a circuit that selects one of several data sources, such as a register file read port, an immediate decoder, and a forwarding path, and supplies it to the operand input port of the arithmetic logic circuit. (23) "Hardware switching of input data" means that a multiplexer (selector) physically located upstream of the operand input port of an arithmetic logic circuit electrically switches at the gate level which of its multiple input terminals the signal from which passes to the output terminal, based on a signal decoded from a state indicator, rather than selection by the execution of a software instruction (for example, a process of selecting an input value by a conditional branch instruction or a process of selecting a value by a conditional move instruction). This switching is performed independently of the instruction decoding stage or instruction execution stage of the instruction pipeline and does not depend on the value of the program counter or the contents of the instruction register. (24) "Policy memory" means a hardware memory element that holds thresholds, condition tables, or decision rules that are matched with state indicators. It has an update path independent of the computation data path and can be configured to allow for dynamic changes to its contents. (25) "Threshold referenced by the state evaluation circuit" refers to a numerical criterion that the state evaluation circuit references to compare with the state index. Specifically, it is a numerical criterion that is compared with the cumulative depth value stored in the depth region of the state index, and the operating mode of the output control gate circuit (transmission, blockage, or switching to an alternative signal) is determined based on whether the depth value is equal to or greater than the threshold. In this embodiment, the threshold may include the following two types. (a) Warning Threshold: A reference value for when the depth value exceeds this threshold, which triggers the output control gate circuit 109 to initiate minor output constraints, such as limiting the output to the saturation value. (b) Critical Threshold: A reference value that, when the depth value exceeds this threshold, causes the output control gate circuit 109 to completely shut off the output or replace it with a default fail-safe value. The warning threshold is set to a value smaller than the danger threshold (e.g., warning threshold = 3, danger threshold = 5), enabling graceful degradation of output as depth increases. The threshold may include an attribute mask value used for matching against a specific bit pattern in the attribute domain, in addition to a comparison criterion for the depth domain. For example, a configuration may be adopted in which a pair of depth threshold and attribute mask value is used as the threshold to determine the combined conditions of "depth is 3 or greater" and "the attribute has a division by zero bit set". (26) The “decision table referenced by the state evaluation circuit” refers to a data structure that defines the correspondence between a range or pattern of state index values ​​and the operating modes of the output control gate circuit. The decision table is used to describe more complex decision conditions that cannot be expressed by thresholding (numerical comparison with one or more thresholds). The input (key) of the decision table is the depth value and / or attribute value of the state index, and the output (value) is the decision signal J (a signal encoding an output mode such as pass-through, blockage, saturation, or substitution) supplied to the output control gate circuit. The physical implementation form of the decision table is not limited and may include any of the following: (a) Lookup Table (LUT): A configuration in which the value of a state index is input as an address, and the corresponding decision signal is read from a memory element (SRAM, flip-flop array, etc.) that stores the decision signal. (b) Associative memory (CAM: Content Addressable Memory): A configuration that performs parallel comparisons between the value of a state index and the stored pattern, and outputs a judgment signal corresponding to the matched entry. (c) Condition register array: Multiple condition registers are configured to store the decision conditions (depth range, attribute mask, and corresponding output mode) in each of them, and the value of the state index is compared in parallel with the contents of each condition register. (27) The "or" in "threshold or decision table" is intended to encompass both configurations in which the policy memory holds a threshold and configurations in which it holds a decision table. The threshold method is suitable for simple configurations in which the decision is completed by only a few numerical comparisons and has the advantage of a small circuit size. The decision table method is suitable for complex decision conditions such as multi-stage decisions based on combinations of depth and attributes, or individual output mode selection according to specific attribute patterns.

[0046] <First Embodiment> <Overview of the arithmetic processing system> The overview of the arithmetic processing system in the first embodiment will be described with reference to Figure 1. Figure 1 is a block diagram showing the overall configuration of the arithmetic processing system in this embodiment. Figure 1 comprehensively shows the components that make up the arithmetic processing system 1, the signal paths between them, and the configuration that is not connected to the control flow change circuit. Hereinafter, the overall configuration of the arithmetic processing system 1 will be outlined with reference to Figure 1, and then the details of each component will be described sequentially.

[0047] As shown in Figure 1, the arithmetic processing system 1 has a configuration that adds the ESRCS module 10 to the arithmetic logic circuits 101 and value registers 102 of an existing processor. The ESRCS module 10 is shown as an area enclosed by a thick border in Figure 1 and comprises an abnormality detection circuit 103, a write-back control circuit 104, a state register 105, a state transition circuit 106 (including a depth update circuit 106a and an attribute update circuit 106b), and a recursive data path 107 (including a decoder 107a and a selector 107b).

[0048] The signal flow in Figure 1 is as follows: The calculation result of the arithmetic logic circuit 101 is supplied to the anomaly detection circuit 103. The anomaly detection circuit 103 outputs an anomaly detection signal EX, which is supplied to the write-back control circuit 104 and the state transition circuit 106. The anomaly detection signal EX is not connected to any of the PC update circuit, exception vector generation circuit, or interrupt control circuit (unconnected). The write-back control circuit 104 masks the write enable signal WE based on the anomaly detection signal EX and supplies the masked signal WE' to the value register 102. The state transition circuit 106 cumulatively updates the depth and attributes of the state register 105. The state index output from the state register 105 is fed back to the input side of the arithmetic logic circuit 101 via the decoder 107a and selector 107b of the recursive data path 107.

[0049] Figure 1 also shows an Output Governance section enclosed in a dashed frame. The Output Governance section is an optional configuration that includes a state evaluation circuit 108, a policy memory 110, and an output control gate circuit 109, and provides the function of switching the output from the value register 102 to the external bus to pass through, block, or switch to an alternative signal based on a state indicator.

[0050] With the above configuration, the arithmetic processing system 1 continues calculations without stopping the pipeline or changing the control flow, even when an unusual calculation state occurs. In other words, in this system, an exception, which is an unusual calculation state that occurs during the calculation process, is treated not as an "event to be processed" but as a "state to be maintained".

[0051] Here, Figure 2 is a block diagram showing the arrangement of the arithmetic processing system 1 within the CPU pipeline, in comparison with the configuration of a conventional CPU. The left side of Figure 2 shows the processing flow for exceptions, which are unique computational states that occur during the computation process in a conventional CPU (Execute → Exception detection → Trap occurrence → PC rewrite → Exception handler), and the right side shows the processing flow in the arithmetic processing system 1 according to this embodiment (Execute → Anomaly detection → ESRCS module 10 → WriteBack).

[0052] As shown on the left side of Figure 2, in a conventional CPU pipeline, if an unusual computation state (exception) occurs in the Execute stage, an exception detection signal is transmitted to the program counter (PC) update circuit and the exception vector generation circuit, a trap occurs, the PC is rewritten, and the control flow transitions to the exception handler. As a result, the pipeline stops or flushes, and the computation execution time becomes undefined.

[0053] In contrast, as shown on the right side of Figure 2, the arithmetic processing system 1 according to this embodiment places the ESRCS module 10 between the output of the Execute stage and the WriteBack stage, instead of the Trap processing path in the conventional structure. On the right side of Figure 2, the dashed line and termination symbol indicate that the signal path from the abnormality detection circuit 103 to the PC update circuit and interrupt controller is terminated (disconnected). The ESRCS module 10 is located at the boundary (WriteBack boundary) where the calculation result is written back to the register.

[0054] <Functional Configuration of the Arithmetic Processing System> The following describes in detail each component shown in Figure 1, while clearly indicating its relationship with existing CPU architectures. Figure 3 is a block diagram showing the internal structure of the ESRCS module 10 as a separated structure of a Value Path (left side of Figure 3) and a State Path (right side of Figure 3). In Figure 3, solid lines represent the basic components of this disclosure, and dashed lines represent optional components.

[0055] (Arithmetic logic circuit 101) The arithmetic logic circuit 101 is a hardware circuit that performs digital calculations on the data to be calculated, and it directly utilizes the ALU or FPU provided in the existing processor. The arithmetic logic circuit 101 may have a pipeline structure that advances multiple calculation stages in synchronization with the clock signal CLK. No changes are required to the internal structure of the arithmetic logic circuit 101, and the output bus and status flag output of the existing arithmetic unit are supplied to the ESRCS module 10.

[0056] (Value register 102) The value register 102 is a register to which the calculation result of the arithmetic logic circuit 101 is written back, and it directly uses a general-purpose register or floating-point register from the existing processor's register file. The value register 102 has a standard configuration in which it receives a write enable signal WE as input to the write port, and data is written only when WE is asserted. In this embodiment, only the method of controlling this WE signal differs from the conventional method, and no change is required to the physical structure of the register itself.

[0057] (Abnormality judgment circuit 103) The anomaly detection circuit 103 is a hardware circuit that detects the occurrence of an unusual calculation state based on the output of the arithmetic logic circuit 101 and outputs an anomaly detection signal EX. The anomaly detection circuit 103 monitors at least one of the following signal sources. (1) Signal patterns at predetermined bit positions on the arithmetic unit output bus (bit patterns indicating NaN, reserved bit patterns, etc.) (2) Calculation status flag lines (overflow flag, division by zero flag, underflow flag, etc.)

[0058] Existing processor ALU / FPUs typically include status flag generation circuits to detect calculation result overflows, division by zero, etc. (for example, the flag bit of the MXCSR register in the x86 architecture, the flag bit of the FPSCR in the ARM architecture, etc.). The anomaly detection circuit 103 can be configured as an OR gate or logic synthesis circuit that accepts these existing flag output signals as input. In other words, the basic detection function for anomaly detection utilizes existing processor circuits, and a new part is added that integrates their outputs and outputs them as a single anomaly detection signal EX.

[0059] In conventional processors, the output of the status flag is connected to the program counter update circuit or the exception vector generation circuit via the exception mask register. In contrast, in this embodiment, the output signal EX of the abnormality determination circuit 103 has no electrical connection to these control flow change circuits. That is, signal EX is used only as an input to the write-back control circuit 104 and the state transition circuit 106, and is not connected to the input terminals of the PC update circuit, the exception vector generation circuit, or the interrupt controller.

[0060] Here, the anomaly detection circuit 103 outputs an anomaly detection signal EX (1 bit) indicating the presence or absence of an unusual calculation state, as well as an anomaly type signal Type (M bits) indicating the type of source of the detected unusual calculation state. The anomaly type signal Type is a one-hot or multi-hot bit pattern in which only the bit position corresponding to the detected anomaly condition is set to high (=1), and the other bit positions are kept low (=0). The following is an example of a specific configuration in which the anomaly detection circuit 103 generates the Type signal. (1) A configuration in which each output line of the individual status flag outputs (division by zero flag, overflow flag, underflow flag, etc.) provided by the existing ALU / FPU is directly connected to the corresponding bit position of the Type signal. In this case, the existing flag outputs of the ALU / FPU are used as source type information. (2) A combinational logic circuit is provided to analyze the bit pattern of the output bus of the arithmetic logic circuit 101, and this logic circuit detects bit patterns of NaN (all 1s in the exponent and non-zero in the mantissa according to the IEEE 754 standard), infinity (all 1s in the exponent and zero in the mantissa), etc., and asserts the corresponding Type bit. (3) A configuration that combines (1) and (2) above, and further adds an operation type signal supplied from the instruction decoding circuit (a signal indicating whether the operation currently being executed is addition, division, floating-point operation, etc.) to the upper bits of the Type signal. In this case, both the source type and the operation type are output as a single Type signal. In all configurations, the Type signal is supplied to the attribute update circuit 106b of the state transition circuit 106 simultaneously with the anomaly detection signal EX, and is used for logical OR superposition on the attribute area.

[0061] (Rewrite control circuit 104) The write-back control circuit 104 is a circuit that physically blocks the writing of calculation results from the arithmetic logic circuit 101 to the value register 102 based on the anomaly detection signal EX. The write-back control circuit 104 takes a logical AND operation between the write enable signal WE input to the write port of the value register 102 and the inverted signal of the anomaly detection signal EX (logical negation of EX), and supplies the result to the value register 102 as a new write enable signal WE'.

[0062] In other words, the operation of the write-back control circuit 104 is as follows: WE' = WE AND (NOT EX) Under normal conditions (EX=0): WE'=WE, and writing proceeds as usual. In case of an abnormality (EX=1): WE' becomes 0, and writing is blocked. The value register 102 retains the previous valid value.

[0063] The write-back control circuit 104 can be constructed with a single AND gate (or an equivalent logic circuit), resulting in an extremely small circuit size. It is implemented in the WriteBack stage of an existing processor by inserting the AND gate into the WE signal path of the register file. Here, the write-back control circuit 104 does not stop the clock signal CLK of the arithmetic logic circuit 101 (it is not clock gating). The arithmetic logic circuit 101 and its pipeline continue to operate regardless of whether there is an abnormality, and only writing to the value register 102 is selectively blocked. As an alternative implementation of the write-back control circuit 104, instead of a write enable signal, a tristate buffer or analog switch can be placed on the data path between the output bus of the arithmetic logic circuit 101 and the write data port of the value register 102. When the abnormality detection signal EX is asserted, the buffer is transitioned to a high-impedance state, thereby blocking the physical transmission of the write data itself. This configuration is effective for register configurations where controlling the write enable signal is difficult (for example, latch-type registers that do not have a WE signal).

[0064] Here, the "hardware suppression" operation in this disclosure is structurally distinguished from software suppression by the following two properties. First, the decision and execution of suppression are performed independently of the instruction decoding stage or instruction execution stage of the instruction pipeline. That is, regardless of what instruction the processor's instruction decoding circuit is decoding, the AND gate immediately masks the write enable signal based on the assertion of the anomaly detection signal EX. Second, the execution of suppression does not consume clock cycles. Since the AND gate is a combinational logic circuit and not a flip-flop synchronized with the clock signal, the delay from the assertion of the anomaly detection signal EX to the deassertion of the write enable signal WE' is only the propagation delay of the logic gate.

[0065] (State register 105) The state register 105 is a physical memory element that stores state indicators, and is a newly added component in this embodiment. The state register 105 is independent of the value register 102 in the following respects. (1) Independent bit width: May have a different bit width from the bit width of value register 102 (e.g., 32 bits or 64 bits). (2) Independent identification space: A unique register address is assigned, selected by a decoding circuit separate from the address decoding circuit of the existing register file. (3) Independent update control: The update is controlled by an update signal independent of the write-back control (WE') of value register 102.

[0066] The state indicator stored in the state register 105 has the following structure. (1) Depth Field: An N-bit counter value that records the cumulative number of occurrences of a unique computational state. N is determined by the implementation, but for example, 8 bits (maximum cumulative 255 times) or 16 bits may be used. (2) Attribute Field: An M-bit bit field that indicates the type of unusual computation state that occurred. Each bit corresponds to a different type (division by zero, overflow, underflow, undefined operation, etc.).

[0067] Here, the specific bit configuration of the attribute information stored in the attribute area of ​​the state register 105 is illustrated below. One possible configuration is to assign the attribute area only to the source type. In this case, each of the M bits in the attribute area corresponds one-to-one with a different source type. For example, if M=8, a configuration can be adopted in which bit 0 is assigned to division by zero, bit 1 to overflow, bit 2 to underflow, bit 3 to undefined operation, bit 4 to reserved bit pattern detection, and the remaining bits 5 to 7 are reserved for future expansion. The anomaly detection circuit 103 outputs an anomaly type signal Type (for example, Type=0b00000001 when division by zero is detected, and Type=0b0000010 when overflow is detected) indicating the bit position corresponding to the type of unique calculation state detected. The attribute update circuit 106b superimposes this Type signal on the existing value in the attribute area using logical OR, so that bits of all anomaly types that have occurred in the past are cumulatively retained. For example, if division by zero occurs in cycle N and an overflow occurs in cycle N+3, the value in the attribute area transitions from 0b00000001 to 0b0000011, and the history of both division by zero and overflow occurrences is stored as a bit field.

[0068] A second configuration example involves assigning the attribute area to both the source type and the operation type. In this case, the M bits of the attribute area are divided into two subfields, with the lower subfield assigned to the source type and the upper subfield assigned to the operation type. For example, if M=8, bits 0-3 are assigned to the source type (division by zero, overflow, underflow, undefined operation), and bits 4-7 are assigned to the operation type (integer addition / subtraction, integer multiplication / division, floating-point addition / subtraction, floating-point multiplication / division). The anomaly detection circuit 103 outputs an anomaly type signal Type (for example, Type=0b1000_0001 when division by zero is detected during floating-point division) by combining the bit pattern indicating the source type and the bit pattern indicating the operation type. The attribute update circuit 106b superimposes this Type signal using logical OR, thereby accumulating information on "which type of anomaly occurred in which type of operation". This configuration is useful in anomaly cause analysis when a subsequent state evaluation circuit 108 or feedback control process determines whether anomalies are concentrated in a specific type of operation.

[0069] A third configuration example involves allocating the attribute area to both the source type and external sensor information. The state transition circuit 106 can receive signals from external sensors. In this case, a configuration can be adopted in which some bits of the attribute area are allocated to the source type detected within the arithmetic logic circuit, and other bits are allocated to abnormal information supplied from external sensors (temperature sensors, voltage sensors, radiation detectors, etc.). For example, by allocating the lower 4 bits of the attribute area to the source type originating from the arithmetic logic circuit and the upper 4 bits to the abnormality type originating from the external sensor (overtemperature, voltage anomaly, radiation detection, etc.), the occurrence history of both arithmetic and physical abnormalities can be managed uniformly within the same attribute area.

[0070] The state register 105 is implemented as a dedicated group of flip-flops located adjacent to the existing register file. It does not require any modification of the internal structure of the existing register file; it is implemented by adding an N+M bit group of flip-flops outside the register file and providing dedicated address decoding logic.

[0071] Here, in this disclosure, the statement that the state register 105 is "assigned to a unique register identification space selected by an independent address decoding circuit" means the following structure. In a typical processor register file, the selection of each register is performed by inputting a register number signal (e.g., a 4-bit or 5-bit binary value) output by the instruction decoding circuit to an address decoding circuit (demultiplexer), and the decoding circuit asserting the word line of the corresponding register. In this configuration, all general-purpose registers share the same address decoding circuit, and the register to be selected is uniquely determined by the value of the register specification field in the instruction. In this embodiment, the state register 105 is not included in the decoding targets of the above-mentioned general-purpose register address decoding circuit. That is, no value of the register number signal output by the instruction decoding circuit asserts the word line of the state register 105. The word line of the state register 105 is controlled by a dedicated decoding circuit (hereinafter referred to as the "state register decoding circuit") provided inside the ESRCS module 10. The state register decode circuit receives an update request signal from the state transition circuit 106 or a read request signal from the recursive data path 107 as input, and asserts the word line of the state register 105 based on these signals.

[0072] This configuration provides the following technical benefits. Firstly, normal register access commands from software (such as LOAD and STORE) for value registers (general-purpose register files) cannot access the state register 105. The contents of the state register 105 are updated and read only by the internal control signals of the ESRCS module 10, thus physically protecting them from unintended overwriting or tampering by software. Secondly, since the update control of the value register (mask control by the write enable signal WE') and the update control of the state register (cumulative update by the state transition circuit 106) are performed on physically independent signal paths, it is possible to perform value protection (write-back blocking) and state accumulation (depth and attribute updates) in parallel within the same cycle. Thirdly, the bit width of the state register 105 (N+M bits) is not constrained by the bit width of the value register (e.g., 32 bits or 64 bits). Since the state register 105 is a memory element physically independent of the general-purpose register file, it is possible to freely set a different bit width from the value register depending on the number of bits required for the depth and attribute areas of the state index.

[0073] The following configurations are examples of implementation forms for the "independent address decoding circuit" described above. The first configuration involves providing a dedicated demultiplexer circuit inside the ESRCS module 10 to decode the write request signal from the state transition circuit 106 and drive the word line of the state register 105. In this case, the input to the demultiplexer is an internal signal of the state transition circuit 106 and is unrelated to the register specification field of the instruction decoding circuit. The second configuration involves assigning the state register 105 to a specific address in the memory-mapped I / O space and detecting access to that address with a dedicated address decoding circuit. In this case, the address decoding circuit is implemented as a comparison circuit that detects a specific bit pattern on the address line of the system bus and is provided as a circuit that is physically independent of the address decoding circuit of the general-purpose register file. The third configuration involves assigning the state register 105 to a privileged identification space similar to the system register space of existing processors (for example, the MSR space of x86, the system register space of ARM). In either configuration, the decoding circuit used for selecting the state register 105 does not share input signal lines with the decoding circuit used for selecting the general-purpose register file, and the two operate independently. Furthermore, a configuration in which the state register selection control and update control are performed internally via a signal path independent of that of the general-purpose register, although it appears from the outside to belong to the same address space as the general-purpose register in the system bus address space, may also be included as one aspect of the "independent address decoding circuit" in this disclosure.

[0074] (State transition circuit 106) The state transition circuit 106 is a logic circuit that updates the state index stored in the state register 105 based on the abnormality detection signal EX, and has a structure that includes two sub-circuits: the depth update circuit 106a and the attribute update circuit 106b. (1) Depth update circuit 106a: This is a hardware counter (adder) that increments the value in the depth region of the state register 105 by 1 when the abnormality detection signal EX is asserted. When normal (EX=0), the added value is 0 and the depth does not change. Depth(new) = Depth(old) + EX (2) Attribute update circuit 106b: When the abnormality detection signal EX is asserted, this circuit superimposes the abnormality type signal Type onto the existing value in the attribute area of ​​the state register 105 by a logical OR operation. Under normal conditions, the Type signal is masked and the attribute does not change. Attr(new)=Attr(old) OR (Type AND EX)

[0075] The state transition circuit 106 can be constructed with one adder, a group of AND gates, and a group of OR gates, resulting in a small circuit size. The update performed by the state transition circuit 106 is non-destructive, the depth increases monotonically, and attribute bits are retained cumulatively once set.

[0076] (Recursive data path 107) The recursive data path 107 is a wiring structure that feeds back the state index output from the state register 105 to the input side of the arithmetic logic circuit 101. The recursive data path 107 includes the following components. (1) Decoder 107a: A combinational logic circuit that decodes the values ​​in the depth region and / or attribute region of the state register 105 and generates a selector control signal S. (2) Selector 107b: A multiplexer that physically switches an operand between a normal operand and an alternative value based on the selector control signal S.

[0077] Under normal conditions (depth below the threshold), S=0 and the normal operand is supplied. If the depth exceeds the threshold, S=1 and an alternative value is supplied. This switching is performed automatically at the hardware level without changing the program counter. It is implemented by adding one input port to the operand selector of the existing processor and connecting the signal line from state register 105.

[0078] Here, in the feedback paths shown in Figures 1 and 3, "the input side of the arithmetic logic circuit 101" refers to the input stage of the operand selector (multiplexer) located immediately before the operand input port of the arithmetic logic circuit 101. The selector 107b of the recursive data path 107 is implemented as an additional input port to this operand selector, and based on the selector control signal S output by the decoder 107a, it selects either a normal operand (a value read from the register file) or an alternative value (a bitmask value, a saturation value, or an alternative constant) and supplies it to the operand input port of the arithmetic logic circuit 101. This connection allows switching of input data based on state indicators to be performed before the arithmetic logic circuit 101 starts calculations, without going through the instruction decoding circuit.

[0079] Furthermore, the operand switching by the recursive data path 107 is structurally distinct from the selection of input values ​​by software in the following respects: Firstly, the decision-making body for switching is a hardware circuit (decoder 107a) and does not involve the execution of a software instruction. Decoder 107a is a combinational logic circuit that directly receives the output of the state register 105 and does not have a control signal from the instruction decoding circuit as input. Secondly, the execution body for switching is a hardware circuit (selector 107b) and does not depend on the value of the program counter. Selector 107b is a multiplexer circuit that electrically connects either the normal operand input terminal or the alternative value input terminal to its output terminal according to the level (high or low) of the selector control signal S output by decoder 107a, and operates independently of the instruction execution state. Thirdly, the timing of the switching is synchronized with the update of the state index and does not depend on the execution timing of a particular instruction.

[0080] (Control flow disconnected configuration) Figure 4 is a block diagram showing the signal path of the output signal EX of the abnormality detection circuit 103 in comparison with the configuration of a conventional CPU. As shown on the left side of Figure 4, in a conventional CPU, the exception detection signal is sequentially transmitted to the PC update circuit, the exception vector generation circuit, and the interrupt controller, causing a change in the control flow. In contrast, as shown on the right side of Figure 4, in this embodiment, the abnormality detection signal EX is supplied only as an input to the write-back control circuit 104 and the state transition circuit 106, and has no electrical connection to the PC update circuit, the exception vector generation circuit, and the interrupt controller. With this structure, the abnormality detection signal EX is terminated within the data path and does not propagate to the control flow change system at all.

[0081] As shown in Figure 4, the destination of the signal EX is limited to the write-back control circuit 104 and the state transition circuit 106, and there are no physical signal paths to any other circuits. This configuration directly corresponds to the configuration requirement in this disclosure that "the abnormality detection signal is supplied only as an input to the write-back control circuit and the state transition circuit."

[0082] In conventional processors, the detection signal for arithmetic exceptions is connected to the PC update circuit, the exception vector generation circuit, and the interrupt controller via the exception mask register and exception priority logic. In this embodiment, the system does not physically have this signal path. With this configuration, even if an unusual calculation state occurs, the program counter is not changed, the pipeline is not stopped or flushed, and no interrupt is generated. The arithmetic logic circuit 101 continues to execute instructions at the same number of clock cycles regardless of whether an abnormality is present or not.

[0083] Here, the "PC update circuit (circuit that controls the update of the program counter)", "exception vector generation circuit (exception transition circuit)", and "interrupt controller (circuit that controls interrupt requests)" are circuits that are standard in a typical processor architecture, and these circuits may also exist within the processor in this embodiment. The feature of this embodiment is not that these circuits do not exist, but that the output signal EX of the abnormality detection circuit 103 does not have an electrical connection (physical wiring of signal lines) to the input terminals of these circuits. In other words, while the function of the processor to change the control flow for normal branch instructions and external interrupts is maintained, only control flow changes caused by arithmetic exceptions are structurally eliminated by the absence of a signal path. As shown in Figure 4, the destination of the abnormality detection signal EX is limited to the write-back control circuit 104 and the state transition circuit 106, and there are no physical signal paths to the PC update circuit, exception transition circuit, and interrupt controller. In this embodiment, the abnormality detection signal EX is not connected to the input terminals of internal control systems such as microcode control logic, instruction scheduler, or pipeline control unit. This structurally eliminates the possibility of anomaly detection signals influencing the control flow through indirect paths such as microcode branching.

[0084] (State evaluation circuit 108 and output control gate circuit 109) The arithmetic processing system 1 may optionally include a state evaluation circuit 108 and an output control gate circuit 109. These constitute an output governance mechanism.

[0085] The state evaluation circuit 108 compares the state index read from the state register 105 with the decision condition held in the policy memory 110 and outputs a decision signal J. Based on the decision signal J, the output control gate circuit 109 switches the output of the value held in the value register 102 to the external bus to one of the following: (1) Transparency: The value of value register 102 is output directly to the external bus. (2) Blocking: Disables output to the external bus. (3) Substitute signal: outputs a saturation value, a mask value, or a fail-safe default value.

[0086] Hereinafter, a specific example of a configuration in which the state evaluation circuit 108 refers to a threshold stored in the policy memory 110 is shown below. As a first configuration example (single-stage threshold comparison), there can be mentioned a configuration in which the policy memory 110 holds a single danger threshold Th (e.g., Th=5), and the state evaluation circuit 108 compares the depth value Depth of the state indicator with the threshold Th by means of a digital comparator. When Depth<Th, a determination signal J="pass" is output, and the output control gate circuit 109 outputs the value of the value register 102 to an external bus as it is. When Depth≧Th, a determination signal J="block" is output, and the output control gate circuit 109 outputs the fail-safe default value to the external bus. As a second configuration example (multi-stage threshold comparison), there can be mentioned a configuration in which the policy memory 110 holds two thresholds, which are a warning threshold Th_w (e.g., Th_w=3) and a danger threshold Th_c (e.g., Th_c=5), and the state evaluation circuit 108 compares the depth value with each of the thresholds respectively by means of two digital comparators. Three-stage determination is performed: when Depth<Th_w, the result is "pass"; when Th_w≦Depth<Th_c, the result is "saturation" (the output is limited to the saturation value); and when Depth≧Th_c, the result is "block". This configuration achieves graceful degradation when combined with the configuration "selecting any one of mask processing, fixing processing to a predetermined saturation value, or replacement processing to a default value by means of a hardware multiplexer" described in claim 14. As a third configuration example (composite threshold comparison of depth and attribute), there can be mentioned a configuration in which the policy memory 110 holds a set (Th_d, Mask_a) of a depth threshold and an attribute mask, and the state evaluation circuit 108 determines the composite condition of "Depth≧Th_d" and "(Attr AND Mask_a)≠0". This configuration achieves output control that takes into account the type of abnormality, such as blocking the output only when "the depth is 3 or more and division by zero has occurred", for example.

[0087] Furthermore, a specific example of a configuration in which the state evaluation circuit 108 refers to a decision table stored in the policy memory 110 is shown below. One possible configuration is to configure the policy memory 110 as an SRAM that references an address that combines the depth value and attribute value of the state indicator (for example, an address of 8 bits for depth + 8 bits for attribute = a total of 16 bits). Each address in the SRAM stores the value of the judgment signal J corresponding to the depth-attribute combination (for example, a 2-bit output mode code: 00 = transparent, 01 = saturated, 10 = alternative, 11 = blocked). The state evaluation circuit 108 is implemented with a simple configuration that only connects the output of the state register 105 to the address input of the SRAM, and does not require a digital comparator. This configuration offers high flexibility because it is possible to define individual output modes for any combination of depth and attribute. For example, differentiated output control according to the type of source can be realized, such as "saturated output if the depth is 2 or more and the overflow bit is set" or "immediate blocked if the depth is 1 or more and the division by zero bit is set". A second configuration example (condition register array method) involves configuring the policy memory 110 as a condition register array having multiple entries (for example, 4 entries or 8 entries). Each entry includes depth comparison conditions (lower and upper limits), attribute mask conditions (mask pattern and expected value), and a corresponding output mode code. The state evaluation circuit 108 compares the output of the state register 105 with the conditions of each entry in parallel and outputs the output mode code of the entry with the highest priority among the entries whose conditions match as a decision signal J. This configuration requires less memory capacity (only the number of entries × entry width) compared to the LUT method and is efficient even when the bit width of the depth is large.

[0088] The specific mechanism for "hardware-based dynamic switching" of thresholds or decision tables stored in policy memory 110 is shown below. One mechanism (rewriting table contents) involves rewriting the contents of the policy memory 110 via an update path (such as a memory-mapped I / O bus or debug interface) in response to changes in external context signals (signals indicating safety requirement levels or task priority). For example, in an automated driving system, if the safety requirement level changes from "normal driving" to "emergency braking," an external safety management unit rewrites the warning threshold in the policy memory 110 from 3 to 1 and the danger threshold from 5 to 2, thereby dynamically applying stricter output control. Since this rewriting is performed via an update path independent of the data path of the arithmetic logic circuit 101 (configuration requirement of claim 11), the policy change is completed without stopping the arithmetic processing. A second mechanism (selection of the reference table) involves pre-storing multiple threshold sets or decision tables (for example, two tables, a "high-safety mode table" and a "normal mode table") within the policy memory 110, and instantly selecting the reference table in hardware by switching the upper bits of the address or a bank selection signal in response to an external context signal. In this configuration, the time required to rewrite the table contents is unnecessary, and the delay from the change in the context signal to the start of application of the new policy is minimized. For example, if the context signal indicates a 2-bit safety requirement level (00=normal, 01=caution, 10=warning, 11=emergency), the four tables can be switched in one clock cycle by using these 2 bits as the upper 2 bits of the address in the policy memory 110. A third mechanism (threshold selection by a multiplexer) involves providing multiple threshold registers (for example, a group of threshold registers for high-safety mode and a group of threshold registers for normal mode) within the policy memory 110, and using a multiplexer that takes an external context signal as a control input to select the threshold to be supplied to the comparator of the state evaluation circuit 108. This configuration is the simplest implementation of adding a dynamic switching function to the threshold method, and since it can be implemented with only a multiplexer and multiple threshold registers, the circuit size is small.

[0089] The following are examples of specific application scenarios for the dynamic switching described above, related to their industrial applicability. One example of its application is the dynamic modification of safety requirement levels in autonomous driving and advanced driver-assistance systems (AD / ADAS). While the vehicle is driving normally, relatively lenient thresholds (e.g., warning threshold = 5, danger threshold = 10) are applied, but during the execution of safety-related tasks such as emergency braking or obstacle avoidance, the thresholds are dynamically switched to stricter ones (e.g., warning threshold = 1, danger threshold = 3) in response to contextual signals from an external safety management ECU. A second application example is switching based on task priority in a multitasking environment. Among the multiple tasks managed by the real-time OS, a strict threshold set is used during the execution of safety-related tasks (tasks with a high ASIL level), and a more tolerant threshold set is used during the execution of non-safety-related tasks (background processing, etc.). This switching is achieved by connecting the task priority signal output by the OS task scheduler to the bank selection signal of policy memory 110. A third application example is the control of the trade-off between inference accuracy and speed in AI inference accelerators. In situations where high-precision inference is required (e.g., medical image diagnosis), strict thresholds are used to block outliers early, while in situations where high-speed inference is prioritized (e.g., real-time object detection), more tolerant thresholds are used to maintain inference throughput, enabling dynamic switching according to the application.

[0090] Furthermore, the output data path from the value register 102 to the external bus has a physical configuration in which it is connected only via the output control gate circuit 109. The policy memory 110 is configured to be writable via an update path independent of the data path of the arithmetic logic circuit 101.

[0091] <Processing flow of the arithmetic processing system> The following describes the processing flow in the arithmetic processing system 1 when a unique calculation state occurs, along the time axis, with reference to the timing chart in Figure 5. Figure 5 shows the timing relationships of the pipeline clock (CLK), calculation result, anomaly detection signal EX, post-mask write enable signal WE', value register update, state register update (State update), and feedback signal S over cycles N-2 to N+5. Cycle N is the cycle in which the unique calculation state occurred.

[0092] (Phase 0: System initialization and normal operation) At system startup (such as during a system reset), the state register 105 is initialized to its default initial value (depth = 0, attribute = all bits 0). As shown in cycles N-2 and N-1 of Figure 5, in normal calculation cycles where no unusual calculation state is detected, the anomaly detection signal EX remains low (= 0), WE' = WE, and the calculation result of the arithmetic logic circuit 101 is written back to the value register 102 as usual. The state register 105 is not updated (State update = low), and since the feedback signal S = 0, the recursive data path 107 selects the normal operand. The output control gate circuit 109 (optional configuration) transmits the contents of the value register 102 to the external bus based on the determination conditions of the policy memory 110.

[0093] (Phase 1: Anomaly detection and immediate protection of values, Cycle N) In cycle N of Figure 5, the anomaly detection circuit 103 detects an unusual calculation state, such as division by zero, based on the output of the arithmetic logic circuit 101 or an internal status signal. The anomaly detection circuit 103 asserts the anomaly detection signal EX to high (=1) within the same cycle.

[0094] The assertion of the anomaly detection signal EX immediately activates the write-back control circuit 104. As shown in Figure 5, WE' transitions to low (=0) in cycle N, and writing to the value register 102 is physically blocked. As a result, the value register 102 retains the immediately preceding valid value determined in cycle N-1. Here, as shown by the CLK signal in Figure 5, the pipeline clock continues without stopping in cycle N, and the arithmetic logic circuit 101 proceeds with processing the next instruction without interruption.

[0095] Furthermore, as shown in Figures 1 and 4, the anomaly detection signal EX is not transmitted to the PC update circuit, the exception vector generation circuit, or the interrupt controller. As a result, the program counter continues to point to the address of the next instruction, and the pipeline proceeds without stopping (flashing) even once.

[0096] Specific application examples include its use in control chips for autonomous driving and advanced driver-assistance systems (AD / ADAS). In autonomous driving systems, calculations on sensor data such as LiDAR and cameras can result in division by zero or overflow due to abnormal values ​​of reflected light or noise. With conventional exception trapping methods, the pipeline stops each time such an unusual condition occurs, causing the execution time of the control loop to fluctuate, thus impairing the temporal determinism of vehicle control. According to this embodiment, even if an abnormal value occurs in the sensor data, the pipeline does not stop, and the most recent valid sensor value is retained, allowing the calculation to continue. As a result, the execution time of the control loop is kept constant, ensuring the safety of vehicle control.

[0097] (Phase 2: Non-destructive accumulation of state, cycle N) In parallel with value protection (Phase 1), within the same cycle N, the state transition circuit 106 updates the state index of the state register 105. As shown in the State update signal in Figure 5, writing to the state register is performed in cycle N. The depth update circuit 106a increments the value in the depth domain by 1 (Depth=0→1), and the attribute update circuit 106b superimposes the type of singular state that occurred (for example, a bit indicating division by zero) onto the attribute domain using logical OR.

[0098] If multiple singular states occur in the same or consecutive cycles, the state transition circuit 106 cumulatively retains this information through logical combination (superposition) to prevent the loss of past occurrence history. For example, if division by zero occurs in cycle N and an overflow occurs in the following cycle N+1, the depth is incremented to 2, and the attribute area is cumulatively retained with both the division by zero bit and the overflow bit set.

[0099] A specific application example is its use in AI inference accelerators. In the inference operations of deep learning models, overflows caused by quantization errors and saturation of activation functions can occur frequently. In conventional methods, the pipeline is flushed each time an overflow occurs, significantly reducing inference throughput. According to this embodiment, the number of overflow occurrences is accumulated as the depth of the state index, making it possible to quantitatively evaluate the reliability of the inference results based on the depth while continuing inference operations without stopping the pipeline.

[0100] (Phase 3: Recursive feedback of the state and computational transformation, from cycle N+1 onwards) As shown by the feedback signal S in Figure 5, from cycle N+1 onward, the updated state index is fed back to the input side of the arithmetic logic circuit 101 via the recursive data path 107. The decoder 107a decodes the depth and attributes of the state index and asserts the selector control signal S to high (=1). As a result, the selector 107b automatically switches the input operand from a normal value to an alternative value (zero, a predetermined mask value, a saturated value, etc.).

[0101] This switching is performed autonomously by the hardware without any software instruction intervention (execution of a conditional branch instruction). The program counter remains unchanged, and the arithmetic logic circuit 101 continues the calculation based on the substituted operand without interrupting the processing of the next instruction. As shown in Figure 5, even after cycle N+1 when the feedback signal S goes high, CLK, the calculation result, and WE' continue to operate at their normal timings.

[0102] A specific application example is its use in high-security cryptographic processing equipment. In cryptographic processing, fluctuations in execution time can become a side channel for leaking secret key information. Conventional exception handling methods change the control flow depending on whether or not an error occurs in the calculation, resulting in differences in execution time and creating a vulnerability to timing attacks. According to this embodiment, even when a singular state occurs, input switching by the feedback signal S is performed at the hardware level, and the execution path and the number of execution cycles do not depend on whether or not an error occurs, thus achieving structural protection against timing attacks.

[0103] (Phase 4: Output control by physical gates, at output stage) At the stage when the calculation result is output to the external bus, the state evaluation circuit 108 (optional configuration) compares the reference value in the policy memory 110 with the state index and performs the final output governance determination. This determination is performed by a hardware comparison circuit completely independent of the instruction decoding system.

[0104] If the judgment result satisfies predetermined danger conditions (for example, if the depth is greater than or equal to the danger threshold, or if a specific abnormality type bit is set in the attribute), the output control gate circuit 109 is activated, and the output to the external bus is either physically blocked or replaced with a default fail-safe value (saturation value, mask value, etc.) and output.

[0105] Specific application examples include aerospace control and high-reliability robot control. In aerospace environments, abnormal values ​​may occur in calculation results due to soft errors (SEU: Single Event Upset) caused by cosmic rays. In conventional methods, when a soft error occurs, the pipeline stops, disrupting the execution timing of the control loop and reducing the accuracy of attitude control. According to this embodiment, anomalous states caused by soft errors accumulate, and when the depth exceeds a threshold, the output control gate circuit 109 automatically outputs a fail-safe value, thereby realizing hardware-driven safe operation without stopping the pipeline.

[0106] (Continuous operation scenario) The processing described in Phases 1 through 4 is executed sequentially in each cycle of the pipeline. As shown in Figure 5, handling of singular states that occur in cycle N (value protection, state update) is completed within cycle N, and input switching based on the feedback signal S is performed automatically from cycle N+1 onwards. If the singular state does not occur again after cycle N, EX remains low (=0), WE' returns to WE, and writing to value register 102 resumes. Meanwhile, the feedback signal S remains high as long as the depth of the state index is above the threshold, and calculations based on the alternative operand continue.

[0107] Furthermore, if singular states occur consecutively (for example, if different types of singular states occur in cycles N, N+3, and N+5), the depth increases monotonically from 1 to 2 to 3, and bits for each type of anomaly are cumulatively superimposed in the attribute area. The state evaluation circuit 108 performs stepwise output control based on this accumulated depth and attributes. For example, if the depth reaches a warning threshold (e.g., 3), the output is limited to a saturation value, and if it reaches a danger threshold (e.g., 5), the output is completely shut off and replaced with a fail-safe value, thus achieving graceful degradation.

[0108] Specific application examples include power control and motor control in industrial equipment. In power conversion calculations such as inverter control, calculation errors caused by power supply noise and switching surges can occur sporadically. According to this embodiment, the number of sporadic errors is accumulated and managed as a depth, so that calculations continue in the case of transient noise (when the depth is low), and when errors occur repeatedly (when the depth exceeds a threshold), the system gradually transitions to fail-safe operation, thereby realizing adaptive control according to the severity of the error. Since the control loop continues without stopping even once, dangerous situations such as sudden motor stops are avoided.

[0109] Similarly, applications to medical device control are also noteworthy. In life support systems and precision diagnostic equipment, instantaneous shutdown of the control processor is unacceptable. According to this embodiment, even if a calculation error occurs, the control flow is not changed and calculations continue, thus reducing the risk of interruption to life support functions.

[0110] <Notes regarding implementation flexibility> The processing flow described above is merely one example for realizing this disclosure. The type of arithmetic logic circuit, the physical bit width of each register, the address space allocation, the specific gate configuration of the control logic, the transmission timing (number of clock cycles) of each signal, and the threshold settings of the policy memory can be appropriately modified or optimized according to specific design requirements and the hardware environment to be implemented. Furthermore, configurations that integrate some of the functions of each circuit into a single module or distribute them across multiple submodules are also within the scope of the technical concept of this disclosure.

[0111] <Use in semiconductor products and IP form> Due to its structural independence, the arithmetic processing system 1 according to this embodiment can be provided and distributed in the following diverse forms: Firstly, it can be incorporated into semiconductor products as a standalone microprocessor, SoC, or accelerator module. Secondly, it can be provided as a "plug-in" circuit module that can be added to the microarchitecture layer without changing the existing instruction set architecture (ISA), such as an FPGA IP core or an RTL library for ASIC design. Thirdly, it can also be provided as a specific function die using chiplet technology.

[0112] According to the arithmetic processing system 1 described above, it is possible to provide a technology that can maintain the continuity and safety of calculations even when an unusual calculation state occurs during the calculation process.

[0113] <Second Embodiment> The arithmetic processing system 2 according to the second embodiment comprises an existing processor 201 and memory 202. No changes are made to the hardware configuration, and all functions are implemented as programs executed by the processor 201.

[0114] The second embodiment implements the functions corresponding to each component of the first embodiment as software processing, as follows. (a) Anomaly detection circuit 103 → Anomaly detection process (b) Write-back control circuit 104 → Write-back control process (c) State register 105 + state transition circuit 106 → state update process (d) Recursive data path 107 → Feedback control processing (e) Control flow disconnected → Branchless instruction sequence configuration

[0115] <Term definition> In the following embodiments, terms common to the first embodiment follow the definitions of the first embodiment. In addition, the following terms have meanings specific to this embodiment. (1) A "branchless instruction sequence" is an instruction sequence that does not include any conditional branch instructions and consists only of arithmetic operation instructions, logical operation instructions, and conditional selection instructions. In the execution of a branchless instruction sequence, the program counter is always incremented sequentially and no conditional jumps occur. (2) "Conditional selection operation" refers to an operation that selects one of two values ​​based on a condition value without using a conditional branch instruction. (a) Conditional move instructions (e.g., x86 CMOV instruction, ARM CSEL instruction) (b) Predicate execution instructions (e.g., ARM predicate instructions) (c) SIMD selection instructions (e.g., SSE / AVX BLEND instruction, NEON BSL instruction) (3) The “value retention area” refers to a memory area that holds the most recent valid value allocated in memory. It functionally corresponds to the value register 102 in the first embodiment. (4) The "state retention area" refers to a memory area that stores state indicators allocated in memory. It functionally corresponds to the state register 105 in the first embodiment. (5) The "state data structure" is a fixed-length bit field structure placed in the state holding area, and includes a depth field and an attribute field. It has a structure equivalent to the state index of the state register 105 in the first embodiment. (6) “Anomaly judgment value” refers to a value that expresses the result of an anomaly judgment on the calculation result as 0 or 1. It functionally corresponds to the anomaly detection signal EX in the first embodiment.

[0116] <Overview and Functional Configuration of the Computational Processing System> Figure 6 is a configuration diagram showing the overall configuration of the arithmetic processing system 2 according to the second embodiment. As shown in Figure 6, the arithmetic processing system 2 comprises an existing processor (CPU) 201 and memory 202 connected to the processor 201. The processor 201 is equipped with an existing ALU / FPU, and no changes are made to the hardware configuration itself. All functions of this embodiment are implemented as branchless instruction sequences executed by the processor 201.

[0117] As shown in Figure 6, the following three data areas are allocated on memory 202. Firstly, the value holding area V is an area that holds the immediately preceding valid value of the calculation target and functionally corresponds to the value register 102 of the first embodiment. Secondly, the state holding area S is a fixed-length bit field structure that includes the depth field S.depth and the attribute field S.attr and functionally corresponds to the state register 105 of the first embodiment. Thirdly, the policy area P (optional configuration shown by the dashed line) is an area that stores thresholds and judgment conditions for output control and functionally corresponds to the policy memory 110 of the first embodiment.

[0118] In the second embodiment, the value register 102 of the first embodiment is implemented as a value holding area V (variable) in memory, the state register 105 of the first embodiment is implemented as a state holding area S (structure) in memory, and the control flow disconnected configuration of the first embodiment is implemented as a branchless instruction sequence (an instruction sequence that does not include conditional branch instructions).

[0119] <Processing flow of the arithmetic processing system> Figure 7 is a flowchart showing the processing flow in the second embodiment. As shown in Figure 7, after the calculation is performed, the arithmetic processing system 2 sequentially executes the following steps: error detection processing, write-back control processing, state update processing, feedback control processing, and output control processing (optional), and then loops to the next calculation after the output. Here, in each step in Figure 7, all steps consist only of arithmetic operations, logical operations, and conditional selection operations, and do not include any conditional branching instructions (if statements, jump instructions, try-catch, etc.).

[0120] The processing flow in the arithmetic processing system 2 according to the second embodiment will be described below with reference to Figure 7, while clearly indicating its correspondence with the first embodiment.

[0121] (Step 1: Anomaly detection process) As shown in Figure 7, the processor 201 first performs an abnormality determination process on the calculation result after the calculation is performed. This process corresponds to the abnormality determination circuit 103 of the first embodiment. In the abnormality determination process, an abnormality determination value ex (0 or 1) is calculated by arithmetic or logical operations as follows, without using conditional branch instructions.

[0122] Specifically, since NaN is the only value that is not equal to itself in the IEEE 754 standard, NaN can be detected as a comparison instruction without conditional branching using ex_nan=(result != result). Similarly, overflow and division by zero checks are performed using bitwise operations, and the results of these checks are combined using logical OR to calculate an integrated abnormality detection value ex=ex_nan|ex_ovf|ex_divz. Throughout this entire process, no conditional changes to the program counter occur.

[0123] Furthermore, depending on the processor architecture, some have a configuration that forcibly generates an exception trap when certain operations such as division by zero are performed. When applying this embodiment to such a processor, one of the following configurations can be adopted. First, a configuration in which the operand (e.g., divisor) is pre-evaluated by an arithmetic or logical operation to determine whether it meets an abnormal condition before the operation is performed, and if it does, the operation itself is replaced with an alternative operation (e.g., a safe division with the divisor replaced by 1). This pre-evaluation and selection of the alternative operation are achieved by a conditional selection operation (CMOV / CSEL, etc.) without using a conditional branch instruction. Second, a configuration in which the exception mask function provided by the processor (e.g., the exception mask bit in the MXCSR register of x86, or the trap enable bit in the FPCR of ARM) is used to suppress the generation of traps for specific operation exceptions, and a default value compliant with the IEEE 754 standard (NaN, ±Inf, etc.) is output as the operation result, and then an abnormality determination process is performed on the output value afterward. In either configuration, the entire process of abnormality detection, write-back control, state update, and feedback control is maintained as an instruction sequence that does not include conditional branch instructions.

[0124] (Step 2: Write-back control process) Next, based on the abnormality determination value ex, the processor 201 executes a write-back control process. This process corresponds to the write-back control circuit 104 of the first embodiment. In the write-back control process, either the calculation result or the immediately preceding valid value held in the value holding area V is selected without using a conditional branch instruction.

[0125] The arithmetic expression V = result × (1 - ex) + V × ex shown in Figure 7 is an example of selection by arithmetic operation. Under normal conditions (ex = 0), V = result and the calculation result is written back; under abnormal conditions (ex = 1), V is not changed and the previous valid value is retained. This operation is functionally equivalent to the operation in the first embodiment where writing to value register 102 is masked by WE' = WE AND (NOT EX). Alternatively, this can also be achieved by conditional move instructions (CMOV / CSEL) or bit mask operations (selection using mask = -ex). In either method, no conditional branch instructions are used.

[0126] (Step 3: State update process) Next, based on the abnormality determination value ex, the processor 201 executes a state update process. This process corresponds to the state transition circuit 106 (depth update circuit 106a and attribute update circuit 106b) of the first embodiment.

[0127] Depth updates are performed using the calculation formula S.depth=S.depth+ex shown in Figure 7. Under normal conditions (ex=0), the added value is 0 and the depth does not change, while under abnormal conditions (ex=1), the depth increases by 1. Attribute updates are performed using S.attr=S.attr|(type_bits&(-ex)). -ex is a bit mask where all bits are 1 (mask transparent) when ex=1 and all bits are 0 (mask blocked) when ex=0, and the abnormality type bit is superimposed on the attribute area by logical OR only under abnormal conditions. These operations are identical to the addition operation of the depth update circuit 106a and the logical OR operation of the attribute update circuit 106b in the first embodiment, respectively.

[0128] (Step 4: Feedback control process) Next, based on the state index stored in the state holding area S, the processor 201 performs feedback control processing. This processing corresponds to the recursive data path 107 (decoder 107a and selector 107b) of the first embodiment.

[0129] As shown in Figure 7, the comparison result between depth and threshold is calculated as either 0 or 1 using sel=(S.depth>=threshold), and the input data for subsequent calculations is switched using input=normal×(1-sel)+alt×sel. When the depth is less than the threshold (sel=0), the normal operand is used, and when it is greater than or equal to the threshold (sel=1), the alternative value is used. This entire process consists only of arithmetic operations without conditional branching instructions, and no conditional changes to the program counter occur.

[0130] (Step 5: Output control processing) Next, the processor 201 compares the state indicator with the determination conditions stored in the policy area P and executes output control processing. This processing corresponds to the state evaluation circuit 108 and output control gate circuit 109 of the first embodiment.

[0131] In the calculation formula shown in Figure 7, block=(S.depth>=P.critical_th) represents the success or failure of the cutoff condition, and sat=(S.depth>=P.warn_th)&(!block) represents the success or failure of the saturation condition, both expressed as 0 or 1. The output value out=V×(1-block)×(1-sat)+sat_val×sat+safe_val×block outputs a fail-safe value if the depth is above the critical threshold, a saturation value if it is above the warning threshold, and a normal value otherwise. This graceful degradation is functionally equivalent to the switching of transmission, cutoff, and substitution by the output control gate circuit 109 in the first embodiment, and the entire process is realized using only arithmetic operations that do not include conditional branch instructions.

[0132] (Invariance of loops and instruction execution paths) As shown in Figure 7, after the output, the process returns to execution of the next operation via a "to the next operation" loop, and steps 1 through 5 above are repeatedly executed. In this way, this processing flow consists entirely of arithmetic operations, logical operations, and conditional selection operations, and does not include any conditional branching instructions (if statements, jump instructions, try-catch constructs, etc.).

[0133] With this configuration, the instruction sequence executed by processor 201 is always the same, regardless of whether the abnormality judgment value ex is 0 (normal) or 1 (abnormal). That is, the comparison operation in step 1, the conditional selection operation in step 2, the addition / logical OR operation in step 3, the comparison / selection operation in step 4, and the selection operation in step 5 are all executed regardless of whether the operation result is normal or abnormal. The program counter is always incremented sequentially, and no conditional jumps occur.

[0134] This property is the software-level equivalent of the "control flow disconnected" configuration in the first embodiment. In the first embodiment, the invariance of the control flow is guaranteed because the anomaly detection signal EX is not electrically connected to the PC update circuit. In the second embodiment, the invariance of an equivalent instruction execution path is guaranteed because the anomaly determination value ex is not used as an operand in a conditional branch instruction. In either embodiment, since the occurrence or absence of a unique calculation state is not reflected in the execution path and execution time, deterministic execution time is guaranteed and side-channel tolerance is ensured.

[0135] (Specific operation scenario: Consecutive occurrences of division by zero) The following describes a specific scenario in which division by zero occurs repeatedly, following the processing flow in Figure 7. The initial state is as follows: value retention area V=10.0, state retention area S.depth=0, S.attr=0x00, threshold=3, normal operand normal=dividend, alternative value alt=0.0.

[0136] First calculation (normal): Dividend a = 6.0, divisor b = 2.0. Result = 3.0 (normal value). Step 1 determines ex = 0. Step 2 V = 3.0 × (1 - 0) + 10.0 × 0 = 3.0 (value updated). Step 3 S.depth = 0 + 0 = 0 (no change). Step 4 sel = (0 >= 3) = 0, input = normal (operand maintained as usual).

[0137] Second operation (division by zero occurs): Dividend a = 5.0, divisor b = 0.0. result = +Inf (according to the IEEE definition). In step 1, overflow is detected and ex = 1. In step 2, V = Inf × (1 - 1) + 3.0 × 1 = 3.0 (the most recent valid value is retained). In step 3, S.depth = 0 + 1 = 1, S.attr = 0x00|0x01 = 0x01 (the division by zero bit is set). In step 4, sel = (1 >= 3) = 0, input = normal (normal operand maintained because the threshold is not reached).

[0138] Third and fourth operations (division by zero occurs again): Similarly, ex is determined to be 1, and V remains at 3.0. S.depth increases from 2 to 3. In step 4 of the fourth operation, sel = (3 >= 3) = 1, and input = normal × 0 + alt × 1 = 0.0 (switching to an alternative value). Subsequent operations are designed to use a safe alternative value (e.g., 1.0) instead of the alternative value 0.0 as the divisor, thereby preventing a chain of division by zero.

[0139] Throughout the entire process of the above scenario, no conditional branch instructions were executed. The instruction sequences executed by processor 201 were completely identical between the first operation, where ex was 0, and the second through fourth operations, where ex was 1, resulting in no difference in the number of execution cycles. Due to this property, it is difficult to estimate the occurrence of an operation error through external timing analysis.

[0140] (Note regarding implementation flexibility) The above processing flow is just one example of how to implement the present invention. The selection of specific instructions for conditional selection operations (CMOV, CSEL, BLEND, etc.), the arrangement of bit fields in the state data structure, the setting of thresholds, and the content of alternative values ​​can be appropriately changed or optimized depending on the processor architecture and application. Furthermore, the method of write-back control processing in step 2 can be selected from an arithmetic operation method (multiplication selection), a conditional move instruction method (CMOV / CSEL), or a bitmask operation method, depending on the instruction set of the target processor.

[0141] The arithmetic processing system 2 described above also provides a technology that can maintain the continuity and safety of calculations even when an unusual calculation state occurs during the calculation process.

[0142] <Other variations> The embodiments described above are merely examples, and this disclosure may be modified as appropriate without departing from its essence. For example, the processes and means described in this disclosure can be freely combined and implemented as long as no technical inconsistencies arise. [Explanation of Symbols]

[0143] 1. Processing System 10····ESRCS module 101... Arithmetic logic circuits 102...Value Register 103...Abnormality judgment circuit 104...Write-back control circuit 105... State Register 106...State transition circuit 107...Recursive data path

Claims

1. A value register that holds the value to be calculated, A state register is configured as a memory element independent of the value register, and stores a state index that indicates the history of occurrences of unique calculation states that occurred during the calculation process. An arithmetic logic circuit that performs calculations based on the value held in the aforementioned value register, An abnormality determination circuit that determines whether a predetermined abnormality condition defined as the unique calculation state has been met, based on the process or result of the calculation in the aforementioned arithmetic logic circuit, A write-back control circuit, based on the abnormality detection signal output by the abnormality determination circuit, hardware-wise suppresses the writing of the calculation result from the arithmetic logic circuit to the value register and maintains the immediately preceding valid value held in the value register, A state transition circuit that updates the state index stored in the state register based on the abnormality detection signal, The state index output from the state register is fed back to the input side of the arithmetic logic circuit, and a recursive data path is provided that hardware switches the input data in subsequent calculations based on the state index. A computing system comprising: The anomaly detection signal is supplied only as an input to the write-back control circuit and the state transition circuit, and does not have an electrical connection to any of the inputs of the circuit that controls the update of the program counter, the exception transition circuit that controls branching to the exception handler, and the circuit that controls interrupt requests. This configuration ensures that even when the unusual calculation state occurs, the control flow is not changed and calculations by the arithmetic logic circuit continue. A processing system that includes exception state retention and control.

2. The state register is a memory element that has a bit width independent of the value register and is assigned to a unique register identification space selected by an independent address decoding circuit. A calculation processing system comprising exception state retention and control as described in claim 1.

3. The state index is structured data that includes a depth region that holds depth information recording the cumulative number of occurrences of the unusual calculation state, and an attribute region that holds attribute information indicating the source type or operation type of the unusual calculation state. A calculation processing system comprising exception state retention and control as described in claim 1.

4. The state transition circuit has a configuration that cumulatively increments the depth information using a hardware counter, or stores the attribute information by non-destructively superimposing or concatenating it with an existing bit sequence using at least one of a logical OR circuit, an exclusive OR circuit, or a bit shift coupling circuit. A calculation processing system comprising exception state retention and control as described in claim 3.

5. The write-back control circuit has a configuration that, without stopping the clock signal of the arithmetic logic circuit, masks the write enable signal input to the write port of the value register using a logic gate based on the anomaly detection signal, and selectively suppresses only writing to the value register while the arithmetic logic circuit is continuing to operate. A calculation processing system comprising exception state retention and control as described in claim 1.

6. The recursive data path includes a selector that takes a signal obtained by decoding at least a portion of the state indicator as input, and the selector is configured to physically switch the operand supplied to the next stage of the arithmetic logic circuit to a predetermined bitmask value, shift amount, or alternative constant without changing the control flow, even during the period when the anomaly detection signal is asserted. A calculation processing system comprising exception state retention and control as described in claim 1.

7. The valid value held in the value register immediately prior to the error is a normal calculation result in which the abnormal calculation state was not detected by the abnormality detection circuit during past calculation cycles, and the write-back control circuit has a configuration that maintains the safe value last confirmed when an abnormality occurs as the valid value by performing latch control which permits updating the value register only when the abnormality detection circuit determines that it is normal. A calculation processing system comprising exception state retention and control as described in claim 1.

8. The aforementioned arithmetic logic circuit has a pipeline structure that advances multiple arithmetic stages in synchronization with a clock signal. The abnormality determination circuit determines whether the abnormality condition is met at a predetermined stage in the pipeline structure. The state index updated by the state transition circuit is propagated to the next stage in synchronization with the data path to the value register via the interstage register of the pipeline structure. A calculation processing system comprising exception state retention and control as described in claim 1.

9. The abnormality detection circuit has a configuration that determines the occurrence of the unusual calculation state by detecting a signal change corresponding to at least one of division by zero, overflow, underflow, undefined operation, or predetermined reserved bit pattern at a predetermined bit position or calculation status flag line of the arithmetic logic circuit. A calculation processing system comprising exception state retention and control as described in claim 1.

10. A state evaluation circuit that compares the state index with predetermined judgment conditions, The system further comprises an output control gate circuit that, based on a determination signal from the state evaluation circuit, physically performs one of the following actions: transmit, block, or switch the output of the value held in the value register to an alternative signal. The output data path from the value register to the outside is configured to be connected only via the output control gate circuit. A calculation processing system comprising exception state retention and control as described in claim 1.

11. The state evaluation circuit further comprises a policy memory that holds the determination conditions referenced by the state evaluation circuit, The policy memory consists of hardware memory elements and is configured to be writable via an update path independent of the data path of the arithmetic logic circuit. A calculation processing system comprising exception state retention and control as described in claim 10.

12. The policy memory has a configuration that allows the state evaluation circuit to dynamically switch the threshold or decision table it references in hardware, in response to an external context signal indicating a safety requirement level or task priority. A calculation processing system comprising exception state retention and control as described in claim 11.

13. The state evaluation circuit and the output control gate circuit are configured to be driven by an independent control clock having a different frequency or phase from the clock of the arithmetic logic circuit. A calculation processing system comprising exception state retention and control as described in claim 10.

14. The output control gate circuit has a configuration in which, depending on the state indicator, a hardware multiplexer selects one of the following processes for the output value of the value register: masking, fixing to a predetermined saturation value, or replacement to a system-defined default value, and outputs the result to the outside. A calculation processing system comprising exception state retention and control as described in claim 10.

15. The state transition circuit has a configuration that receives a signal from an external sensor that detects physical anomalies and is located outside the arithmetic logic circuit, and stores anomaly information based on the signal in the same state register as anomaly information caused by calculations. A calculation processing system comprising exception state retention and control as described in claim 1.

16. The aforementioned arithmetic processing system is implemented as an expansion module or IP core located adjacent to the arithmetic unit of an existing processor, and has a configuration that performs calculations while being physically separated from the processor's interrupt request signal lines and program counter update logic. A calculation processing system comprising exception state retention and control as described in claim 1.

17. In a configuration in which multiple arithmetic logic circuits are arranged in parallel, each arithmetic logic circuit has its own independent state register and state transition circuit, and is configured to isolate the occurrence of the unique calculation state in one arithmetic logic circuit from the calculation progress and control flow of other arithmetic logic circuits at the hardware level. A calculation processing system comprising exception state retention and control as described in claim 1.

18. The computation data output to the outside is configured such that at least a portion of the state indicator is physically or structurally attached as a sideband signal or a predetermined field in the packet header, and that the state indicator can be captured by another computation processing system on the receiving end. A calculation processing system comprising exception state retention and control as described in claim 1.

19. A method for performing calculations in an arithmetic processing system comprising a value register for holding a value to be calculated and a state register independent of the value register, The abnormality detection circuit determines that a predetermined abnormal condition, defined as a unique calculation state, has been met based on the process or result of the calculation in the arithmetic logic circuit, and outputs an abnormality detection signal. Based on the aforementioned anomaly detection signal, the writing of the calculation result from the arithmetic logic circuit to the value register is suppressed by hardware, and the immediately preceding valid value held in the value register is maintained. The steps include updating the state index stored in the state register based on the anomaly detection signal, The updated state index is fed back to the input side of the arithmetic logic circuit, and the input data in subsequent calculations is hardware-switched based on the state index. It has, The aforementioned anomaly detection signal is used only to suppress writing to the value register and to control the updating of the state indicator, and is not used to control the updating of the program counter, branching to the exception handler, or interrupt requests. As a result, even when the aforementioned unusual calculation state occurs, the control flow is not changed and calculations by the arithmetic logic circuit continue. A method for performing arithmetic operations that includes exception state retention and control.

20. A processing system comprising a processor and a memory connected to the processor, The memory is provided with a value storage area for holding values ​​to be calculated, and a state storage area configured as a storage area independent of the value storage area for storing state indicators that show the history of occurrences of unique calculation states that occurred during the calculation process. The aforementioned processor, An abnormality determination process that calculates an abnormality determination value by arithmetic or logical operation, without using conditional branch instructions, whether or not a predetermined abnormal condition defined as the aforementioned unique calculation state has been met with respect to the result of the calculation, Based on the aforementioned abnormality determination value, a write-back control process selects either the result of the calculation or the immediately preceding valid value held in the value holding area without using a conditional branch instruction, by a conditional selection operation or a bitmask operation, and updates the value in the value holding area. A state update process that, based on the aforementioned abnormality determination value, cumulatively updates the depth information in the state index held in the state holding area by addition, or combines and updates the attribute information by logical OR or exclusive OR operation, A feedback control process that, based on the state index held in the state holding area, switches the input data in subsequent calculations to a predetermined mask value, saturation value, or alternative value by conditional selection calculation or bitmask calculation without using conditional branch instructions, Execute, The aforementioned abnormality determination value is used only for controlling the write-back control process and the state update process, and is not used as an operand in a conditional branch instruction. As a result, the abnormality determination process, the write-back control process, the state update process, and the feedback control process are all executed as an instruction sequence that does not include a conditional branch instruction, and the same instruction execution path is maintained regardless of whether or not the unusual calculation state occurs. A processing system that includes exception state retention and control.

21. The conditional selection operation in the write-back control process is characterized by being executed using one of the conditional move instruction, predicate execution instruction, or SIMD selection instruction provided by the processor. A calculation processing system comprising exception state retention and control as described in claim 20.

22. The state index is characterized in that it is arranged in memory as a fixed-length bit field structure including a depth field indicating the cumulative number of occurrences of the unique computation state and an attribute field indicating the type of unique computation state that occurred. A calculation processing system comprising exception state retention and control as described in claim 20.

23. The feedback control process is characterized by calculating a selection value of 0 or 1 by arithmetic operation without using a conditional branch instruction based on the comparison result between the depth information of the state index and a predetermined threshold, and using this selection value as a multiplication coefficient or bitmask to perform a selection between a normal operand and an alternative value. A calculation processing system comprising exception state retention and control as described in claim 20.

24. The processor further performs output control processing that compares the state indicator with predetermined policy data held in the memory, and, based on the comparison result, permits, prohibits, or replaces the value held in the value holding area with an alternative value to an external output destination, without using conditional branch instructions. A calculation processing system comprising exception state retention and control as described in claim 20.

25. A method for performing calculations in a computing system comprising a processor and memory, wherein the processor performs calculations, The steps include: calculating an abnormality determination value as an arithmetic or logical operation, without using conditional branch instructions, whether or not a predetermined abnormal condition, defined as a unique calculation state, has been met for the result of the calculation; Based on the aforementioned abnormality determination value, the steps include selecting either the result of the calculation or the immediately preceding valid value held in the memory, without using a conditional branch instruction, by a conditional selection operation or a bitmask operation, and updating the value in the memory; Based on the aforementioned abnormality determination value, the depth information and attribute information of the state index held in the memory are cumulatively updated. Based on the updated state index, the input data for subsequent calculations is switched by a conditional selection operation or a bitmask operation without using a conditional branch instruction. It has, The aforementioned abnormality determination value is used only to control the updating of the value in memory and the updating of the state index, and is not used as an operand of a conditional branch instruction. As a result, all of the aforementioned steps are executed as an instruction sequence that does not include a conditional branch instruction, and the same instruction execution path is maintained regardless of whether or not the unusual calculation state occurs. A method for performing arithmetic operations that includes exception state retention and control.

26. An arithmetic processing program, which includes exception state retention and control, is executed by the arithmetic processing system described in any one of claims 20 to 24.

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