Manufacturing method for semiconductor devices

Abstract

To provide a manufacturing method for a semiconductor device that can form a locally thick insulating film in which contamination of impurities is suppressed.SOLUTION: A manufacturing method for a semiconductor device according to an embodiment includes a first deposition step, a second deposition step, and an oxidation step. The first deposition step forms a first film made of silicon on the surface of a substrate composed of silicon carbide. The second deposition step forms a second film on the surface of the first film. The oxidation step forms a third film by thermally oxidizing the first film from the surface side. In the second deposition step, the second film is not formed on a portion of the first film and the portion is exposed, or in the second deposition step, the film thickness of the second film formed on a portion of the first film is smaller than the film thickness of the second film formed on another portion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, as semiconductor devices have become more miniaturized, there has been a need for structures that can achieve miniaturization while increasing the dielectric strength by locally thickening the insulating film in areas where dielectric breakdown is likely to occur within the semiconductor device. Therefore, methods have been proposed to form locally thick insulating films using film deposition methods such as chemical vapor deposition (CVD). However, in this case, there is a problem in that impurities are easily mixed into the insulating film. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2014-56912 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a method for manufacturing a semiconductor device that can form a locally thick insulating film while suppressing the inclusion of impurities. [Means for solving the problem]

[0005] The semiconductor device manufacturing method of the embodiment comprises a first film formation step, a second film formation step, and an oxidation step. In the first film formation step, a first film made of silicon is formed on the surface of a substrate made of silicon carbide. In the second film formation step, a second film is formed on the surface of the first film. In the oxidation step, the first film is thermally oxidized from the surface side to form a third film. In the second film formation step, the second film is not formed on a portion of the first film, leaving that portion exposed. Alternatively, in the second film formation step, the film thickness of the second film formed on a portion of the first film is smaller than the film thickness of the second film formed on other portions. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] Flowchart of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] A schematic diagram of the substrate formation process in the first embodiment. [Figure 4] A schematic diagram of the ion implantation process in the first embodiment. [Figure 5] A schematic diagram of the trench formation process in the first embodiment. [Figure 6] A schematic diagram of the first film formation process in the first embodiment. [Figure 7] A schematic diagram of the inhibitor adsorption step in the second film formation step of the first embodiment. [Figure 8] A schematic diagram of the precursor adsorption step in the second film formation step of the first embodiment. [Figure 9] A schematic diagram of the film formation process in the second film formation step of the first embodiment. [Figure 10] A schematic diagram of the first oxidation step in the first embodiment. [Figure 11] A schematic diagram of the etching process in the first embodiment. [Figure 12] A schematic diagram of the second oxidation step in the first embodiment. [Figure 13] A schematic diagram of the electrode formation process in the first embodiment. [Figure 14]Schematic diagram of the interlayer insulating film forming step according to the first embodiment. [Figure 15] Schematic diagram of the first oxidizing step of a modification applicable to the first embodiment. [Figure 16] Schematic diagram of the second film forming step of a modification applicable to the first embodiment. [Figure 17] It is a part of the flowchart of the method for manufacturing a semiconductor device according to the second embodiment. [Figure 18] Schematic diagram of the precursor adsorption step in the second film forming step according to the second embodiment. [Figure 19] Schematic diagram of the film forming step in the second film forming step according to the second embodiment. [Figure 20] Schematic diagram of the first oxidizing step according to the second embodiment. [Figure 21] Schematic diagram of the first and second etching steps according to the second embodiment. [Figure 22] Schematic diagram of the third etching step according to the second embodiment. [Figure 23] Schematic diagram of the third film forming step according to the second embodiment. [Figure 24] Schematic diagram of the second oxidizing step according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment will be described with reference to the drawings.

[0008] In this specification, the concepts of "upper" and "lower" are not necessarily terms indicating a relationship with the direction of gravity. In the following description, the notations n, n - and p, p - represent relative levels of the impurity concentration in each conductivity type. That is, n - indicates that the n-type impurity concentration is relatively lower than that of n. Also, p - indicates that the p-type impurity concentration is relatively lower than that of p. Note that the n - type may be simply described as n-type, and the p - type may be simply described as p-type in some cases.

[0009] (First Embodiment) FIG. 1 is a schematic cross-sectional view of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 of the present embodiment is a trench-type metal-oxide-semiconductor field-effect transistor (MOSFET, hereinafter referred to as MOSFET).

[0010] The semiconductor device 1 includes a base substrate 10, an insulating film 30 (gate insulating film), a gate electrode 20, an interlayer insulating film 40, a source electrode 21, a drain electrode 24, a source wiring 22, and a protective electrode 25.

[0011] The base substrate 10 is made of silicon carbide (SiC). The silicon carbide constituting the base substrate 10 preferably has a hexagonal crystal structure, and more preferably has a 4H polytype. The base substrate 10 is formed by epitaxially growing silicon carbide on a single crystal silicon carbide substrate. Silicon carbide (SiC) has a dielectric breakdown electric field approximately 10 times larger than that of silicon (Si). Therefore, by using silicon carbide as the base substrate 10 of the semiconductor device 1, the impurity concentration can be increased while maintaining the withstand voltage, and a low-resistance, low-loss MOSFET for high power can be configured. The base substrate 10 includes an n - layer 12, a p-type body layer 13, an n-region 14, and a contact region 15.

[0012] n - layer 12 is n-type due to addition of a dopant. The p-type body layer 13 is provided on the n - layer 12. The n-region 14 is n-type. The n - layer 12 is n - type. The n-region 14 is provided on the p-type body layer 13. The n-region 14 is separated from the n - layer 12 by the p-type body layer 13. The n-region 14 has a relatively higher n-type impurity concentration than the n - layer 12. The contact region 15 is p-type. The p-type body layer 13 is p -It has a type. The contact region 15 is formed on a portion of the p-type body layer 13 so as to connect to the p-type body layer 13. The contact region 15 has a relatively higher concentration of p-type impurities than the p-type body layer 13.

[0013] The base material 10 has a trench 5. The trench 5 opens upward. The inner surface of the trench 5 includes a bottom surface 5b and a side wall surface 5a extending upward from the bottom surface 5b. The bottom surface 5b of the trench 5 is n - It is placed in layer 12. The side wall surface 5a of trench 5 passes through the p-type body layer 13 from the upper surface of n region 14 to n - It extends up to layer 12.

[0014] The insulating film 30 covers the inner surface of the trench 5, i.e., the side wall surface 5a and the bottom surface 5b. The insulating film 30 has a side wall film 31 provided on the side wall surface 5a of the trench 5 and a bottom film 32 provided on the bottom surface 5b. The side wall film 31 extends upward from the bottom film 32. The film thickness T2 of the bottom film 32 is greater than the film thickness T1 of the side wall film 31. When the semiconductor device 1 is driven, the electric field tends to concentrate at the corner between the bottom surface 5b and the side wall surface 5a of the trench 5, and the withstand voltage at this location tends to become a problem. According to this embodiment, by making the film thickness T1 of the side wall film 31 relatively thin, the semiconductor device 1 can be miniaturized, while by making the film thickness T2 of the bottom film 32 relatively thick, the withstand voltage at the corner can be increased, and a semiconductor device 1 with excellent insulating properties can be constructed. The film thickness T2 of the bottom film 32 is preferably 1 nm or more greater than the film thickness T1 of the side wall film 31 (T2-T1≧1nm), and more preferably 10 nm or more greater (T2-T1≧10nm).

[0015] The gate electrode 20 is embedded in the trench 5. An insulating film 30 is interposed between the gate electrode 20 and the inner surface of the trench 5. That is, the insulating film 30 separates the substrate 10 and the gate electrode 20 within the trench 5. The gate electrode 20 faces the surface of the p-type body layer 13 via the insulating film 30. The upper surface of the gate electrode 20 is at approximately the same height as the upper surface of the portion of the insulating film 30 located on the upper surface of the n-region 14. An interlayer insulating film 40 is provided so as to cover the portion of the insulating film 30 that extends onto the upper surface of the n-region 14 and the gate electrode 20.

[0016] The source electrode 21 penetrates the interlayer insulating film 40 and is in contact with the n region 14 and the contact region 15, respectively. The source wiring 22 is provided on the source electrode 21 and the interlayer insulating film 40 so as to be in contact with the source electrode 21. The drain electrode 24 is provided on the surface of the substrate 10 opposite to the surface where the trench 5 is provided. The protective electrode 25 covers the drain electrode 24.

[0017] Next, a method for manufacturing the semiconductor device 1 will be described. Figure 2 is a flowchart showing each step in the manufacturing method of the semiconductor device 1 according to this embodiment. The manufacturing method of the semiconductor device 1 according to this embodiment includes a substrate formation step S10, an ion implantation step S20, a trench formation step S30, a first film formation step S40, a second film formation step S50, a first oxidation step (oxidation step) S60, an etching step S70, a second oxidation step (oxide film formation step) S80, a gate electrode formation step S90, an interlayer insulating film formation step S100, a source electrode formation step S110, a source wiring formation step S120, a drain electrode formation step S130, and a protective electrode formation step S140.

[0018] Figure 3 is a schematic diagram of the substrate formation process S10 of this embodiment. In the substrate formation process S10, for example, on a pre-prepared silicon carbide single crystal substrate, a silicon carbide to which nitrogen (N) or phosphorus (P) has been introduced is formed. - The substrate 10 is manufactured by forming layer 12 by epitaxial growth. The single crystal substrate is removed by polishing in a final step, for example, but this is not shown in the illustration.

[0019] Figure 4 is a schematic diagram of the ion implantation process S20 of this embodiment. In the ion implantation process S20, a p-type body layer 13, an n-region 14, and a contact region 15 are formed. In the ion implantation process S20, an acceptor such as aluminum (Al) is ion-implanted from the upper surface of the substrate 10 in order to form the p-type body layer 13. Next in the ion implantation process S20, a donor such as phosphorus (P) is ion-implanted from the upper surface of the substrate 10 in order to form the n-region 14. As a result, n - A substrate 10 is formed having a layer 12, a p-type body layer 13, and an n-region 14. In the ion implantation step S20, an acceptor such as aluminum is then ion-implanted to form a contact region 15. In this embodiment, the p-type body layer 13 and the n-region 14 may be formed by epitaxial growth with the addition of impurities instead of the ion implantation step S20.

[0020] Next, an activation heat treatment is performed to activate the impurities added by ion implantation. The temperature of this heat treatment is preferably between 1500°C and 1900°C, for example, around 1700°C. The heat treatment time is, for example, around 30 minutes. The atmosphere for the heat treatment is preferably an inert gas atmosphere, for example, an argon (Ar) atmosphere.

[0021] Figure 5 is a schematic diagram of the trench formation process S30 of this embodiment. The trench formation process S30 forms trenches in a substrate 10 made of silicon carbide. In the trench formation process S30, first, a mask 91 having an opening 91a that partially exposes the n region 14 is formed on the substrate 10. The opening 91a of the mask 91 is formed corresponding to the position of the trench 5. In the opening 91a of the mask 91, the n region 14, the p-type body layer 13, and n - A portion of layer 12 is removed by etching. This forms a trench 5 in the substrate 10. After the trench 5 is formed, the mask 91 is removed.

[0022] Figure 6 is a schematic diagram of the first film formation step S40 of this embodiment. The first film formation step S40 is a step in which a silicon film (first film) 50 is formed on the inner surface of the trench 5. The silicon film 50 is made of silicon. In the first film formation step S40, the silicon film 50 is formed by, for example, a reduced-pressure CVD method (LP-CVD).

[0023] Figures 7 to 9 are schematic diagrams showing each step of the second film formation process S50 of this embodiment. The second film formation process S50 of this embodiment includes an inhibitor adsorption process S51 (Figure 7), a precursor adsorption process S52 (Figure 8), and a film formation process S53 (Figure 9). The second film formation process S50 is a process of forming a barrier film (second film) 60 on a part of the silicon film 50 provided on the inner surface of the trench 5 by atomic layer deposition (ALD). In the following description, the region of the silicon film 50 provided on the side wall surface 5a of the trench 5 is called the side wall film 51, and the region provided on the bottom surface 5b of the trench 5 is called the bottom film 52. In the second film formation process S50 of this embodiment, the barrier film 60 is formed only on the bottom film 52. In this embodiment, the barrier film 60 is made of silicon oxide (SiO2). However, the material of the barrier coating 60 is not limited to this embodiment.

[0024] Figure 7 is a schematic diagram of the inhibitor adsorption step S51 of this embodiment. The inhibitor adsorption step S51 is a step in which a factor that inhibits the adsorption of the precursor 72 (see Figure 8), which will be described later, (hereinafter referred to as inhibitor 71) is adsorbed onto the sidewall coating 51. In the manufacturing method of the semiconductor device 1 of this embodiment, examples of inhibitor 71 include SAMs (Self-Assembled Monolayers), SIMs (small molecule inhibitors), and surface termination using nitrogen atoms (N) or hydrogen atoms (H). In the inhibitor adsorption step S51, the inhibitor 71 is formed on the silicon coating 50 by CVD. More specifically, a gas containing the inhibitor 71 is introduced into the processing chamber. After the inhibitor 71 has been adsorbed, the gas containing the inhibitor 71 is exhausted from the processing chamber.

[0025] In the inhibitor adsorption step S51 of this embodiment, the pressure of the gas containing the inhibitor 71 and the gas introduction time are controlled so that the inhibitor 71 does not reach the innermost part of the inner surface of the trench 5. As a result, the inhibitor 71 is adsorbed on the upper region of the sidewall coating 51 on the inner surface of the trench 5, but not on the lower region of the sidewall coating 51 or the bottom coating 52.

[0026] Figure 8 is a schematic diagram of the precursor adsorption step S52 of this embodiment. In the precursor adsorption step S52, a gas containing the precursor 72 is introduced into the processing chamber. Examples of the precursor 72 in the manufacturing method of the semiconductor device 1 of this embodiment include TDMAS, Orthrus, 3DMAS, and SAM24. The precursor 72 does not adsorb to the portion of the silicon coating 50 surface where the inhibitor 71 is adsorbed. Therefore, the precursor 72 selectively adsorbs to the lower region of the sidewall coating 51 and the bottom coating 52 on the inner surface of the trench 5. After the precursor 72 is adsorbed, the gas containing the precursor 72 is exhausted from the processing chamber. Plasma may be generated when adsorbing the precursor 72.

[0027] Figure 9 is a schematic diagram of the film formation process S53 of this embodiment. In the film formation process S53, a reaction gas containing reactants that will form the basis of the barrier film 60 is introduced into the processing chamber. In the manufacturing method of the semiconductor device 1 of this embodiment, in the film formation process S53, SiO2 is formed by reacting O3 or radicals in the plasma (e.g., O radicals) with adsorbed molecules (precursors). The reaction gas reacts with the atoms of the precursor 72 only at the positions where the precursor 72 is adsorbed, forming a barrier film 60 made of silicon oxide (SiO2). For this reason, the barrier film 60 is formed only in the lower region of the sidewall film 51 and the bottom film 52. After the barrier film 60 is formed, the reaction gas is exhausted from the processing chamber.

[0028] As described above, after going through the second film formation process S50, the barrier film 60 is formed only in the lower region of the sidewall film 51 and the bottom film 52. That is, in the second film formation process, a portion of the silicon film 50 (bottom film 52) provided on the inner surface of the trench 5 is covered with the barrier film 60, while the other portion of the silicon film 50 (sidewall film 51) is exposed from the barrier film 60. Therefore, the combined film of the silicon film 50 and the barrier film 60 becomes locally thicker in the area where the barrier film 60 is formed. In this embodiment, the film thickness TA of the barrier film 60 is set to TA. When ALD is used as the second film formation process S50, the film thickness TA of the barrier film 60 is preferably set to, for example, 300 nm or less, considering the film formation rate of ALD from the viewpoint of productivity.

[0029] In this embodiment, ALD is used in the second film deposition step S50. With ALD, atomic layers can be deposited one layer at a time, thus reducing the inclusion of impurities and allowing the barrier film 60 to be deposited with a stoichiometric composition. Therefore, by using ALD as the second film deposition step S50, a barrier film 60 with a uniform and highly controlled film thickness can be selectively deposited on a part of the inner surface of the trench 5. Furthermore, when ALD is used in the second film deposition step S50, the deposition on the sidewall film 51 can be partially restricted by using an inhibitor, so that a part of the silicon film 50 (sidewall film 51) can be exposed. In this embodiment, the case in which the barrier film 60 is not formed on the sidewall film 51 in the second film deposition step S50 has been described. However, as will be explained in the later modification (Figure 16), a thin film barrier film 60A may be formed on the sidewall film 51. In this case, the thickness of the barrier coating 60A formed on the sidewall coating 51 should be smaller than the thickness of the barrier coating 60A formed on the bottom coating 52.

[0030] Figure 10 is a schematic diagram of the first oxidation step S60 of this embodiment. The first oxidation step S60 is a step in which the silicon film 50 is thermally oxidized from the surface side to form a first oxide film 80 made of silicon oxide (SiO2). In the first oxidation step S60, the temperature, time, oxygen concentration, etc. are adjusted to thermally oxidize only a part of the surface side of the silicon film 50 to form the first oxide film (third film) 80. This thermal oxidation is carried out at a temperature such that silicon is thermally oxidized but silicon carbide is not substantially thermally oxidized.

[0031] In the following explanation, the portion of the first oxide film 80 formed on the sidewall film 51 is referred to as the first portion 80a, and the portion formed on the bottom film 52 is referred to as the second portion 80b. After the first oxidation step S60, the first portion 80a with a film thickness T3 is formed on the surface of the sidewall film 51. In addition, the second portion 80b with a film thickness T4 is formed on the interface side of the bottom film 52 with the barrier film 60. Note that the thermal oxidation of the bottom film 52 proceeds on the underside of the first oxide film 80, and is therefore slightly slower than the thermal oxidation of the sidewall film 51. Consequently, the film thickness T4 of the second portion 80b of the first oxide film 80 is slightly smaller than the film thickness T3 of the first portion 80a.

[0032] After the first oxidation step S60, a silicon oxide (SiO2) film consisting only of a first oxide film 80 (first portion 80a) with a thickness T3 is formed on the sidewall film 51. On the other hand, a laminated film is formed on the bottom film 52 after the first oxidation step S60, consisting of a barrier film 60 with a thickness TA and a first oxide film 80 (second portion 80b) with a thickness T4. Here, the sum of the thicknesses of the barrier film 60 and the first oxide film 80 on the bottom film 52 (TA+T4) is greater than the thickness T3 of the first oxide film 80 on the sidewall film 51 (TA+T4>T3). Therefore, the thickness of the oxide film on the silicon film 50 in the portion formed on the bottom surface 5b of the trench 5 (TA+T4) is greater than the thickness T3 of the portion formed on the sidewall surface 5a.

[0033] FIG. 11 is a schematic diagram of the etching step S70 of the present embodiment. The etching step S70 is a step of etching and removing the barrier film 60 and a part of the first oxide film 80. The etching step S70 can be performed by various means such as wet etching using hydrofluoric acid, chemical dry etching, and reactive ion etching (RIE), for example.

[0034] The etching step S70 of the present embodiment removes a predetermined film thickness from the surface side of the oxide film formed on the surface of the base material 10. The film thickness TB removed in the etching step S70 is larger than the film thickness T3 of the first portion 80a shown in FIG. 10, and smaller than the sum of the film thicknesses of the barrier film 60 and the second portion 80b (TA+T4) (T3<TB<TA+T4). Therefore, on the inner side surface of the trench 5 after the etching step S70, only the second portion 80b of the first oxide film 80 located on the bottom surface 5b remains, and the first portion 80a on the side wall surface 5a is removed.

[0035] It should be noted that the film thickness TB removed in the etching step S70 is preferably larger than the film thickness TA of the barrier film 60 (TB>TA). This can suppress the oxide film derived from the barrier film 60 from remaining on the bottom surface 5b, allow only the oxide film formed by thermal oxidation to remain, and improve the crystal uniformity of the insulating film 30. It should be noted that the barrier film 60 does not necessarily need to be completely removed, and may remain.

[0036] FIG. 12 is a schematic diagram of the second oxidation step S80 of the present embodiment. The second oxidation step S80 is a step of thermally oxidizing the entire silicon film 50 remaining after the first oxidation step S60 and the etching step S70 to form the insulating film 30. That is, the second oxidation step S80 is a step of forming the insulating film (fourth film) 30 made of silicon oxide on the inner side surface of the trench 5. This thermal oxidation is performed at a temperature such that silicon is thermally oxidized and silicon carbide is substantially not thermally oxidized.

[0037] Through the second oxidation process S80, the sidewall film 51 and bottom film 52 of the silicon film 50 are oxidized, and a second oxide film 59 derived from the silicon film 50 is formed on the inner surface of the trench 5. The second oxide film 59 derived from the silicon film 50 and the first oxide film 80 formed on the second oxide film 59 combine to form an insulating film 30 on the inner surface of the trench 5. As described above, since the first oxide film 80 remains only on the bottom surface 5b of the trench 5, the bottom film 32 of the insulating film 30 is composed of the second oxide film 59 derived from the silicon film 50 and the first oxide film 80. On the other hand, the sidewall film 31 of the insulating film 30 is composed only of the second oxide film 59 derived from the silicon film 50. For this reason, the thickness T2 of the bottom film 32 of the insulating film 30 is greater than the thickness T1 of the sidewall film 31.

[0038] Figure 13 is a schematic diagram of the gate electrode formation step S90 of this embodiment. In the gate electrode formation step S90, a gate electrode 20 is formed inside the trench 5 on the insulating film 30. The gate electrode 20 can be formed, for example, by deposition of a conductor or doped polysilicon film and CMP (Chemical Mechanical Polishing).

[0039] Figure 14 is a schematic diagram of the interlayer insulating film formation process S100 of this embodiment. In the interlayer insulating film formation process S100, the interlayer insulating film 40 is formed on the gate electrode 20 and the insulating film 30 so as to cover the exposed surface of the gate electrode 20.

[0040] Next, although specific illustrations are omitted, the source electrode formation process, source wiring formation process, drain electrode formation process, and protective electrode formation process are carried out, and as shown in Figure 1, the source electrode 21, source wiring 22, drain electrode 24, and protective electrode 25 are formed in order. The source electrode 21 is formed after openings are formed in the interlayer insulating film 40 and insulating film 30 by etching, exposing the n region 14 and contact region 15.

[0041] By following the above steps, a semiconductor device 1 can be manufactured that has an insulating film 30 in which the film thickness T2 on the bottom surface 5b of the trench is greater than the film thickness T1 on the side wall surface 5a.

[0042] Next, a first modified example that can be adopted in this embodiment will be described. In the manufacturing method of the semiconductor device 1 of this embodiment, in the first oxidation step S60, only a portion of the silicon film 50 is oxidized from the surface side, and the oxidized portion is removed in the subsequent etching step S70. However, in the first oxidation step S60, the entire silicon film 50 may be oxidized and used as is as part of the insulating film 30. Figure 15 is a schematic diagram of the first oxidation step S60 of a modified example that can be adopted in this embodiment. In the first oxidation step S60 of this modified example, the entire silicon film 50 is thermally oxidized to form a first oxide film 80A. Furthermore, the film consisting of the barrier film 60 and the first oxide film 80A is used as the insulating film 30A of the modified example. In the insulating film 30A of this modified example, only the first oxide film 80A is placed on the side wall surface 5a of the trench, while the barrier film 60 is placed on the bottom surface 5b in addition to the first oxide film 80A. Therefore, the film thickness T5b on the bottom surface 5b of the insulating film 30A can be made larger than the film thickness T5a on the side wall surface 5a. In this modified example, after the first oxidation step S60 is performed, the gate electrode formation step S90 and subsequent steps are carried out in the above-described procedure without performing the etching step S70 and the second oxidation step S80. In other words, according to this modified example, it is possible to omit some steps for forming the insulating film 30A, thereby simplifying the manufacturing process of the semiconductor device 1. In the above-described embodiment, the barrier film 60 is removed in the etching step S70, and the thickness of the insulating film 30 is secured separately by thermal oxidation. In this way, in the above-described embodiment, only the oxide film formed by thermal oxidation is used as the insulating film 30, thereby improving the crystalline uniformity of the insulating film 30.

[0043] Furthermore, a second modification that can be adopted in this embodiment will be described. Furthermore, in this embodiment, the case in which only the silicon film 50 that remained unoxidized in the first oxidation step S60 (Figure 10) is thermally oxidized in the second oxidation step S80 (Figure 12) and used as the insulating film 30 has been described. However, after the etching step S70 (Figure 11), a new film made of silicon may be formed on the silicon film 50 and the first oxide film 80. In this case, the new silicon film is thermally oxidized together with the silicon film 50 in the second oxidation step S80, and together with the first oxide film 80 remaining after the etching step S70 (Figure 11), it constitutes the insulating film 30. In this case, a thicker insulating film 30 can be formed than in this embodiment.

[0044] Furthermore, a third modification that can be adopted in this embodiment will be described. Furthermore, in this embodiment, the case in which ALD is used in the second film deposition step S50 has been described. However, as a modification of the second film deposition step S50, the case in which CVD is used is also conceivable. Figure 16 is a schematic diagram showing the modified second film deposition step S50. Examples of CVD that can be used in the second film deposition step S50 of this modified version include HDPCVD (high density plasma chemical vapor deposition), SACVD (selective area chemical vapor deposition), and PECVD (plasma-enhanced chemical vapor deposition). In this modified version, the barrier film 60A is formed not only on the bottom surface 5b of the trench 5 but also on the side wall surface 5a, but the film thickness TCa of the barrier film 60A on the side wall surface 5a is smaller than the film thickness TCb on the bottom surface 5b. In other words, in the second film formation step S50, the film thickness TCa of the barrier film 60A formed on a portion of the silicon film 50 (sidewall film 51) is smaller than the film thickness TCb of the barrier film 60A formed on the other portion (bottom film 52). In this modified example, as in the above-described embodiment, the entire barrier film 60A is removed by etching step S70 after the silicon film 50 is thermally oxidized in the first oxidation step S60 to form the first oxide film 80. As in the above-described embodiment, in etching step S70, the first oxide film 80 on the bottom surface 5b can be left intact depending on the difference in film thickness of the barrier film 60A.

[0045] The configurations of the first embodiment are summarized below. The manufacturing method of the semiconductor device 1 of this embodiment comprises a first film formation step S40, a second film formation step S50, and a first oxidation step (oxidation step) S60. The first film formation step S40 is a step of forming a silicon film 50 made of silicon (Si) on the surface of a substrate 10 made of silicon carbide (SiC). The second film formation step S50 is a step of forming a barrier film 60 on a part of the surface of the silicon film 50. The first oxidation step S60 is a step of forming a first oxide film 80 by thermal oxidation of the silicon film 50 from the surface side. In the second film formation step S50, the barrier film 60 is not formed on a part of the silicon film 50 and that part is exposed, or the thickness of the barrier film 60 formed on a part of the silicon film 50 is smaller than the thickness of the barrier film 60 formed on other parts.

[0046] According to the above configuration, after the first oxidation step S60, the thickness of the composite film of the barrier film 60 and the first oxide film 80 can be locally varied on the surface of the substrate 10. In the above embodiment, by etching this composite film (etching step S70), a portion of the first oxide film 80 is left intact to form a locally thicker insulating film 30. In the above modified example (see Figure 15), this composite film is used as the insulating film 30A, forming a locally thicker insulating film 30A in which the barrier film 60 and the first oxide film 80 are laminated. Thus, according to the above configuration, by selectively adjusting the thickness of the barrier film 60, it is possible to form insulating films 30 and 30A with freely adjustable arrangement and thickness. As a result, a small semiconductor device 1 with excellent voltage resistance can be manufactured by forming a thicker insulating film 30 and 30A only in the parts where improved insulation performance is required. According to the above configuration, the insulating film 30A can be made of an oxide film obtained by thermal oxidation of a film deposited as silicon, or an oxide film formed by ALD. In other words, according to the above configuration, films deposited using CVD are not used as insulating films 30 and 30A. Therefore, compared to the case in which insulating films are formed by CVD, it is possible to form locally thick insulating films 30 and 30A with suppressed impurity contamination.

[0047] In the above configuration, the first oxidation step S60 may be a step in which only a part of the silicon film 50 is thermally oxidized to form a first oxide film 80 (Figure 10), or it may be a step in which all of the silicon film 50 is thermally oxidized to form a first oxide film 80A (see Figure 15).

[0048] The manufacturing method of the semiconductor device 1 in this embodiment includes an etching step S70 and a second oxidation step (oxide film formation step) S80. The etching step S70 is a step of etching the barrier film 60 and at least a part of the first oxide film 80. The second oxidation step S80 is a step of forming an insulating film (fourth film) 30 made of silicon oxide (SiO2) on the surface of the substrate 10.

[0049] According to the above configuration, the barrier film 60 can be removed by etching in etching step S70, and then the insulating film 30 can be formed in the second oxidation step S80. Therefore, the insulating film 30 can be formed by thermal oxidation alone without leaving any film derived from the barrier film 60 on the insulating film 30, and the crystalline uniformity of the insulating film 30 can be improved.

[0050] The manufacturing method of the semiconductor device 1 of this embodiment includes a trench formation step S30 in which a trench 5 is formed in the substrate 10 before the first film deposition step S40. The portion of the silicon film 50 in which no barrier film 60 is formed (or only a thin barrier film is formed) is the portion that is formed on the side wall surface 5a of the trench 5. The other portion of the silicon film 50 in which the barrier film 60 is formed is the portion that is formed on the bottom surface 5b of the trench 5. With this configuration, the barrier film 60 can be formed only on the bottom surface 5b of the trench 5, or the barrier film 60 on the bottom surface 5b can be made thicker than the barrier film 60 on the side wall surface 5a. As a result, for example, in the insulating films 30, 30A, the insulating performance of the bottom film 32 can be made higher than the insulating performance of the thinly formed portion (side wall film 31). When the semiconductor device 1 is a trench-type MOSFET, the electric field tends to concentrate near the corners of the bottom surface 5b of the trench 5, making dielectric breakdown likely to occur. As shown in this embodiment, by making the bottom film 32 of the insulating film 30 thicker than other parts, the insulating properties of the trench-type MOSFET can be improved.

[0051] In the manufacturing method of the semiconductor device 1 of this embodiment, the barrier film 60 is silicon oxide (SiO2). With this configuration, both the barrier film 60 and the first oxide film 80 are made of silicon oxide. Therefore, the oxygen diffusion coefficients of the barrier film 60 and the first oxide film 80 are approximately the same, and in the first oxidation step S60, an oxide film of sufficient thickness can be formed on the underside of the barrier film 60. Furthermore, when performing the etching step S70, the barrier film 60 and the first oxide film 80 can be etched simultaneously, thereby simplifying the manufacturing process.

[0052] (Second embodiment) Figure 17 is a flowchart showing some of the steps involved in the manufacturing method of the semiconductor device 1 according to the second embodiment. In the descriptions of each embodiment described below, components that are the same as those in the embodiments already described are denoted by the same reference numerals, and their descriptions are omitted.

[0053] As shown in Figure 17, the second embodiment includes a second film formation step S150, a first oxidation step S160, an etching step S170, and an oxide film formation step S180. Note that in the manufacturing method of the second embodiment, the same configuration as in the manufacturing method of the first embodiment will not be described. That is, in the second embodiment, the explanation of the substrate formation step S10, ion implantation step S20, trench formation step S30, and first film formation step S40, which are performed before each step shown in Figure 17, and the explanation of the gate electrode formation step S90, interlayer insulating film formation step S100, source electrode formation step S110, source wiring formation step S120, drain electrode formation step S130, and protective electrode formation step S140, which are performed after each step shown in Figure 17, will be omitted.

[0054] The second film formation step S150 of this embodiment includes a precursor adsorption step S151 and a film formation step S152. The second film formation step S150 is a step of forming a barrier film (second film) 160 by ALD on a part of the silicon film 50 provided on the inner surface of the trench 5. In this embodiment, the barrier film 160 is silicon nitride (SiN).

[0055] Figure 18 is a schematic diagram of the precursor adsorption process S151 of this embodiment. In the precursor adsorption process S151, a gas containing the precursor 172 is introduced into the processing chamber. Examples of the precursor 172 in this embodiment include chlorosilane, organosilane, and heterosilane. Furthermore, the gas containing the precursor 172 is exhausted from the processing chamber before it sufficiently reaches the bottom surface 5b of the trench 5. As a result, in the precursor adsorption process S151 of this embodiment, the precursor 172 is adsorbed on the sidewall coating 51 on the inner surface of the trench 5, but not on the bottom coating 52 or the sidewall coating 51 in the vicinity of the bottom coating 52.

[0056] Figure 19 is a schematic diagram of the film formation process S152 of this embodiment. In the film formation process S152, a reaction gas containing reactants that form the basis of the barrier film 160 is introduced into the processing chamber. Examples of reaction gases include NH3 plasma. The reaction gas reacts with the atoms of the precursor 172 only at the positions where the precursor 172 is adsorbed to form the barrier film 160. For this reason, the barrier film 160 is formed only in the upper region of the side wall film 51 within the trench 5. After the barrier film 160 is formed, the reaction gas is exhausted from the processing chamber.

[0057] As described above, through the second film formation process S150, the barrier film 160 made of silicon nitride (SiN) is formed only in the upper region of the side wall film 51 within the trench 5. In other words, in the second film formation process S150, the barrier film 160 is not formed on a portion of the silicon film 50 (bottom film 52), and that portion is exposed.

[0058] As a variation of the second film formation step S150, a barrier film 160 may be formed with a uniform thickness on the entire inner surface of the trench 5, including the bottom surface 5b, by ALD, and then only the barrier film 160 on the bottom film 52 may be removed by reactive ion etching (RIE). In this case, in the precursor adsorption step, the precursor is adsorbed onto the entire inner surface of the trench 5. As a result, in the film formation step, a barrier film is formed on the entire inner surface of the trench 5.

[0059] Figure 20 is a schematic diagram of the first oxidation step S160 of this embodiment. The first oxidation step S160 is a step in which the silicon film 50 is thermally oxidized from the surface side to form a first oxide film (third film) 180. Silicon nitride (SiN), which constitutes the barrier film 160, has a smaller oxygen diffusion coefficient compared to silicon oxide (SiO2). Therefore, in the first oxidation step S160, the thermal oxidation progresses more slowly on the underside of the barrier film 160. Consequently, in the first oxidation step S160, the film thickness T6 of the first portion 180a formed on the underside of the barrier film 160 of the first oxide film 180 is smaller than the film thickness T7 of the second portion 180b exposed from the barrier film 160. In this embodiment, only a portion of the silicon film 50 on the boundary side with the barrier film 60 becomes the first oxide film 180. On the other hand, the silicon film 50 exposed from the barrier film 160 oxidizes throughout its thickness to become the first oxide film 180.

[0060] In this embodiment, the case in which silicon nitride is used as the barrier film 160 has been described, but if the oxygen diffusion coefficient of the barrier film 160 is smaller than that of silicon oxide, a similar first oxide film 180 can be formed.

[0061] Figures 21 and 22 are schematic diagrams of the etching process S170 of this embodiment. The etching process S170 of this embodiment includes a first etching process S171 and a second etching process S172 shown in Figure 21, and a third etching process S173 shown in Figure 22. As shown in Figure 21, the first etching process S171 and the second etching process S172 are processes for etching and removing the barrier film 160 and a part of the first oxide film 180. Furthermore, as shown in Figure 22, the third etching process S173 is a process for etching and removing the silicon film 50. In other words, the etching process S170 of this embodiment is performed in stages: etching to remove the barrier film 160 made of silicon nitride, etching to remove the first oxide film 180 made of silicon oxide, and etching to remove the silicon film 50 made of silicon.

[0062] As shown in Figure 21, in the first etching step S171, the entire barrier film 160 is removed. In the second etching step S172, only the film thickness T6 of the first portion 180a of the first oxide film 180 is etched. As a result, after the second etching step S172, only the first oxide film 180 remains on the lower region of the side wall surface 5a and the bottom surface 5b of the trench 5, while only the silicon film 50 remains on the upper region of the side wall surface 5a. As shown in Figure 22, in the third etching step S173, the entire silicon film 50 is removed. After etching step S170, only the first oxide film 180 remains in the trench 5.

[0063] Figures 23 and 24 are schematic diagrams of the oxide film formation process S180. The oxide film formation process S180 is a process of forming an insulating film (fourth film) 130 made of silicon oxide (SiO2) on the surface of the substrate 10. The oxide film formation process S180 in this embodiment includes a third film formation process S181 shown in Figure 23 and a second oxidation process S182 shown in Figure 24.

[0064] As shown in Figure 23, the third film formation step S181 is a step in which a silicon (Si) film of uniform thickness 155 is formed on the surface of the substrate 10. In the third film formation step S181, the silicon film 155 is formed by, for example, a reduced-pressure CVD method (LP-CVD).

[0065] As shown in Figure 24, the second oxidation step S182 is a step in which the silicon film 155 formed in the third film formation step S181 is thermally oxidized to form a second oxide film 159. The second oxidation step S182 is performed at a temperature such that the silicon is thermally oxidized but the silicon carbide is not substantially thermally oxidized. After the second oxidation step S182, the inner surface of the trench 5 is covered with the first oxide film 180 and the second oxide film 159 derived from the silicon film 155. The first oxide film 180 and the second oxide film 159 constitute an insulating film 130. As described above, the first oxide film 180 remains only on the bottom surface 5b of the trench 5 and on the side wall surface 5a near the bottom surface 5b. Therefore, after the oxide film formation step S180, a locally thick insulating film 130 is formed on the inner surface in the lower regions of the bottom surface 5b and the side wall surface 5a.

[0066] According to the manufacturing method of the semiconductor device 1 of this embodiment, a locally thick insulating film 130 can be formed on the inner surface of the trench 5. This makes it possible to improve the insulating performance of the thickly formed portion compared to the thinly formed portion, and to manufacture a small semiconductor device 1 with excellent voltage resistance. Furthermore, according to this embodiment, a film formed using CVD is not used as the insulating film 130, and compared to the case in which the insulating film is formed by CVD, it is possible to form a locally thick insulating film 130 with suppressed impurity contamination.

[0067] In the manufacturing method of the semiconductor device 1 of this embodiment, as shown in Figure 20, the barrier film 160 was provided only in the upper region of the sidewall film 51 in the second film deposition step S150, and not in the lower region. As a result, as shown in Figure 24, the final insulating film 130 is stepped on the sidewall surface 5a of the trench 5, thereby further enhancing the insulation of the corners of the trench 5. However, in the second film deposition step S150, the barrier film 160 may be provided over the entire sidewall film 51 to form an insulating film 30 with a uniform film thickness on the sidewall surface 5a.

[0068] The configurations of the second embodiment are summarized below. According to the manufacturing method of the semiconductor device 1 of this embodiment, in the second film formation step S150, the silicon film 50 provided on the side wall surface 5a of the trench 5 (i.e., the side wall film 51) is covered with the barrier film 160, and the silicon film 50 provided on the bottom surface 5b of the trench 5 (i.e., the bottom film 52) is exposed from the barrier film 160. With this configuration, the barrier film 160 can be formed on the side wall surface 5a of the trench 5, and the combined film of the silicon film 50 and the barrier film 160 can form locally thicker portions on the side wall surface 5a of the trench 5.

[0069] In the manufacturing method of the semiconductor device 1 of this embodiment, similar to the first embodiment (see Figure 2), a trench formation step S30 is included before the first film deposition step S40 in which trenches 5 are formed in the substrate 10. As shown in Figure 19, a portion of the silicon film 50 in which no barrier film 160 is formed (or only a thin barrier film is formed) is the portion that is formed on the bottom surface 5b of the trench 5. The other portion of the silicon film 50 in which the barrier film 160 is formed is the portion that is formed on the side wall surface 5a of the trench 5. In this way, the thickness of the insulating film 130 may be locally increased by selecting the region in which the barrier film 160 is formed.

[0070] In the manufacturing method of the semiconductor device 1 of this embodiment, the barrier film 160 has a lower oxygen diffusion coefficient than silicon oxide. With this configuration, as shown in Figure 20, in the first oxidation step S160, the first oxide film 180 can be made thinner on the underside of the barrier film 160, and the first oxide film 180 can be made thicker in the portion exposed from the barrier film 160.

[0071] In the embodiments and their modifications described above, the cases described involved locally increasing the thickness of the insulating films 30, 30A, and 130 on the bottom surface 5b of the trench 5 compared to other parts. However, by using a similar method, it is also possible to locally increase the thickness of the insulating film near the opening of the trench 5. Furthermore, even in structures without trenches 5, it is possible to form locally thickened insulating films.

[0072] Furthermore, the embodiments and their variations described above can be combined with each other. For example, a barrier film made of the material (silicon nitride) described in the second embodiment may be provided at the same position as the barrier film described in the first embodiment. Similarly, a barrier film made of the material (silicon oxide) described in the first embodiment may be provided at the same position as the barrier film described in the second embodiment. In these cases, for example, an insulating film can be formed in which the thickness of the bottom portion and the side wall portion are reversed.

[0073] According to at least one embodiment described above, the barrier films 60, 60A, and 160 can form films of different thicknesses on the surface of the substrate 10, and locally thick insulating films 30, 30A can be formed with suppressed impurity contamination.

[0074] The present invention includes the following appended embodiments. (Note 1) A first film formation step in which a first film made of silicon is formed on the surface of a substrate made of silicon carbide, A second film formation step of forming a second film on the surface of the first film, The process includes an oxidation step of forming a third film by thermally oxidizing the first film from the surface side, In the second film formation step, On a portion of the first coating, the second coating is not formed and that portion is exposed. Alternatively, the thickness of the second coating formed on the portion of the first coating is smaller than the thickness of the second coating formed on the other portion. A method for manufacturing a semiconductor device. (Note 2) An etching step of etching the second coating and at least a portion of the third coating, The process includes an oxide film formation step of forming a fourth film made of silicon oxide on the surface of the substrate, A method for manufacturing a semiconductor device as described in Appendix 1. (Note 3) Prior to the first film formation step, there is a trench formation step in which trenches are formed in the substrate, The portion of the first coating is the portion that is formed on the side wall surface of the trench, The other portion of the first coating is the portion formed on the bottom surface of the trench. A method for manufacturing a semiconductor device as described in Appendix 1 or 2. (Note 4) Prior to the first film formation step, there is a trench formation step in which trenches are formed in the substrate, The portion of the first coating is the portion that is formed on the bottom surface of the trench, The other portion of the first coating is the portion formed on the side wall surface of the trench. A method for manufacturing a semiconductor device as described in Appendix 1 or 2. (Note 5) The second film formation step is a step of forming the second film by atomic layer deposition. A method for manufacturing a semiconductor device as described in any one of the appendices 1 to 4. (Note 6) The second coating is silicon oxide. A method for manufacturing a semiconductor device as described in any one of the appendices 1 to 5. (Note 7) The second coating has a lower oxygen diffusion coefficient than silicon oxide. A method for manufacturing a semiconductor device as described in any one of the appendices 1 to 5.

[0075] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0076] 1…Semiconductor device, 5…Tender, 5a…Sidewall, 5b…Bottom, 10…Substrate, 12…Layer, 30, 130…Insulating film (4th film), 50…Silicone film (1st film), 60, 160…Barrier film (2nd film), 80, 180…1st acidified film (3rd film), S30…Tender formation process, S40…1st film formation process, S5 0, S150…Second film formation process, S53, S152…Film forming process, S60…First acidification process, S70, S170…Eating process, S80…Second acidification process (acidification film forming process), S180…Acidification film forming process, T1, T2, T3, T4, T6, T7, TA, T5a, T5b, TCa, TCb…Film thickness

Claims

1. A first film formation step in which a first film made of silicon is formed on the surface of a substrate made of silicon carbide, A second film formation step of forming a second film on the surface of the first film, The process includes an oxidation step of thermally oxidizing the first coating from the surface side to form a third coating, In the second film formation step, On a portion of the first coating, the second coating is not formed and that portion is exposed. Alternatively, the thickness of the second coating formed on the portion of the first coating is smaller than the thickness of the second coating formed on the other portion. A method for manufacturing a semiconductor device.

2. An etching step of etching the second coating and at least a portion of the third coating, The process includes an oxide film forming step of forming a fourth film made of silicon oxide on the surface of the substrate, A method for manufacturing a semiconductor device according to claim 1.

3. Prior to the first film formation step, there is a trench formation step in which trenches are formed in the substrate, The portion of the first coating is the portion that is formed on the side wall surface of the trench, The other portion of the first coating is the portion formed on the bottom surface of the trench. A method for manufacturing a semiconductor device according to claim 1.

4. Prior to the first film formation step, there is a trench formation step in which trenches are formed in the substrate, The portion of the first coating is the portion that is formed on the bottom surface of the trench, The other portion of the first coating is the portion formed on the side wall surface of the trench. A method for manufacturing a semiconductor device according to claim 1.

5. The second film formation step is a step of forming the second film by atomic layer deposition. A method for manufacturing a semiconductor device according to any one of claims 1 to 4.

6. The second coating is silicon oxide. A method for manufacturing a semiconductor device according to any one of claims 1 to 4.

7. The second coating has a lower oxygen diffusion coefficient than silicon oxide. A method for manufacturing a semiconductor device according to any one of claims 1 to 4.

Images