Signal processing circuit and light detection device

Abstract

In a signal processing circuit 21, an input terminal 22 is configured to accept input of an analog signal output from an avalanche photodiode 11 operating in a Geiger mode. A comparison circuit 23 outputs a signal based on a component that exceeds a threshold, among components contained in a signal input to the comparison circuit 23. An adjusting circuit 25 includes an AC coupling unit 42, a level shifter unit 43, and a reference value adjusting unit 44. The AC coupling unit 42 performs AC coupling of the input terminal 22 and the comparison circuit 23. The level shifter unit 43 adjusts a voltage of the signal input to the comparison circuit 23 to a value lower than a reverse bias voltage applied to the avalanche photodiode 11. The reference value adjusting unit 44 adjusts a reference value of the signal input to the comparison circuit 23.

Description

[Technical Field]

[0001] This invention relates to a signal processing circuit and a light detection device. [Background technology]

[0002] A photodetector is known in which an avalanche photodiode operating in Geiger mode is connected to a signal processing circuit (for example, Patent Document 1). In Patent Document 1, the signal processing circuit includes a pre-stage circuit that receives light with the avalanche photodiode and a post-stage circuit that processes the signal output from the pre-stage circuit. The pre-stage circuit includes an AC coupling section. The AC coupling section is provided between the avalanche photodiode and the post-stage circuit, and the avalanche photodiode and the post-stage circuit are AC coupled. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2017-538281 [Overview of the project] [Problems that the invention aims to solve]

[0004] It is conceivable to install a comparator circuit between the AC coupling section and the subsequent circuit to remove noise components from the signal from the avalanche photodiode. The comparator circuit is, for example, a circuit element such as a comparator and an inverter, which outputs a signal based on the components in the input signal that exceed a threshold. As a result, noise components are removed. In such a configuration, in order to improve the accuracy of light detection by the avalanche photodiode, it is necessary to further improve the signal transmission speed to the subsequent circuit.

[0005] Each aspect of the present invention aims to provide a signal processing circuit and an optical detection device that can improve the signal transmission speed to a subsequent circuit while ensuring the accuracy of noise reduction. [Means for solving the problem]

[0006] The inventors of this application have arrived at a configuration that includes an AC coupling section and a level shifter section in order to further improve the signal transmission speed to the subsequent circuit. With this configuration, the parasitic capacitance between the avalanche photodiode and the comparator circuit is reduced in the AC coupling section, and the change in the signal output from the avalanche photodiode is accelerated. In other words, quenching is accelerated. The level shifter section adjusts the voltage of the signal input to the comparator circuit to a value lower than the voltage applied to the avalanche photodiode between the AC coupling section and the comparator circuit. With a configuration including such an AC coupling section and a level shifter section, the acceleration of quenching and the reduction in the voltage of the signal input to the comparator circuit combine to dramatically improve the signal transmission speed to the subsequent circuit. Furthermore, a relatively higher voltage can be secured on the avalanche photodiode side than in the AC coupling section, while the voltage can be set lower on the subsequent circuit side than in the AC coupling section.

[0007] If a relatively high voltage is secured on the avalanche photodiode side compared to the AC coupling point, the photon detection efficiency in the avalanche photodiode can be ensured. If the voltage is set lower on the downstream circuit side compared to the AC coupling point, circuit elements that can operate with a relatively low power supply voltage can be used in the downstream circuit. If the power supply voltage used to operate the circuit elements is suppressed, the power consumption in the downstream circuit can be significantly reduced. The lower the power supply voltage used to operate the circuit elements, the smaller the size of the circuit elements can be, and the lower the parasitic capacitance in the circuit elements can be. If the size of the circuit elements in the downstream circuit is reduced, the overall size of the signal processing circuit can also be reduced. If the parasitic capacitance in the circuit elements is reduced, the power consumption in the downstream circuit can be further suppressed, and the input / output response speed in the downstream circuit can be further improved. For example, when a metal oxide-semiconductor field effect transistor (MOSFET) is used as a circuit element, the lower the power supply voltage of the MOSFET, the smaller the gate length of the MOSFET can be. If the gate length of the MOSFET is reduced, the parasitic capacitance in the downstream circuit can be reduced.

[0008] However, the inventor of the present application has encountered the problem related to signal noise removal in the comparison circuit in the configuration where an AC coupling section and a level shifter section are provided. The threshold in the comparison circuit may vary. The resistance values of the level shifter section and the comparison circuit may also vary. Such variations in the threshold and the resistance value may occur, for example, in the manufacturing process. If the resistance values of the level shifter section and the comparison circuit are different, the reference value of the signal input to the comparison circuit is also different. Therefore, both the threshold in the comparison circuit and the reference value of the signal input to the comparison circuit may vary. For this reason, noise removal is difficult, and it is difficult to ensure the accuracy of noise removal. In consideration of such a problem, the inventor of the present application, as a result of further intensive research, has found a new circuit configuration as a regulation circuit that regulates the signal input to the comparison circuit. This regulation circuit includes an AC coupling section, a level shifter section, and a reference value regulation section. The reference value regulation section regulates the reference value of the signal input to the comparison circuit. If the reference value of the signal input to the comparison circuit is regulated according to the variation of the threshold of the comparison circuit, the accuracy of noise removal can be ensured.

[0009] In one embodiment of the present invention, a signal processing circuit comprises an input terminal, a comparison circuit, a regulation circuit, and a post-stage circuit. The input terminal is configured to receive an analog signal output from an avalanche photodiode operating in Geiger mode. The comparison circuit removes a noise component from the signal input to the input terminal by comparing information related to the signal input to the input terminal with a threshold. The regulation circuit regulates the signal input to the comparison circuit. The post-stage circuit processes the signal output from the comparison circuit. The comparison circuit outputs a signal based on a component exceeding the threshold among the components included in the signal input to the comparison circuit. The regulation circuit includes an AC coupling section, a level shifter section, and a reference value regulation section. The AC coupling section AC-couples the input terminal and the comparison circuit. The level shifter section, arranged between the AC coupling section and the comparison circuit, regulates the voltage of the signal input to the comparison circuit to a value lower than the reverse bias voltage applied to the avalanche photodiode. The reference value regulation section regulates the reference value of the signal input to the comparison circuit.

[0010] In one aspect described above, the signal processing circuit comprises an adjustment circuit that adjusts a signal input to the comparison circuit. The adjustment circuit includes an AC coupling section, a level shifter section, and a reference value adjustment section. According to this configuration, while the transmission speed of the signal to the subsequent-stage circuit is significantly improved, the accuracy of noise removal can also be ensured by adjusting the reference value according to the threshold of the comparison circuit.

[0011] In one aspect described above, the reference value adjustment section may include a circuit element and a terminal electrically connected to the comparison circuit through the circuit element. The circuit element has a resistance component. The circuit element may include a variable resistance section configured to be capable of changing the resistance value of the resistance component of the circuit element. In this case, the reference value of the signal input to the comparison circuit can be easily adjusted by changing the resistance value in the variable resistance section.

[0012] In one aspect described above, the signal processing circuit may further comprise a control section. The control section may be electrically connected to the variable resistance section. The control section may control the resistance value between said terminal and the comparison circuit. In this case, the reference value of the signal input to the comparison circuit can be easily controlled.

[0013] In one aspect described above, said variable resistance section may include an FET or an IGBT. The control section includes a bandgap reference circuit, and may control the voltage applied to the gate of the FET or IGBT based on the bandgap reference circuit. In this case, since the bandgap reference circuit can output a voltage independent of temperature, the reference value of the signal input to the comparison circuit can be controlled more accurately.

[0014] In one aspect described above, said variable resistance section may include a MOSFET. The MOSFET may connect said terminal to the comparison circuit. The source of the MOSFET may be coupled to the comparison circuit. In this case, the reference value of the signal input to the comparison circuit can be adjusted more easily.

[0015] In one embodiment described above, the reference value adjustment unit may include first and second circuit elements, a first terminal, and a second terminal. The first and second circuit elements each have a resistive component. A first potential may be applied to the first terminal. The first terminal may be electrically connected to a comparator circuit through the first circuit element. A second potential lower than the first potential may be applied to the second terminal. The second terminal may be electrically connected to a comparator circuit through the second circuit element. At least one of the first and second circuit elements may include a variable resistor section that corresponds to the circuit element and is configured to change the resistance value of the resistive component of the at least one of them. In this case, changing the resistance value in the variable resistor section can improve the adjustment range of the reference value of the signal input to the comparator circuit.

[0016] In one embodiment described above, the first circuit element may include an N-channel type first MOSFET as a variable resistor. The second circuit element may include a P-channel type second MOSFET as a variable resistor. The sources of both the first and second MOSFETs may be connected to a comparator circuit. In this case, the reference value of the signal input to the comparator circuit can be easily and accurately controlled.

[0017] In one embodiment described above, the AC coupling section may include a capacitor. The level shifter section may include a circuit element having a resistive component and a terminal to which a voltage lower than the reverse bias voltage is applied. The terminal of the level shifter section may be electrically connected to the capacitor and the comparator circuit through the circuit element of the level shifter section. In this case, the voltage of the signal input to the comparator circuit can be easily adjusted to a value lower than the reverse bias voltage applied to the avalanche photodiode.

[0018] In one of the above embodiments, the comparator circuit may include an inverter. In this case, the signal transmission speed to the subsequent circuit can be further improved compared to when a comparator with a more complex structure is used.

[0019] In one embodiment described above, the signal processing circuit may further include at least one of an active quenching circuit and an active recharge circuit. The active quenching circuit performs active quenching on the avalanche photodiode based on a signal from the downstream circuit. The active recharge circuit performs active recharging on the avalanche photodiode based on a signal from the downstream circuit. In this case, the time required for quenching and recharging is further reduced by the synergistic effect of at least one of the active quenching circuit and the active recharge circuit and the adjustment circuit. Furthermore, while ensuring the photon detection efficiency in the avalanche photodiode, circuit elements with relatively low voltage withstand voltage can be used in the downstream circuit.

[0020] A photodetector in another aspect of the present invention comprises the above-mentioned signal processing circuit, an avalanche photodiode, and a quenching resistor electrically connected to the avalanche photodiode. The AC coupling unit AC-couples the avalanche photodiode and the quenching resistor with a comparator circuit.

[0021] In the above alternative embodiment, the signal transmission speed to the subsequent circuit is significantly improved, while the accuracy of noise reduction can also be ensured by adjusting the reference value according to the threshold of the comparison circuit. As a result, the detection accuracy of light incident on the avalanche photodiode can be further improved. [Effects of the Invention]

[0022] Each aspect of the present invention can provide a signal processing circuit and an optical detection device that can improve the signal transmission speed to a subsequent circuit while ensuring the accuracy of noise reduction. [Brief explanation of the drawing]

[0023] [Figure 1] This is a schematic perspective view showing an example of a light detection device according to one embodiment. [Figure 2] This is an exploded perspective view showing an example of a light detection device. [Figure 3]This is a schematic circuit diagram of a part of the light detection device. [Figure 4] This is a schematic circuit diagram of a part of the light detection device. [Figure 5] This is a schematic circuit diagram of a part of the photodetector in a modified example of this embodiment. [Figure 6] This is a schematic circuit diagram of a part of the photodetector in a modified example of this embodiment. [Figure 7] This is a schematic circuit diagram of a part of the photodetector in a modified example of this embodiment. [Figure 8] This is a schematic circuit diagram of a part of the photodetector in a modified example of this embodiment. [Figure 9] This is a schematic circuit diagram of a part of the photodetector in a modified example of this embodiment. [Figure 10] This is a diagram illustrating the signal transformation in the comparative example. [Figure 11] This is a diagram illustrating the signal conversion in this embodiment. [Figure 12] This is a diagram to explain noise reduction. [Figure 13] This is a schematic circuit diagram of a part of the photodetector in a modified example of this embodiment. [Figure 14] This is a schematic circuit diagram of a part of the photodetector in a modified example of this embodiment. [Figure 15] This diagram illustrates the signals input to the comparator circuit in a modified example. [Modes for carrying out the invention]

[0024] Embodiments of the present invention will be described in detail below with reference to the attached drawings. In this description, the same reference numerals will be used for elements that are the same or have the same function, and redundant explanations will be omitted.

[0025] First, the configuration of the photodetector in this embodiment will be described with reference to Figures 1 and 2. Figure 1 is a schematic perspective view showing an example of the photodetector according to this embodiment. Figure 2 is an exploded perspective view of the example of the photodetector shown in Figure 1.

[0026] The light detection device 1 detects light incident on the avalanche photodiode. Hereafter, the avalanche photodiode will be referred to as "APD". Below, the light detection device 1 will be described as a back-side incident light detection device, but the light detection device 1 may also be a front-side incident light detection device.

[0027] As shown in Figures 1 and 2, the light detection device 1 comprises a light-receiving substrate 10, a circuit board 20, and a glass substrate 30. The circuit board 20 faces the light-receiving substrate 10. The glass substrate 30 faces the light-receiving substrate 10. The light-receiving substrate 10 is positioned between the circuit board 20 and the glass substrate 30. In this embodiment, the planes parallel to the main surfaces of the light-receiving substrate 10, the circuit board 20, and the glass substrate 30 are the XY axis planes, and the direction perpendicular to each main surface is the Z axis direction. In the configuration shown in Figures 1 and 2, the light-receiving substrate 10 and the circuit board 20 are stacked in the Z axis direction.

[0028] The light-receiving substrate 10 is, for example, a semiconductor substrate that has a rectangular shape in plan view. The light-receiving substrate 10 has two opposing main surfaces 1Na and 1Nb. Main surface 1Na corresponds to the light incident surface of the light-receiving substrate 10.

[0029] The light-receiving substrate 10 has at least one pixel U, as shown in Figure 2. The light detection device 1 detects light incident on the pixel U. For example, the light-receiving substrate 10 has multiple pixels U. The multiple pixels U are arranged in a matrix in a two-dimensional arrangement on the light-receiving substrate 10, for example. The light-receiving substrate 10 outputs a signal from each pixel U. The light detection device 1 detects the light incident on each pixel U based on the signal output from each pixel U. The multiple pixels U are arranged in the X-axis direction and the Y-axis direction.

[0030] The glass substrate 30 has two opposing main surfaces 30a and 30b. The glass substrate 30 has a rectangular shape in plan view. Main surface 30b faces the main surface 1Na of the light-receiving substrate 10. Main surfaces 30a and 30b are flat. The glass substrate 30 and the light-receiving substrate 10 are optically connected by an optical adhesive OA. The glass substrate 30 may be formed directly on the light-receiving substrate 10.

[0031] The circuit board 20 has two opposing main surfaces 20a and 20b. The circuit board 20 has a rectangular shape in plan view. The light receiving substrate 10 is connected to the circuit board 20. The main surfaces 20a and 1Nb face each other.

[0032] The circuit board 20 has at least one signal processing circuit 21, as shown in Figure 2. The signal processing circuit 21 reads the signal output from the pixel U. The signal processing circuit 21 is electrically connected to the pixel U of the light receiving substrate 10. The signal processing circuit 21 is electrically connected to the pixel U, for example, through a bump electrode BE. For example, the circuit board 20 has a plurality of signal processing circuits 21. For example, the plurality of signal processing circuits 21 are arranged in a two-dimensional array on the main surface 20a side of the circuit board 20. For example, the signal processing circuit 21 and the pixel U are electrically connected in a one-to-one relationship by a bump electrode BE. In a modified example of this embodiment, the signal processing circuit 21 and the pixel U may be electrically connected to each other through pad electrodes provided on the light receiving substrate 10 and the circuit board 20, respectively, without going through a bump electrode BE. In this specification, "electrically connected" includes cases where they are electrically connected through other elements.

[0033] Next, the circuit configuration of the photodetector will be described with reference to Figure 3. Figure 3 is a schematic circuit diagram of a part of the photodetector. The photodetector 1 comprises an APD 11, a quenching resistor 12, a bump electrode BE, and a signal processing circuit 21. The light-receiving substrate 10 comprises an APD 11 and a quenching resistor 12. The aforementioned pixel U is composed of an APD 11 and a quenching resistor 12. Each pixel U is composed of one APD 11 and one quenching resistor 12. For example, the APD 11 and the signal processing circuit 21 are electrically connected to each other in a one-to-one relationship.

[0034] The APD11 is configured to operate in Geiger mode. The APD11 forms a light-receiving area for each pixel U that detects light. The quenching resistor 12 is electrically connected in series with the APD11. The quenching resistor 12 is composed of, for example, a passive element. In the configuration shown in Figure 3, the quenching resistor 12 is coupled to the cathode of the APD11. In this specification, “coupled” does not include connections via elements other than wiring among the elements described herein, but does not exclude connections via elements not described herein.

[0035] The photodetector 1 further includes terminals 13, 14, and 15. In the configuration shown in Figure 3, terminal 13 is connected to the anode of the APD 11. In this configuration, terminal 14 is connected to the cathode of the APD 11 and the quenching resistor 12. Terminal 15 is connected to the quenching resistor 12 and is electrically connected to terminal 14 via the quenching resistor 12. In this configuration, a higher voltage is applied to terminal 15 than to terminal 13. As a result, a reverse bias voltage is applied to the APD 11 that causes it to break down. For example, terminal 13 is connected to ground and a voltage greater than or equal to the breakdown voltage is applied to terminal 15. In this embodiment, the voltage applied to terminal 15 corresponds to the reverse bias voltage. For example, the voltage applied to terminal 15 is 40V or higher. For example, if the breakdown voltage of the APD 11 is 40V, the excess bias is 10V, and the voltage applied to terminal 15 is 50V.

[0036] As a modification of this embodiment, the quenching resistor 12 may be connected to the anode of the APD11. In this case, terminal 13 is connected to the cathode of the APD11. In this case, terminal 14 is connected to the anode of the APD11 and the quenching resistor 12. In this configuration, a lower voltage is applied to terminal 15 than to terminal 13. As a result, a reverse bias voltage is applied to the APD11 that causes it to break down. In this modification, for example, terminal 13 is connected to ground, and the voltage applied to terminal 15 is -40V or less. For example, if the breakdown voltage of the APD11 is 40V, the excess bias is 10V, and the voltage applied to terminal 15 is -50V.

[0037] The signal processing circuit 21 is electrically connected in series with the APD 11 and the quenching resistor 12. In the configuration shown in Figure 3, the signal processing circuit 21 is electrically connected to terminal 14 through bump electrode BE. The signal processing circuit 21 includes an input terminal 22, a comparison circuit 23, an adjustment circuit 25, and a control unit 26. In the signal processing circuit 21, for example, the input terminal 22, the comparison circuit 23, and the adjustment circuit 25 constitute a pre-stage circuit. The signal processing circuit 21 further includes a post-stage circuit 24 that processes the signal output from the pre-stage circuit.

[0038] The input terminal 22 is electrically connected to the corresponding pixel U among multiple pixels U. The input terminal 22 is connected to terminal 14, and through terminal 14, is electrically connected to the APD 11 and the quenching resistor 12. In the configuration shown in Figure 3, the input terminal 22 is a pad electrode connected to the bump electrode BE. The signal output from the APD 11 is input to the input terminal 22 in response to the incidence of light on the APD 11. The APD 11 outputs an analog signal in response to the incidence of light. The analog signal output from the APD 11 is input to the input terminal 22.

[0039] The comparison circuit 23 removes noise components from the input signal by comparing information about the input signal with a threshold value. The comparison circuit 23 compares information about the signal input to input terminal 22 with a threshold value and removes noise components related to the signal input to input terminal 22 through this comparison. The comparison circuit 23 outputs a signal based on the components of the signal input to the comparison circuit 23 that exceed the threshold value. The comparison circuit 23 outputs only the components of the signal input to the comparison circuit 23 that exceed the threshold value. The threshold value of the comparison circuit 23 is set to remove components other than those indicating the incidence of light on the APD 11. For example, the threshold value of the comparison circuit 23 is a predetermined value. For example, the threshold value of the comparison circuit 23 is a value determined in the manufacturing process and is an intrinsic value of the comparison circuit 23.

[0040] In this specification, "exceeding the threshold" includes not only cases where the value transitions to a value greater than the threshold, but also cases where the value transitions to a value less than the threshold. In the configuration shown in Figure 3, the comparator circuit 23 outputs a signal based on the component in the signal input to the comparator circuit 23 that transitions to a value less than the threshold.

[0041] The comparator circuit 23 receives an analog signal based on the signal output from the APD 11 via the input terminal 22. The comparator circuit 23 also receives a signal indicating the voltage fluctuation applied to terminal 14. The input to the comparator circuit 23 is a voltage corresponding to the voltage applied to terminal 14.

[0042] The comparator circuit 23 is configured to output a digital signal corresponding to the value of the input analog signal. The comparator circuit 23 outputs a digital signal based on the signal output from the APD 11. The digital signal output from the comparator circuit 23 is, for example, a HighLow signal indicating the timing of light incidence on the APD 11.

[0043] The comparator circuit 23 includes, for example, an inverter 41. The inverter 41 is a so-called NOT gate. A voltage corresponding to the voltage applied to electrode 51b of capacitor 51 (described later) is applied to the input of inverter 41. In other words, a voltage corresponding to the voltage applied to terminal 57 is applied to the input of inverter 41. When a voltage exceeding a threshold is input, inverter 41 outputs a predetermined voltage. The output of inverter 41 is, for example, Low when a voltage greater than the threshold is input, and High when a voltage less than the threshold is input. The threshold of inverter 41 is determined internally. For example, the threshold of inverter 41 is determined by a circuit element provided inside inverter 41. The threshold of inverter 41 is determined by, for example, a transistor configured inside inverter 41. The comparator circuit 23 does not necessarily have to include a comparator whose threshold is determined by a voltage applied from outside the comparator circuit 23; the comparator circuit 23 may consist only of inverter 41. The comparator described above consists of an analog circuit that includes an amplifier internally, while the inverter 41 consists of an analog circuit that does not include an amplifier. For example, the inverter 41 is composed of a switch circuit that includes a transistor such as a MOSFET. The inverter 41 may also be composed of, for example, a CMOS (Complementary MOS) circuit.

[0044] The subsequent circuit 24 processes the signal output from the comparator circuit 23. The subsequent circuit 24 processes, for example, the digital signal output from the comparator circuit 23. The subsequent circuit 24 performs, for example, at least one of the following: reading the signal output from the comparator circuit 23, controlling other circuits in the signal processing circuit 21, and detecting light incident on the APD 11. The subsequent circuit 24 controls other circuits in the signal processing circuit 21 based on the signal output from the comparator circuit 23. The subsequent circuit 24 performs, for example, detecting light incident on the APD 11 based on the signal output from the comparator circuit 23. The comparator circuit 23 and the subsequent circuit 24 are configured, for example, by an ASIC (Application Specific Integrated Circuit). In a modified example of this embodiment, the comparator circuit 23 and the subsequent circuit 24 may be configured by an FPGA (Field Programmable Gate Array).

[0045] The adjustment circuit 25 adjusts the signal input to the comparison circuit 23. The adjustment circuit 25 is located between the input terminal 22 and the comparison circuit 23. The signal input to the input terminal 22 is input to the comparison circuit 23 via the adjustment circuit 25. The adjustment circuit 25 includes an AC coupling unit 42, a level shifter unit 43, and a reference value adjustment unit 44.

[0046] The AC coupling section 42 AC-couples the input terminal 22 and the comparison circuit 23. The AC coupling section 42 AC-couples the terminal 14 and the comparison circuit 23. The AC coupling section 42 AC-couples the APD 11 and the quenching resistor 12 and the comparison circuit 23. The AC coupling section 42 includes a capacitor 51.

[0047] Capacitor 51 includes electrodes 51a and 51b that are insulated from each other. Electrode 51a is connected to input terminal 22. Electrode 51a is electrically connected to terminal 14 through input terminal 22 and bump electrode BE. Electrode 51a is electrically connected to the input of comparator circuit 23. Capacitor 51 is electrically connected in series with APD 11 and quenching resistor 12, and is also electrically connected in series with inverter 41 of comparator circuit 23.

[0048] The level shifter unit 43 sets the voltage of the signal input to the comparator circuit 23 to a predetermined value. Between the AC coupling unit 42 and the comparator circuit 23, the level shifter unit 43 adjusts the voltage of the signal input to the comparator circuit 23 to a value lower than the reverse bias voltage applied to the APD 11. The level shifter unit 43 includes a circuit element 52 and terminals 53 and 54.

[0049] Circuit element 52 has a resistive component. In the configuration shown in Figure 3, circuit element 52 includes a resistive element 61. The resistive element 61 is a passive element. The resistive element 61 includes, for example, a polysilicon resistor. Terminal 53 is connected to the electrode 51b of the capacitor 51 and the resistive element 61. The resistive element 61 is electrically connected in series with the capacitor 51 of the AC coupling section 42 through terminal 53. The resistive element 61 is electrically connected in series with the inverter 41 of the comparator circuit 23 through terminal 53. Terminal 54 is electrically connected to terminal 53 through the resistive element 61. Terminal 54 is electrically connected to the electrode 51a of the capacitor 51 and the inverter 41 of the comparator circuit 23 through circuit element 52.

[0050] A voltage lower than the reverse bias voltage is applied to terminal 54. In the configuration shown in Figure 3, a voltage higher than the threshold voltage of the comparator circuit 23 is applied to terminal 54. When the output of the comparator circuit 23 is High, terminal 54 is configured such that the voltage of the output of the comparator circuit 23 is equivalent to the voltage applied to terminal 54. The voltage applied to terminal 54 is, for example, 1.8V.

[0051] The reference value adjustment unit 44 adjusts the reference value of the signal input to the comparison circuit 23. The signal input to the comparison circuit 23 is an analog signal. The "reference value" is the reference value of the amplitude in the analog signal. For example, the reference value is the center value or lower limit of the amplitude. The signal input to the comparison circuit 23 fluctuates with respect to the reference value set by the reference value adjustment unit 44. The reference value adjustment unit 44 includes at least one of the circuit elements 55 and 56. In this embodiment, the reference value adjustment unit 44 includes both the circuit element 55 and the circuit element 56. The case in which the reference value adjustment unit 44 includes both the circuit element 55 and the circuit element 56 will be described below. In this embodiment, the reference value adjustment unit 44 further includes terminals 57, 58, and 59. If the circuit element 55 corresponds to the first circuit element, then the circuit element 56 corresponds to the second circuit element. If terminal 58 corresponds to the first terminal, then terminal 59 corresponds to the second terminal.

[0052] Circuit elements 55 and 56 each have a resistive component. At least one of circuit elements 55 and 56 includes a variable resistor configured to change the resistance value of the resistive component of that at least one. Terminal 57 connects circuit elements 55 and 56 to the comparator circuit 23. Terminal 58 is electrically connected to the input of the comparator circuit 23 through circuit elements 55 and terminal 57. Terminal 59 is electrically connected to the input of the comparator circuit 23 through circuit elements 56 and terminal 57. A first potential is applied to terminal 58. A second potential, lower than the first potential, is applied to terminal 59. The voltage applied to terminal 58 is, for example, 1.8V. Terminal 59 is connected to ground, for example.

[0053] For example, at least one of circuit element 55 and circuit element 56 includes, for example, a transistor 62 or a transistor 63 as a variable resistor. Circuit element 55 includes transistor 62, and circuit element 56 includes transistor 63. Transistor 62 connects terminal 58 to the comparison circuit 23. Transistor 63 connects terminal 59 to the comparison circuit 23. In this embodiment, transistors 62 and 63 are field-effect transistors (FETs). In the configuration shown in Figure 3, transistor 62 is an N-channel FET, and transistor 63 is a P-channel FET.

[0054] As a variation of this embodiment, transistors 62 and 63 may be bipolar junction transistors (BJTs) or insulated gate bipolar transistors (IGBTs).

[0055] In this embodiment, transistors 62 and 63 are metal-oxide-semiconductor FETs (MOSFETs). As a modification of this embodiment, transistors 62 and 63 may be junction FETs (JFETs).

[0056] The control unit 26 controls the reference value of the signal input to the comparison circuit 23 by controlling the reference value adjustment unit 44. As shown in Figure 4, the control unit 26 is electrically connected to the reference value adjustment unit 44 and controls at least one of the circuit elements 55 and 56. In this embodiment, the light-receiving substrate 10 has a plurality of pixels U, and the control unit 26 controls the reference value of the signal input to the comparison circuit 23 connected to each pixel U. The control unit 26 is electrically connected, for example, to each of the plurality of reference value adjustment units 44, each connected to each of the plurality of pixels U. The control unit 26 controls, for example, the plurality of reference value adjustment units 44, each connected to each of the plurality of pixels U, at once.

[0057] The control unit 26 may be included in the subsequent circuit 24. The control unit 26 is electrically connected to the variable resistor of the reference value adjustment unit 44 and controls the resistance value between terminal 58 or terminal 59 and the comparison circuit 23. For example, if transistors 62 and 63 are FETs or IGBTs, the control unit 26 is electrically connected to the gates of transistors 62 and 63 in the reference value adjustment unit 44. For example, if transistors 62 and 63 are BJTs, the control unit 26 is electrically connected to the bases of transistors 62 and 63 in the reference value adjustment unit 44. The following explanation will mainly use the case where transistors 62 and 63 are MOSFETs as an example.

[0058] In the configuration shown in Figure 3, the sources of both the MOSFETs of transistors 62 and 63 are connected to the comparator circuit 23. Terminal 57 connects the source of the MOSFET of transistor 62, the source of the MOSFET of transistor 63, and the input of the comparator circuit 23 to each other. Terminal 58 is connected to the drain of the MOSFET of transistor 62. Terminal 59 is connected to the drain of the MOSFET of transistor 63. The control unit 26 controls the voltage applied to the gates of the MOSFETs of transistors 62 and 63. For example, if the MOSFET of transistor 62 corresponds to the first MOSFET, then the MOSFET of transistor 63 corresponds to the second MOSFET.

[0059] As a variation of the configuration shown in Figure 3, as shown in Figure 5, transistor 62 may be a P-channel FET and transistor 63 may be an N-channel FET. In this case, terminal 57 connects the drain of the MOSFET of transistor 62, the drain of the MOSFET of transistor 63, and the input of the comparator circuit 23 to each other. Terminal 58 is connected to the source of the MOSFET of transistor 62. Terminal 59 is connected to the source of the MOSFET of transistor 63.

[0060] The control unit 26 is composed of, for example, one or more ASICs. In a modified version of this embodiment, the control unit 26 may be composed of an FPGA.

[0061] In the configuration shown in Figure 4, the control unit 26 includes a bandgap reference circuit 65 and a terminal 66. The bandgap reference circuit 65 outputs a constant voltage that is independent of temperature, based on the voltage applied to terminal 66. When transistors 62 and 63 are FETs or IGBTs, the control unit 26 controls the voltage applied to the gates of the FETs or IGBTs based on the bandgap reference circuit 65. For example, the control unit 26 uses the output of the bandgap reference circuit 65 to adjust the voltage applied to the gates of the FETs or IGBTs of transistors 62 and 63 to compensate for changes in the input to the comparator circuit 23 in response to changes in ambient temperature.

[0062] Next, with reference to Figures 6 to 8, a modified photodetector according to this embodiment will be described. Figures 6 to 8 are schematic circuit diagrams of parts of the photodetector according to this modified embodiment. These modifications are generally similar to or the same as the embodiments described above.

[0063] First, the differences between the embodiment described above and the modified example shown in Figure 6 will be explained. The photodetector 1A shown in Figure 6 differs from the photodetector 1 in the embodiment described above in terms of the configuration of the level shifter section 43. In the photodetector 1A, the level shifter section 43 includes a circuit element 52A instead of the circuit element 52. The circuit element 52A of the level shifter section 43 includes a variable resistor section that can change the resistance value of the resistive component instead of the resistive element 61. In this modified example, the circuit element 52A includes a transistor 71 as the variable resistor section.

[0064] Transistor 71 is, for example, an FET. In the configuration shown in Figure 6, transistor 71 is an N-channel FET. Transistor 71 is a MOSFET. In a further variation of this modification, transistor 71 may be a BJT or an IGBT. Transistor 71 may also be a JFET.

[0065] In this modified example, the resistance value of circuit element 52A is controlled, for example, by the control unit 26. The resistance value of circuit element 52A may be controlled by a control unit other than the control unit 26, or it may be preset by a person. For example, if transistor 71 is an FET or IGBT, the control unit 26 is electrically connected to the gate of transistor 71 of the reference value adjustment unit 44. For example, if transistor 71 is a BJT, the control unit 26 is electrically connected to the bases of transistors 62 and 63 of the reference value adjustment unit 44. The following explanation will mainly use the case where transistors 62 and 63 are MOSFETs as an example.

[0066] In the configuration shown in Figure 6, the source of the MOSFET of transistor 71 is connected to terminal 53. Terminal 53 is connected to the electrode 51b of capacitor 51 and the source of the MOSFET of transistor 71. The drain of the MOSFET of transistor 71 is connected to terminal 54. The control unit 26 is electrically connected to the gate of the MOSFET of transistor 71 and controls the voltage applied to the gate.

[0067] As a further modification of the configuration shown in Figure 6, as shown in Figure 7, transistors 62 and 71 may be P-channel FETs and transistor 63 may be an N-channel FET. In this case, terminal 57 connects the drain of the MOSFET of transistor 62, the drain of the MOSFET of transistor 63, and the input of the comparator circuit 23 to each other. Terminal 58 is connected to the source of the MOSFET of transistor 62. Terminal 59 is connected to the source of the MOSFET of transistor 63. Terminal 53 is connected to the electrode 51b of capacitor 51 and the drain of the MOSFET of transistor 71. Terminal 54 is connected to the source of the MOSFET of transistor 71.

[0068] Next, the differences between the above-described embodiment and the modified examples shown in Figures 8 and 9 will be explained. The photodetector 1B and photodetector 1C shown in Figures 8 and 9 differ from the photodetector 1 in the above-described embodiment in terms of the configuration of the reference value adjustment unit 44.

[0069] In the photodetector 1B shown in Figure 8, the reference value adjustment unit 44 includes circuit element 56B instead of circuit element 56. Circuit element 56B includes a resistor 73 instead of a transistor 63. The resistor 73 is a passive element. The resistor 73 includes, for example, a polysilicon resistor. Terminal 57 is electrically connected to terminal 59 through the resistor 73. In the configuration shown in Figure 8, transistor 62 is an N-channel FET. In the configuration shown in Figure 8, transistor 62 may also be a P-channel FET.

[0070] In the photodetector 1C shown in Figure 9, the reference value adjustment unit 44 includes a circuit element 55C instead of a circuit element 55. The circuit element 55C includes a resistor 75 instead of a transistor 62. The resistor 75 is a passive element. The resistor 75 includes, for example, a polysilicon resistor. Terminal 58 is electrically connected to terminal 57 through the resistor 75. In the configuration shown in Figure 9, the transistor 63 is a P-channel FET. In the configuration shown in Figure 9, the transistor 62 may be an N-channel FET.

[0071] Next, the effects of the photodetectors 1, 1A, 1B, 1C and the signal processing circuit 21 will be explained with reference to Figures 10 to 12. Figure 10 is a diagram illustrating the signal conversion in the comparative example. Figure 11 is a diagram illustrating the signal conversion in the signal processing circuit 21 of the photodetector 1. Figure 12 is a diagram illustrating the noise removal in the signal processing circuit 21 of the photodetector 1.

[0072] When light is incident on APD11, avalanche multiplication occurs in APD11, and current flows between terminals 15 and 13 through APD11. As a result, a voltage drop occurs across quenching resistor 12. Therefore, the voltage at input terminal 22 changes depending on the incidence of light on APD11. overdecreases from the above. The reverse bias voltage applied to APD 11 depends on the voltage at input terminal 22. V over is a value obtained by subtracting the breakdown voltage value of APD 11 from the reverse bias voltage value applied to APD 11. When the voltage at input terminal 22 drops to the minimum value, recharging is started. When recharging is started, the voltage at input terminal 22 also rises.

[0073] Comparison circuit 23 outputs a signal based on components exceeding a threshold among components included in a signal input to comparison circuit 23. The output voltage of comparison circuit 23 is such that when the voltage input to comparison circuit 23 is the threshold voltage V th rises when the voltage falls below, and the voltage input to comparison circuit 23 is the threshold voltage V th falls when the voltage exceeds

[0074] In FIG. 10, data D101 indicates the voltage at input terminal 22 in the comparative example, and data D102 indicates the voltage output from comparison circuit 23 in the comparative example. In the comparative example of FIG. 10, the voltage indicated by data D101 corresponds to the voltage input to comparison circuit 23. In FIG. 10, data D101 starts to change at time T in response to incidence of light on APD 11 101 starts to decrease at, and at time T 102 falls below the threshold voltage V th . Data D102 indicates that when data D101 falls below the threshold voltage V th at time T when it falls below 102 starts to rise at, and when data D101 exceeds the threshold voltage V th at time T when it exceeds 103 starts to fall at. The time from when data D101 starts to decrease until the value of data D101 falls below the threshold voltage V th is the time between time T 102 and time T 101 is the difference between

[0075] In the comparative example shown in Figure 10, the adjustment circuit 25 is removed from the signal processing circuit 21, and the input terminal 22 and the comparison circuit 23 are electrically connected without going through the adjustment circuit 25. The time required for quenching of the APD 11 depends on the product of the resistance value of the quenching resistor 12 and the parasitic capacitance in the signal processing circuit 21. In this comparative example, the parasitic capacitance between the input terminal 22 and the comparison circuit 23 has an effect, and the time required for quenching is relatively long. The time required for quenching corresponds to the time required for the voltage at the input terminal 22 to fall in response to the incidence of light on the APD 11. Therefore, in this modified example, when light is incident on the APD 11, the voltage at the input terminal 22 falls relatively smoothly. For this reason, the value of data D101 decreases from the time data D101 starts to fall until it reaches the threshold V th The time until the value falls below a certain level is relatively long. Thus, in this modified example, the transmission time from when light is incident on the APD11 until the signal indicating the incidence of light on the APD11 is transmitted to the subsequent circuit 24 is relatively long.

[0076] Furthermore, in this comparative example, the voltage output from the comparison circuit 23 rises to the overvoltage value required for the APD11 to operate in Geiger mode. Therefore, the subsequent circuit 24, located after the comparison circuit 23, requires the use of circuit elements with relatively high voltage withstand capabilities. Generally, the larger the size of a circuit element, the higher its voltage withstand capability. For this reason, the size of the subsequent circuit 24 in this comparative example is relatively large.

[0077] In the photodetectors 1, 1A, 1B, and 1C, the signal processing circuit 21 includes an adjustment circuit 25 that adjusts the signal input to the comparison circuit 23. The adjustment circuit 25 includes an AC coupling unit 42, level shifter units 43 and 43A, and reference value adjustment units 44, 44B, and 44C. With this configuration, the parasitic capacitance between the APD 11 and the comparison circuit 23 is reduced in the AC coupling unit 42, and quenching is also accelerated. Therefore, when light is incident on the APD 11, the voltage at the input terminal 22 drops more sharply than in the comparative example. The level shifter unit 43 adjusts the voltage of the signal input to the comparison circuit 23 to a value lower than the reverse bias voltage applied to the APD 11 between the AC coupling unit 42 and the comparison circuit 23.

[0078] In Figure 11, data D1 represents the voltage at the input terminal 22 of the photodetector 1, data D2 represents the voltage input to the comparator circuit 23 of the photodetector 1, and data D3 represents the voltage output from the comparator circuit 23 of the photodetector 1. In Figure 11, data D1 begins to decrease at time T1 in response to the incidence of light on the APD11. Data D2 begins to decrease in response to the change in data D1. At time T2, data D2 reaches a threshold V th It falls below that threshold V. As a result, data D3 is below the threshold V of data D2. th It began to rise at time T2 when it fell below the threshold V, and data D2 reached threshold V th It began to decline at time T3, when it exceeded the limit.

[0079] When data D1 starts to decrease, the value of data D2 reaches the threshold V. th The time until it falls below this value is the difference between time T2 and time T1. The difference between time T2 and time T1 in Figure 11 is the same as the difference between time T1 and time T2 in Figure 10. 101 and time T 102 It is smaller than the difference. Therefore, after data D1 starts to decrease, data D1 reaches the threshold V. th The time until it falls below threshold V is from when data D101 starts to decrease until data D101 reaches threshold V. th It takes less time than it falls below that level.

[0080] Thus, with the signal processing circuit 21 of the photodetectors 1, 1A, 1B, and 1C, the speed of quenching by the AC coupling unit 42 and the reduction of the signal voltage input to the comparison circuit 23 by the level shifter unit 43 combine to significantly improve the signal transmission speed to the subsequent circuit 24.

[0081] According to the AC coupling section 42 and level shifter sections 43, 43A of the photodetectors 1, 1A, 1B, 1C, a relatively high voltage can be secured on the APD11 side than on the AC coupling section 42 side, while the voltage can be set lower on the downstream circuit 24 side than on the AC coupling section 42 side. In Figure 11, the maximum value of data D1 is V over Therefore, the maximum value of data D2 is V over Lower V ini Therefore, the maximum value of the output of the comparison circuit 23 is also reduced. In Figure 11, the maximum value of data D3 is V over Lower V DD As a result, while ensuring the photon detection efficiency in APD11, the subsequent circuit 24 can use circuit elements with a lower withstand voltage than in the comparative example in Figure 10. Generally, the lower the withstand voltage of a circuit element, the smaller the size of the circuit element. The smaller the size of the circuit element, the lower the power consumption of the circuit element. Furthermore, the smaller the size of the circuit element, the lower the parasitic capacitance of the circuit element, and the faster the input / output response of the signal. Therefore, if circuit elements with a relatively low withstand voltage are used in the subsequent circuit 24, the overall size of the subsequent circuit 24 can be reduced, the power consumption of the subsequent circuit 24 can be reduced, and the faster the input / output response of the signal within the subsequent circuit 24 can also be improved.

[0082] In Figure 12, signal component S1 is the component input to the comparator circuit 23 in response to the incidence of light on the APD11, and signal components S2, S3, and S4 are noise components input to the comparator circuit 23. The signal components S1, S2, S3, and S4 input to the comparator circuit 23 are compared to a reference value V base This is a component that fluctuates relative to a reference value. The comparison circuit 23 uses the threshold value V of the signal components S1, S2, S3, S4. thThe circuit outputs a signal based on components exceeding the threshold V. In the state shown in Figure 12, the signal output from the comparison circuit 23 does not include information indicating the input of signal components S2, S3, and S4, but includes information indicating the input of signal component S1. In this case, the subsequent circuit 24 can accurately detect the incidence of light on the APD11. On the other hand, signal components S2, S3, and S4 also exceed the threshold V. th The threshold V exceeds the threshold V. th and reference value V base If this setting is enabled, the signal output from the comparison circuit 23 will also contain noise components. In this case, the accuracy of detecting the incidence of light on the APD 11 in the subsequent circuit 24 will also decrease.

[0083] In the configuration including the AC coupling section 42 and the level shifter sections 43, 43A, the threshold V in the comparison circuit 23 th There is a risk of variation. In a configuration that includes the AC coupling section 42 and the level shifter sections 43, 43A, but does not include the reference value adjustment sections 44, 44B, 44C, there is also a risk of variation in the resistance values ​​of the level shifter section 43 and the comparison circuit 23. The resistance values ​​may vary by about 20%. If the resistance values ​​of the level shifter section 43 and the comparison circuit 23 are different, the reference value V of the signal input to the comparison circuit 23 may vary. base Also different. In a configuration that includes the AC coupling section 42 and the level shifter sections 43, 43A, but does not include the reference value adjustment sections 44, 44B, 44C, the threshold V in the comparison circuit 23 is different. th The reference value V of the signal input to the comparison circuit 23. base There is a risk of variation in both of these factors. Therefore, noise reduction is difficult, and ensuring the accuracy of noise reduction is challenging.

[0084] The signal processing circuit 21 of the light detection devices 1, 1A, 1B, and 1C includes a reference value adjustment unit 44, 44B, and 44C, in addition to the AC coupling unit 42 and the level shifter units 43 and 43A. The reference value adjustment units 44, 44B, and 44C adjust the reference value V of the signal input to the comparison circuit 23. base Adjust the reference value V of the signal input to the comparison circuit 23. base The threshold V of the comparison circuit 23 thIf adjusted according to the variation, the accuracy of noise reduction can be ensured. Therefore, according to the signal processing circuit 21 of the photodetectors 1, 1A, 1B, 1C, the signal transmission speed to the subsequent circuit 24 is significantly improved, while the reference value V according to the threshold of the comparison circuit 23 is maintained. base By adjusting this setting, the accuracy of noise reduction can also be ensured.

[0085] The circuit elements 52 and 52A of the level shifter sections 43 and 43 are polysilicon resistors or MOSFETs. In this case, the same resistance values ​​as the circuit elements 55 and 56 of the reference value adjustment sections 44, 44B, and 44C can be easily achieved, and the ease of manufacturing the signal processing circuit 21 is ensured.

[0086] The reference value adjustment sections 44, 44B, and 44C include circuit elements 55 and 56 and terminals 58 and 59. Each of the circuit elements 55 and 56 has a resistive component. The circuit elements 55 and 56 include a variable resistor section configured to change the resistance value of the resistive component. In this case, the reference value of the signal input to the comparator circuit 23 can be easily adjusted by changing the resistance value in the variable resistor section.

[0087] Furthermore, in the reference value adjustment sections 44, 44B, and 44C, a first potential is applied to terminal 58. Terminal 58 is electrically connected to the comparator circuit 23 through circuit element 55. A second potential lower than the first potential is applied to terminal 59. Terminal 59 is electrically connected to the comparator circuit 23 through circuit element 56. At least one of circuit element 55 and circuit element 56 includes a variable resistor configured to change the resistance value of the resistive component of the at least one of them. When both circuit element 55 and circuit element 56 are provided, the adjustment range of the reference value of the signal input to the comparator circuit 23 can be improved. When both circuit element 55 and circuit element 56 include a variable resistor, the adjustment range of the reference value of the signal input to the comparator circuit 23 can be further improved.

[0088] The control unit 26 is electrically connected to the variable resistors of the reference value adjustment units 44, 44B, and 44C. The control unit 26 controls the resistance value between terminal 58 or terminal 59 and the comparison circuit 23. In this case, the reference value of the signal input to the comparison circuit 23 can be easily controlled.

[0089] At least one of circuit elements 55 and 56 includes a FET or IGBT as a variable resistor. The control unit 26 includes a bandgap reference circuit 65 and controls the voltage applied to the gate of the FET or IGBT based on the bandgap reference circuit 65. In this case, since the bandgap reference circuit 65 can output a voltage independent of temperature, the reference value of the signal input to the comparator circuit 23 can be controlled more accurately. When a FET or IGBT is used for circuit element 55 or circuit element 56, external adjustment is easier than current control because the circuit elements 55 and 56 are controlled by voltage.

[0090] At least one of circuit element 55 and circuit element 56 includes a MOSFET as a variable resistor. The MOSFET connects terminal 58 or terminal 59 to the comparator circuit 23. The source of the MOSFET is connected to the comparator circuit 23. In this case, the reference value of the signal input to the comparator circuit 23 can be adjusted more easily. When a MOSFET is used for circuit element 55 or circuit element 56, the signal processing circuit 21 is easier to manufacture than when an IGBT or JFET is used.

[0091] Circuit element 55 includes an N-channel MOSFET. Circuit element 56 includes a P-channel MOSFET. The sources of both the MOSFETs of circuit element 55 and circuit element 56 are connected to the comparator circuit 23. In this case, the reference value of the signal input to the comparator circuit 23 can be easily and accurately controlled.

[0092] The AC coupling section 42 includes a capacitor 51. The level shifter sections 43 and 43A include circuit elements 52 and 52A having a resistive component and a terminal 54 to which a voltage lower than the reverse bias voltage is applied. The terminal 54 of the level shifter sections 43 and 43A is electrically connected to the capacitor 51 and the comparator circuit 23 through the circuit elements 52 and 52A of the level shifter sections 43 and 43A. In this case, the voltage of the signal input to the comparator circuit 23 can be easily adjusted to a value lower than the reverse bias voltage applied to the APD 11.

[0093] The comparator threshold is determined by the voltage applied from outside the comparison circuit 23, and the threshold V of the inverter 41. th This is determined internally within the inverter 41. The threshold V of the inverter 41 th The noise level varies due to the manufacturing process. In the comparator, the threshold is determined by a voltage applied from outside the comparator circuit 23, so even if the resistance values ​​of the comparator circuit 23 and the level shifter section 43 vary, the noise can be removed by adjusting the threshold. Therefore, the signal output from the comparator is more accurate than the signal output from the inverter 41. On the other hand, since the number of circuit elements constituting the inverter 41 is less than the number of circuit elements constituting the comparator, the signal transmission speed in the inverter 41 is faster than the signal transmission speed in the comparator.

[0094] In the photodetectors 1, 1A, 1B, and 1C, the comparison circuit 23 includes an inverter 41. In this case, the signal transmission speed to the subsequent circuit 24 can be further improved compared to when a comparator with a more complex structure is used. Furthermore, the photodetectors 1, 1A, 1B, and 1C include reference value adjustment units 44, 44B, and 44C. Therefore, the reference value V is adjusted by the reference value adjustment units 44, 44B, and 44C. base By adjusting the threshold V of inverter 41, th Noise caused by this can also be removed.

[0095] Next, with reference to Figure 13, a modified photodetector according to this embodiment will be described. Figure 13 is a schematic circuit diagram of a part of the photodetector according to this modified embodiment. This modified version is generally similar to or the same as the embodiment described above. The photodetector 1D in this modified version differs from the photodetector 1 in the embodiment described above in that the signal processing circuit 21 is configured to perform active recharging and active quenching. The differences between the embodiment described above and the modified version will be mainly described below.

[0096] The photodetector 1D further comprises at least one of an active quenching circuit 27 and an active recharge circuit 28. In the configuration shown in Figure 13, the photodetector 1D comprises both the active quenching circuit 27 and the active recharge circuit 28. The active quenching circuit 27 and the active recharge circuit 28 are electrically connected to a downstream circuit 24 and are controlled based on signals from the downstream circuit 24. In other words, the downstream circuit 24 controls at least one of the active quenching circuit 27 and the active recharge circuit 28. The active quenching circuit 27 quenches the APD 11 based on signals from the downstream circuit 24. The active recharge circuit 28 recharges the APD 11 based on signals from the downstream circuit 24. The active quenching circuit 27 and the active recharge circuit 28 are provided, for example, on a circuit board 20.

[0097] The active quenching circuit 27 includes a circuit element 81, terminals 82 and 83. The circuit element 81 switches the conduction state between terminals 82 and 83 based on a signal from the subsequent circuit 24. Terminal 83 is connected to the input terminal 22 and the AC coupling unit 42. Terminal 83 is connected to the input terminal 22 and the electrode 51a of the capacitor 51. The input terminal 22 is electrically connected to the electrode 51a through terminal 83.

[0098] The circuit element 81 includes a transistor 91. Transistor 91 connects terminals 82 and 83. In this modified example, transistor 91 is an FET. In the configuration shown in Figure 13, transistor 91 is an N-channel FET. In this modified example, transistor 91 is a MOSFET. As a further modification of this modification, transistor 91 may be a BJT or an IGBT. Transistor 91 may also be a JFET. The following explanation will mainly use the case where transistor 91 is a MOSFET as an example.

[0099] The source of the MOSFET of transistor 91 is connected to terminal 82. The drain of the MOSFET of transistor 91 is connected to terminal 83. The gate of the MOSFET of transistor 91 is electrically connected to the subsequent circuit 24 without passing through the delay circuit 86. A voltage lower than the voltage applied to terminal 15 is applied to terminal 82. A voltage equivalent to, for example, the voltage applied to terminal 13 is applied to terminal 82. Terminal 82 is connected to, for example, ground.

[0100] The active recharge circuit 28 includes a circuit element 84, terminals 85 and 83, and a delay circuit 86. The circuit element 84 switches the conduction state between terminals 85 and 83 based on a signal from the downstream circuit 24.

[0101] Circuit element 84 includes a transistor 92. Transistor 92 connects terminals 85 and 83. In this modified example, transistor 92 is an FET. In the configuration shown in Figure 13, transistor 92 is a P-channel FET. In this modified example, transistor 91 is a MOSFET. As a further modification of this modification, transistor 92 may be a BJT or an IGBT. Transistor 92 may also be a JFET. The following explanation will mainly use the case where transistor 92 is a MOSFET as an example.

[0102] The source of the MOSFET of transistor 92 is connected to terminal 85. The drain of the MOSFET of transistor 92 is connected to terminal 83. The gate of the MOSFET of transistor 92 is electrically connected to the downstream circuit 24 through the delay circuit 86. A voltage higher than the voltage applied to terminal 82 is applied to terminal 85. A voltage higher than the voltage applied to terminal 13 is applied to terminal 85. For example, a voltage equivalent to the excess bias is applied to terminal 85. For example, terminals 13 and 82 are connected to ground, and a voltage greater than or equal to the breakdown voltage is applied to terminal 15. For example, the breakdown voltage of APD11 is 40V and the excess bias is 10V. For example, the voltage applied to terminal 15 is 50V and the voltage applied to terminal 85 is 10V.

[0103] The delay circuit 86 is a circuit that delays an input signal by a predetermined time before outputting it. The delay circuit 86 receives the signal output from the subsequent circuit 24. The delay circuit 86 delays the time it takes for the signal output from the subsequent circuit 24 to be transmitted to the circuit element 84.

[0104] In the configuration shown in Figure 13, transistor 62 is an N-channel FET and transistor 63 is a P-channel FET. As a further variation of the configuration shown in Figure 13, as shown in Figure 14, transistor 62 may be a P-channel FET and transistor 63 may be an N-channel FET. In this case, terminal 57 connects the drain of the MOSFET of transistor 62, the drain of the MOSFET of transistor 63, and the input of the comparator circuit 23 to each other. Terminal 58 is connected to the source of the MOSFET of transistor 62. Terminal 59 is connected to the source of the MOSFET of transistor 63.

[0105] Next, with reference to Figure 15, the operation and effects of the photodetector 1D and the signal processing circuit 21 of the photodetector 1D will be explained. Figure 15 is a diagram illustrating the signal input to the comparator circuit in this modified example. In Figure 15, data D4 indicates the voltage input to the comparator circuit 23 of the photodetector 1D. The maximum value of data D4 is V, similar to data D2. ini That is the case.

[0106] The signal processing circuit 21 of the photodetector 1D further comprises at least one of an active quenching circuit 27 and an active recharge circuit 28. As shown in Figure 15, the data D4, which represents the voltage input to the comparator circuit 23 of the photodetector 1D, begins to decrease at time T6 due to quenching by the quenching resistor 12. When the signal output from the comparator circuit 23 is input to the subsequent circuit 24, it outputs signals to the active quenching circuit 27 and the active recharge circuit 28.

[0107] The active quenching circuit 27 performs active quenching on the APD11 based on a signal from the subsequent circuit 24. For example, in the active quenching circuit 27, a voltage is applied to the gate of the MOSFET of transistor 91 by the signal output from the subsequent circuit 24. As a result, the resistance between the drain and source of the MOSFET of transistor 91 decreases, and the voltage at terminal 83 approaches the voltage at terminal 82. In this way, active quenching occurs. Due to this active quenching, the data D4 drops more sharply between time T7 and time T8 than the quenching between time T6 and time T7.

[0108] The active recharge circuit 28 performs active recharging on the APD11 based on a signal from the downstream circuit 24. The signal input to the active recharge circuit 28 from the downstream circuit 24 is delayed by the delay circuit 86. Therefore, the signal output from the downstream circuit 24 reaches the transistor 92 of the active recharge circuit 28 at time T9, a predetermined time after it has reached the transistor 91 of the active quenching circuit 27. For example, in the active recharge circuit 28, a voltage is applied to the gate of the MOSFET of transistor 92 by the signal output from the downstream circuit 24. As a result, the resistance between the drain and source of the MOSFET of transistor 92 decreases, and the voltage at terminal 83 approaches the voltage at terminal 85. In this way, active recharging occurs. Due to this active recharging, data D4 is obtained at time T9 and time T 10 Between these points, the voltage rises more rapidly than when active recharge is not performed. Since the signal processing circuit 21 of the photodetector 1D includes an AC coupling section 42, a voltage equivalent to the voltage applied to terminal 15 can be applied to terminal 85.

[0109] Thus, the synergistic effect of at least one of the active quenching circuit 27 and the active recharge circuit 28 with the adjustment circuit 25 further reduces the time required for quenching and recharging. Furthermore, while ensuring the photon detection efficiency in the APD 11, circuit elements with relatively low voltage tolerances can be used in the subsequent circuit 24. If the recharge speed is improved, the time during which light cannot be detected can be reduced.

[0110] While embodiments and modifications of the present invention have been described above, the present invention is not necessarily limited to the embodiments described above, and various modifications are possible without departing from the spirit of the invention.

[0111] For example, in the above-described embodiment, an example was described in which the light detection device 1 comprises a light-receiving substrate 10 and a circuit board 20 facing each other in the Z-axis direction. However, the light-receiving substrate 10 and the circuit board 20 may be arranged in the XY axis direction. The light-receiving substrate 10 and the circuit board 20 may be formed integrally.

[0112] In the above-described embodiment, an example was explained in which the signal processing circuit 21 and the pixel U are electrically connected to each other through a bump electrode BE. However, the signal processing circuit 21 and the pixel U may be electrically connected to each other without using the bump electrode BE. For example, the signal processing circuit 21 and the pixel U may be electrically connected to each other by bonding of pad electrodes. The signal processing circuit 21 and the pixel U may be electrically connected to each other by wire bonding.

[0113] If the light-receiving substrate 10 and the circuit board 20 are integrally formed, the signal processing circuit 21 and the pixel U may be electrically connected to each other by metal wiring provided within or on the substrate. In this case, the input terminal 22 may be a wire or a connection point of a wire.

[0114] In the embodiment described above, the case in which the light-receiving substrate 10 has a plurality of pixels U arranged in a matrix in two dimensions was explained. The light-receiving substrate 10 may also have a plurality of pixels U arranged in a single row.

[0115] In the embodiments described above, the case in which the light-receiving substrate 10 includes multiple pixels U has been explained. The light-receiving substrate 10 may include only one pixel U. The light-receiving substrate 10 may include only one APD 11. In this case, the circuit board 20 may include only one signal processing circuit 21.

[0116] When the light-receiving substrate 10 has multiple pixels U, the control unit 26 may control the reference value of the signal input to the comparison circuit 23 for each pixel U. In other words, the control unit 26 may control each of the multiple reference value adjustment units 44 connected to each of the multiple pixels U. For example, the control unit 26 may generate a control signal for each comparison circuit 23 connected to the pixel U and control the reference value adjustment unit 44 corresponding to each comparison circuit 23.

[0117] When the light-receiving substrate 10 has multiple pixels U, the control unit 26 may simultaneously control the reference value of the signal input to the comparison circuit 23 connected to each pixel U for all pixels U included in the light-receiving substrate 10. For example, the control unit 26 may simultaneously control all reference value adjustment units 44 connected to each pixel U for all pixels U included in the light-receiving substrate 10.

[0118] The control unit 26 may control the reference value of the signal input to the comparison circuit 23 connected to the pixel U included in each group, for each predetermined group. For example, the control unit 26 may generate a control signal for each group and control a plurality of reference value adjustment units 44 for each predetermined group. In this case, each group may consist of, for example, a plurality of pixels U arranged in the same column or row, and a plurality of adjustment circuits 25 connected to each of these pixels U. Each group may consist of a plurality of adjacent pixels U, and a plurality of adjustment circuits 25 connected to each of these pixels U. Each group may consist of a plurality of adjacent columns, and a plurality of adjustment circuits 25 connected to each of these pixels U. Each group may consist of a plurality of adjacent rows, and a plurality of adjustment circuits 25 connected to each of these pixels U. Each group may consist of a plurality of spaced-apart pixels U, and a plurality of adjustment circuits 25 connected to each of these pixels U.

[0119] The control unit 26 and the subsequent circuit 24 may be formed as a single unit. In this case, the reference value adjustment unit 44 may be controlled based on the signal output from the subsequent circuit 24.

[0120] In the above-described embodiment, an example was explained in which the photodetector 1 includes a glass substrate 30. However, the photodetector 1 does not necessarily have to include a glass substrate 30. In this case, for example, the main surface 1Na of the light-receiving substrate 10 is exposed.

[0121] The above-described modifications may be combined in any way. For example, the active quenching circuit 27 and the active recharge circuit 28 may be provided in the signal processing circuit 21 of the photodetectors 1A, 1B, and 1C. The level shifter section 43A of the photodetector 1A may be provided in the signal processing circuit 21 of the photodetector 1B or the photodetector 1C. [Explanation of Symbols]

[0122] 1, 1A, 1B, 1C, 1D… Light detection device, 12… Quenching resistor, 13, 14, 15, 53, 54, 57, 58, 59, 66, 82, 83, 85… Terminals, 21… Signal processing circuit, 22… Input terminal, 23… Comparison circuit, 24… Subsequent circuit, 25… Adjustment circuit, 26… Control unit, 27… Active quenching circuit, 28… Active recharge circuit, 41… Inverter, 42… AC coupling unit, 43, 43A… Level shifter unit, 44, 44B, 44C… Reference value adjustment unit, 51… Capacitor, 52, 52A, 55, 55C, 56, 56B, 81, 84… Circuit elements, 65… Bandgap reference circuit, V th ...threshold, V base …Reference value.

Claims

1. An input terminal to which an analog signal output from an avalanche photodiode operating in Geiger mode is input, A comparison circuit removes noise components related to the signal input to the input terminal by comparing information about the signal input to the input terminal with a threshold value. An adjustment circuit that adjusts the signal input to the comparison circuit, The system includes a subsequent circuit that processes the signal output from the comparison circuit, The comparison circuit outputs a signal based on the component in the signal input to the comparison circuit that exceeds the threshold. The adjustment circuit described above is An AC coupling unit that AC couples the input terminal and the comparison circuit, Between the AC coupling unit and the comparator circuit, a level shifter unit is provided which adjusts the voltage of the signal input to the comparator circuit to a value lower than the reverse bias voltage applied to the avalanche photodiode. A signal processing circuit including a reference value adjustment unit that adjusts the reference value of the signal input to the comparison circuit.

2. The reference value adjustment unit includes a circuit element having a resistive component and a terminal electrically connected to the comparison circuit through the circuit element. The signal processing circuit according to claim 1, wherein the circuit element includes a variable resistor configured to change the resistance value of the resistive component of the circuit element.

3. The signal processing circuit according to claim 2, further comprising a control unit which is electrically connected to the variable resistor and controls the resistance value between the terminal and the comparison circuit.

4. The variable resistor section includes an FET or an IGBT. The signal processing circuit according to claim 3, wherein the control unit includes a bandgap reference circuit and controls the voltage applied to the gate of the FET or the IGBT based on the bandgap reference circuit.

5. The variable resistor section includes a MOSFET, The MOSFET connects the terminals to the comparison circuit. The signal processing circuit according to claim 2, wherein the source of the MOSFET is connected to the comparator circuit.

6. The aforementioned reference value adjustment unit includes first and second circuit elements, each having a resistive component. The terminal includes a first terminal to which a first potential is applied and which is electrically connected to the comparison circuit through the first circuit element, and a second terminal to which a second potential lower than the first potential is applied and which is electrically connected to the comparison circuit through the second circuit element. The signal processing circuit according to claim 2, wherein at least one of the first circuit element and the second circuit element corresponds to the circuit element and includes the variable resistor section configured to change the resistance value of the resistance component of the at least one of the circuit elements.

7. The first circuit element includes an N-channel type first MOSFET as the variable resistor section. The second circuit element includes a P-channel type second MOSFET as the variable resistor section. The signal processing circuit according to claim 6, wherein the sources of both the first MOSFET and the second MOSFET are connected to the comparison circuit.

8. The AC coupling section includes a capacitor, The signal processing circuit according to claim 1, wherein the level shifter portion includes a circuit element having a resistive component and a terminal to which a voltage lower than the reverse bias voltage is applied and which is electrically connected to the capacitor and the comparator circuit through the circuit element of the level shifter portion.

9. The signal processing circuit according to claim 1, wherein the comparison circuit includes an inverter.

10. The signal processing circuit according to claim 1, further comprising at least one of an active quenching circuit that performs active quenching on the avalanche photodiode based on a signal from the downstream circuit, and an active recharge circuit that performs active recharging on the avalanche photodiode based on a signal from the downstream circuit.

11. A signal processing circuit according to any one of claims 1 to 10, The avalanche photodiode and, The avalanche photodiode is further equipped with a quenching resistor that is electrically connected to the avalanche photodiode. The AC coupling section AC-couples the avalanche photodiode and the quenching resistor with the comparator circuit in the photodetector.

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