Integration process using boron-doped silicon material

Abstract

To provide a method for deposition, etching and removal of materials containing boron or boron and silicon materials in a semiconductor integration process.SOLUTION: An integrated process includes depositing a boron-containing material or silicon and boron-containing materials onto a substrate disposed in a processing region of a semiconductor processing chamber, etching portions of the boron-containing material or silicon and boron-containing materials with a chlorine-containing precursor to form one or more features in the substrate, and removing remaining portions of the boron-containing material or silicon and boron-containing materials from the substrate using a fluorine-containing precursor.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Cross-Reference to Related Applications

[0001] This application claims the priority benefit of U.S. Patent Application No. 63 / 053,693 entitled "INTEGRATION PROCESSES UTILIZING BORON-DOPED SILICON MATERIALS" filed on July 19, 2020, which is incorporated by reference in its entirety for all purposes.

[0002]

[0002] The present technology relates to semiconductor integration processes. More specifically, the present technology relates to methods for depositing, etching, and removing materials including boron or boron and silicon materials.

Background Art

[0003]

[0003] Integrated circuits are enabled by processes that produce complex patterned layers of materials over a substrate surface. Forming patterned material on a substrate requires controlled methods for forming and removing exposed material. As device miniaturization progresses, material uniformity can affect subsequent operation. For example, many processing operations utilize mask materials or sacrificial materials to facilitate pattern transfer and structure formation in or between layers of a semiconductor substrate. As the number of different materials used in processing increases and the critical dimensions of structural features shrink, the use of masks with enhanced selectivity for various exposed materials becomes increasingly important.

[0004]

[0004] Accordingly, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technology addresses these and other needs.

Summary of the Invention

[0005]

[0005] An exemplary processing method may include depositing a boron-containing material or a silicon and boron-containing material on a substrate placed within a processing area of ​​a semiconductor processing chamber. The method may include etching portions of the boron-containing material or silicon and boron-containing material with a chlorine-containing precursor to form one or more features on the substrate. The method may also include removing the remaining portions of the boron-containing material or silicon and boron-containing material from the substrate using a fluorine-containing precursor.

[0006]

[0006] In some embodiments, the boron-containing material may be a silicon and boron-containing material. Depositing the boron-containing material may involve supplying the silicon-containing precursor and the boron-containing precursor to the processing area of ​​the semiconductor processing chamber. Depositing the boron-containing material may involve supplying the hydrogen-containing precursor together with the silicon-containing precursor and the boron-containing precursor. The flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor may be about 2:1 or greater. Depositing the boron-containing material may involve forming a plasma of all precursors within the processing area of ​​the semiconductor processing chamber. The silicon-containing precursor may be silane or may contain silane. The boron-containing precursor may be diborane or may contain diborane. Removal may be carried out at a rate of about 35 nm / min or greater. The boron-containing material may be characterized by a film thickness of about 20 nm or greater.

[0007]

[0007] The substrate temperature may be maintained at approximately 400°C or higher while depositing the boron-containing material on the substrate. The substrate temperature may be maintained at approximately 200°C or higher during removal. Etching may include forming a plasma of bromine-containing precursors. Etching may include contacting the boron-containing material with the plasma emissions of the bromine-containing precursors. Etching may include stopping the supply of the bromine-containing precursors. Etching may include forming a plasma of chlorine-containing precursors. Etching may include contacting the boron-containing material with the plasma emissions of the chlorine-containing precursors. Etching may include forming a plasma of an etchant mixture containing chlorine-containing precursors and oxygen-containing precursors. Etching may include contacting the boron-containing material with the plasma emissions of the etchant mixture while forming a plasma at a first plasma output. Etching may include increasing the first plasma output to a second plasma output after the first period. Etching may involve transferring a pattern from an overlapping mask material through a boron-containing material. Etching may involve applying bias power during a first period. Etching may involve stopping the bias power after the first period. Removal may involve forming a remote plasma of an etchant mixture containing fluorine-containing precursors and hydrogen-containing precursors. Removal may involve contacting the boron-containing material with the plasma emissions of the etchant mixture. Removal may involve removing the boron-containing material with a selectivity of about 20:1 or more compared to other exposed materials on the substrate. The remote plasma may be formed with a plasma output of about 2.0 kW or more.

[0008]

[0008] Some embodiments of the present technology may encompass processing methods. The method may include depositing a silicon-and-boron-containing material on a substrate placed within a processing area of ​​a semiconductor processing chamber. The method may include etching portions of the silicon-and-boron-containing material to form one or more features on the substrate. Etching may include forming a plasma of an etchant mixture containing a chlorine-containing precursor and an oxygen-containing precursor. Etching may include contacting the silicon-and-boron-containing material with plasma emissions of the etchant mixture while forming a plasma at a first plasma output. Etching may include increasing the first plasma output to a second plasma output after a first period. The method may include removing the remaining portion of the silicon-and-boron-containing material from the substrate using a fluorine-containing precursor.

[0009]

[0009] In some embodiments, the silicon and boron-containing material may be characterized by a boron concentration of about 40 atomic percent or more. The etchant mixture may contain a fluorine-containing precursor. The flow rate ratio of the fluorine-containing precursor to the oxygen-containing precursor to the chlorine-containing precursor may be about 1:5:10 or more. The method may include applying bias power during a first period. The method may include stopping the bias power after the first period. The plasma may be formed at a pulse frequency of about 500 Hz or more. The duty cycle of the bias power during plasma formation may be about 40% or less.

[0010]

[0010] Some embodiments of the present technology may encompass processing methods. The method may include depositing a silicon- and boron-containing material on a substrate placed within a processing area of ​​a semiconductor processing chamber. The method may include etching portions of the silicon- and boron-containing material with a chlorine-containing precursor to form one or more features on the substrate. The method may include removing the remaining silicon- and boron-containing material from the substrate. Removal may include forming a remote plasma of an etchant mixture containing a fluorine-containing precursor and a hydrogen-containing precursor. Removal may include contacting the silicon- and boron-containing material with plasma emissions of the etchant mixture. The method may include removing the silicon- and boron-containing material at a rate of about 35 nm / min or more. In some embodiments, the temperature of the substrate during removal is maintained at about 200°C or higher, and the remote plasma may be formed with a plasma output of about 2.0 kW or higher. The substrate may include exposed areas of titanium nitride, and the etchant mixture may contain ammonia.

[0011]

[0011] Such technologies can offer more advantages than conventional systems and technologies. For example, the materials according to embodiments of this technology can improve selectivity for various materials to be etched. This allows thinner layers to be used for patterning and can reduce risks associated with pattern transfer, including structural twisting due to etchant collisions and loss of critical dimensions due to etching timing. Furthermore, this technology can improve the etching removal of mask materials and increase the throughput of semiconductor processing. These embodiments and other embodiments, along with their many advantages and features, are described in more detail below in conjunction with the accompanying drawings.

[0012]

[0012] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1]A schematic cross-sectional view of an exemplary processing chamber according to several embodiments of this technology is shown. [Figure 2] A schematic cross-sectional view of an exemplary processing chamber according to several embodiments of this technology is shown. [Figure 3] A schematic cross-sectional view of an exemplary processing chamber according to several embodiments of this technology is shown. [Figure 4] The following are illustrative steps of an integration method according to several embodiments of this technology. [Figure 5A] The following are schematic isometric subdivisions of the substrate during the pattern transfer process according to several embodiments of this technology. [Figure 5B] The following are schematic isometric subdivisions of the substrate during the pattern transfer process according to several embodiments of this technology. [Figure 6] The following are exemplary steps that may be included in methods according to several embodiments of this technology. [Figure 7] The following are exemplary steps that may be included in methods according to several embodiments of this technology. [Figure 8] The following are exemplary steps that may be included in methods according to several embodiments of this technology. [Figure 9] The following are exemplary steps that may be included in methods according to several embodiments of this technology. [Figure 10A] The following are schematic cross-sectional views of the substrate during the removal process according to several embodiments of this technology. [Figure 10B] The following are schematic cross-sectional views of the substrate during the removal process according to several embodiments of this technology. [Modes for carrying out the invention]

[0014]

[0023] Several drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and are not to be considered drawn to scale unless explicitly stated to be drawn to scale. Furthermore, as schematic diagrams, the drawings are provided to facilitate understanding, may not include all aspects or information compared to realistic depictions, and may include material that is emphasized for illustrative purposes.

[0015]

[0024] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to reference numerals by characters that distinguish between similar components. When only a first reference numeral is used herein, the description is applicable to any of the similar components having the same first reference numeral regardless of the character.

[0016]

[0025] During semiconductor manufacturing, various deposition and etching processes may be utilized to fabricate a number of structures on a substrate. Mask materials may be used to partially etch a material or etch to form features over an entire substrate. As device miniaturization progresses, selectivity between materials is improved, and structure formation can be facilitated, manufacturing can be facilitated by utilizing improved hard masks. For example, compared to thermally formed amorphous silicon hard masks, boron-incorporated silicon films are characterized by improved hardness and other material properties, which can facilitate the use of the film as a mask material. Increasing hardness can improve the utilization of mask materials for any number of processes. For example, many memory structures can include the formation of high aspect ratio apertures. In DRAM structures, capacitor contacts may be formed, and in 3D NAND, memory holes or contact openings may be formed. Storage node contacts may also be formed. Using a harder film as a mask helps maintain local critical dimension uniformity across the substrate, and thinner films may be available. However, increased hardness can make it more difficult to etch and remove the mask and sacrificial layer.

[0017]

[0026] The present technology can overcome these limitations by utilizing adjustable boron-containing films and silicon-and-boron-containing films in semiconductor processing. In addition, the use of improved processes for etching and removal may not adversely affect throughput. Furthermore, the removal rate according to some embodiments of the present technology can be improved by adjusting the chamber structure and configuration to promote an increase in etching rate with high selectivity. This can facilitate rapid removal of residual material while substantially or completely retaining other materials exposed during removal. After describing general aspects of a chamber according to some embodiments of the present technology, in which a plasma treatment process described below may be performed, specific methodologies may be described. It is understood that the technology described is not intended to be limited to the specific films, chambers, or processes described, as the technology may be used to improve numerous film formation processes and be applicable to a variety of processing chambers and processes.

[0018]

[0027] Figure 1 shows a cross-sectional view of an exemplary processing chamber 100 according to several embodiments of the present technology. This figure may illustrate a system incorporating one or more aspects of the present technology and / or a system capable of performing one or more deposition or other processing steps according to embodiments of the present technology. Additional details of the chamber 100 or the method performed may be described further below. While the chamber 100 may be used to form a film layer according to several embodiments of the present technology, it should be understood that the method may be similarly performed in any chamber in which film formation may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 located inside the chamber body 102, and a lid assembly 106 connected to the chamber body 102 and enclosing the substrate support 104 within a processing space 120. The substrate 103 may be provided to the processing space 120 through an opening 126 which may conventionally be sealed for processing using a slit valve or door. The substrate 103 may be located on the surface 105 of the substrate support during processing. The substrate support 104 may be rotatable along an axis 147 in which the shaft 144 of the substrate support 104 may be located, as indicated by the arrow 145. Alternatively, the substrate support 104 may be lifted to rotate it as needed during the deposition process.

[0019]

[0028] A plasma profile modulator 111 may be located within the processing chamber 100 to control the plasma distribution across the substrate 103 placed on the substrate support 104. The plasma profile modulator 111 includes a first electrode 108 which may be located adjacent to the chamber body 102, thereby separating the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member, or may be a ring electrode. The first electrode 108 may be a continuous loop along the periphery of the processing chamber 100 surrounding the processing space 120, or may be discontinuous at positions selected as desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or a plate electrode, such as in a secondary gas distributor.

[0020]

[0029] One or more isolators 110a, 110b may be ceramic or metal oxides, dielectric materials such as aluminum oxide and / or aluminum nitride, and may be in contact with the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define openings 118 for distributing the process precursor into the processing space 120. The gas distributor 112 may be connected to a first power source 142, such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power supply that may be connected to the processing chamber. In some embodiments, the first power source 142 may be an RF power supply.

[0021]

[0030] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, while the faceplate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered by a first power source 142, such as the one shown in Figure 1, or in some embodiments, the gas distributor 112 may be connected to earth.

[0022]

[0031] The first electrode 108 may be connected to a first tuning circuit 128 that can control the grounding path of the processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be a variable capacitor or other circuit element, or may include these. The first tuning circuit 128 may be one or more inductors 132, or may include these. The first tuning circuit 128 may be any circuit that enables a variable or controllable impedance under the plasma conditions present in the processing space 120 during processing. In some of the illustrated embodiments, the first tuning circuit 128 may include a first circuit leg and a second circuit leg connected in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B connected in series with the first electronic controller 134. A second inductor 132B may be positioned between the first electronic controller 134 and a node that connects both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 is a voltage sensor or a current sensor, connected to the first electronic controller 134, and may allow for some degree of closed-loop control of the plasma conditions inside the processing space 120.

[0023]

[0032] The second electrode 122 may be connected to the substrate support 104. The second electrode 122 may be incorporated into the substrate support 104 or connected to the surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other dispersed structure of conductive elements. The second electrode 122 may be a tuning electrode and may be connected to a second tuning circuit 136 by a conduit 146 (e.g., a cable with a selected resistance such as 50 ohms) located within the shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140 which may be a second variable capacitor. The second electronic sensor 138 may be a voltage sensor or a current sensor and may be connected to the second electronic controller 140 to provide further control over the plasma conditions in the processing space 120.

[0024]

[0033] A third electrode 124, which may be a bias electrode and / or an electrostatic chucking electrode, may be connected to a substrate support 104. The third electrode is connected to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these power sources or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0025]

[0034] The lid assembly 106 and substrate support 104 in Figure 1 can be used with any processing chamber for plasma or heat treatment. During operation, the processing chamber 100 can perform real-time control of the plasma conditions in the processing space 120. The substrate 103 is placed on the substrate support 104, and process gas can flow through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gas can be discharged from the processing chamber 100 through the outlet 152. Power can be connected to the gas distributor 112 to establish plasma in the processing space 120. In some embodiments, the substrate may be electrically biased using a third electrode 124.

[0026]

[0035] When the plasma is excited in the processing space 120, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. The electronic controllers 134 and 140 can then be used to adjust the flow characteristics of the ground path, which are represented by two tuning circuits 128 and 136. Setpoints can be given to the first tuning circuit 128 and the second tuning circuit 136 so that independent control of the deposition rate and the uniformity of the plasma density from the center to the edge is achieved. In embodiments where both electronic controllers are variable capacitors, the electronic sensors can independently adjust the variable capacitors to maximize the deposition rate and minimize thickness non-uniformity.

[0027]

[0036] Each of the tuning circuits 128 and 136 may have a variable impedance that can be adjusted using their respective electronic controllers 134 and 140. If the electronic controllers 134 and 140 are variable capacitors, the capacitance range of each variable capacitor and the inductances of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range depends on the frequency and voltage characteristics of the plasma and may have the minimum capacitance range of each variable capacitor. Therefore, when the capacitance of the first electronic controller 134 is at its minimum or maximum, the impedance of the first tuning circuit 128 may be high. As a result, a plasma shape with minimum aerial or lateral coverage above the substrate support is created. When the capacitance of the first electronic controller 134 reaches the value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma may grow to its maximum, thus effectively covering the entire working area of ​​the substrate support 104. If the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may contract away from the chamber wall, potentially reducing the air coverage of the substrate support. The second electronic controller 140 may have a similar effect, so as the capacitance of the second electronic controller 140 changes, the air coverage of the plasma above the substrate support increases or decreases.

[0028]

[0037] Electronic sensors 130 and 138 may be used to tune their respective circuits 128 and 136 in a closed loop. Depending on the type of sensor used, a setpoint for current or voltage may be attached to each sensor. The sensors may be provided with control software that determines adjustments to their respective electronic controllers 134 and 140 to minimize deviation from the setpoint. As a result, the plasma shape may be selected and dynamically controlled during processing. The foregoing description is based on electronic controllers 134 and 140, which may be variable capacitors, but it should be understood that any electronic component with adjustable characteristics may be used to provide tuning circuits 128 and 136 with adjustable impedance.

[0029]

[0038] Figure 2 shows a schematic cross-sectional view of an exemplary processing chamber 200 suitable for patterning a material layer placed on a substrate 202 within the processing chamber 200. For example, the chamber 200 may be an exemplary etching chamber, which can be configured to facilitate pattern transfer or etching of materials according to the Art, including boron-containing materials and boron and silicon-containing materials. While the exemplary processing chamber 200 may be suitable for performing a patterning process, it will be understood that embodiments of the Art may be performed in any number of chambers configured to perform the operation according to embodiments of the Art. The plasma processing chamber 200 may include a chamber body 205 that defines a processing area 201 in which the substrate can be processed. The chamber body 205 may have side walls 212 and a bottom 218, which are connected to ground 226. The side walls 212 have liners 215 to protect the side walls 212, which may extend the time between maintenance cycles of the plasma processing chamber 200. The dimensions of the chamber body 205 and related components of the plasma processing chamber 200 are not limited and can generally be proportionally larger than the size of the substrate 202 processed within them. Examples of substrate sizes include diameters of 200 mm, 250 mm, 300 mm, and 450 mm, and are particularly common for display substrates and solar cell substrates.

[0030]

[0039] The chamber body 205 may support the chamber lid assembly 210 so as to surround the processing area 201. The chamber body 205 may be manufactured from aluminum or other suitable material. A substrate access port 213 may be formed through the side wall 212 of the chamber body 205. This facilitates the transfer of substrates 202 into and out of the plasma processing chamber 200. The access port 213 may be connected to the transfer chamber and / or other chambers of the substrate processing system, as described above. A pumping port 245 may be formed through the side wall 212 of the chamber body 205 and connected to the processing area 201. A pumping device may be connected to the processing area 201 through the pumping port 245 to evacuate the internal space and control the internal pressure. The pumping device may include one or more pumps and throttle valves.

[0031]

[0040] A gas panel 260 is connected to the chamber body 205 by a gas line 267 to supply process gases into the processing area 201. The gas panel 260 includes one or more process gas sources 261, 262, 263, 264 and may additionally include inert gases, non-reactive gases, and reactive gases that can be used for any number of processes. Examples of process gases that may be supplied by the gas panel 260 include, but are not limited to, hydrocarbon-containing gases including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, argon, chlorine, nitrogen, helium, or oxygen, as well as any number of additional materials. In addition, the process gas may include any number of nitrogen, chlorine, fluorine, oxygen, and hydrogen-containing gases, such as BCl3, C2F4, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, NH3, CO2, SO2, CO, N2, NO2, N2O, and H2, among any number of additional precursors.

[0032]

[0041] Valve 266 controls the flow of process gas from sources 261, 262, 263, and 264 of the gas panel 260 and may be managed by controller 265. The flow of gas supplied from the gas panel 260 to the chamber body 205 may include a combination of gases from one or more sources. The lid assembly 210 may include nozzles 214. Nozzles 214 may be one or more ports for introducing process gases from sources 261, 262, 263, and 264 of the gas panel 260 into the processing area 201. After the process gases are introduced into the plasma processing chamber 200, the gases may be excited to form a plasma. Antennas 248, such as one or more inductor coils, may be provided adjacent to the plasma processing chamber 200. The antenna power supply 242 supplies power to the antenna 248 through the matching circuit 241, inductively coupling energy (e.g., RF energy) to the process gas and maintaining the plasma formed from the process gas within the processing area 201 of the plasma processing chamber 200. Alternatively, or in addition to the antenna power supply 242, processing electrodes below and / or above the substrate 202 may be used to capacitively couple RF power to the process gas and maintain the plasma within the processing area 201. The operation of the power supply 242 may be controlled by a controller (e.g., controller 265) that also controls the operation of other components within the plasma processing chamber 200.

[0033]

[0042] A substrate support pedestal 235 may be provided within the processing area 201 to support the substrate 202 during processing. The substrate support pedestal 235 may include an electrostatic chuck 222 for holding the substrate 202 during processing. The electrostatic chuck ("ESC") 222 may use electrostatic attraction to hold the substrate 202 against the substrate support pedestal 235. The ESC 222 may be powered by an RF power supply 225 integrated with a matching circuit 224. The ESC 222 may include an electrode 221 embedded in a dielectric body 251. The electrode 221 may be connected to the RF power supply 225 and provide a bias. This bias attracts plasma ions formed by the process gas in the processing area 201 to the ESC 222 and the substrate 202 located on the pedestal. The RF power supply 225 may cycle on and off, or pulse, during the processing of the substrate 202. The ESC222 may have an isolator 228 to prevent the sidewalls of the ESC222 from being too attracted to the plasma in order to extend the service life of the ESC222. In addition, the substrate support pedestal 235 may have a cathode dryer 236 to protect the sidewalls of the substrate support pedestal 235 from the plasma gas and to extend the maintenance interval of the plasma processing chamber 200.

[0034]

[0043] Electrode 221 may be connected to a power supply 250. The power supply 250 may supply a chucking voltage to electrode 221 ranging from approximately 200 volts to approximately 2000 volts. The power supply 250 may also include a system controller for controlling the operation of electrode 221 by directing a DC current to electrode 221 for chucking and dechucking the substrate 202. ESC 222 may include a heater located within a pedestal and coupled to the power supply for heating the substrate. Meanwhile, a cooling base 229 supporting ESC 222 may include conduits for circulating a heat transfer fluid to maintain the temperature of ESC 222 and the substrate 202 placed on it. ESC 222 may be configured to operate within the temperature range required by the thermal balance of the device being manufactured on the substrate 202. For example, ESC 222 may be configured to maintain the substrate 202 at a temperature ranging from approximately -150°C or below to approximately 500°C or above, depending on the process being performed.

[0035]

[0044] A cooling base 229 may be provided to assist in temperature control of the substrate 202. To mitigate process drift and time, the temperature of the substrate 202 may be maintained substantially constant by the cooling base 229 while the substrate 202 is in the cleaning chamber. In some embodiments, the temperature of the substrate 202 may be maintained between approximately -150°C and approximately 500°C throughout the subsequent cleaning process, although any temperature may be utilized. A covering 230 may be placed on the ESC 222 along the outer circumference of the substrate support pedestal 235. The covering 230 may be configured to shield the upper surface of the substrate support pedestal 235 from the plasma environment inside the plasma processing chamber 200 while containing etching gases in desired portions of the exposed upper surface of the substrate 202. As described above, lift pins are selectively translated through the substrate support pedestal 235 to lift the substrate 202 above the substrate support pedestal 235, thereby facilitating access to the substrate 202 by a transport robot or other suitable transport mechanism.

[0036]

[0045] The controller 265 may be used to control the processing sequence and adjust the gas flow from the gas panel 260 to the plasma processing chamber 200 and other process parameters. When executed by the CPU, the software routines translate the CPU into an application computer, such as a controller that controls the plasma processing chamber 200, and as a result, the process is executed in accordance with this disclosure. The software routines may also be stored and / or executed by a second controller that may be associated with the plasma processing chamber 200.

[0037]

[0046] Figure 3 shows a schematic cross-sectional view of an exemplary processing chamber 300 according to several embodiments of the present technology. The processing chamber 300 may be suitable for performing material removal on a substrate 302 within the processing chamber 300. For example, the chamber 300 may be an exemplary etching or removal chamber that can be configured to facilitate the removal of materials according to the present technology, including boron-containing materials and boron and silicon-containing materials.

[0038]

[0047] Figure 3 may illustrate components located on the chamber body 301, such as on a lid plate 305, which can define multiple process regions for any other configuration that can benefit from one or more components of a tandem chamber, a standalone chamber, or a stack. A lid stack may include a spacer 310 located on the lid plate. This can radially define a processing region 304 to which a pedestal or other substrate support may extend together with the substrate, as previously described. The pedestal 303 or other substrate support may extend through the chamber body 301 and support a substrate 302. This substrate may include a boron-containing material or a boron and silicon-containing material, as described throughout this art. A showerhead 315 located on the spacer 310 may define the processing region from above. While the showerhead 315 shows a single-channel showerhead, it will be understood that a dual-channel showerhead may also be used. The shower head 315 may include a resistive element 317 that can be used to heat the shower head during operation.

[0039]

[0048] Above the showerhead 315, there may be an electrode 320 located on the showerhead, but in some embodiments, a thermal spacer may at least partially separate the two components, for example, the showerhead may be heated while the electrode is cooled. The electrode may define or include a channel 322 extending around the plate through which a temperature-controlled fluid can flow. An isolator 325 may be located above the electrode, and a faceplate 330 may be located above the isolator. The faceplate may include a channel 332 defined within the faceplate for the flow of a temperature-controlled fluid. The electrode, faceplate, and isolator define a remote plasma region 327 between the components, in which a capacitively coupled plasma may be formed. The isolator electrically insulates the faceplate from the electrode, thereby allowing the components to be charged or grounded, and thus forming a precursor plasma flowing into the remote plasma region. In some embodiments, the high-temperature electrode, which may be, for example, the faceplate, may be powered with higher power, thereby increasing the ion density to increase the etching rate.

[0040]

[0049] Some embodiments of this technology can provide high etching rates for masks or other materials. Therefore, the capacitively coupled plasma that can be formed between the faceplate and the electrode may be generated with increased plasma power to increase the plasma density in space, and the generation of plasma emissions may be increased to increase the etching of the substrate material within the processing area. In some embodiments, the plasma is generated with a plasma power of about 2.0 kW or more, and may be generated with plasma power of about 2.5 kW or more, about 3.0 kW or more, about 3.5 kW or more, about 4.0 kW or more, about 4.5 kW or more, about 5.0 kW or more, about 5.5 kW or more, about 6.0 kW or more, or higher. However, this increase in plasma power may increase the influence of the plasma within the chamber.

[0041]

[0050] For example, many surfaces or components may be coated with protective coatings to improve erosion and / or corrosion effects within the remote plasma region. For instance, an oxide coating may be formed on a component that may be aluminum or any other material used in a semiconductor chamber. One such oxide coating may be yttrium oxide. As the plasma output increases within the remote plasma region, the plasma energy may also increase the temperature of the electrode and adjacent components. This can increase the impact on the coated surface and increase the plasma effect on corners and other materials. Also, coatings such as yttrium oxide may begin to decompose when the temperature exceeds 150°C. Therefore, to limit the degradation of this coating, a fluid may be flowed through a channel 322 formed in the electrode 320, maintaining a temperature of approximately 150°C or less, approximately 125°C or less, approximately 100°C or less, approximately 90°C or less, approximately 80°C or less, approximately 70°C or less, approximately 60°C or less, approximately 50°C or less, or below during processing.

[0042]

[0051] In addition, to further reduce damage, the opening profiles of the openings formed inside the faceplate and electrodes may be modified. For example, in some prior art, one or more openings in the faceplate and electrodes may be characterized by conical or tapered sections extending to the surface facing the distant plasma region. These regions are more difficult to coat with protective materials such as yttrium oxide or other oxide coatings, and the coating thickness may decrease further toward the conical portion. In addition, the conical portion may limit the amount of flat surface between adjacent cones. This increases charge accumulation in these regions, further increasing defects in the coating, and all of these can increase the likelihood of arc generation within the region. The conical portion may also promote a hollow cathode effect within the cone, drawing the plasma further into the conical portion and further increasing damage to the thinner coating within the conical portion. In some prior art, when low plasma power is used, such as less than 2.5 kW or less than 1.0 kW, arc discharge or damage to the coating may be acceptable, but the risk of arc discharge is low and the resulting damage may be low. At high plasma power levels, such as those used in some embodiments of this technology, these materials may further damage components and increase particle displacement to the substrate. This technology may be modified in one or more ways to limit or prevent arc discharge while forming a high-power plasma.

[0043]

[0052] For example, in some embodiments, the opening formed through the faceplate and electrodes may be characterized by a counterbore or countersunk profile extending toward the distant plasma region, as shown in the illustration. Here, the opening may be characterized by a shortened diameter extending toward the surface facing the distant plasma region and a larger diameter or taper extending toward the opposite surface. This facilitates the coating process on the plasma-facing surface, improves component protection from high-energy plasma species, and can limit sharp angles or prominent edges that are prone to generating arc paths.

[0044]

[0053] The blocker plate 335 is located in a recess of the faceplate and may be bolted to a gas box 340 connected to the faceplate at its outer edge. The outlet manifold 345 is connected to the gas box and may include an internal plenum from which the gas can be mixed before being supplied to the chamber. The electrode 320 is an ion suppressor that allows ions formed in the capacitively coupled plasma to be filtered from the plasma emitters, thereby allowing etching to be performed substantially or exclusively by radical species, protecting the structure and improving selectivity. The electrode 320 may act as one of two electrodes for generating a remote plasma within the processing chamber, as described above. In some embodiments, the electrode 320 is a single integrated component and includes a channel 322 defined within the electrode, which may extend around the electrode. As described above, the channel may, in some embodiments, allow for temperature control of the electrode 320 during processing. The electrode 320 is characterized by a first surface facing the remote plasma region and a second surface opposite the first surface, which may face, for example, a showerhead. As shown in the figure, a recess may be formed within the second surface of the electrode, which may increase the mixing and distribution of the fluid in the chamber.

[0045]

[0054] Conventional electrodes may also include recesses defined within the first surface of the electrode, which can partially define the plasma envelope within a remote plasma region. These recesses, similar to those formed along the second surface of the electrode, can generate a corner profile around them. This setup may work well in some conventional capacitively coupled plasma processes where the plasma output may be less than 1,000 watts. However, in some embodiments of this technology where the plasma output may be several thousand watts, these corner profiles can cause several problems. For example, as described above, the corner profiles can make plasma coating with a protective layer more difficult, potentially leading to thinner or gapped coatings in these areas and increasing the chances of damage. In addition, plasma profiles within remote plasma regions may include increased edge density and electric field concentration, further damaging the coating in these areas. If the coating is incomplete or thin, it may become more susceptible to damage. In addition, the increased charge density can accumulate on the upper ridge of the recess, increasing the possibility of arc discharge and material damage, and potentially leading to an even greater increase in the number of particles on the substrate being processed.

[0046]

[0055] As a result, electrodes according to some embodiments of the present technology may be characterized by a substantially planar profile in the active region of the processing chamber. Electrode 320 may include a substantially flat surface across the electrode surface facing the faceplate. This may extend through the inner annular edge of the isolator 325 to a region where an O-ring or elastomer element may be located between the components. This facilitates surface coating of the electrode, and the faceplate is similarly characterized by a substantially planar surface, which may also be coated with a protective material as described above. The openings defined through the faceplate and electrodes may be characterized by opposing counterbore or countersunk profiles, as discussed above. Here, the portion characterized by a reduced diameter may extend to the surface of a component facing or defining a remote plasma region. The surface of a component facing a remote plasma region does not include a conical or tapered portion, which, as described above, can lead to coating challenges and increase the possibility of arc discharge.

[0047]

[0056] Because recesses on the surface of components facing the remote plasma region can partially define the plasma region, and because the faceplate and electrodes can maintain similar plasma profile characteristics characterized by substantially planar profiles along these surfaces, the isolator can be modified to maintain remote plasma region characteristics. For example, in some embodiments, the distance of the recesses may be incorporated into the isolator to maintain the electrode spacing in the remote plasma region. Thus, in some embodiments, the isolator can maintain plasma characteristics between electrodes by being characterized by a thickness or height of at least about 5 mm, and by heights of about 6 mm or more, about 7 mm or more, about 8 mm or more, about 9 mm or more, about 10 mm or more, about 11 mm or more, about 12 mm or more, about 13 mm or more, about 14 mm or more, about 15 mm or more, or more.

[0048]

[0057] In addition, remote plasma regions are characterized by increased plasma density in the edge regions of the plasma envelope, which can increase the potential for problems in these regions. To control the plasma envelope in remote plasma regions, openings through components do not need to extend very far radially outward along the plate. For example, in some embodiments, one or more components may not have openings at a distance from an edge of the remote plasma region. For example, as illustrated, in some embodiments, electrodes may not include openings in a region extending to the inner annular radius of the isolator. For example, openings through electrodes may not be formed at a radial distance of about 2 mm or more from the inner annular edge of the isolator, nor at distances of about 3 mm or more, about 4 mm or more, about 5 mm or more, about 6 mm or more, about 7 mm or more, about 8 mm or more, about 9 mm or more, about 10 mm or more, about 11 mm or more, about 12 mm or more, about 13 mm or more, about 14 mm or more, about 15 mm or more, or greater. This can further suppress plasma effects within the remote plasma region.

[0049]

[0058] The exemplary chambers described above may be used in several embodiments of an integration process that may include the formation, etching, and removal of materials as described above. The described chambers should not be considered limiting, and it should be understood that any chamber that can be configured to perform the operations described may be used similarly. The chambers may be combined in a single mainframe or separated across mainframes for processing. Figure 4 shows exemplary steps of integration method 400 according to several embodiments of the Art. The method may be performed in various processing chambers and one or more mainframes or tools, including any of the processing chambers 100, 200, or 300 described above. Method 400 may include several optional steps. These steps may or may not be specifically related to some embodiments of the method according to the Art. For example, many of the steps, while described to provide a broader range of structure formation, may be performed by alternative methodologies that are not critical to the Art or would be easily understood. Method 400 may describe steps schematically shown in Figures 5A-5B. These examples will be described in conjunction with the steps of Method 400. The diagram shows only a partial schematic, and it should be understood that the substrate may include any number of additional materials and features having various properties and characteristics as shown in the diagram.

[0050]

[0059] Method 400 may include additional steps before commencing the enumerated steps. For example, the additional processing steps may include forming a structure on the semiconductor substrate, which may include both forming and removing materials. For example, a transistor structure, a memory structure, or any other structure may be formed. The prior processing steps may be performed in the chamber in which Method 400 may be performed, or the processing may be performed in one or more other processing chambers before supplying the substrate to one or more semiconductor processing chambers in which Method 400 may be performed. Nevertheless, Method 400 may optionally include supplying the semiconductor substrate to a processing area of ​​a semiconductor processing chamber, such as the processing chamber 100 described above, or to another chamber, which may include the components described above. The substrate may be deposited on a substrate support, which may be a pedestal, such as a substrate support 104, and which may be present in a processing area of ​​a chamber, such as the processing space 120 described above.

[0051]

[0060] A substrate after several processes have been performed becomes a substrate 505 or structure 500, which may represent one or more underlying structures. Structure 500 should be understood to represent only some of the top layers being processed in order to illustrate aspects of the art. However, it should be understood that any number of layers, materials, or structures may be formed beneath the illustrated materials. For example, substrate 505 may represent a material on which one or more features may be formed, and may represent additional masking or structural layers. Substrate 505 may exemplify an oxide material 506 and an etching stop layer such as silicon nitride 508 located on top. While these materials may be discussed throughout, it should be understood that other underlying materials and substrate materials may include silicon, germanium, dielectric materials containing silicon oxide or silicon nitride, metallic materials, or any number of combinations of these materials, which may be substrate 505 or materials formed on substrate 505.

[0052]

[0061] In step 405, the boron-containing material or the boron and silicon-containing material 510 may be deposited on the substrate 505. Exemplary deposition methods encompassed by this technique may be further described below, for example, with reference to Figure 6. Additional processing may be performed after the deposition of the mask material and before any additional steps of this method. For example, the pattern to be transferred to the boron and silicon-containing material 510 may be applied in any number of ways. In one non-limiting example, an additional mask 512 may be formed on the boron and silicon-containing material, and a structure or pattern 514 may be formed through the mask and then transferred to the boron and silicon-containing material 510. The mask 512 may be any sacrificial material such as an oxide or nitride, and photolithography or other lithography steps may be performed to generate the pattern 514. Pattern 514 is illustrated as a set of equal openings formed through a mask, which could be used to form cell capacitors for DRAM or memory holes for 3D NAND, but any pattern may be generated, and the illustration should be understood as not intended to limit the art.

[0053]

[0062] In step 410, the pattern may be transferred to the underlying structure 508 through the boron and silicon-containing material 510. Etching may remove a portion of the material 510, for example, to generate the pattern through the material. Figure 5B shows the pattern 514 transferred to the underlying boron and silicon-containing material as pattern 520. As described above, compared to amorphous silicon mask material, boron-doped mask material, i.e., boron mask, can provide improved hardness and material strength. As a result, masks with reduced thickness can be used. The advantages of reducing thickness may include a reduction in deposition time, but further advantages can be realized during pattern transfer. For example, when performing pattern transfer such as aperture openings, the etching process may be affected by the thickness of the material. For example, the further into the structure the etching proceeds, the more likely it is that ions and radicals of the etchant will affect the sidewalls as they move. This can result in some wrinkles and twists within the structure, which may affect the material properties of the material later deposited in the aperture. Furthermore, longer etching processes increase the residence time of the etchant, which in turn increases the time the upper region is exposed to the etchant, potentially affecting the critical dimensions of the opening. This leads to increased loss of critical dimensions, which may be more pronounced in the edge regions. In this case, the influence of an additional chamber may cause a reorientation of the etchant within the chamber, again increasing the isotropic nature of removal. Therefore, films manufactured according to this technique may have beneficial effects on many processing modes.

[0054]

[0063] While some embodiments of this technology can provide reduced thickness masking, the technology can generate material thicknesses over a wide range. For example, the deposition process according to embodiments of this technology generates boron-containing materials or boron and silicon-containing materials, which in some embodiments are conformal and are characterized by material thicknesses of about 10 nm or more, and may be characterized by material thicknesses of about 20 nm or more, about 30 nm or more, about 50 nm or more, about 75 nm or more, about 100 nm or more, about 200 nm or more, about 300 nm or more, about 400 nm or more, about 500 nm or more, about 600 nm or more, about 700 nm or more, about 800 nm or more, about 900 nm or more, about 1,000 nm or more, or greater.

[0055]

[0064] After the pattern transfer step, in some embodiments, an additional etching step may be performed to further transfer the pattern to the underlying structure, such as contacts or other interconnecting materials. After the final pattern transfer or etching is performed, in step 415, the boron and silicon-containing material may be removed from the structure. As described above, incorporating boron can improve film hardness and etching resistance. Conventional etching can be limited by slow etching speed or low selectivity for other exposed materials. Therefore, the removal step of this technology can rapidly remove the material from the underlying structure while maintaining high selectivity for exposed materials. Better removal can be achieved by using a chamber configured to generate plasma at a higher plasma output without arc discharge or damage to the chamber.

[0056]

[0065] The individual deposition, etching, and removal steps of this technology may include any number of additional embodiments, steps, or features described below. It should be understood that any embodiment of any individual process may be incorporated into the accumulation method according to embodiments of this technology. Figure 6 shows exemplary steps of deposition method 600 that may be included in the accumulation method according to several embodiments of this technology. This method may be performed in various processing chambers, including the processing chamber 100 described above. Method 600 may include several optional steps. These steps may or may not be specifically associated with some embodiments of the method according to this technology. Furthermore, any embodiment of method 600 may be considered optional within a broader accumulation method into which any number of embodiments of method 600 may be incorporated. For example, many of the steps described are provided to offer a broader range of structure formation but may be performed by alternative methodologies that are not critical to this technology or would be easily understood.

[0057]

[0066] Method 600 may include additional steps before commencing the enumerated steps. For example, additional processing steps may include forming a structure on a semiconductor substrate, which may include both forming and removing material. The prior processing steps may be performed in the chamber in which Method 600 may be performed, or in one or more other processing chambers before supplying the substrate to the semiconductor processing chamber in which Method 600 may be performed. Nevertheless, Method 600 may optionally include supplying the semiconductor substrate to the processing area of ​​a semiconductor processing chamber, such as the processing chamber 100 described above, or to another chamber, which may include the components described above. The substrate may be a pedestal, such as a substrate support 104, and may be deposited on a substrate support, which may be located in the processing area of ​​a chamber, such as the processing space 120 described above.

[0058]

[0067] The substrate can be any number of materials on which the materials described above can be deposited. In some embodiments, optional processing steps, such as pretreatment, may be performed to prepare the surface of the substrate for deposition. For example, pretreatment may be performed to provide specific ligand terminations on the surface of the substrate to facilitate nucleation of the film to be deposited. For example, in non-limiting examples, other molecular ends, including any combination of these atoms or radicals such as hydrogen, oxygen, carbon, nitrogen, or amidogen or other functional groups, may be adsorbed, reacted, or formed on the surface of the substrate. In addition, material removal may be performed, such as reduction of native oxides or etching of the material, or any other steps may be performed to prepare one or more exposed surfaces of the substrate for deposition.

[0059]

[0068] In step 605, one or more precursors may be supplied to the processing area of ​​the chamber. For example, in an exemplary embodiment in which a boron-containing silicon film may be formed, a silicon-containing precursor and a boron-containing precursor may be supplied to the processing area of ​​the processing chamber. In some embodiments of the art, plasma-enhanced deposition may be performed to accelerate the reaction and deposition of the material. Some embodiments of the art may encompass the formation or deposition of silicon and boron materials that can be conventionally characterized by increased surface roughness compared to, for example, thermally produced silicon films. In some embodiments, the nucleation of these silicon and boron materials may form islands on the substrate. These islands may be formed three-dimensionally to different heights during initial film formation and maintained during film growth.

[0060]

[0069] Some embodiments of this technology may include providing an additional hydrogen-containing precursor in an optional step 610, which is provided together with silicon-containing and boron-containing precursors. The supplied precursors may all be used in step 615 to form a plasma within the processing area of ​​the semiconductor processing chamber. In step 620, the silicon and boron materials may be deposited on the substrate. By incorporating the hydrogen-containing precursor in some embodiments, the formation of islands during nucleation may be reduced or limited.

[0061]

[0070] By incorporating an additional hydrogen source, film modification or profile etching can be performed simultaneously with material deposition. For example, through reactions and / or physical interactions with features formed in silicon and boron materials, hydrogen radicals can trim island formation while a more uniform formation profile is generated. As a result, islands may not elongate as much as in conventional processes. To provide sufficient hydrogen radicals in the process, hydrogen-containing precursors may be included at a higher flow rate than one or both of the silicon-containing precursors or boron-containing precursors. For example, in some embodiments, the flow rate ratio of the hydrogen-containing precursor to the silicon-containing precursor and / or the boron-containing precursor, or both, is about 1:1 or higher, and in some embodiments, it may be about 2:1 or higher, about 3:1 or higher, about 4:1 or higher, about 5:1 or higher, about 6:1 or higher, about 8:1 or higher, about 10:1 or higher, about 15:1 or higher, about 20:1 or higher, about 25:1 or higher, about 30:1 or higher, about 35:1 or higher, about 40:1 or higher, about 45:1 or higher, about 50:1 or higher, or higher. As will be further described below, in some embodiments, the ratio of the hydrogen to the silicon and / or boron precursor is about 100:1 or higher, and further dilution may be performed to about 500:1 or higher, about 1,000:1 or higher, about 1,500:1 or higher, about 2,000:1 or higher, about 2,500:1 or higher, or higher.

[0062]

[0071] For example, depending on the precursor used, silicon-containing precursors may be supplied at a flow rate of approximately 500 sccm or less, and may be supplied at flow rates of approximately 400 sccm or less, approximately 300 sccm or less, approximately 200 sccm or less, approximately 100 sccm or less, approximately 90 sccm or less, approximately 80 sccm or less, approximately 70 sccm or less, approximately 60 sccm or less, approximately 50 sccm or less, or lower. Similarly, boron-containing precursors may be supplied at a flow rate of approximately 1000 sccm or less, and may be supplied at flow rates of approximately 800 sccm or less, approximately 600 sccm or less, approximately 500 sccm or less, approximately 450 sccm or less, approximately 400 sccm or less, approximately 350 sccm or less, approximately 300 sccm or less, approximately 250 sccm or less, approximately 200 sccm or less, or lower. Any additional ranges within these ranges, or combinations of the specified or unspecified numbers, may also be used.

[0063]

[0072] The hydrogen-containing precursor is supplied at a flow rate of approximately 1,000 sccm or more, and may be supplied at flow rates of approximately 1,200 sccm or more, approximately 1,400 sccm or more, approximately 1,600 sccm or more, approximately 1,800 sccm or more, approximately 2,000 sccm or more, approximately 2,200 sccm or more, approximately 2,400 sccm or more, approximately 2,600 sccm or more, approximately 2,800 sccm or more, approximately 3,000 sccm or more, or higher. Increasing the amount of hydrogen-containing precursor can further smooth the surface of the deposited membrane, but it may increase the amount of hydrogen incorporated into the deposited membrane. Therefore, in some embodiments, the hydrogen-containing precursor is supplied at a flow rate of about 4,000 sccm or less, and may be supplied at a flow rate of about 3,800 sccm or less, about 3,600 sccm or less, about 3,400 sccm or less, about 3,200 sccm or less, about 3,000 sccm or less, about 2,800 sccm or less, about 2,600 sccm or less, or lower. In addition, in some embodiments where higher dilution can be performed, the hydrogen-containing precursor is supplied at a flow rate of about 5,000 sccm or more, and may be supplied at a flow rate of about 10,000 sccm or more, about 15,000 sccm or more, about 20,000 sccm or more, about 25,000 sccm or more, or higher. In some embodiments, the flow rate of the silicon or boron precursor can be further reduced to 200 sccm or less, and may be reduced to about 150 sccm or less, about 100 sccm or less, about 50 sccm or less, about 30 sccm or less, about 20 sccm or less, about 10 sccm or less, or below.

[0064]

[0073] The film can be deposited on the substrate to any thickness. The surface roughness of the fabricated film is not limited to the problems during film nucleation described above. For example, film growth and plasma termination may also affect surface roughness in some embodiments of this technique. For instance, once sufficient film growth has occurred, the process may be terminated by extinguishing the plasma in the processing chamber, for example, by cutting off power to the electrode that generates the plasma. Plasma termination may also increase surface roughness by causing an increase in the amount of physical interaction of residual ions after deposition is complete. It may be assumed that both the nucleation effect and the plasma termination effect are constant regardless of the thickness of the film formed. However, tests have shown that the roughness of the deposited film increases as the film thickness increases. Consequently, a roughness effect occurs similarly during film growth, and the film roughness may further increase as the film thickness increases. Therefore, the resulting film may be characterized by an increase in roughness that can affect the uniformity of subsequent etching.

[0065]

[0074] For example, thermally produced silicon, such as polysilicon or other silicon materials, may be characterized by a relatively low average roughness, such as less than approximately 0.5 nm or less than approximately 0.2 nm. Alternatively, the film may be characterized by a range of relatively low roughness, such as the difference between the highest and lowest peaks on the formed film. For example, the roughness range may be less than or equal to approximately 1.5 nm or less, or less than or equal to approximately 1 nm. However, for silicon and boron films produced without using one or more embodiments of this technology, the average roughness may be greater than or equal to approximately 2 nm, 3 nm, or more for films of similar thickness, but as mentioned above, the roughness may increase with increasing film thickness. Furthermore, the roughness range of the produced silicon and boron materials is greater than or equal to approximately 10 nm, and again, depending on the film thickness, may be greater than or equal to approximately 15 nm. If such imbalances between films become large during subsequent etching operations, uniformity of the etching operation becomes a challenge, and additional operations, such as chemical-mechanical polishing, may be required.

[0066]

[0075] However, this technique can reduce or significantly reduce both the average roughness and roughness range of the resulting silicon and boron films by substantially co-etching using an additional hydrogen-containing precursor, or by performing one or more additional adjustments as further described below. The resulting films may be characterized by an average thickness of about 2 nm or less and by an average roughness of about 1.5 nm or less, about 1.0 nm or less, about 0.9 nm or less, about 0.8 nm or less, about 0.7 nm or less, about 0.6 nm or less, about 0.5 nm or less, about 0.4 nm or less, about 0.3 nm or less, about 0.2 nm or less, or less. In addition, in some embodiments, roughness can be substantially controlled regardless of film thickness. This may allow for the avoidance of additional chemical and mechanical polishing steps, as the deposited film can be characterized by any of the illustrated average roughness ranges. In addition, the roughness range across the deposited film is approximately 10 nm or less, and can be approximately 9 nm or less, approximately 8 nm or less, approximately 7 nm or less, approximately 6 nm or less, approximately 5 nm or less, approximately 4 nm or less, approximately 3 nm or less, approximately 2 nm or less, approximately 1 nm or less, or even lower. As a result, improved materials can be manufactured that offer advantages of films and masks compared to conventional materials and processes, and that may reduce the manufacturing process by limiting or reducing the number of polishing steps.

[0067]

[0076] With respect to silicon-containing precursors and boron-containing precursors, any number of precursors can be used in this technology. For example, silicon-containing precursors may include any silicon-containing material, such as organic silanes, which may include silanes, disilanes, and other materials including higher-order silanes. Additional silicon-containing materials may include silicon, carbon, oxygen, or nitrogen, such as trisilylamine. Boron-containing materials may include boranes such as borane and diborane, or other multi-center bonded boron materials, as well as any other boron-containing materials that can be used to produce silicon and boron-containing materials. For example, boron-containing materials may include dimethylamine borane, trimethylborane, triethylborane, or any other boron-containing material or combination of boron-containing materials. The incorporation of boron in the silicon film may be based on incorporation in any proportion. For example, the manufactured film includes the incorporation of approximately 5 atomic percent or more of boron, and in some embodiments, approximately 10 atomic percent or more of boron, approximately 15 atomic percent or more of boron, approximately 20 atomic percent or more of boron, approximately 25 atomic percent or more of boron, approximately 30 atomic percent or more of boron, approximately 35 atomic percent or more of boron, approximately 40 atomic percent or more of boron, approximately 45 atomic percent or more of boron, approximately 50 atomic percent or more of boron, and approximately 55 atomic percent or more of boron. This may include boron incorporation, such as boron incorporation of approximately 60 atomic% or more, boron incorporation of approximately 65 atomic% or more, boron incorporation of approximately 70 atomic% or more, boron incorporation of approximately 75 atomic% or more, boron incorporation of approximately 80 atomic% or more, boron incorporation of approximately 85 atomic% or more, boron incorporation of approximately 90 atomic% or more, and boron films that do not contain silicon and are essentially pure boron films, or films of boron and hydrogen, which may include boron incorporation of 100 atomic% or more.

[0068]

[0077] One or more additional aspects of the deposition can also be adjusted to improve the deposition aspect being performed. For example, plasma power can affect the degree of hydrogen dissociation. Any number of hydrogen-containing precursors can be used, and in some embodiments, diatomic hydrogen may be included. For some silicon and boron-containing materials, the material is sufficiently reactive at deposition temperatures that may involve minimal plasma enhancement. For example, some prior arts utilize plasma power of about 200 watts or less. This art utilizes higher or much higher plasma power, which can accelerate hydrogen dissociation, increase hydrogen radicals, and reduce roughness as previously described.

[0069]

[0078] For example, in some embodiments, the plasma power can be maintained at approximately 1,000 watts or more, and can be maintained at approximately 1,200 watts or more, approximately 1,400 watts or more, approximately 1,600 watts or more, approximately 1,800 watts or more, approximately 2,000 watts or more, approximately 2,200 watts or more, approximately 2,400 watts or more, approximately 2,600 watts or more, approximately 2,800 watts or more, approximately 3,000 watts or more, or above. This increase in plasma power can also improve the dissociation and activation of other precursors, and thus the deposition rate can also be improved. As a result, the film deposition rate can be comparable to, if not improved to, conventional deposition, despite the material being simultaneously etched during deposition. Then, simultaneous deposition and etching can be maintained continuously or sequentially for profile correction until the target film thickness is generated. Depending on the plasma process performed, the plasma power density can also be maintained, and frequency and power modulation can be enabled. For example, in some embodiments, the plasma power density is approximately 0.25 W / cm² 2 The above level is maintained, approximately 0.5 W / cm² 2 Above, approximately 1.0W / cm 2 Above, approximately 1.5W / cm 2 Above, approximately 2.0W / cm 2 Above, approximately 2.5W / cm 2 It may be maintained at or above this level.

[0070]

[0079] The substrate temperature can further affect deposition. For example, in some embodiments, the substrate may be maintained at a temperature of about 400°C or higher, and may be maintained at temperatures of about 420°C or higher, about 440°C or higher, about 460°C or higher, about 480°C or higher, about 500°C or higher, or higher. By performing deposition according to some embodiments of the art, hydrogen etching may be performed during deposition to reduce the roughness of the formed film. However, the amount of hydrogen radicals generated by the enhanced plasma and hydrogen supply may also increase the amount of hydrogen incorporated into the resulting film. This may increase the compressive stress within the film. For example, the deposited film (as-deposited film) may be characterized by a compressive stress of about -800 MPa or higher, which may be partly due to hydrogen incorporation. As a result, in some embodiments, method 600 may include a step to reduce hydrogen incorporation into the film.

[0071]

[0080] For example, in some embodiments, method 600 may include, in an optional step 625, thermal annealing of the formed silicon and boron-containing material. Deposition may be carried out at a first temperature, but thermal annealing may be carried out at a second temperature higher than the first temperature. For example, thermal annealing may be carried out at a temperature of about 480°C or higher. Thermal annealing may be carried out at a temperature of about 500°C or higher, about 510°C or higher, about 520°C or higher, about 530°C or higher, about 540°C or higher, about 550°C or higher, about 560°C or higher, about 570°C or higher, about 580°C or higher, about 590°C or higher, about 600°C or higher, or higher. Thermal annealing may be carried out for a period of about 0.5 minutes or more, about 1 minute or more, about 2 minutes or more, about 3 minutes or more, about 4 minutes or more, about 5 minutes or more, about 6 minutes or more, or longer.

[0072]

[0081] Thermal annealing can remove the amount of hydrogen incorporated into the membrane and relieve compressive stress. For example, in some embodiments, after thermal annealing, the compressive stress in the membrane can be maintained at approximately -700 MPa or less, approximately -650 MPa or less, approximately -600 MPa or less, approximately -550 MPa or less, approximately -500 MPa or less, approximately -450 MPa or less, approximately -400 MPa or less, approximately -350 MPa or less, approximately -300 MPa or less, approximately -250 MPa or less, approximately -200 MPa or less, approximately -150 MPa or less, approximately -100 MPa or less, or below.

[0073]

[0082] The pressure within the processing area can affect the amount of ionization and physical interactions occurring during deposition. Lowering the processing pressure may increase ion interactions. Therefore, in some embodiments, the processing pressure during deposition may be maintained at or below approximately 50 Torr, approximately 40 Torr, approximately 30 Torr, approximately 20 Torr, approximately 15 Torr, approximately 10 Torr, approximately 9 Torr, approximately 8 Torr, approximately 7 Torr, approximately 6 Torr, approximately 5 Torr, approximately 4 Torr, approximately 3 Torr, approximately 2 Torr, or below.

[0074]

[0083] Tests have shown that incorporating argon may increase roughness, and therefore, limiting or excluding argon may improve film roughness. However, tests have shown that excluding argon from the treatment precursor may increase film delamination. Therefore, in some embodiments, argon may nevertheless be included with silicon-containing and boron-containing precursors. To limit the effect on roughness, the flow rate ratio of argon precursor to hydrogen-containing precursor is maintained at approximately 2:1 or less, and may be maintained at approximately 1:1 or less, approximately 0.8:1 or less, approximately 0.7:1 or less, approximately 0.6:1 or less, approximately 0.5:1 or less, approximately 0.4:1 or less, approximately 0.3:1 or less, approximately 0.2:1 or less, approximately 0.1:1 or less, or lower.

[0075]

[0084] Combinations or further adjustments of processing parameters can also affect and improve additional aspects of the generated film. Incorporating boron into the hard mask film can improve selectivity for many films. Since the film stack contains more material related to both the hard mask release process and the subsequent film etching process, improving selectivity can reduce the number of additional steps performed. Increasing the crystallinity of the film can also improve etching selectivity, but conventional techniques have resulted in a decrease or deterioration of line edge roughness and line width roughness when increasing the crystallinity of the film. As a result, many techniques attempt to keep the film amorphous silicon. This technique can increase the crystallinity of the formed film, at least partially, thereby improving etching selectivity, but by limiting the crystallinity, this technique can maintain line edge roughness and line width roughness.

[0076]

[0085] When the hydrogen flow rate ratio increase according to the embodiment of this technology is applied to silicon and boron precursors, the degree of crystallinity may increase. However, by using the processing parameters described above, the degree of crystallinity can be maintained at approximately 50 Å or less, approximately 40 Å or less, approximately 30 Å or less, approximately 20 Å or less, approximately 15 Å or less, approximately 10 Å or less, approximately 7 Å or less, approximately 5 Å or less, approximately 3 Å or less, or below. However, if the degree of crystallinity increases by approximately 2 Å or more, improved etching selectivity can be obtained.

[0077]

[0086] However, an increase in the hydrogen content in the plasma can also increase the incorporation of hydrogen into the film. This can affect film stress, as mentioned earlier, and may also affect other film properties. For example, hard mask films are characterized by their extinction coefficient for different wavelengths of light, which can affect the lithography process. Amorphous silicon materials are characterized by an extinction coefficient of approximately 0.2 for certain parameters, which may allow lithography at film thicknesses up to approximately 800 nm based on lower reflectivity, but this can affect the view through the mask. Silicon and boron films are characterized by an increasing extinction coefficient for similar parameters, but the extinction coefficient can decrease, at least partially, as hydrogen incorporation increases. For example, with increasing boron incorporation, the extinction coefficient can increase to approximately 0.3 or higher, approximately 0.35 or higher, approximately 0.4 or higher, approximately 0.45 or higher, or even higher.

[0078]

[0087] A higher extinction coefficient can make lithography challenging and may require additional processing. For example, these increased extinction coefficients may limit the lithographic field of view to film thicknesses of approximately 400 nm or less, approximately 300 nm or less, or even lower. However, by increasing the hydrogen incorporation, the increased plasma density can be used to reduce the extinction coefficient to approximately 0.35 or less, approximately 0.33 or less, approximately 0.30 or less, approximately 0.28 or less, approximately 0.25 or less, or even lower. This may allow lithography to be extended to thicknesses of approximately 400 nm or more, approximately 450 nm or more, approximately 500 nm or more, or even higher, without performing additional alignment key opening operations. By increasing the temperature and plasma characteristics, it may be possible to form film structures that improve properties such as extinction coefficient and etching selectivity, even with increased hydrogen incorporation. Hydrogen incorporation can also be increased by processing at low temperatures, such as below 400°C or approximately 350°C, but differences in the film properties of such films produced may lead to further hydrogen gas release in subsequent processing, as mentioned earlier. By processing at higher temperatures, the thermal stability of the hydrogen-incorporated films formed as described above may be improved. In addition, by depositing according to embodiments of this technology, the roughness of silicon and boron-containing films can be reduced, improving the hard mask effect. During the subsequent etching in the optional step 630, the etching limit dimensions can be maintained more uniformly with this technology than if this technology were not implemented, as can be further described below. By reducing surface roughness, improved etching and structural development can be obtained.

[0079]

[0088] Once the silicon and boron materials are formed on the substrate, one or more additional steps may be performed to pattern the material. For example, an etching process may be performed to form one or more features through the silicon and boron-containing material. Figure 7 shows exemplary steps of an etching method 700 that may be included in the integration method according to several embodiments of the present art. The method may be performed in various processing chambers, including the processing chamber 200 described above. Method 700 may include several optional steps. These steps may or may not be specifically associated with some embodiments of the method according to the present art. Furthermore, any aspect of Method 700 may be considered an option within a broader integration method in which any number of aspects of Method 700 may be incorporated. For example, many of the steps described are to provide a broader range of structure formation but may be performed by alternative methodologies that are not important to the present art or would be easily understood.

[0080]

[0089] Method 700 may include additional steps before commencing the enumerated steps. For example, the additional processing steps may include forming a structure on a semiconductor substrate, which may include boron and silicon-containing materials, which may include both the formation and removal of materials. The prior processing steps may be performed in the chamber in which Method 700 may be performed, or in one or more other processing chambers before supplying the substrate to the semiconductor processing chamber in which Method 700 may be performed. Nevertheless, Method 700 may optionally include supplying the semiconductor substrate to a processing area of ​​a semiconductor processing chamber, such as the processing chamber 200 described above, or to another chamber, which may include the components described above. The substrate may be deposited on a substrate support located in the processing area of ​​a chamber, such as the processing area 201 described above, using a chuck such as an electrostatic chuck 222.

[0081]

[0090] The substrate is any number of materials on which materials can be deposited as described above, and may include boron and silicon-containing materials that can be deposited by one or more steps of Method 600 described above. In some embodiments, one or more additional steps may be performed before the start of Method 700. For example, an additional masking material may be deposited or formed on the boron and silicon-containing material to initiate pattern transfer. For example, an oxide or other mask layer may be formed on the boron and silicon-containing material as described above. Photolithography or other patterning may be performed to generate a pattern through the mask down to the level of the boron and silicon-containing material.

[0082]

[0091] Method 700 may include one or more steps for etching through a boron- and silicon-containing material. A bromine-containing precursor may be supplied to the processing area in step 705. Plasma is formed in the precursor in step 710, and the plasma emissions may etch through the boron- and silicon-containing material in step 715. The bromine precursor is any bromine-containing material, and in some embodiments may be or contain hydrogen bromide. Radical bromine-based materials may interact through the boron- and silicon-containing material to provide a clean, straight etching profile. In addition, bromine radicals may maintain a flat etching front profile within the material. However, the etching rate may be relatively slower than with other etchant precursors. As a result, in some embodiments, Method 700 may include additional steps utilizing one or more additional precursors. For example, a second etching process may be performed after etching a first amount of material with a bromine-containing precursor.

[0083]

[0092] For example, after etching using a certain amount of bromine, the chamber may be purged or the flow of bromine may be stopped. In step 720, a chlorine-containing precursor, such as diatomic chlorine or any other chlorine-containing precursor previously described, may be supplied to the processing area. In step 725, a plasma is formed from the precursor, and in step 730, a second etching may be performed using a radical chlorine species. Radical chlorine may etch faster than bromine, but chlorine may generate a pinched taper at the etching front, which may affect the critical dimensions of the entire material. This method may be repeated, or the process may be repeated to alternate between two etching processes, which may be characterized by a higher etching rate based on the chlorine etching process, while maintaining a flatter etching front based on the bromine etching process. The process may be looped any number of times, depending on the thickness of the boron and silicon-containing material, and may be looped about 2 or more times, about 10 or more times, about 25 or more times, about 50 or more times, about 100 or more times, about 200 or more times, or more. A greater number of loops allows for the creation of a cleaner pattern through the material, but a greater number of loops can increase the time required to perform the method. In some embodiments, the etching method may be started and ended at the bromine portion of the etching process. This can ensure that the critical dimensions of the bottom structure are better maintained.

[0084]

[0093] In some embodiments, by performing the loop process as described, the limit dimensions of patterns such as openings can be maintained more uniformly, both from a top-down perspective and across the entire substrate. For example, in some embodiments, the limit dimensions at the top or bottom of a feature are maintained across the substrate between the central and edge regions, and the diameter of the opening formed in the edge region is at least about 80% of the diameter of the opening formed in the center of the substrate, and may be at least about 85%, at least about 90%, at least about 95%, at least about 98%, or more than the diameter of the opening formed in the center of the substrate.

[0085]

[0094] Loop processes can inevitably increase the etching time of the process by adding time during the precursor switching step. Therefore, some embodiments of the Art may also utilize a continuous process using a single etchant mixture. Figure 8 shows exemplary steps of etching method 800 that may be included in the integration method according to some embodiments of the Art. The method may be performed in various processing chambers, including the processing chamber 200 described above. Method 800 may include several optional steps. These steps may or may not be specifically associated with some embodiments of the method according to the Art. Furthermore, any aspect of method 800 may be considered an option within a broader integration method in which any number of aspects of method 800 may be incorporated. For example, many of the steps described are provided to offer a broader range of structure formation but may be performed by alternative methodologies that are not important to the Art or would be easily understood.

[0086]

[0095] Method 800 may include additional steps before commencing the enumerated steps. For example, as with respect to Method 700 described above, the additional processing steps may include forming a structure on a semiconductor substrate containing boron and silicon-containing material, which may include both forming and removing the material. The prior processing steps may be performed in the chamber in which Method 800 may be performed, or in one or more other processing chambers before supplying the substrate to the semiconductor processing chamber in which Method 800 may be performed. Nevertheless, Method 800 may optionally include supplying the semiconductor substrate to a processing area of ​​a semiconductor processing chamber, such as the processing chamber 200 described above, or to another chamber that may contain the components described above. The substrate may be a chuck, such as an electrostatic chuck 222, and may be deposited on a substrate support located in the processing area of ​​a chamber, such as the processing area 201 described above. The substrate may include any of the materials described above, including boron and silicon-containing material, and a previously patterned upper layer mask structure.

[0087]

[0096] Method 800 may include providing an etchant mixture into a processing area of ​​a processing chamber in step 805. The etchant mixture may include one or more precursors that can work together to protect sidewall features during the etching process. In some embodiments, the etchant mixture may include a chlorine-containing precursor and an oxygen-containing precursor. The chlorine-containing precursor may include diatomic chlorine, as well as any other chlorine-containing precursors described above. The oxygen-containing precursor used in any step as described throughout this Art may include O2, N2O, NO2, O3, H2O, and any other oxygen-containing precursors. In some embodiments, the etchant mixture may also include a fluorine-containing precursor. This precursor may be or include any precursor described elsewhere in this Disclosure.

[0088]

[0097] In step 810, a plasma may be formed with an etchant mixture and any supplied carrier or inert precursor. The plasma may be formed at a first plasma output. A bias power may be applied in an optional step 815 while the plasma output is being applied. Plasma generation is formed from the plasma source as previously described and may be formed at a first plasma output. This allows the etchant precursor to dissociate in order to generate plasma emitters. The bias power may draw the plasma emitters into the structure, generating an anisotropic etching profile and maintaining the pattern through the structure. Etching may be performed for a period corresponding to the duty cycle of the bias power, as will be further described below. At the end of the first period, in step 820, the first plasma output may be increased to a second plasma output. The precursor may be continuously flowed while the plasma output is changing. In some embodiments, the bias power may be stopped during the second period in an optional step 825. Again, the second period is the remainder of the duty cycle applied to the bias power, and the first and second periods may correspond to the duration of the pulse frequency applied to the plasma output. Over the duration of the process and for a continuous period, the plasma emitters come into contact with the boron and silicon-containing material, which is etched in step 830. This can transfer a pattern onto the material, as previously described.

[0089]

[0098] As explained earlier, the applied bias can draw the etchant to the substrate, resulting in a more anisotropic etching process. Due to the reactivity of the etchant material, plasma emissions can remove other exposed materials, such as oxides on the sidewalls of the upper layer material. This can increase the limit dimensions of features and impair control of process uniformity. Incorporating oxygen-containing precursors can promote the redeposition of oxide materials removed during the process, performing passivation on the exposed surface to maintain limit dimensions. However, the etchant is more reactive than the passivation process and may continue to erode the limit dimensions. Therefore, this etching process can be performed using level-to-level plasma generation as described above, allowing for controlled etching while promoting passivation.

[0090]

[0099] If the bias power is stopped, chlorine etching continues, which can slow down the etching front. In addition, increasing the source plasma output can increase the plasma density, generating more oxygen radicals and potentially increasing passivation. Similarly, stopping the bias power can cause isotropic interactions with the sidewalls of the structure to be protected, which may result in additional passivation. By controlling the supply rate of the constituent precursor, the process can be run continuously while both etching and passivation occur during the constituent period of the pulse frequency. In some embodiments, the pulse frequency applied to one or both power supplies is about 100 Hz or higher, and may be about 250 Hz or higher, about 500 Hz or higher, about 1,000 Hz or higher, about 2,000 Hz or higher, or higher.

[0091]

[0100] During the pulse frequency, the source power can be maintained continuously while a duty cycle is applied to the bias power to control etching. For example, the bias power may be switched off according to the duty cycle while the first plasma output is increased after a set time for the duty cycle of the bias power. In one non-limiting example, the source power may be applied at the first plasma output at time T0, and the bias power may be applied at the first power at time T0. Thus, etching can be increased until the duty cycle switches the bias power off at time T1. Simultaneously with the switch off of the bias power, at time T1, the first plasma output may be switched from the first power to the second power. This can occur until time T2, which corresponds to the next T0 of the next period of the pulse at any of the frequencies, as described above. Thus, the time between time T0 and time T2 is one period at the pulse frequency, and time T1 can be the application of the duty cycle at the corresponding pulse frequency.

[0092]

[0101] The bias power can be applied at any power, up to approximately 2,000W, and may be approximately 1,500W or less, 1,400W or less, 1,300W or less, 1,200W or less, 1,100W or less, 1,000W or less, 900W or less, 800W or less, or lower. The duty cycle is approximately 50% or less, and in some embodiments may be approximately 45% or less, 40% or less, 35% or less, 30% or less, 25% or less, 20% or less, 15% or less, or lower. The plasma output of the plasma source may differ between the first and second periods. For example, in the first period, the plasma source power is approximately 1,000W or more, and may be approximately 1,100W or more, approximately 1,200W or more, approximately 1,300W or more, approximately 1,400W or more, approximately 1,500W or more, or higher. In some embodiments, the source power and bias power during the first period may be the same. In the second period, the source power may increase to approximately 2,000W or more, and to a second power of approximately 2,200W or more, approximately 2,400W or more, approximately 2,600W or more, approximately 2,800W or more, approximately 3,000W or more, or higher. The process may then be carried out continuously until etching is complete.

[0093]

[0102] In some embodiments, the substrate is maintained at a temperature of about 200°C or higher, and during the method, it may be maintained at a temperature of about 225°C or higher, about 250°C or higher, about 275°C or higher, about 300°C or higher, or higher. Maintaining a higher temperature allows volatile byproducts to be removed more easily as volatile substances and to become gaseous more easily. The limiting dimensions may be influenced by the specific structure formed, but in some embodiments, the formed openings are characterized by a diameter of about 50 nm or less, and may be characterized by a diameter of 40 nm or less, about 30 nm or less, about 20 nm or less, about 10 nm or less, or lower. Due to the etching rate that can be performed, the amount of byproducts generated may increase in some embodiments. By including a fluorine-containing precursor, mask clogging may be reduced because the additional etchant further decomposes the byproduct material and flows more easily from the generated pattern. In addition, the pressure inside the processing chamber is maintained at approximately 500 mTorr or less, and may be maintained at approximately 100 mTorr or less, approximately 50 mTorr or less, approximately 20 mTorr or less, or even lower.

[0094]

[0103] The etchant precursor may be provided in proportion to the fluorine-containing precursor in some embodiments of the present technology. For example, the mixture may contain a first amount of fluorine-containing precursor, a second amount of oxygen-containing precursor, and a third amount of chlorine-containing precursor. In some embodiments, the oxygen-containing precursor is provided at a flow rate of about twice or more the flow rate of the fluorine-containing precursor, and may be about three times or more, about four times or more, about five times or more, about six times or more, about seven times or more, about eight times or more, about nine times or more, about ten times or more, or more. For example, in some embodiments, the oxygen-containing precursor is flowed at a rate of about 25 sccm or more, and may be flowed at a rate of about 50 sccm or more, about 75 sccm or more, about 100 sccm or more, or more. The chlorine-containing precursor is supplied at a flow rate of approximately twice or more than that of the oxygen-containing precursor, and may be approximately four times or more, approximately six times or more, approximately eight times or more, approximately ten times or more, approximately twelve times or more, approximately fourteen times or more, approximately sixteen times or more, approximately twenty times or more, or more. For example, in some embodiments, the oxygen-containing precursor is flowed at a speed of approximately 250 sccm or more, and may be flowed at a speed of approximately 500 sccm or more, approximately 750 sccm or more, approximately 1,000 sccm or more, or more.

[0095]

[0104] After pattern transfer is complete, boron and silicon-containing materials may be removed from the substrate. Figure 9 shows an exemplary step of removal method 900, which may be included in the integration method according to several embodiments of the present technology. This method may be performed in various processing chambers, including the processing chamber 300 described above. Method 900 may include several optional steps. These steps may or may not be specifically associated with some embodiments of the method according to the present technology. Furthermore, any aspect of Method 900 may be considered an option within a broader integration method in which any number of aspects of Method 900 may be incorporated. For example, many of the steps are described to provide a broader range of structure formation, but may be performed by alternative methodologies that are not important to the present technology or would be easily understood. Method 900 may describe the steps schematically shown in Figures 10A-10B. These figures will be explained in conjunction with the steps of Method 900. The figures show only partial schematics, and it should be understood that the substrate may include any number of additional materials and features having various properties and aspects as shown in the figures.

[0096]

[0105] Method 900 may include additional steps before commencing the enumerated steps. For example, the additional processing steps may include additional removal steps or treatments through boron and silicon-containing materials, which may include both material formation and removal. The prior processing steps may be performed in the chamber in which Method 900 may be performed, or in one or more other processing chambers before supplying the substrate to the semiconductor processing chamber in which Method 900 may be performed. Nevertheless, Method 900 may optionally include supplying the semiconductor substrate to the processing area of ​​a semiconductor processing chamber such as the processing chamber 300 described above, or to another chamber which may include the components described above. The substrate may be a chuck such as a pedestal 303 and may be deposited on a substrate support which may be present in the processing area 304 of the chamber described above.

[0097]

[0106] A substrate after several processes have been performed becomes a substrate 1005 or structure 1000, which may represent one or more underlying structures. It should be understood that structure 1000 may not represent all layers, materials, or structures that may be formed beneath the indicated material. For example, substrate 1005 may represent a material on which one or more features may be formed and may represent additional masking or structural layers. Substrate 1005 may illustrate a boron and silicon-containing material 1006 that is removed after patterning. Figure 10A shows a first structure that may be provided, and Figure 10B shows a second structure that may be processed. In a structure such as that illustrated in Figure 10A, patterning may expose a contact structure 1008a. Trenches, openings, or features may be filled with protective material 1010 as illustrated. In a structure such as that illustrated in Figure 10B, patterning may leave the contact structure 1008b exposed during the removal process.

[0098]

[0107] In step 905, one or more etchant precursors may be supplied to the processing chamber, such as in the remote plasma region 327, as previously described. Plasma may be formed in this region in step 910 and flowed into the processing region to contact the boron and silicon-containing material in step 915 and remove it from other exposed structures. As shown in the figure, one or more materials may be exposed during the etching process, but etching of these exposed materials may be minimized. However, in some embodiments, the boron and silicon-containing material may be formed in a manner that extends the exposure to the material. For example, in some embodiments as shown, edge regions that may not be patterned may be characterized by a greater thickness of mask material than the central region. As a result, the removal process may completely expose the central patterned material while still removing material from the edge regions. Therefore, in some embodiments, the removal process may be adjusted to increase the etching rate so as to ensure that the etching selectivity for each exposed material is sufficiently high to limit damage to the structure, and further to limit the time required to remove the material from the substrate.

[0099]

[0108] The precursors used in this technology may include fluorine-containing precursors and additional precursors as described below. An exemplary fluorine-containing precursor is nitrogen trifluoride, which may be flowed into a remote plasma region. The remote plasma region is separated from the processing region but may be fluidically connected to it. Other sources of fluorine may be used with or instead of nitrogen trifluoride. Generally, the fluorine-containing precursors are flowed into the remote plasma region and may include at least one precursor selected from the group consisting of atomic fluorine, diatomic fluorine, nitrogen trifluoride, carbon tetrafluoride, hydrogen fluoride, xenon difluoride, fluorinated organic molecules or hydrocarbons such as fluoromethane or difluoromethane, and various other fluorine-containing precursors used or useful in semiconductor processing.

[0100]

[0109] In some embodiments of this technology, additional precursors may also be supplied along with a fluorine-containing precursor. For example, a hydrogen-containing precursor may be supplied, or one or more other precursors such as argon, nitrogen, helium, or other precursors. Hydrogen is readily ionizable and, in some embodiments, can facilitate processing and increase the ion density in the processing area, thereby increasing the formation of etchants. The hydrogen-containing precursor may be or may include hydrogen, hydrocarbons, or any hydrogen-containing precursor.

[0101]

[0110] Pressure and temperature can affect the process and etching rate. The pressure in the processing chamber is maintained at approximately 20 mTorr or less, and can be maintained at approximately 10 Torr or less, approximately 5 Torr or less, approximately 1 Torr or less, or below. The temperature of the substrate support is maintained at approximately 100°C or higher, which can increase the removal rate in some embodiments, and can be maintained at approximately 150°C or higher, approximately 175°C or higher, approximately 200°C or higher, approximately 225°C or higher, approximately 250°C or higher, or above. Plasma power can similarly affect the etching rate. In some embodiments, the removal process is performed at a capacitively coupled plasma power of approximately 2.0 kW or higher, and can be performed at a plasma power of approximately 2.5 kW or higher, approximately 3.0 kW or higher, approximately 3.5 kW or higher, approximately 4.0 kW or higher, or higher.

[0102]

[0111] The materials that may be exposed during removal may include several materials, such as metals for contact landing, such as tungsten. These materials may include several dielectric materials, such as silicon oxide, silicon nitride, and silicon carbonitride. In addition, in some embodiments, such as those illustrated in Figure 10A, the material supplied to the trench, opening, or feature may be, for example, titanium nitride or several other transition metal nitrides, or may include these. To limit the etching of the transition metal nitrides, an additional precursor, such as a nitrogen-containing precursor, may be supplied along with the etchant precursor. The nitrogen-containing precursor may include ammonia or any other nitrogen-containing material, and may suppress the etching of the transition metal nitrides while performing the removal of boron and silicon-containing materials with other etchant materials.

[0103]

[0112] By performing the processes described above, the etching selectivity of boron and boron-silicon materials to silicon oxide, silicon nitride, silicon carbonitride, and tungsten or other metals can be maintained at about 100:1 or higher, and can be increased to about 200:1 or higher, about 400:1 or higher, about 600:1 or higher, about 800:1 or higher, about 1,000:1 or higher, or higher. In some embodiments, one or more of these materials may remain substantially unetched while removing boron or boron-silicon-containing materials. In addition, the etching selectivity of boron and boron-silicon materials to titanium nitride can be maintained at about 20:1 or higher, and can be increased to about 40:1 or higher, about 80:1 or higher, about 100:1 or higher, about 150:1 or higher, about 200:1 or higher, or higher.

[0104]

[0113] By generating plasma emitters in a remote plasma region, ion filtration from the plasma emitters becomes possible while they are flowing through the electrodes as described above. This can increase the etching rate by reducing the impact component of etching. In addition, by utilizing the remote plasma region within the chamber instead of a remote plasma source unit outside the chamber, recombination and complete ionization of the constituent etchant material can be limited. High-plasma-power etching makes it possible to remove boron and silicon-containing materials at etching rates of approximately 30 nm / min or more, and can provide etching rates of approximately 35 nm / min or more, approximately 40 nm / min or more, approximately 45 nm / min or more, approximately 50 nm / min or more, approximately 55 nm / min or more, approximately 60 nm / min or more, approximately 65 nm / min or more, approximately 70 nm / min or more, approximately 75 nm / min or more, approximately 80 nm / min or more, or higher. This can limit interaction with other exposed materials, shorten the overall removal time during processing, and improve throughput. By executing processes according to several embodiments of this technology, process integration can reduce throughput and produce higher-quality devices compared to conventional technologies.

[0105]

[0114] In the preceding description, numerous details have been provided to provide an understanding of various embodiments of the Technology for explanatory purposes. However, it will be apparent to those skilled in the art that certain embodiments can be carried out without some of these details, or with additional details.

[0106]

[0115] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the above description should not be construed as limiting the scope of the Art. Moreover, while methods or processes may be described sequentially or stepwise, it should be understood that steps may be performed simultaneously or in an order different from that listed.

[0107]

[0116] Where a range of values ​​is given, unless explicitly stated otherwise in the context, each intervening value between the upper and lower limits of that range is specifically disclosed down to the smallest unit of the lower limit. This includes any smaller range between any listed or unlisted intervening values ​​within the listed range, and any other listed or intervening values ​​within that listed range. The upper and lower limits of such narrower ranges may be individually included in or excluded from that range. Each range in which either or both limit values ​​are included in a narrower range, or neither is included in a narrower range, is further encompassed in this art and covers any limit values ​​that are specifically excluded from the listed range. Where a listed range includes one or both limit values, it also includes ranges that exclude either or both of these included limit values.

[0108]

[0117] As used herein and in the claims, the singular forms “a,” “an,” and “the” include multiple references unless the context clearly indicates otherwise. Thus, for example, “a precursor” refers to multiple such precursors, and “the layer” refers to one or more layers and equivalents well known to those skilled in the art, and the same applies to other forms.

[0109]

[0118] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described features, integers, components, or steps, but not to exclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. Forming a plasma of an etchant mixture containing a chlorine-containing precursor and an oxygen-containing precursor, While forming the plasma with the first plasma output, the silicon and boron-containing material on the substrate placed within the processing area of ​​the semiconductor processing chamber is brought into contact with the plasma emitted from the etchant mixture. After the first period, the first plasma output is increased to a second plasma output to generate oxygen radicals and promote passivation in order to form one or more features on the substrate. including, Etching method.

2. The etching method according to claim 1, wherein the silicon and boron-containing material is characterized by a boron concentration of about 40 atomic percent or more.

3. The etchant mixture is Fluorine-containing precursors The etching method according to claim 1, further comprising the above, wherein the flow rate ratio of the fluorine-containing precursor to the oxygen-containing precursor to the chlorine-containing precursor is about 1:5:10 or more.

4. Applying bias power during the first period, The bias power is stopped after the first period. The etching method according to claim 1, further comprising:

5. The etching method according to claim 4, wherein the plasma is formed with a pulse frequency of approximately 500 Hz or higher.

6. The etching method according to claim 5, wherein the duty cycle of the bias power during the formation of the plasma is about 40% or less.

7. Forming a remote plasma of an etchant mixture containing a fluorine-containing precursor and a hydrogen-containing precursor, The method involves forming the plasma with a first plasma output while bringing a silicon and boron-containing material on a substrate located within the processing area of ​​a semiconductor processing chamber into contact with the plasma emissions of the etchant mixture, wherein the silicon and boron-containing material defines one or more features on the substrate, and bringing the silicon and boron-containing material into contact with the plasma emissions of the etchant mixture. After the first period, the first plasma output is increased to a second plasma output to generate oxygen radicals and promote passivation in order to form one or more features on the substrate. After forming the pattern, the silicon and boron-containing material is removed at a rate of approximately 35 nm / min or more. including, Etching method.

8. The etching method according to claim 7, wherein the temperature of the substrate during removal is maintained at approximately 200°C or higher, and the remote plasma is formed with a plasma output of approximately 2.0 kW or higher.

9. The etching method according to claim 7, wherein the substrate further comprises exposed areas of titanium nitride, and the etchant mixture further comprises ammonia.

10. Forming a plasma of an etchant mixture containing a chlorine-containing precursor and an oxygen-containing precursor, While forming the plasma with the first plasma output, the silicon and boron-containing material on the substrate placed within the processing area of ​​the semiconductor processing chamber is brought into contact with the plasma emitted from the etchant mixture. After the first period, the first plasma output is increased to the second plasma output in order to form one or more features on the substrate. Includes, The etching method is characterized by the silicon and boron-containing material having a boron concentration of approximately 40 atomic percent or more.

11. Forming a plasma of an etchant mixture containing a chlorine-containing precursor and an oxygen-containing precursor, While forming the plasma with the first plasma output, the silicon and boron-containing material on the substrate placed within the processing area of ​​the semiconductor processing chamber is brought into contact with the plasma emitted from the etchant mixture. After the first period, the first plasma output is increased to the second plasma output in order to form one or more features on the substrate. Includes, The etchant mixture is An etching method further comprising a fluorine-containing precursor, wherein the flow rate ratio of the fluorine-containing precursor to the oxygen-containing precursor to the chlorine-containing precursor is approximately 1:5:10 or higher.

12. Forming a plasma of an etchant mixture containing a chlorine-containing precursor and an oxygen-containing precursor, While forming the plasma with the first plasma output, the silicon and boron-containing material on the substrate placed within the processing area of ​​the semiconductor processing chamber is brought into contact with the plasma emitted from the etchant mixture. After the first period, the first plasma output is increased to the second plasma output in order to form one or more features on the substrate. Includes, Applying bias power during the first period, The bias power is stopped after the first period. An etching method further including the following.

13. The etching method according to claim 12, wherein the plasma is formed at a pulse frequency of about 500 Hz or higher.

14. The etching method according to claim 13, wherein the duty cycle of the bias power during the formation of the plasma is about 40% or less.

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