Inter-chip interconnection using bridge chips

Abstract

A method of fabricating a bridge multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface having a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips secured by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two of the plurality of chips secured by the molding material.

Description

Technical Field

[0001] The present disclosure generally relates to multi-chip interconnection technology, and more particularly to a method for fabricating a bridge multi-chip assembly structure, and a bridge multi-chip assembly structure fabricated by the method. Background Art

[0002] Current computing technology requires high-density interconnections between multiple chips, such as between a central processing unit (CPU) and a memory, and between an artificial intelligence (AI) accelerator and a memory. One structure for interconnecting multiple chips is a bridge structure, in which the multiple chips are connected by a bridge chip that implements high-density interconnection.

[0003] An Embedded Multi-die Interconnect Bridge (EMIB) structure, in which a small silicon die is embedded in an organic substrate under the edges of two interconnected dies, has been used as a structure for interconnecting multiple chips. However, such a structure has assembly problems. For example, due to the difference in coefficient of thermal expansion between the chip and the organic substrate, the mechanical stress around the joint between the chip and the bridge die is relatively large. Such mechanical stress may cause failure during the bonding process between the chip and the organic substrate, and deteriorates the yield of packaged products. Therefore, it is desirable to develop a novel multi-chip interconnection technology that allows multiple chips to be connected by a bridge chip while reducing the mechanical stress generated around the joint between the chips and the bridge chip. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a method for fabricating a bridge multichip assembly structure is provided. The method comprises preparing a carrier substrate. The method further comprises arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface on which a set of terminals is formed. The method further comprises depositing a molding material between the plurality of chips and on the carrier substrate. The method further comprises removing the carrier substrate from the plurality of chips fixed with the molding material. The method further comprises bonding a bridge chip to corresponding sets of terminals of at least two of the plurality of chips fixed with the molding material.

[0005] The method according to the embodiments of the present disclosure makes it possible to fabricate a bridge multi-chip assembly structure in which multiple chips are connected by bridge chips, while reducing the stress generated around the joint between the chips and bridge chips by firmly fixing the multiple chips together.

[0006] According to at least one embodiment, the front surface of each chip may include a set of bumps for connection to an organic substrate. Multiple chips may be arranged on a layer of carrier substrate such that the front surface of each chip faces the carrier substrate. Preparing the carrier substrate may include preparing the carrier substrate, coating the carrier substrate with a resin material, and patterning the resin material such that when the multiple chips are arranged and the molding material is deposited, it produces a layer of carrier substrate having space to accommodate the set of bumps of each chip.

[0007] In such embodiments, the front surface of the chip is not embedded in the molding material, and the set of bumps prevents deformation even if the set of bumps is formed on the chip before the chip is placed and the molding material is deposited.

[0008] According to at least one embodiment, the method may further include forming a set of bumps on the front surface of a plurality of chips fixed with a molding material for connection to an organic substrate. In such embodiments, the carrier substrate layer may be an adhesive layer.

[0009] According to at least one embodiment, the front surface of each chip may include a set of bumps for connection to an organic substrate. The distance between the back surface of the bridge chip and the plane of the front surfaces of the multiple chips, or the sum of the thickness of the bridge chip and the height of the joint between the chips and the bridge chip, may be less than the height of the bumps. In such embodiments, this eliminates the need to form recesses, cavities, or trenches in the organic substrate to avoid interference between the bridge chip and the organic substrate, thereby reducing manufacturing costs.

[0010] According to at least one embodiment, installing a bridge chip may include forming a joint between two or more of the multiple chips and the bridge chip via a corresponding set of terminals. Installing a bridge chip may further include applying an underfill material to at least the locations corresponding to the joint between the bridge chip and two or more of the multiple chips. In such embodiments, two or more of the multiple chips and the bridge chip are further firmly fixed to each other before bonding to an organic substrate.

[0011] According to at least one embodiment, depositing the molding material may include depositing the molding material in at least the gaps between a plurality of chips such that the back surface of each chip is exposed. In such embodiments, the resulting structure is suitable for high-performance chips because the exposed back surface of the chip is available for heat dissipation (for example, by attaching a heat sink to the back surface of the chip).

[0012] According to at least one embodiment, depositing the molding material may include depositing the molding material between and on top of multiple chips. Depositing the molding material may further include thinning at least the molding material from the back of the chips so that the pre-formed multi-chip structure, which includes multiple chips and a portion of the molding material, has a uniform thickness. In such embodiments, variations or deviations in the thickness of the chips, or both, become acceptable.

[0013] According to at least one embodiment, the carrier substrate may be in wafer or panel form, and when a molding material is deposited, the wafer or panel-shaped structure may come to contain multiple chips and a portion of the molding material. The method may further include dicing the wafer or panel-shaped structure to obtain a single bridge multi-chip assembly. In such embodiments, a wafer-level fabrication process becomes available, which allows for improved alignment accuracy between chips and between each chip and the bridge chip, as well as improved fabrication efficiency.

[0014] According to at least one embodiment, the front surface of each chip may include a set of bumps for connection to an organic substrate, and the carrier substrate may include an array of micropads on which each chip will be placed. Placing multiple chips may include temporarily fixing the set of bumps and the array of micropads. Removing the carrier substrate and layers from the multiple chips may include debonding the array of micropads from the set of bumps. In such embodiments, the multiple chips can be firmly bonded to the carrier substrate during the deposition of the molding material.

[0015] According to another embodiment of the present disclosure, a bridge multichip assembly structure is provided. The bridge multichip assembly structure includes a plurality of chips arranged in a predetermined layout. Each chip has a front surface including a set of terminals. The bridge multichip assembly structure further includes a molding material for securing the plurality of chips and exposing the front surface of each chip. The bridge multichip assembly structure further includes a bridge chip that connects at least two of the plurality of chips via corresponding sets of terminals.

[0016] In such embodiments, the entire front surface of each chip is not covered with molding material. In such embodiments, the bridge multi-chip assembly structure can reduce the stress generated around the joints between chips and bridge chips during its manufacturing process. Thus, its manufacturing yield can be improved.

[0017] According to at least one embodiment, the front surface of each chip may further include a set of joints (i.e., chip-substrate joints) that connect to an organic substrate. The distance between the back surface of the bridge chip and the plane of the front surfaces of the multiple chips, or the sum of the thickness of the bridge chip and the height of the joint between the chip and the bridge chip (i.e., chip-bridge joint), may be less than the height of the joint (i.e., chip-substrate joint). In such embodiments, this eliminates the need to form recesses, cavities, or trenches in the organic substrate to avoid interference with the bridge chip, thereby reducing manufacturing costs.

[0018] Another embodiment of the present disclosure discloses a method for manufacturing a multi-chip assembly structure. The method comprises preparing a carrier substrate. The method further comprises arranging a plurality of chips on the carrier substrate. Each chip has a front surface on which a set of terminals is formed. Each chip has a back surface opposite to the front surface. The chips among the plurality have a uniform chip thickness between their respective front and back surfaces. The method further comprises placing a mold in close contact with the back surfaces of the plurality of chips. The method further comprises depositing the molding material such that the molding material is in contact with the mold, between the plurality of chips, and on the carrier substrate. The method further comprises removing the carrier substrate from the plurality of chips fixed with the molding material.

[0019] In such embodiments, the mold can be used to facilitate the deposition of the molding material, which can be a simpler and more efficient method for depositing the molding material in a desired arrangement. In such embodiments, the back surface of a chip having substantially uniform chip thickness (as used herein, a chip having substantially uniform chip thickness may have variations in chip thickness, the variations being negligible, or having no impact on the resulting structure, or both) may be easily exposed by simply removing the mold.

[0020] Another embodiment of the present disclosure discloses a method for manufacturing a multi-chip assembly structure. The method comprises preparing a carrier substrate. The method further comprises arranging a plurality of chips on the carrier substrate. Each chip has a front surface on which a set of terminals is formed. Each chip has a back surface opposite to the front surface. The chips of the plurality have different chip thicknesses between their respective front and back surfaces. The method further comprises arranging a mold with space between the back surfaces of the plurality of chips. The method further comprises depositing a molding material such that the molding material is in contact with the mold, between the plurality of chips, and on the carrier substrate. The method further comprises removing the carrier substrate from the plurality of chips fixed with the molding material.

[0021] In such embodiments, the mold can be used to facilitate the deposition of the molding material, which can be a simpler and more efficient method for depositing the molding material in the desired arrangement. In such embodiments, the back surfaces of chips with differences in thickness, which are significant, or which would have an impact on the resulting structure, or both, may be easily exposed by removing the mold and the material until the desired back surface is exposed. Thus, in such embodiments, differences in chip thickness become acceptable.

[0022] Another embodiment of the present disclosure discloses a method for manufacturing a multi-chip assembly structure. The method comprises preparing a carrier substrate having a surface. The carrier substrate includes a release layer disposed in direct contact with the surface and a pattern layer disposed in direct contact with the release layer. The method further comprises arranging a plurality of chips on the layers of the carrier substrate. Each chip has a front surface on which a set of terminals is formed. The method further comprises depositing a molding material between the plurality of chips and on the pattern layer of the carrier substrate. The method further comprises removing the carrier substrate and the release layer from the plurality of chips fixed with the molding material.

[0023] In such embodiments, the method does not require the use of a mold, which can be advantageous in certain situations by providing flexibility in the deposition of the molding material. More specifically, in such embodiments, it is possible to deposit the molding material in such a manner that only the gaps between adjacent chips are filled, while the space around the chips is not filled with the molding material.

[0024] The above summary is not intended to describe any of the illustrated embodiments or implementations of the Disclosure. Additional features and benefits are realized through the technology of the Disclosure. Other embodiments and aspects of the Disclosure are described in detail herein and are deemed to be part of the claimed disclosure.

[0025] The drawings contained in the present disclosure are incorporated herein and form a part of the present specification. The drawings, together with the description, illustrate embodiments of the present disclosure and serve to explain the principles of the present disclosure. It should be noted that the drawings only illustrate typical embodiments, and do not limit the present disclosure. It should also be noted that the sizes and relative positions of elements and layers in the drawings are not necessarily drawn to scale. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] [Figure 1] Fig. 1 is a flowchart of an example of a method for fabricating a bridge multi-chip assembly structure in which a plurality of chips are interconnected by a bridge chip according to an embodiment of the present disclosure. [Figure 2A] Fig. 2 is a schematic cross-sectional view of a bridge multi-chip assembly structure after being bonded to an organic substrate, according to an embodiment of the present disclosure. [Figure 2B] Fig. 3 is a schematic top view of a bridge multi-chip assembly structure after being bonded to an organic substrate, according to an embodiment of the present disclosure. [Figure 3A] Fig. 4 is a schematic cross-sectional view of a bridge multi-chip assembly structure before being bonded to an organic substrate, according to an embodiment of the present disclosure. [Figure 3B] Fig. 5 is a schematic top view of a bridge multi-chip assembly structure before being bonded to an organic substrate, according to an embodiment of the present disclosure. [Figure 4] Figs. 6(A) to 6(G) are diagrams of examples of components after implementation of a part of a process for manufacturing a bridge multi-chip assembly structure according to an embodiment of the present disclosure. [Figure 5A] Fig. 7 is a schematic cross-sectional view of a patterned layer formed on a carrier substrate during a process according to an embodiment of the present disclosure. [Figure 5B] Fig. 8 is a schematic top view of a patterned layer formed on a carrier substrate during a process according to an embodiment of the present disclosure. [Figure 6]Figures (A) to (F) are diagrams of examples of components after some steps of the process for manufacturing a bridge multichip assembly structure according to embodiments of the present disclosure. [Figure 7] (A) to (C) are diagrams of examples of components after some steps of the process for depositing molding material between and around multiple chips, and on pattern layers formed on a carrier substrate, according to embodiments of the present disclosure. [Figure 8] (A) to (C) are diagrams of examples of components after part of another process for depositing molding material between and around a plurality of chips and on a pattern layer formed on a carrier substrate, according to embodiments of the present disclosure. [Figure 9A] This figure shows an example of depositing molding material between and around multiple chips, and on a pattern layer formed on a carrier substrate, according to an embodiment of the present disclosure. [Figure 9B] This figure shows an example of a structure used to securely fix multiple chips to a pattern layer on a carrier substrate, according to embodiments of the present disclosure. [Figure 10] (A) to (G) are diagrams illustrating examples of components after some steps of the process for manufacturing a bridge multichip assembly structure according to embodiments of the present disclosure. [Figure 11] This is a schematic cross-sectional view of a bridge multichip assembly structure after bonding to a recessed organic substrate according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0027] In the following, this disclosure will be described in relation to specific embodiments, but it will be understood by those skilled in the art that the embodiments described herein are merely illustrative and are not intended to limit the scope of this disclosure.

[0028] One or more embodiments of this disclosure relate to a method for fabricating a bridge multichip assembly structure that interconnects multiple chips using bridge chips, and a bridge multichip assembly structure fabricated by this method.

[0029] Each chip to be bridged has a first surface on which a set of terminals is formed, and a second surface opposite the first surface. The set of terminals on each chip is used for bridging. The first surface on which the set of terminals for bridging is formed may be called the "front," and the second surface opposite the front may be called the "back." In certain embodiments, the front of each chip also includes a set of bumps used for connecting to an organic substrate. The terminals may be of any suitable form. In certain embodiments, the set of terminals for bridging is a set of contact pads, with or without pre-soldering.

[0030] Figure 1 shows a flowchart of an example of Method 10 for fabricating a bridge multi-chip assembly structure that interconnects multiple chips using bridge chips according to embodiments of the present disclosure. Method 10 includes, in operation 12, preparing a carrier substrate having layers. Method 10 further includes, in operation 14, arranging multiple chips on the layers of the carrier substrate in a predetermined layout. Method 10 further includes, in operation 16, depositing molding material between the multiple chips and on the layers of the carrier substrate. Method 10 further includes, in operation 18, removing the carrier substrate and layers from the multiple chips fixed with molding material. Method 10 further includes, in operation 20, bonding bridge chips to two or more of the multiple chips fixed with molding material via corresponding sets of terminals.

[0031] Referring to Figures 2A-2B and 3A-3B, diagrams of bridge multichip assembly structures according to examples of embodiments of the present disclosure are shown.

[0032] Figures 2A and 2B show a bridge multi-chip assembly structure 150 containing four chips 100A to 100D bonded to an organic substrate 140. Figures 3A and 3B show the bridge multi-chip assembly structure 150 before bonding to the organic substrate 140. The bridge multi-chip assembly structure 150 shown in Figures 2A to 2B and 3A to 3B includes an interconnection structure for interconnecting the four chips 100A to 100D by three bridge chips 120AB, 120AC, and 120BD. However, this is merely an example. The number of chips to be interconnected is not limited, nor is the number of bridge chips to be used to interconnect the chips. In a particular example, a structure may also be envisioned that includes four chips bridged by a single bridge chip overlapping each corner of the four chips. In general, a bridge multi-chip assembly structure according to embodiments of the present disclosure is a structure that interconnects two or more chips with one or more bridge chips.

[0033] Chips 100A to 100D are sometimes collectively referred to as chip 100. Each of chips 100A to 100D may also be simply referred to as chip 100, even without a corresponding letter, when the identification of a specific chip is not important. Similarly, bridge chips 120AB, 120AC, and 120BD are sometimes collectively referred to as bridge chip 120. Each of the bridge chips may also be simply referred to as bridge chip 120, even without a corresponding letter, when the identification of a specific bridge chip is not important.

[0034] Figures 2A and 3A show cross-sectional views of the bridge multi-chip assembly structure 150 before and after bonding to the organic substrate 140, respectively. Figure 2B shows a top view of the bridge multi-chip assembly structure 150 after bonding to the organic substrate 140. Figure 3B shows a bottom view of the bridge multi-chip assembly structure 150 before bonding to the organic substrate 140. Note that the cross-sectional views shown in Figures 2A and 3A correspond to the cross-sections represented by the dashed lines A to A' shown in the top and bottom views of Figures 2B and 3B, respectively.

[0035] The bridge multi-chip assembly structure 150 shown in Figures 2A and 2B includes four chips 100A, 100B, 100C, and 100D, as well as three bridge chips 120AB, 120AC, and 120BD. Each bridge chip 120 overlaps with and connects two of the chips 100A-100D. For example, bridge chip 120AB connects two adjacent chips 100A and 100B via corresponding chip-bridge joints 130A and 130B. Bridge chip 120AC connects two adjacent chips 100A and 100C, and bridge chip 120BD connects the other two adjacent chips 100B and 100D. In the bridge multi-chip assembly structure 150 shown in Figures 2A-2B and 3A-3B, chip 100A is connected to the adjacent chip 100C by bridge chip 120AC, chip 100B is connected to the adjacent chip 100D by bridge chip 120BD, and chips 100A and 100B are connected to each other by bridge chip 120AB. However, the connection configuration between the multiple chips 100 is not limited, and any connection configuration may be assumed.

[0036] Each chip 100 has a front surface 102A and a back surface 104A. The four chips 100A to 100D are bonded upside down (for example, with the front surface facing downwards) to the organic substrate 140, as shown in Figure 2A. The four chips 100A to 100D are arranged in a predetermined layout, as shown in Figure 2B. Each bridge chip 120 is positioned on the front surface 102 of two adjacent chips 100.

[0037] Each chip 100 may include, but is not limited to, a semiconductor chip (also called a "die") containing an integrated circuit. The integrated circuit of each chip 100 may include electrical elements, electro-optical elements, or electromagnetic elements fabricated therein, or combinations thereof, and wiring for connecting these elements to terminals formed on the front surface 102A of the chip 100. Each chip 100 may have one or more processor functions, such as a central processing unit (CPU), a digital signal processor (DSP), a general-purpose computing-on-graphics processing unit (GPGPU), memory, an AI accelerator, or a system-on-a-chip (SoC). Each chip 100 may be made from a semiconductor material, such as Si, SiGe, Ge, GaAs, GaP, InSb, or another semiconductor material having similar related properties. Such semiconductor chips generally have a low coefficient of thermal expansion (CTE).

[0038] In the embodiments shown in Figures 2A and 2B and Figures 3A and 3B, the bridge multi-chip assembly structure 150 is a heterogeneous integrated package in which at least two chips having different functions are integrated into one package. However, in other embodiments, the bridge multi-chip assembly structure 150 may be a homogeneous integrated package in which multiple chips having the same function are integrated into one package. Furthermore, in yet another embodiment, the bridge multi-chip assembly structure 150 may be a semi-finished product of such a homogeneous or heterogeneous integrated package.

[0039] The front panel 102 includes a set of terminals for bridging (note that in Figures 2A and 2B, a set of chip-bridge joints 130 is already formed on the set of terminals of each chip 100), as well as a set of bumps for connecting to the organic substrate 140 (note that in Figures 2A and 2B, a set of chip-substrate joints 146 is already formed by using the set of bumps of each chip 100). The terminals may be of any suitable form, including pads (with or without pre-soldering), bumps, etc. The bumps for connecting to the organic substrate 140 may be controlled collapse chip connection (C4) solder bumps.

[0040] Multiple chips 100 are surrounded by expansion portions 110 made from a molding material, which firmly secure the chips 100 to each other. The expansion portions 110 are formed between any pair of adjacent chips 100 and around the multiple chips 100. In the embodiments described, as shown in Figures 2A and 2B and 3A and 3B, the multiple chips 100 are incorporated into the expansion portions 110 to give them the shape of a single chip. The expansion portions 110 extend the area of ​​the front surface 102 of the chips 100. As shown in Figure 3A, the portion of the expansion portion 110 that fills the gaps between the chips 100 is called the gap portion 110G, while the portion of the expansion portion 110 that fills around the multiple chips 100 is called the peripheral portion 110P. The structure 114 including the multiple chips 100 and the expansion portions 110 surrounding the multiple chips 100 is called a pre-molded multi-chip structure. The thickness of the pre-formed multi-chip structure 114 is preferably substantially uniform.

[0041] The extension portion 110 is made from a molding material, which may include, but is not limited to, a thermosetting resin, a thermoplastic resin, or a composite compound. In certain embodiments, it may be preferable to use an epoxy-based resin material containing epoxy resin as the main component. The molding material may also include fillers in addition to the resin material to firmly fix the multiple chips 100 together.

[0042] In the embodiment described, the back surface 104 of the chip 100 is exposed from the molding material. Such a structure in which the back surface 104 of the chip 100 is exposed from the molding material (and further exposed from the package) is suitable for high-performance chips because the exposed back surface 104 can be used for heat dissipation. For example, a heat sink may be attached to the back surface 104 of the chip 100.

[0043] Each bridge chip 120 may include, but is not limited to, semiconductor chips to which interconnections are fabricated. A bridge chip 120 (e.g., 120AB) may interconnect each terminal formed on one side to a corresponding terminal formed on the other side, such that each terminal formed on one side is coupled to one chip (e.g., 100A) and the corresponding terminal formed on the other side is coupled to another chip (e.g., 100B).

[0044] In certain embodiments, each bridge chip 120 may be made from a semiconductor material such as Si, SiGe, Ge, GaAs, GaP, or InSb. As shown in Figure 3A, the bridge chip 120AB may also have a front surface 122AB and a back surface 124AB opposite the front surface 122AB. Each bridge chip 120 may have a surface as indicated in the figure by the letters corresponding to each bridge chip 120. The front surface 122AB is the surface on which the set of chip-bridge joints 130 is formed. The chip-bridge joints 130 of the bridge chip 120AB may be divided into two subsets, including a first subset 130A for connecting to chip 100A and a second subset 130B for connecting to chip 100B.

[0045] The bridge tip 120 is generally smaller than the tip 100 that will be bridged. In the bridge multi-tip assembly structure 150, the bridge tip 120 is bonded at its end to both of the two adjacent tips 100 by a set of tip-bridge joints 130A, 130B. Each of the tip-bridge joints 130 may be a microbump much smaller than a typical C4 bump.

[0046] As shown in Figures 2A, 3A, and 3B, the bridge multi-chip assembly structure 150 further includes underfill material 132 formed around the chip-bridge joint 130 between the bridge chip 120 and the corresponding adjacent chip 100. The underfill material 132 is indicated in the figures with letters corresponding to each bridge chip 120. The underfill material 132 (e.g., 132AB) encloses the chip-bridge joint 130 (e.g., 130A, 130B) and firmly secures the bridge chip 120 (e.g., 120AB) and the corresponding adjacent chip 100 (e.g., 100A, 100B) to each other. An example of the underfill material 132 may include an epoxy-based resin material.

[0047] The gap portion 110G of the extension portion 110 that secures two adjacent chips 100 (e.g., 100A, 100B) has an interface 112 that contacts the corresponding underfill material 132. The interface 112 is substantially coplanar with the plane of the front surface 102 (e.g., 102A) of the two adjacent chips 100 (e.g., 100A, 100B).

[0048] As shown in Figure 3B, before bonding to the organic substrate 140, there is a set of bumps 106 for each chip 100 of the bridge multi-chip assembly structure 150. The bumps 106 are indicated in the figure with letters corresponding to each chip 100. Each bump 106 may be any suitable form, including but not limited to solder bumps and solder-capped Cu pillar bumps. Each bump 106 is to become a chip-substrate joint 146 after bonding to the organic substrate 140, as shown in Figures 2A and 2B. The set of bumps 106 for each chip 100 (and the resulting chip-substrate joint 146) forms a two-dimensional array with one or more overlapping notch areas of the corresponding bridge chips 120. The joint 146 is indicated in the figure with letters corresponding to each chip 100. A set of chip-bridge joints 130 (e.g., 130A) for a specific chip 100 (e.g., 100A) and a specific bridge chip 120 (e.g., 120AB) also forms a two-dimensional array placed in the notch areas of a two-dimensional array of bumps 106 (e.g., 106A) of chip 100 (e.g., 100A). Each notch area is placed around a position corresponding to the center of two adjacent chips 100 (e.g., 100A, 100B).

[0049] In a specific example, each chip 100 may be approximately square, with dimensions of approximately 10-30 mm x approximately 10-30 mm, and a thickness of approximately 750-800 micrometers when considering a 300 mm wafer, or 50 micrometers when considering back grinding. Each chip 100 may have bumps, for example, with a pitch of approximately 100-200 micrometers, a diameter of approximately 50-100 micrometers, and a height of approximately 50-100 micrometers.

[0050] In certain examples, the bridge tip 120 may have dimensions of approximately 1 to 5 millimeters x approximately 2 to 10 millimeters and a thickness of approximately 30 to 250 micrometers. The bridge tip 120 may have microbumps with a pitch of approximately 20 to 80 micrometers, a diameter of approximately 10 to 40 micrometers, and a height of approximately 10 to 40 micrometers.

[0051] In certain embodiments, the distance between the back surface 124 of the bridge chip 120 and the plane of the front surface 102 of the adjacent chip 100, or the sum of the thickness of the bridge chip and the height of the microbump or joint between the chip 100 and the bridge chip 120, is less than the height of the bump 106 or joint 146 between the chip 100 and the organic substrate 140.

[0052] The thinner the bridge tip 120, the more fragile it becomes. Therefore, the bridge tip 120 generally needs to have a certain minimum thickness to withstand the mechanical stress acting on it. In particular, the force acting on the periphery of the bridge tip 120 increases relatively when the adjacent tip 100 bonded to the bridge tip 120 is separated. Furthermore, the mechanical stress increases relatively as the CTE difference between the tip 100 and the organic substrate 140 increases. However, if the bridge tip 120 is thicker than a certain thickness, it will no longer fit into the gap between the tip 100 and the organic substrate 140, as the gap distance is limited by the height of the bump 106 or joint 146.

[0053] Therefore, one method for accommodating thicker bridge chips may include forming recesses, cavities, or trenches on the front surface of the organic substrate to avoid interference between the thicker bridge chips and the organic substrate. In contrast, if there is an extended portion 110 of the molding material (in particular, its gap portion 110G) that firmly secures multiple chips 100, thinner bridge chips become possible, thereby eliminating the need to form such recesses, cavities, or trenches in the organic substrate 140.

[0054] As shown in Figure 2A, the bridge multichip assembly structure 150 does not contain any recesses, cavities, or trenches beneath the bridge chip 120. This reduces the manufacturing cost of the bridge multichip assembly structure. However, this does not prevent the formation of recesses, cavities, or trenches in the organic substrate 140.

[0055] As shown in Figures 2A and 2B, the bridge multichip assembly structure 150 further includes an encapsulation material 148 formed between the pre-molded multichip structure 114 and the organic substrate 140. The encapsulation material 148 encapsulates a set of bridge chips 120 and chip-substrate joints 146 between the multiple chips 100 and the organic substrate 140. Underfill material 132 formed around the chip-bridge joints 130 may be absorbed into the encapsulation material 148. The underfill material 132 and the encapsulation material 148 firmly secure the unstable components of the bridge multichip assembly structure 150. An example of the encapsulation material 148 may include an epoxy-based resin material. Although the underfill material 132 and the encapsulation material 148 are referred to by different names, they may be substantially the same.

[0056] The organic substrate 140 is connected to multiple chips 100 by a set of chip-substrate joints 146. The organic substrate 140 has an array of terminals 144 formed on the bottom surface 142 of the organic substrate opposite the top surface 141 to which the multiple chips 100 are bonded. The array of terminals 144 is provided for the subsequent mounting of the bridge multichip assembly structure 150 to the next level assembly, such as a motherboard. The array of terminals 144 may be, for example, a ball grid array (BGA), a land grid array (LGA), or a pin grid array (PGA).

[0057] The organic substrate 140 may be an organic laminate or a similar material. The organic substrate 140 may include three distinct parts: a surface finish for soldering and bonding, a build-up layer containing most of the wiring and vias, and a core that provides mechanical strength. Optionally, a solder mask may be provided on the laminate, or a build-up dielectric may be provided on the top surface 141. Thus, the organic substrate 140 may include multiple wiring layers and insulating layers.

[0058] The core of the organic substrate 140 is typically composed of glass fiber reinforced epoxy coated with a subtractively circuit-modified copper sheet. While multilayer cores are available, the core most commonly consists of a single dielectric layer formed by conventional laminated printed circuit board processing techniques. Wiring within the organic substrate 140 connects the upper chip-substrate joint 146 to the corresponding lower terminal 144. Such organic or resin materials typically have a higher CTE than the material of the chip 100.

[0059] With reference to Figures 4(A) to 4(G), 5A and 5B, and 6(A) to 6(F), schematic drawings illustrate the process for manufacturing a bridge multichip assembly structure according to an example of an embodiment of the present disclosure. Figures 4(A) to 4(G) and 6(A) to 6(F) illustrate the process for manufacturing the bridge multichip assembly structure 150 shown in Figures 2A and 2B and Figures 3A and 3B. Note that Figures 4(A) to 4(G) and 6(A) to 6(F) show cross-sectional views of the structure.

[0060] According to at least one embodiment of this disclosure, Figures 4(A) to 4(C) and 5A to 5B illustrate the results of carrying out operation 12 of method 10 shown in Figure 1.

[0061] As shown in Figure 4(A), the manufacturing process may include preparing or providing a carrier substrate 300, which may be in wafer or panel form. The carrier substrate 300 may be rigid to support a structure formed on its upper surface. Examples of the carrier substrate 300 include, but are not limited to, semiconductor wafers such as silicon wafers, glass panels, and similar materials.

[0062] As shown in Figure 4(B), the manufacturing process may also include coating a resin material onto the carrier substrate 300 to form a resin layer 302. The resin material may be a photoresist resin. Any positive or negative type photoresist resin can be used. The fabrication of the resin layer 302 may include performing conventional coating techniques, such as spin coating.

[0063] As shown in Figure 4(C), the manufacturing process may further include patterning the resin material on the carrier substrate 300 to provide a pattern layer 304 having spaces (or openings) 306. In Figure 4(C), for illustrative purposes, only one element is assigned a number as a representative example. However, the same numbers apply to other corresponding components shown in Figures 4(A) to 4(G), Figures 5A and 5B, and Figures 6(A) to 6(F). The set of bumps 106 of each chip 100 to be placed will be accommodated when performing subsequent steps. Patterning of the resin layer 302 may typically involve performing conventional photolithography techniques, which may include pre-baking, exposure, post-exposure baking, development, and post-baking.

[0064] By performing the operations discussed above with reference to Figures 4(A) to 4(C), a carrier substrate 300 is provided having a pattern layer 304 that is patterned to define a predetermined layout of a plurality of chips 100.

[0065] Figures 5A and 5B illustrate the pattern layer 304 formed on the carrier substrate 300 by the process illustrated in Figure 4(C). More specifically, Figure 5A shows a cross-sectional view of the pattern layer 304 formed on the carrier substrate 300, and Figure 5B shows a top view of the pattern layer 304. Note that the cross-sectional view shown in Figure 5A corresponds to the cross-section represented by the dashed line B to B' shown in the top view of Figure 5B.

[0066] In Figures 5A and 5B, the contours of the chips 100 to be placed are indicated by dashed rectangles 308. In the figures, only one dashed rectangle is labeled with the number 308, as a representative example. As shown in Figures 5A and 5B, the space 306 fabricated in layer 304 for each chip 100 is slightly smaller in width and height than the contour 308 of the chip 100. Thus, the pattern layer 304 has a portion 305 (shown in Figure 5A) that will overlap with the peripheral region of the chip 100. This portion 305 will support the front of the chip 100 in the peripheral region when the chip 100 is placed on the carrier substrate 300. For reference, there is a peripheral region for each chip 100. In at least one embodiment, the peripheral region for each chip 100 is several hundred micrometers wide. The presence of this overlapping portion 305 makes the front surfaces 102 of the chips 100 coplanar, facilitating vertical alignment between the chips 100 even if there are significant variations / deviations in the thickness of the chips 100.

[0067] According to at least one embodiment of the present disclosure, Figure 4(D) illustrates the result of carrying out operation 14 of method 10 shown in Figure 1. As shown in Figure 4(D), the manufacturing process may include arranging a plurality of chips 100 on a pattern layer 304 in a predetermined layout in which each front 102 is oriented toward the carrier substrate 300. The front 102 of each chip 100 includes a set of terminals 108 for bridging and a set of bumps 106 for bonding to the organic substrate 140, and is placed upside down on the carrier substrate 300. The set of bumps 106 of each chip 100 (and the set of terminals 108 as well) are accommodated in a space 306 formed in the pattern layer 304 when the plurality of chips 100 are arranged.

[0068] Placing multiple chips 100 on the carrier substrate 300 in a predetermined layout may include using appropriate alignment marks. Alignment marks on the chip side can be formed on the front surface 102A of each chip 100. Alignment marks on the carrier substrate 300 can be formed on the upper surface of the carrier substrate 300. Post-sintering in a standard lithography process may be delayed until after the placement of the chips 100 in order to more firmly bond the chips 100 to the pattern layer 304.

[0069] According to at least one embodiment of the present disclosure, Figure 4(E) illustrates the result of carrying out operation 16 of method 10 shown in Figure 1. As shown in Figure 4(E), the manufacturing process may further include depositing molding material 310 between and around the plurality of chips 100, and in the pattern layer 304, to form portions corresponding to the extended portions 110 shown in Figures 2A and 2B and Figures 3A and 3B. The deposition of the molding material results in a wafer or panel-shaped structure 312 (also called a pre-formed multi-chip structure) containing the plurality of chips 100 and the molding material 310. The set of bumps 106 of each chip 100 (and the set of terminals 108 as well) are housed in the spaces 306 formed in the pattern layer 304 when the molding material 310 is deposited between and around the plurality of chips 100.

[0070] The fabrication of the wafer or panel-shaped structure 312 may be completed by employing conventional molding techniques. The components of the carrier substrate 300 (including the pattern layer 304 and the chips 100), as well as the external rigid structure, may be used as molds to which molten or liquid material is applied. The molding material can also be applied between the chips 100 by supplying the molding material into the gaps between adjacent chips 100 using a squeegee, or other coating techniques, or both, to diffuse the molding material across the entire surface of the structure.

[0071] According to at least one embodiment of the present disclosure, Figure 4(F) illustrates the result of carrying out operation 18 of method 10 shown in Figure 1. As shown in Figure 4(F), the manufacturing process may include the step of removing the carrier substrate 300 and pattern layer 304 from a wafer or panel-shaped structure 312. In certain embodiments, the separation of the carrier substrate 300 from the wafer or panel-shaped structure 312 may be completed by using laser-emittable temporary bonding and debonding techniques. In certain embodiments, the removal of the pattern layer 304 may be completed by dissolving it in a solvent.

[0072] As shown in Figure 4(G), the manufacturing process may include dicing a wafer or panel-shaped structure 312 into multiple bridge multi-chip assemblies. Dicing may be completed by employing conventional dicing techniques such as blade dicing, laser dicing (e.g., stealth dicing, laser ablation dicing), and similar methods. Figure 4(G) illustrates, as an example, a magnified view of a dicing tape 320 after stealth dicing. As shown in Figure 4(G), multiple pre-formed multi-chips 330-1 are obtained, each including a predetermined set of chips 100 and an extension portion 110 surrounding the predetermined set of chips 100.

[0073] As shown in Figure 6(A), the manufacturing process may include picking up a pre-formed multi-chip 330 (for example, one of the pre-formed multi-chips 330-1 illustrated in Figure 4(G)) and preparing bridge chips 120 for each required bridging location. The pre-formed multi-chip 330 includes a predetermined set of chips 100A, 110B and an extension portion 110. Each chip 100 has a front surface 102 including a set of exposed bumps 106 and a set of terminals 108 (108A and 108B). The prepared bridge chips 120 may have sets of terminals 126A, 126B formed on their front surface 122 (as shown in Figure 3A). The set of terminals 126 may be microbumps.

[0074] According to at least one embodiment of the present disclosure, Figure 6(B) illustrates the result of carrying out operation 20 of method 10 shown in Figure 1. As shown in Figure 6(B), the manufacturing process may include bonding a prepared bridge chip 120 to corresponding adjacent chips 100A, 100B in a pre-formed multi-chip 330 to form a set of chip-bridge joints 130A, 130B. As shown in Figure 6(B), the set of chip-bridge joints 130A, 130B between the bridge chip 120 and the corresponding adjacent chips 100A, 100B may be formed by using a corresponding set of terminals 108A, 108B of chips 100A, 100B and a corresponding set of terminals 126A, 126B of bridge chip 120.

[0075] As shown in Figure 6(C), the manufacturing process may include applying underfill material 132 around each bridge tip 120 and the set of bridge-tip joints 130 between the corresponding adjacent tip 100. Applying the underfill material 132 may include conventional underfill techniques, such as a capillary underfilling process.

[0076] The underfill material 132 may be applied after the prepared bridge chips 120 have been bonded to the corresponding adjacent chips 100A and 100B. However, in alternative embodiments, a pre-applied underfill, such as a non-conductive paste, may be used. In such embodiments, before bonding the prepared bridge chips 120 to the corresponding adjacent chips 100A and 100B, the manufacturing process may include applying the underfill material 132 around the locations of the terminals 108 where the set of bridge-chip joints 130 between each bridge chip 120 and the corresponding adjacent chip 100 will be formed by the subsequent bonding process. It should be noted that the product yield can be improved by using capillary underfill instead of pre-applied underfill. Since the bridge tip 120 and the corresponding tip 100 on which the bridge tip 120 is installed are firmly fixed to each other by the expanded portion 110 of the molding material (particularly its gap portion 110G), the usefulness of pre-applied underfill, which can provide strength immediately after bonding, is reduced and may be omitted.

[0077] As shown in Figure 6(D), the manufacturing process may include bonding a pre-formed multi-chip 330, which includes multiple chips 100A, 100B and a bridge chip 120, to an organic substrate 140 in order to form a set of chip-substrate joints 146A, 146B. As shown in Figure 6(D), the pre-formed multi-chip 330 is placed on the top surface 141 of the organic substrate 140.

[0078] As shown in Figure 6(D) and prior to encapsulation as shown in Figure 6(E), mechanical stress around the chip-bridge joint 130 between the chip 100 and the bridge chip 120 is generated by the heat (used in the bonding process) due to the difference in CTE between the chip 100 and the organic substrate 140. Such mechanical stress can reduce and worsen the yield of the packaged product. However, in embodiments of the present disclosure, the chips 100 are firmly fixed to each other by the expanded portion 110 of the molding material (particularly its gap portion 110G), and the bridge chip 120 is bonded to such firmly fixed chips 100, thus preventing joint failure. Thus, displacement between the bridged chips 100 when connected to the organic substrate 140 due to the difference in CTE can be prevented.

[0079] As shown in Figure 6(E), the manufacturing process may include encapsulating the bridge chip 120 and a set of chip-substrate joints 146 between the multiple chips 100 and the organic substrate 140 with an encapsulation material 148.

[0080] As shown in Figure 6(F), the manufacturing process may include fabricating an array of terminals 144 (which are BGA in the example shown in Figure 6(F)) on the bottom surface 142 of the organic substrate 140 to obtain the final integrated package 350. The integrated package 350 can then be supplied for subsequent mounting processes to the next level assembly, such as a motherboard.

[0081] In the embodiment described above, the bridge chip 120 is bonded to a standalone, pre-formed multi-chip 330. However, in other embodiments, before dicing, the bridge chip 120 may be bonded to each portion of the wafer or panel-shaped structure 312, which will become the pre-formed multi-chip structure 330 after dicing.

[0082] With reference to Figures 7(A) to 7(C), the deposition of molding material between and around a plurality of chips 100 according to an example of an embodiment of the present disclosure will be described in more detail. In particular, Figures 7(A) to 7(C) illustrate the results of deposition of molding material in a manner suitable for cases in which the plurality of chips 100 have a uniform chip thickness. Accordingly, Figures 7(A) to 7(C) illustrate the results of carrying out operation 16 of method 10 shown in Figure 1 according to at least one embodiment of the present disclosure.

[0083] As shown in Figure 7(A), depositing the molding material may include placing a structure comprising multiple chips 100, a pattern layer 304, and a carrier substrate 300 between molds 340A and 340B. Mold 340A may be in close contact with the back surface 104 of the chips 100.

[0084] As shown in Figure 7(B), depositing the molding material may also include injecting the molding material into the gaps between the multiple chips 100. As shown in Figure 7(C), injecting the molding material into the gaps between the multiple chips 100 results in a wafer or panel-shaped structure 312 comprising the molding material 310 and the multiple chips 100 such that the back surface 104 of each chip 100 is exposed.

[0085] With reference to Figures 8(A) to 8(C), the deposition of the molding material according to another example of the embodiments of this disclosure will be described in more detail. In particular, Figures 8(A) to 8(C) illustrate the results of deposition of the molding material in a manner suitable for cases where there is a significant variation / deviation in the thickness of the chip 100. Such variation may be caused by differences in the individual wafers from which each chip 100 was isolated, or by differences in the function of the chip 100, or both. Accordingly, Figures 8(A) to 8(C) illustrate the results of carrying out operation 16 of method 10 shown in Figure 1 according to at least one embodiment of this disclosure.

[0086] As shown in Figure 8(A), depositing the molding material may also involve placing a structure comprising a pattern layer 304, a carrier substrate 300, and a plurality of chips 100A, 100B having different chip thicknesses between molds 340A, 340B. Mold 340A is not in close contact with the back surface of the chips 100.

[0087] As further shown in Figure 8(A), depositing the molding material may also involve injecting the molding material 310 into the gaps between the multiple chips 100 and onto the multiple chips 100.

[0088] As shown in Figure 8(B), depositing the molding material may further include removing the mold after the molding material has been injected.

[0089] As shown in Figure 8(C), depositing the molding material may further include thinning the molding material and chips 100 from the back of chips 100A, 100B so that the wafer or panel-shaped structure 312 (pre-formed multi-chip structure) containing multiple chips 100 and the molding material 310 has a uniform thickness. Thinning the molding material and chips 100 involves removing some amount of molding material and chips 100. Thinning may be completed, for example, by performing a back grinding process.

[0090] As shown in Figure 8(C), when thinned, the wafer or panel-shaped structure 312 comprises the molding material 310 and a plurality of chips 100, with each of the chips 100 exposing its back surface 104. Note that in the embodiment described, the wafer or panel-shaped structure 312 is thinned so that the back surface 104 of each chip 100 is exposed. However, in other embodiments, the wafer or panel-shaped structure 312 may have one or more chips whose back surfaces remain covered with the molding material 310.

[0091] With reference to Figure 9A, another example of depositing the molding material according to an embodiment of the present disclosure will be described in more detail. In particular, Figure 9A illustrates the result of depositing the molding material in a manner suitable for cases where molds 340A and 340B are not used. Thus, Figure 9A illustrates the result of performing operation 16 of method 10 shown in Figure 1 according to at least one embodiment of the present disclosure.

[0092] As shown in Figure 9A, depositing the molding material may also involve supplying droplets 356 of the molding material into the gaps 352 between adjacent chips 100 and around multiple chips 100. As further shown in Figure 9A, depositing the molding material may also involve diffusing the applied molding material by pulling the squeegee 354 across the entire surface of the structure (300, 304, 100).

[0093] In the embodiments described, it should be noted that in order to form a wafer or panel-shaped structure 312, not only the gaps between adjacent chips 100 but also the space around the chips 100 are filled with the molding material 310. However, in other embodiments, only the gaps between adjacent chips 100 may be filled, and the space corresponding to the periphery of a given set of chips 100 may not be filled.

[0094] Referring to Figure 9B, a specific example of the embodiment describes how to arrange multiple chips 100 on a carrier substrate 300, and how to remove the carrier substrate 300 and pattern layer 304 from a wafer or panel-shaped structure.

[0095] As shown in Figure 9B, the set of bumps 106 is formed on an under-bump metallurgy (UBM) 360 fabricated on the front surface 102 of each chip 100. Furthermore, the top surface 364 of the carrier substrate 300 includes an array of micropads 362 on which each chip will be placed. Placing multiple chips 100 involves temporarily fixing the set of bumps 106 and the array of micropads 362 by temporary bonding. Removing the carrier substrate 300 and pattern layer 304 from the multiple chips 100 involves debonding the array of micropads 362 from the set of bumps 106 by heating. To minimize volume changes of the solder bumps after debonding, it may be preferable that each micropad 362 be smaller than the corresponding UBM 360 and made from a set of materials with less impact (e.g., Ti or Au) to eliminate changes in solder composition.

[0096] As further shown in Figure 9B, a release layer 370 is located between the carrier substrate 300 and the pattern layer 304. In certain embodiments, the release layer 370 is a laser-emitting layer used in laser-emitting temporary bonding and debonding techniques. After molding, the carrier substrate 300 can be easily separated from the wafer or panel-shaped structure 312 by irradiating the release layer 370 with a laser (e.g., an infrared laser when using a silicon wafer, or a UV laser when using a glass panel) from the back side of the carrier substrate 300.

[0097] In the embodiments described above, the set of bumps 106 is fabricated before chip placement. However, bump formation is not limited to this timing. With reference to Figures 10(A) to 10(G), diagrams illustrating the results of a process for manufacturing a bridge multichip assembly structure according to another example of embodiments of the present disclosure are described. Figures 10(A) to 10(G), together with Figures 6(A) to 6(F), illustrate the results of a process for manufacturing a bridge multichip assembly structure 150, as shown in Figures 2A and 2B and Figures 3A and 3B. Note that Figures 10(A) to 10(G) also show cross-sectional views of the structure. Thus, Figures 10(A) to 10(G) illustrate the results of an implementation of the method 10 shown in Figure 1, according to at least one embodiment of the present disclosure.

[0098] As shown in Figure 10(A), the manufacturing process may include preparing the carrier substrate 300. As shown in Figure 10(B), the manufacturing process may also include applying an adhesive material to the carrier substrate 300 to form an adhesive layer 402. The adhesive material may be a resin material. The adhesive layer 402 may be manufactured by performing a conventional coating technique, such as spin coating. By performing the operations discussed above with reference to Figures 10(A) and 10(B), a carrier substrate 300 is provided having a patterned layer 304 that is patterned to define a predetermined layout of a plurality of chips 100. Thus, Figures 10(A) and 10(B) illustrate the results of performing operation 12 of method 10 according to one embodiment of the present disclosure.

[0099] As shown in Figure 10(C), the manufacturing process may include arranging a plurality of chips 100 in an adhesive layer 402 in a predetermined layout in which the front surface 102 of each chip 100 is oriented toward the carrier substrate 300. Thus, Figure 10(C) illustrates the result of carrying out operation 14 of method 10 according to one embodiment of the present disclosure.

[0100] In the embodiments shown in Figures 10(A) to 10(G), it is not necessary to place multiple chips 100 on the carrier substrate 300 with the front surface 102 of each chip 100 facing downwards. However, it is preferable to place multiple chips 100 on the carrier substrate 300 with the front surface 102 of each chip 100 facing the carrier substrate 300. The front surface 102 of each chip 100 does not yet contain the set of bumps 106, but as shown in Figure 10(D), when molding material is deposited between the multiple chips 100, the front surfaces of the chips 100 are protected by the adhesive layer 402. Therefore, when multiple chips 100 are placed with the front surface 102 of each chip 100 facing the carrier substrate 300, the front surfaces 102 of the chips 100 become coplanar, facilitating vertical alignment between the chips 100 even if there is a significant variation / deviation in the thickness of the chips 100. Furthermore, this flatness provides advantages during bump formation.

[0101] Multiple chips 100 may be arranged on the carrier substrate 300 by using appropriate alignment marks. Alignment marks on the carrier substrate 300 can be formed on the surface of the carrier substrate 300. The thickness of the adhesive layer 402 is preferably thin so that the alignment marks formed on the carrier substrate 300 can be detected even when the entire area of ​​the wafer is covered with the adhesive layer 402.

[0102] As shown in Figure 10(D), the manufacturing process may further include depositing molding material 310 between and around a plurality of chips 100, as well as on the adhesive layer 402, to form portions corresponding to the extended portions 110 shown in Figures 2A and 2B and Figures 3A and 3B. Thus, Figure 10(D) illustrates the result of carrying out operation 16 of method 10 according to one embodiment of the present disclosure. Once the molding material is deposited, a wafer or panel-shaped structure 312 is formed.

[0103] As shown in Figure 10(E), the manufacturing process may include removing the carrier substrate 300 and adhesive layer 402 from the wafer or panel-shaped structure 312. Thus, Figure 10(E) illustrates the result of performing operation 18 of method 10 according to one embodiment of the present disclosure.

[0104] As shown in Figure 10(F), the manufacturing process may include forming sets of bumps 106 and sets of terminals 108 (contact pads) on the front surface 102 of a plurality of chips 100 in a wafer or panel-shaped structure 312. The bumps may be fabricated by performing conventional bump formation techniques, such as solder evaporation, electroplating of solder alloys, solder paste screening, solder ball placement, injection molding soldering processes, etc.

[0105] As shown in Figure 10(G), the manufacturing process may include dicing a wafer or panel-shaped structure 312 into multiple bridge multichip assemblies. Multiple pre-formed multichips 330-1 are obtained, each identical to the one shown in Figure 4(G). After the steps shown in Figure 10(G), the same process shown in Figures 6(A)–6(F) can be implemented as described with reference to a series of Figures 4(A)–4(G) and Figures 6(A)–6(F).

[0106] Referring to Figure 11, a bridge multichip assembly structure according to another example of an embodiment of the present disclosure will be described. Figure 11 illustrates a bridge multichip assembly structure after bonding to a recessed organic substrate 140, with a recess 143 formed on its upper surface 141. Thus, Figure 11 illustrates the result of carrying out operation 20 of method 10 according to one embodiment of the present disclosure.

[0107] It is preferable to eliminate the need to form depressions, cavities, or trenches in the organic substrate 140, but the formation of depressions, cavities, or trenches in the organic substrate 100 is not prevented. In the embodiment shown in Figure 11, the organic substrate 140 includes depressions 143 to avoid interference between the bridge chip 120AB and the organic substrate 140. Thickening the bridge chip 120 provides sufficient mechanical strength to withstand the mechanical stress acting on the bridge chip 120. The embodiment shown in Figure 11 provides greater strength than in cases where a thinner bridge chip is used.

[0108] Embodiments of the present disclosure provide a method for fabricating a bridge multi-chip assembly structure in which multiple chips are connected by bridge chips, while reducing stress generated around the joint between the chips and bridge chips by firmly fixing the multiple chips together. Additionally, embodiments of the present disclosure provide a bridge multi-chip assembly structure fabricated by the method.

[0109] The methods and bridge multichip assembly structures according to embodiments of this disclosure offer the following advantages: The bridge multichip assembly structure package enables heterogeneous chip integration with high bandwidth, low cost, and low stress around the bridge-chip joint. The cost of the organic substrate (laminate) is lower than that of 2.1D technology, which requires specially designed wiring on the organic laminate, and EMIB technology, which requires a specially designed silicon bridge embedded laminate. Furthermore, using bridge chip 120 reduces costs compared to 2.5D and 2.3D technologies, which require silicon and organic interposers, respectively. It should be noted that small bridge chips are generally cheaper than high-density laminates and silicon interposers. In addition, this disclosure enables a reduction in the number of times the expensive flip-chip bonding process is performed, and this process may only be required for bridge chip bonding. The method according to the embodiments requires only one C4 soldering to the organic substrate, compared to EMIB, which requires flip-chip bonding to the organic substrate as many times as the number of chips to be placed. Furthermore, the stress generated in the assembly may be lower than that of 2.3D and EMIB technologies. In addition, the bridged multi-chip assembly structure according to the embodiments of the disclosure may be more suitable for high-density interconnections than fan-out wafer-level packaging processes that require an organic redistribution layer on the fan-out chip surface.

[0110] It should be noted that the mechanical stress during the manufacturing process due to the CTE difference between the chip and the organic substrate is mitigated for the following reasons: (i) multiple chips 100 are firmly fixed to each other by the expanded portion 110 (particularly the gap portion 110G) of the molding material, and (ii) the bridge chip 120 is bonded to such firmly fixed chips 100. The displacement between the bridged chips 100 when connected to the organic substrate 140 due to the CTE difference is therefore preventable. This can prevent a decrease and deterioration in the yield of the packaged product.

[0111] The molding material firmly secures multiple chips, enabling thinner bridge chips, which further reduces lamination costs. Exposing the back surface of the chips results in a structure more suitable for future high-end modules consisting of many chiplets.

[0112] While the advantages obtained with respect to one or more specific embodiments of this disclosure have been described, it should be understood that some embodiments may not have these potential advantages, and these potential advantages are not necessarily required for all embodiments.

[0113] The technical terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form likewise unless the context clearly indicates otherwise. It will be further understood that the terms “to comprise” or “to comprise” or both, when used herein, specify the presence of a described feature, step, layer, element, or component, or a combination thereof, but do not exclude the presence or addition of one or more other features, steps, layers, elements, components, or groups thereof, or combination thereof.

[0114] All means or steps and corresponding structures, materials, actions, and equivalents of functional elements in the following claims are intended to include any structure, material, or action for performing a function in combination with other claimed elements, if any, specifically claimed. The descriptions of one or more aspects of this disclosure have been presented for illustrative and explanatory purposes, but are not intended to be exhaustive or to limit the disclosure to any form of disclosure.

[0115] Many modifications and variations will be apparent to those skilled in the art without departing from the scope and concept of the embodiments described herein. The terminology used herein has been chosen to best describe the principles, practical applications, or technical improvements to the technologies available on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for fabricating a bridge multichip assembly structure, Prepare a carrier board, The arrangement of a plurality of chips on the carrier substrate in a predetermined layout, wherein each of the plurality of chips has a front surface formed with a set of terminals and a set of bumps for connecting to an organic substrate, and the arrangement is such that the front surface faces the carrier substrate. Depositing molding material between the plurality of chips and on the carrier substrate, Removing the carrier substrate from the plurality of chips fixed with the molding material, Bonding a bridge chip to corresponding sets of terminals of at least two of the plurality of chips fixed with the molding material. Includes, The preparation of the aforementioned carrier substrate is The process involves applying a resin material onto the carrier substrate, The resin material is patterned such that when the plurality of chips are arranged and the molding material is deposited, it provides a space for accommodating the set of bumps. including, method.

2. The method according to claim 1, wherein each bump in the set of bumps is a Cu pillar bump.

3. The method according to claim 1, wherein a portion of the molding material that fixes at least two of the plurality of chips has a surface that is coplanar with the front surfaces of at least two of the plurality of chips.

4. The distance between the back surface of the bridge tip and the front surface of the plurality of tips is shorter than the height of the bump. The method according to claim 1.

5. Installing the aforementioned bridge chip A joint is formed between at least two of the plurality of chips and the bridge chip via the corresponding set of terminals, Applying underfill material around the position corresponding to the joint between the bridge chip and at least two of the plurality of chips. The method according to claim 1, including the method described in claim 1.

6. The aforementioned molding material is deposited The molding material is deposited in the gaps between the plurality of chips so that the back surface of each chip is exposed. The method according to claim 1, including the method described in claim 1.

7. The aforementioned molding material is deposited Depositing the molding material between the plurality of chips and on the plurality of chips, The molding material is thinned from the back side of the multiple chips so that the pre-molded multi-chip structure, which includes the multiple chips and a portion of the molding material, has a uniform thickness. The method according to claim 1, including the method described in claim 1.

8. Bonding the plurality of chips having the bridge chip to an organic substrate, The bridge chip and the joint between the plurality of chips and the organic substrate are enclosed in an encapsulation material. The method according to claim 1, further comprising:

9. The front surfaces of the plurality of chips include a set of bumps for connecting to an organic substrate. The carrier substrate includes an array of micropads on which each of the chips will be placed. The arrangement of the plurality of chips includes temporarily fixing the set of bumps and the array of micropads, Removing the carrier substrate from the plurality of chips includes debonding the array of micropads from the set of bumps. The method according to claim 1.

10. The carrier substrate has a wafer shape, Depositing the molding material yields a wafer-shaped structure comprising the plurality of chips and a portion of the molding material. The method further includes dicing the wafer-shaped structure to obtain a single bridge multichip assembly. The method according to any one of claims 1 to 9.

11. A method for manufacturing a multichip assembly structure for manufacturing a bridge multichip assembly structure, A carrier substrate having a pattern layer is prepared, The arrangement of a plurality of chips on the pattern layer of the carrier substrate, wherein each of the plurality of chips has a front surface formed with a set of terminals for bridging and a set of bumps for connecting to an organic substrate, and the arrangement is such that the front surface faces the carrier substrate. Depositing molding material between the plurality of chips and on the pattern layer of the carrier substrate, Removing the carrier substrate from the plurality of chips fixed with the molding material. Includes, The pattern layer is patterned such that when the plurality of chips are arranged and the molding material is deposited, it provides a space for accommodating the set of bumps. method.

Images