Encoding method, decoding method, apparatus, device, system, and readable storage medium

Abstract

This application belongs to the field of communication technology and discloses an encoding method, a decoding method, an apparatus, a device, a system, and a readable storage medium. The encoding method includes the steps of: obtaining a set of 2n code stream blocks including a control block and a data block, where n is an integer greater than 1; and performing a first encoding on the set of 2n code stream blocks to obtain a target code block, where the target code block includes a type determined based on a control block in the set of 2n code stream blocks and a data unit determined based on a control block and a data block in the set of 2n code stream blocks. The decoding method includes the steps of obtaining a target code block; and performing a first decoding on the target code block based on a type and a data unit of the target code block to obtain a set of 2n code stream blocks, where each set of code stream blocks includes a control block and a data block obtained based on a type and a data unit.

Description

[Technical Field]

[0001] This application relates to the field of communication technology, and more particularly to encoding methods, decoding methods, apparatus, devices, systems, and readable storage media. [Background technology]

[0002] With advancements in communication technology, packet transmission methods over Ethernet are becoming increasingly sophisticated. During packet transmission, packets from the media access control (MAC) layer are divided into blocks based on a fixed length, and these blocks are then transmitted in parallel to the media independent interface (MII). For example, a packet is divided into blocks, and these blocks are then transmitted in parallel to the 800 gigabit (gigabit, G) MII. Here, the 800G MII represents an MII operating at a MAC rate of 800 gigabits per second (Gb / s). The blocks are transmitted through the MII to the physical coding sublayer (PCS). The coded stream blocks received by the PCS from the MII contain data blocks (transmit data, TXD) and control blocks (transmit control, TXC). The TXC and TXD are obtained by processing the packet flow content from the MAC layer via the reconciliation sublayer (RS). TXC is a control character that identifies whether the content of the corresponding byte in TXD is a control signal or a data signal. Control signals include information such as packet start, end, error, and idle state. PCS performs encoding based on the content of TXC / TXD to reduce overhead and provide the necessary synchronization and protection functions.

[0003] In related technologies, the PCS performs 64-bit (bit,B) / 66B encoding on each set of code stream blocks from the MII to obtain a 66-bit code block. Here, the 66-bit code block is either a data code block or a control code block. If the 66-bit code block is a control code block, it includes a 4-bit Hamming distance protected field. When data transmission is performed using a high-speed physical link, every four 66-bit code blocks are coded into a single 256B / 257B code block with a length of 257 bits, and forward error correction (FEC) encoding is performed on the 257-bit code block, and the transmission of the FEC codeword obtained through FEC encoding is performed.

[0004] If uncorrectable FEC codewords exist, the number of error bits within the FEC codeword increases, and because the position of the error bits is not fixed, reliable error bit identification cannot be ensured even by using a Hamming distance-protected field within a 66-bit code block. Furthermore, reliable error bit identification can be implemented through FEC error indication, so there is no need to implement error bit identification by using a Hamming distance-protected field within a 66-bit code block. As a result, since most of the processing in PCS is based on 257-bit code blocks, 64B / 66B encoding processing is no longer necessary. If 64B / 66B encoding processing remains, subsequent code conversion processing will cause unnecessary delays, power consumption, and chip area occupation. [Overview of the project]

[0005] This application provides an encoding method, a decoding method, an apparatus, a system, and a readable storage medium to improve encoding efficiency and decoding efficiency.

[0006] According to the first embodiment, an encoding method is provided. This method includes the following: namely, 2 na step of obtaining n code stream block groups, wherein any code stream block group comprises a control block and a data block, and n is an integer greater than 1. and 2 n a step of performing first encoding on n code stream block groups to obtain a target code block, wherein the target code block is 2 n a type determined based on a control block in the n code stream block groups, and 2 n a step comprising a data unit determined based on control blocks and data blocks in the n code stream block groups.

[0007] by performing first encoding on 2 n code stream block groups including control blocks and data blocks, 2 n by performing 64B / 66B encoding on each of the n code stream block groups, 2 n obtaining n 66-bit code blocks, 2 n without code conversion of the n 66-bit code blocks, the target code block can be obtained, thereby improving encoding efficiency and reducing delay, power consumption and chip area occupation caused by encoding processing. n

[0008] In a possible implementation, the type indicates that the target code block is a data code block. And the data unit is 2 n in a sequence of n code stream block groups, 2 n obtained by performing first encoding on data blocks in the n code stream block groups.

[0009] In a possible implementation, the type indicates that the target code block is a control code block. And the data unit comprises a type indication and code block content, and the code block content is 2 n in a sequence determined based on control blocks and data blocks in the n code stream block groups, 2 n ​The type indication is obtained by performing a first encoding on the data blocks within a group of coded stream blocks, and the type indication is 2 n The type indication is obtained based on the control blocks within each group of code stream blocks, and it indicates the type of each group within the code stream block set.

[0010] In possible implementations, the target code block is an error code block, and the error code block contains error indication data. According to the encoding method of this application, the target code block can be obtained by performing the first encoding on various types of code stream blocks. Therefore, this method is widely applicable.

[0011] In possible implementations, the target code block is determined based on the error detection result. n The error detection result is obtained by processing a group of code stream blocks, and the result is 2 n It is obtained based on the control blocks and data blocks of a group of code stream blocks. In addition, the code stream block in which an error occurred is processed, and the target code block is obtained, thereby ensuring data reliability by distinguishing the erroneous data from the correct data in subsequent data transmission.

[0012] In possible implementations, the error detection result is 2 n The code stream block group contains a content sequence error or content error, and the target code block is 2 n The first encoding is obtained by performing a first encoding on a set of coded stream blocks, which have the correct content sequence and correct content, and error blocks, and the error blocks are 2 n It is obtained from a group of code stream blocks based on code stream blocks that have a content sequence error or a content error.

[0013] In a possible implementation, the control block contains m bits and the data block contains 8m bits, where m is a positive integer.

[0014] In a possible implementation, the value of n is 2, the value of m is 8, and the target code block is 257 bits.

[0015] In possible implementations, 2 n All of these coded stream blocks originate from the Media Independent Interface (MII).

[0016] In possible implementations, after obtaining the target code block, the method further includes the steps of: obtaining the first data by performing a second encoding on the target code block based on the FEC code type; and transmitting the first data. The second encoding is performed on the target code block based on the FEC code type to obtain the first data, thereby enabling the receiver to perform error correction on the received first data to ensure data transmission accuracy.

[0017] According to a second embodiment, a decoding method is provided. This method includes the steps of: obtaining a target code block, the target code block including a type and data units; and performing a first decoding on the target code block based on the type and data units of the target code block. n A step of obtaining n sign stream block groups, where any sign stream block group is obtained based on type and data unit, and includes control blocks and data blocks, where n is an integer greater than 1.

[0018] The target code block is converted to code, 2 n To obtain 66-bit sign blocks, or 2 n There is no need to decode individual 66-bit code blocks, and the control block and data block are included in 2 nSince the code stream blocks are obtained by performing a first decoding on the target code block, decoding efficiency is improved and the delay, power consumption, and chip area occupied by the decoding process are reduced.

[0019] In possible implementations, the type indicates that the target code block is a data code block. And 2 n The data blocks contained in code stream block group i within a group of code stream blocks are obtained in the data unit by performing a first decoding on the content corresponding to code stream block group i, which has a length of 8m, where m is a positive integer and i is between 1 and 2. n The following integers, or i is greater than or equal to 2. n It is an integer less than or equal to -1.

[0020] In possible implementations, the type indicates that the target code block is a control code block, the data unit contains the type indication and the code block content, and the type indication is 2 n Includes 2 bits n One bit within a bit is a group of code stream blocks corresponding to that bit, 2 n This indicates the type of one code stream block group within a group of code stream blocks, and the code block content is 2 n It contains a group of bits. 2 n The control blocks contained within the group of code stream blocks i in each code stream block are obtained based on the type, the bits corresponding to the group of code stream blocks i, which are in the type indicator, and the group of bits corresponding to the group of code stream blocks i, which are in the code block content. Here, i is between 1 and 2. n The following integers, or i is greater than or equal to 2. n It is an integer less than or equal to -1. Furthermore, 2 nThe data blocks contained in code stream block group i within a group of code stream blocks are obtained by performing a first decoding on the group of bits corresponding to code stream block i, which is the group of bits in the code block content, based on the bits in the type indication, which is the bits in code stream block i.

[0021] In possible implementations, 2 n The set of bits consists of the first set of bits and 2 n -1 second set of bits, and the number of bits in the first set of bits is different from the number of bits in the second set of bits.

[0022] In possible implementations, the data unit includes a type indicator, and the type and type indicator indicate that the target code block is an error code block. n The control blocks included in each group of code stream blocks are the first value, and 2 n Each data block in each of the n-numbered code stream block groups is the second value, and the first and second values ​​indicate that the code stream block is an error code stream block.

[0023] According to the decoding method of the present application, the first decoding is performed on various types of target code blocks, and 2 n It is possible to obtain a set of code stream blocks. Therefore, this method is widely applicable.

[0024] In a possible implementation, the steps of obtaining a target code block include: receiving a second data, which is obtained based on a first data encoded using a forward error-corrected FEC code type; and performing a second decoding on the second data to obtain a target code block, wherein the second decoding is an error correction process.

[0025] In possible implementations, the target code block is an error code block obtained when error correction is performed on the second data but fails. Furthermore, the target code block is an error indication for a code block within the FEC codeword, allowing the receiver to determine that the data obtained based on the target code block is error data and thus ensure data accuracy.

[0026] In a possible implementation, the steps of obtaining the target code block include: receiving a second data, which is obtained based on the first data, encoded using a forward error-corrected FEC code type; and performing a second decoding on the second data to obtain the target code block, wherein the second decoding is an error detection process with error correction bypassed.

[0027] In possible implementations, the target code block is the error code block obtained when an error is detected in the second data, but error correction is bypassed.

[0028] In the decoding method provided in this application, the second decoding operation may be a step of performing error correction on the codeword, or a step of performing error detection in which error correction is bypassed. If error correction is performed on the codeword in the second decoding process, and it is determined that error correction cannot be performed on the current codeword (for example, if the number of errors exceeds the error correction capacity), then error instructions must be applied to all code blocks within the codeword. Alternatively, if only error detection in which error correction is bypassed is performed on the codeword in the second decoding process, then error instructions must be applied to all code blocks within the codeword in which errors are detected.

[0029] In possible implementations, 2 nThe code stream blocks are obtained by performing a first decoding on the target code block based on the error detection result, the type of the target code block, and the data unit, with the error detection result being obtained based on the type of the target code block and the data unit. The target code block in which an error occurred is processed, so that the receiver can distinguish between erroneous data and correct data and ensure the reliability of the data.

[0030] In possible implementations, the error detection result includes a content sequence error or content error in the target code block, and 2 n The code stream block group is obtained by performing a first decoding on the second code block based on the type and data units of the second code block, the second code block being a code block obtained by transforming the target code block and having the same number of bits as the target code block.

[0031] In possible implementations, the error detection result includes a content sequence error or content error in the target code block, and 2 n The group of code stream blocks is 2 n Obtained by transforming the first set of code stream blocks, 2 n The first code stream blocks are obtained by performing a first decoding on the target code block, based on the type and data units of the target code block.

[0032] In a possible implementation, the control block contains m bits and the data block contains 8m bits, where m is a positive integer.

[0033] In a possible implementation, the value of n is 2, the value of m is 8, and the target code block is 257 bits.

[0034] In possible implementations, 2 nAll of these coded stream blocks are contained within the Media Independent Interface (MII) format.

[0035] According to a third embodiment, an encoding device is provided. This device includes the following: 2 n An acquisition module configured to acquire n units of code stream block sets, wherein any code stream block set includes control blocks and data blocks, and n is an integer greater than 1. 2 n A first coding module configured to perform a first coding on a group of code stream blocks to obtain a target code block, wherein the target code block is 2 n The type is determined based on the control blocks within a group of code stream blocks, and 2 n A first coding module, comprising control blocks and data units determined based on data blocks within a group of code stream blocks.

[0036] In possible implementations, the type indicates that the target code block is a data code block. And the data unit is 2 n In a sequence determined based on control blocks and data blocks within a group of code stream blocks, 2 n It is obtained by performing the first encoding on the data blocks within the group of coded stream blocks.

[0037] In possible implementations, the type indicates that the target code block is a control code block. The data unit then contains the type indication and the code block content, and the code block content is 2 n In a sequence determined based on control blocks and data blocks within a group of code stream blocks, 2 n The type indication is obtained by performing a first encoding on the data blocks within a group of coded stream blocks, and the type indication is 2 nThe type indication is obtained based on the control blocks within each group of code stream blocks, and it indicates the type of each group within the code stream block set.

[0038] In possible implementations, the target code block is an error code block, and the error code block contains error indication data.

[0039] In possible implementations, the target code block is determined based on the error detection result. n The error detection result is obtained by processing a group of code stream blocks, and the result is 2 n It is obtained based on the control blocks and data blocks within a group of code stream blocks.

[0040] In possible implementations, the error detection result is 2 n The code stream block group contains a content sequence error or content error, and the target code block is 2 n A code stream block having a correct content sequence and correct content within a group of code stream blocks, and 2 n Based on the error blocks within the set of code stream blocks, the first encoding is obtained by performing the first encoding, and the error blocks are 2 n This is obtained based on a content sequence error or a code stream block containing a content error within a group of code stream blocks.

[0041] In a possible implementation, the control block contains m bits and the data block contains 8m bits, where m is a positive integer.

[0042] In a possible implementation, the value of n is 2, the value of m is 8, and the target code block is 257 bits.

[0043] In possible implementations, 2 n All of these coded stream blocks originate from the Media Independent Interface (MII).

[0044] In possible implementations, the device further includes the following: A second coding module configured to perform a second coding on a target code block based on a forward error-corrected FEC code type to obtain the first data; and a transmit module configured to transmit the first data.

[0045] According to a fourth aspect, a decoding device is provided. This device includes the following: An acquisition module configured to acquire a target code block, wherein the target code block includes a type and a data unit. Based on the type and data units of the target code block, a first decoding is performed on the target code block, and 2 n A decoding module configured to acquire n code stream block sets, wherein any code stream block set includes control blocks and data blocks acquired based on type and data units, and n is an integer greater than 1.

[0046] In possible implementations, the type indicates that the target code block is a data code block. And 2 n The data blocks contained in code stream block group i within a group of code stream blocks are obtained in the data unit by performing a first decoding on the content corresponding to code stream block group i, which has a length of 8m, where m is a positive integer and i is between 1 and 2. n The following integers, or i is greater than or equal to 2. n It is an integer less than or equal to -1.

[0047] In possible implementations, the type indicates that the target code block is a control code block, the data unit contains the type indication and the code block content, and the type indication is 2 n Includes 2 bits n One bit within a bit is a group of code stream blocks corresponding to that bit, 2n This indicates the type of one code stream block group within a group of code stream blocks, and the code block content is 2 n Contains a set of bits. 2 n The control blocks included in code stream block group i within a group of code stream blocks are obtained based on the type, the bits corresponding to code stream block group i, which are in the type indicator, and the group of bits corresponding to code stream block group i, which are in the code block content, where i is between 1 and 2. n The following integers, or i is greater than or equal to 2. n It is an integer less than or equal to -1. And 2 n The data blocks contained in code stream block group i within a group of code stream blocks are obtained by performing a first decoding on the group of bits corresponding to code stream block group i, which is the group of bits in the code block content, based on the bits in the type indication, which is the bits corresponding to code stream block group i.

[0048] In possible implementations, 2 n The set of bits consists of the first set of bits and 2 n -1 second set of bits, and the number of bits in the first set of bits is different from the number of bits in the second set of bits.

[0049] In possible implementations, the data unit includes a type indicator, and the type and type indicator indicate that the target code block is an error code block. n The control blocks included in each group of code stream blocks are the first value, and 2 n Each data block in each of the n-numbered code stream block groups is the second value, and the first and second values ​​indicate that the code stream block is an error code stream block.

[0050] In a possible implementation, the acquisition module is configured to: receive a second data, which is acquired based on a first data encoded using a forward error-corrected FEC code type; and perform a second decoding on the second data to acquire a target code block, the second decoding being an error correction process.

[0051] In a possible implementation, the target code block is the code block obtained when error correction is performed on the second data, but the error correction fails.

[0052] In a possible implementation, the acquisition module is configured to: receive a second data, which is acquired based on a first data encoded using a forward error-corrected FEC code type; and perform a second decoding on the second data to acquire the target code block, the second decoding being an error detection process with error correction bypassed.

[0053] In possible implementations, the target code block is the error code block obtained when an error is detected in the second data, but error correction is bypassed.

[0054] In possible implementations, 2 n The code stream block group is obtained by performing a first decoding on the target code block based on the error detection result, the type of the target code block, and the data unit, and the error detection result is obtained based on the type of the target code block and the data unit.

[0055] In possible implementations, the error detection result includes a content sequence error or content error in the target code block, and 2 nThe code stream block group is obtained by performing a first decoding on the second code block based on the type and data units of the second code block, the second code block being a code block obtained by transforming the target code block and having the same number of bits as the target code block.

[0056] In possible implementations, the error detection result includes a content sequence error or content error in the target code block, and 2 n The group of code stream blocks is 2 n Obtained by transforming the first set of code stream blocks, 2 n The initial set of code stream blocks is obtained by performing a first decoding on the target code block, based on the type and data units of the target code block.

[0057] In a possible implementation, the control block contains m bits and the data block contains 8m bits, where m is a positive integer.

[0058] In a possible implementation, the value of n is 2, the value of m is 8, and the target code block is 257 bits.

[0059] In possible implementations, 2 n All of these coded stream blocks are in the Media Independent Interface (MII) format.

[0060] According to the fifth aspect, a network device is provided. The network device includes a processor, which is coupled to a memory, which stores at least one program instruction or code, which is loaded and executed by the processor, enabling the network device to implement an encoding method according to the first aspect or any possible implementation thereof, or a decoding method according to the second aspect or any possible implementation thereof.

[0061] According to the sixth aspect, a computer-readable storage medium is provided, which stores at least one program instruction or code. When the program instruction or code is loaded and executed by a processor, the computer can implement an encoding method according to the first aspect or a possible implementation thereof, or a decoding method according to the second aspect or a possible implementation thereof.

[0062] According to the seventh aspect, a communication system is provided. The system includes a first network device and a second network device, the first network device being configured to perform an encoding method according to either the first aspect or a possible implementation thereof, and the second network device being configured to perform a decoding method according to either the second aspect or a possible implementation thereof.

[0063] According to the eighth aspect, another communication device is provided, which includes a transceiver, memory, and a processor. The transceiver, memory, and processor communicate with each other via an internal connection path. The memory is configured to store instructions. The processor is configured to execute instructions stored in memory to control the transceiver to receive signals and to control the transceiver to transmit signals. Furthermore, when the processor executes instructions stored in memory, the processor is capable of executing an encoding method according to the first aspect or a possible implementation thereof, or a decoding method according to the second aspect or a possible implementation thereof.

[0064] For example, there is one or more processors and one or more memory units.

[0065] For example, the memory may be integrated with the processor, or the memory and processor may be located separately. It's fine. .

[0066] In certain implementation processes, the memory may be non-transitory memory, such as read-only memory (ROM). The memory and processor may be integrated on the same chip or located separately on different chips. The type of memory and the arrangement of the memory and processor are not limited in this application.

[0067] According to the ninth aspect, a computer program product is provided. This computer program product includes computer program code. When the computer program code is executed on a computer, the computer becomes capable of performing an encoding method according to the first aspect or a possible implementation thereof, or a decoding method according to the second aspect or a possible implementation thereof.

[0068] According to the tenth aspect, a chip is provided. The chip includes a processor configured to: invoke instructions from memory, execute instructions stored in memory, and enable a communication device on which the chip is installed to perform an encoding method according to the first aspect or any possible implementation thereof, or a decoding method according to the second aspect or any possible implementation thereof.

[0069] According to the eleventh aspect, another chip is provided. This chip includes an input interface, an output interface, a processor, and memory. The input interface, output interface, processor, and memory are connected via an internal connection path. The processor is configured to execute code in memory. Once the code is executed, the processor is configured to execute an encoding method according to the first aspect or a possible implementation thereof, or a decoding method according to the second aspect or a possible implementation thereof. [Brief explanation of the drawing]

[0070] [Figure 1] This is a schematic diagram showing an implementation environment for an encoding method and a decoding method according to one embodiment of the present application. [Figure 2] This flowchart shows an encoding method according to one embodiment of the present application. [Figure 3] This is a schematic diagram illustrating the process of acquiring a target code block according to one embodiment of the present application. [Figure 4] This is a schematic diagram showing the configuration of a target code block according to one embodiment of the present application. [Figure 5] This is a schematic diagram showing the configuration of another target code block according to one embodiment of the present application. [Figure 6] This is a schematic diagram showing the configuration of another target code block according to one embodiment of the present application. [Figure 7] This is a flowchart showing a decoding method according to one embodiment of the present application. [Figure 8] This is a schematic diagram showing the configuration of an encoding device according to one embodiment of the present application. [Figure 9] This is a schematic diagram showing the configuration of a decoding device according to one embodiment of the present application. [Figure 10] This is a schematic diagram showing the configuration of a network device according to one embodiment of this application. [Figure 11] This is a schematic diagram showing the configuration of another network device according to one embodiment of this application. [Figure 12] This is a schematic diagram showing the configuration of another network device according to one embodiment of this application. [Modes for carrying out the invention]

[0071] The terminology used in the implementation of this application is for the sole purpose of describing the embodiments of this application and is not intended to limit this application. Embodiments of this application are described below with reference to the accompanying drawings.

[0072] As a local area network technology, Ethernet is increasingly widely applied. Since 100 Gigabit Ethernet (GE), data transmission has been carried out at a transmission rate of 25 Gb / s per lane. To correct error bits in received data, FEC coding is introduced at the physical layer, and the transmission of FEC codewords obtained through coding is performed. For example, when data transmission is performed over a 100G lane, the sender can perform FEC coding on the original data by using Reed-Solomon (RS) (528, 514), and one RS codeword block obtained through coding contains a 5140-bit payload and a 140-bit check code. Due to the presence of the check code, the transmission rate required for transmitting the FEC codeword is higher than the transmission rate required for transmitting the original data, for the same transmission rate required to transmit the same payload in the same amount of time.

[0073] To reduce the transmission rate required for FEC codeword transmission, the Ethernet standard uses code conversion to reduce the overhead of the code block before FEC encoding, thereby reducing the transmission rate required for FEC codeword transmission. For example, every four 64B / 66B code blocks are converted to one 256B / 257B code block. Since the overhead of one 257-bit code block is lower than the overhead of four 66-bit code blocks, the transmission rate required for FEC codeword transmission, which is obtained based on a 257-bit code block, is lower. When data transmission is performed over a 100G lane, the transmission rate required for FEC codeword transmission, which is obtained based on the converted code block transmission, is 103.125 Gb / s, and this transmission rate is the same as the transmission rate required for 66-bit code blocks that are not FEC encoded.

[0074] After obtaining the FEC codeword, the receiving side can perform error correction on the FEC codeword. Identification of error bits may be performed through FEC error indication, and most processing in PCS is performed based on 257-bit code blocks. Therefore, the 64B / 66B encoding process and the corresponding code conversion process cause unnecessary delay, power consumption, and chip area occupation.

[0075] Therefore, in order to solve the above problems, embodiments of the present application provide a data transmission method. In the embodiments of the present application, for 2 n code stream block groups (n is an integer greater than 1), by performing first encoding on each group, without performing 64B / 66B encoding on each group of 2 n code stream block groups to obtain 2 n 66-bit code blocks, and without performing code conversion on 2 n 66-bit code blocks, a target code block is obtained. Therefore, encoding efficiency is improved, and delay, power consumption, and chip area occupation caused by encoding processing are reduced.

[0076] According to the method provided in the embodiments of the present application, when first decoding is performed on a target code block, by directly performing first decoding on the target code block, without performing code conversion on the target code block to obtain 2 n 66-bit code blocks, and without decoding 2 n 66-bit code blocks, 2 n code stream block groups including control blocks and data blocks can be obtained. Therefore, decoding efficiency is improved, and delay, power consumption, and chip area occupation caused by encoding processing are reduced.

[0077] The encoding and decoding methods provided in the embodiments of this application are applicable to current Ethernet interface scenarios or other scenarios requiring data transmission. The implementation scenario shown in Figure 1 is used as an example. The implementation scenario includes multiple chips that can exchange information between them to perform data transmission. For example, chip 102 is located on a first network device 101, chip 104 is located on a second network device 103, both chip 102 and chip 104 support FEC encoding and FEC decoding, and channel 105 between the first network device 101 and the second network device 103 can be used for transmitting FEC encoded data. In this case, chip 102 is 2 n A first encoding can be performed on a group of code stream blocks to obtain the target code block, a second encoding can be performed on the target code block based on the first FEC code type to obtain the first data, and the first data can be transmitted to the chip 104 via channel 105. For example, an error bit may occur during the transmission of the first data via channel 105, and the received data is called the second data. After receiving the second data, the chip 104 performs a second decoding on the second data using the first FEC code type to obtain the target code block, and performs a first decoding on the target code block to obtain the second data. nn code stream block sets can be obtained, where n is an integer greater than 1, and the first FEC code type includes, but is not limited to, any one of the following: multiple RS codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, Hamming codes, extended-BCH codes, extended-Hamming codes, fire codes, turbo codes, turbo product codes (TPCs), staircase codes, low-density parity-check (LDPC) codes, or cascaded combinations thereof.

[0078] It can be understood that the implementation scenario shown in Figure 1 may involve multiple network devices, and each network device may contain at least one chip. In Figure 1, only an example with two network devices, each containing one chip, is used for illustrative purposes.

[0079] Referring to the implementation scenario shown in Figure 1, the encoding method provided in one embodiment of this application is shown in Figure 2. For example, the encoding method provided in this embodiment of this application is performed by chip 102 in Figure 1 and includes, but is not limited to, steps 201 and 202.

[0080] Step 201:2 n Obtain n sign stream block sets, where any sign stream block set includes control blocks and data blocks, and n is an integer greater than 1.

[0081] In possible implementations, 2 n All of the code stream blocks are from MII. Based on MII, 2 n The method for obtaining a group of code stream blocks is not limited to the embodiments of this application. For example, the MII is 2n It is the MII specified in the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standards, for example, IEEE 802.3-2018, and other versions of the IEEE 802.3 standards, for obtaining n code stream block groups. For example, specifically, the value of n is 2, and 4 code stream block groups are obtained.

[0082] For example, 2 n For any group among the n code stream block groups, a control block in any code stream block group comprises m bits, and a data block in any code stream block group comprises 8m bits, m is a positive integer, 8m represents 8 times of m, and 8m may alternatively be represented as 8*m. For example, specifically, the value of m is 8, for any code stream block group, a control block in any code stream block group comprises 8 bits, and a data block in any code stream block group comprises 64 bits. In a possible implementation, all the m bits comprised in the control block are control bits, in other words, the control block comprises m control bits. And all the 8m bits comprised in the data block are data, in other words, the data block comprises 8m bits of data.

[0083] For example, a control block comprising 8 control bits is represented as TXC<7:0>, a data block comprising 64-bit data is represented as TXD<63:0>, and the sequence of all bits of the control block and the data block is from the most significant bit (MSB) to the least significant bit (LSB).

[0084] Step 202: 2 n First encoding is performed on n code stream block groups to obtain a target code block. Here, the target code block comprises 2 nThe type is determined based on the control blocks within a group of code stream blocks, and 2 n It includes control blocks and data units determined based on data blocks within a group of code stream blocks.

[0085] For example, in each code stream block group, each control block is 8 bits and each data block is 64 bits. The first encoding is performed on four code stream block groups to obtain one 257-bit target code block. In this embodiment of the present application, the case where n=2 is used as an example. When n is a different value, the first encoding may be performed on each of the four code stream block groups to obtain multiple target code blocks. For example, specifically, when n=3, eight code stream block groups are obtained. The first encoding may be performed on the first four code stream block groups to obtain one target code block, or the first encoding may be performed on the last four code stream block groups to obtain one target code block.

[0086] In possible implementations, 2 n The step of performing a first encoding on a group of code stream blocks to obtain a target code block includes, but is not limited to, the following encoding schemes 1 and 2.

[0087] In encoding scheme 1, the type of target code block is 2 n Based on the control blocks within the group of code stream blocks, it is determined to be a data code block. n In a sequence within a group of coded stream blocks, 2 n A first encoding is performed on the data blocks within the group of code stream blocks to obtain data units. Then, the target code block is obtained based on its type and data units.

[0088] For example, regarding the target code block obtained in encoding scheme 1, the type indicates that the target code block is a data code block. And the data unit is 2 n In a sequence of code stream blocks, 2 n It is obtained by performing the first encoding on the data blocks within the group of coded stream blocks.

[0089] In possible implementations, 2 n If each control block within a group of code stream blocks is equal to the first specified value, the type of the target code block is determined to be a data code block. The first specified value indicates that the type of code stream block is a data code stream block. For example, the control block within each group of code stream blocks is represented as TXC<7:0>, and the first specified value is 0x00. If the TXC<7:0> of each group of code stream blocks is 0x00, then the type of each group of code stream blocks is a data code stream block.

[0090] In possible implementations, the first encoding is 2 n In a sequence of code stream blocks, 2 n Performing an operation on data blocks within a group of coded stream blocks to obtain data units includes the following: namely, 2 n In a sequence of code stream blocks, 2 n The process of obtaining a data unit by separately using the bits contained in the data blocks within a group of code stream blocks as bits of the data unit.

[0091] For example, j represents the sequence number of one of the four code stream block groups, where j=0, 1, 2, or 3. TXD_j<63:0> represents the data block in code stream block group j, tx_coded<256:0> represents the target code block, and tx_coded <0> represents the type of the target code block, and tx_coded<(64j+64):(64j+1)> represents bits (64j+64) to (64j+1) of the target code block. In this case, each bit of tx_coded<256:0> is represented in equations 1 and 2 below. tx_coded <0> =1 (formula 1), tx_coded<(64j+64):(64j+1)>=TXD_j<63:0>, where j=0, 1, 2, or 3 (Equation 2).

[0092] In Equation 1, tx_coded <0> =1 indicates that the type is a data code block. In equation 2, tx_coded<(64j+64):(64j+1)>=TXD_j<63:0> indicates that multiple bits in the data block within each code stream block group are used as multiple bits in the data unit, respectively.

[0093] For example, if j=0, tx_coded<64:1>=TXD_0<63:0> indicates that bits 63 through 0 of the data block in code stream block group 0 are used as bits 64 through 1 of the target code block, respectively. If j=1, tx_coded<128:65>=TXD_1<63:0> indicates that bits 63 through 0 of the data block in code stream block group 1 are used as bits 128 through 65 of the target code block, respectively. If j=2, tx_coded<192:129>=TXD_0<63:0> indicates that bits 63 through 0 of the data block in code stream block group 2 are used as bits 192 through 129 of the target code block, respectively. If j=3, then tx_coded<256:193>=TXD_3<63:0> indicates that bits 63 through 0 of the data block in the code stream block group 3 are used as bits 256 through 193 of the target code block, respectively.

[0094] For example, Figure 3 is a schematic diagram illustrating the process of acquiring a target code block. As shown in Figure 3, for the four code stream block groups to be acquired, in each code stream block group, each control block is represented as TXC<7:0> and each data block is represented as TXD<63:0>. If TXC<7:0> in each of the four code stream block groups is 0x00, the type of the target code block is a data code block. For example, the type of the target code block corresponds to bit 0 of the target code block, and bit 0 is set to 1 to indicate that the type is a data code block. This embodiment of the present application does not impose any limitations on the method of setting bit 0 to a value indicating that the type is a data code block. Based on the sequence of the four code stream block groups, the data unit is acquired by using multiple bits of the data block in the four code stream block groups separately as multiple bits of the data unit. Therefore, the target bit can be acquired based on the type and the data unit.

[0095] For example, Figure 4 shows the structure of the target code block to be acquired. Bit 0 of the target code block indicates the type of the target code block, and bit 0 is set to 1 to indicate that the type of the target code block is a data code block. Bits 1 to 256 of the target code block indicate the data units of the target code block, where D0 represents a 64-bit data block in code stream block group 0, D1 represents a 64-bit data block in code stream block group 1, D2 represents a 64-bit data block in code stream block group 2, and D3 represents a 64-bit data block in code stream block group 3.

[0096] In encoding scheme 2, the type of target code block is 2 n Based on the control blocks within the group of code stream blocks, it is determined to be a control code block. n The identifier value for each coded stream block group is 2 n Obtained based on the control blocks within a group of code stream blocks, the identifier value indicates the type of code stream block. n The identifier values ​​of the individual code stream block groups are used as type indicators. The first encoding is 2 n In a sequence determined based on control blocks and data blocks within a group of code stream blocks, 2 n This process is performed on data blocks within a group of code stream blocks to retrieve the code block content. The target code block is then retrieved based on its type and data unit, and the data unit contains a type indicator and the code block content.

[0097] For example, the target code block obtained in encoding scheme 2 includes a type and a data unit. The type indicates that the target code block is a control code block. The data unit includes a type indicator and code block content, and the code block content is 2 nIn a sequence determined based on control blocks and data blocks within a group of code stream blocks, 2 n The type indication is obtained by performing a first encoding on the data blocks within a group of coded stream blocks, and the type indication is 2 n The type indication is obtained based on the control blocks within each group of code stream blocks, and it indicates the type of each group of code stream blocks. For example, 2 n The sequence determined based on the control blocks and data blocks within the group of code stream blocks is 2 n This is the reception sequence for a group of code stream blocks.

[0098] In possible implementations, 2 n If a control block in at least one of the groups of code stream blocks is a second designation, the type of the target code block can be determined to be a control code block by using the second designation. The second designation indicates that the type of code stream block is a control code stream block, and the second designation is different from the first designation. In other words, 2 n If at least one of the code stream block groups is of the type of a control code stream block, then the type of the target code block is a control code block. For example, a control block in each code stream block group is represented as TXC<7:0>, and its first designation value is 0x00. If the TXC<7:0> of one of the code stream block groups is not 0x00, then the target code block is a control code block.

[0099] For example, 2 n For one of the code stream block groups, if the type of the code stream block group is a data code stream block, the identifier value of the code stream block group is the third specified value. Alternatively, if the type of the code stream block group is a control code stream block, the identifier value of the code stream block group is the fourth specified value. For example, the third specified value is 1 and the fourth specified value is 0. For example, 2n The use of identifier values ​​for groups of coded stream blocks as type indicators includes the following: namely, 2 n The identifier value for each coded stream block group is 2 n In a sequence determined based on control blocks and data blocks within a group of code stream blocks, these are used as type indicator bits, respectively, to obtain a type indicator.

[0100] For example, 2 n In a sequence determined based on control blocks and data blocks within a group of code stream blocks, 2 n Performing a first encoding on data blocks within a group of coded stream blocks to obtain the coded block content includes the following: that is, the first encoding is 2 n In a sequence determined based on control blocks and data blocks within a group of code stream blocks, 2 n This process is performed on data blocks within a group of code stream blocks to obtain the first encoded content in the group of code stream blocks, and the first encoded content in the group of code stream blocks is used as the code block content.

[0101] In possible implementations, the type is a data code stream block (TXC<7:0>=0x00)2 n For one set of code stream blocks within a set of code stream blocks, the first encoded content in the code stream block set is the content of the data block of the code stream block set. n For one code stream block group within a set of code stream block groups, based on the control block and data block cases of the code stream block group, the first encoded content in the code stream block group includes, but is not limited to, cases A1 through A11 below.

[0102] Case A1: The control block is 0x01, bits 7 through 0 of the data block are 0xFB, and the LSB is the first bit transmitted.

[0103] For example, in case A1, a data block contains one control byte and seven data bytes, each also called an octet. If the code stream block group is the first control code stream block group, the initial encoded content in the code stream block group is 60 bits, with the first 4 bits being the block type field (BTF) portion, which is 0x8. If the code stream block group is not the first control code stream block group, the initial encoded content in the code stream block group is 64 bits, with the first 8 bits being the BTF portion, which is 0x78. In either of the above cases, the remaining 56 bits are the bits of the seven data bytes contained in the data block.

[0104] Case A2: The control block is 0xFF, and bits (k+7) through k of the data block are at least one of 0x06, 0x07, or 0xFE, where k = 0, 1, 2, 3, 4, 5, 6, or 7, and the LSB is the first bit transmitted.

[0105] For example, in case A2, the data block contains eight control bytes. If the code stream block group is the first control code stream block group, the first encoded content in the code stream block group is 60 bits, the first 4 bits are the BTF portion, and the BTF portion is 0xE. If the code stream block group is not the first control code stream block group, the first encoded content in the code stream block group is 64 bits, the first 8 bits are the BTF portion, and the BTF portion is 0x1E. Regardless of the above cases, the remaining 56 bits are bits 0 through 6 in the eight control bytes contained in the data block.

[0106] Case A3: The control block is 0x01, bits 7 through 0 of the data block are 0x9C, and the LSB is the first bit to be sent.

[0107] For example, in case A3, the data block contains one control byte and seven data bytes. If the code stream block group is the first control code stream block group, the first encoded content in the code stream block group is 60 bits, the first 4 bits are the BTF portion, and the BTF portion is 0xB. If the code stream block group is not the first control code stream block group, the first encoded content in the code stream block group is 64 bits, the first 8 bits are the BTF portion, and the BTF portion is 0x4B. Regardless of the above cases, the 24 bits after the BTF portion are bits 31 to 8 of the data block. The 4 bits after the data byte are the O code. The O code can be obtained according to the IEEE 802.3 standard. For example, the remaining 28 bits are multiple initial padding bits, which may be obtained based on the data byte of the data block, or all of the multiple initial padding bits may be 0.

[0108] Case A4: The control block is 0xFF, bits 7 through 0 of the data block are 0xFD, and the LSB is the first bit transmitted.

[0109] For example, in case A4, the data block contains 8 control bytes. If the code stream block group is the first control code stream block group, the first encoded content in the code stream block group is 60 bits, the first 4 bits are the BTF portion, and the BTF portion is 0x7. If the code stream block group is not the first control code stream block group, the first encoded content in the code stream block group is 64 bits, the first 8 bits are the BTF portion, and the BTF portion is 0x87. Regardless of the above cases, the 7 bits after the BTF portion are all 0, and the remaining 49 bits are bits 6 through 0 in the last 7 control bytes contained in the data block.

[0110] Case A5: The control block is 0xFE, bits 15 through 8 of the data block are 0xFD, and the LSB is the first bit transmitted.

[0111] For example, in case A5, the data block contains one data byte and seven control bytes. If the code stream block group is the first control code stream block group, the first encoded content in the code stream block group is 60 bits, the first 4 bits are the BTF portion, and the BTF portion is 0x9. If the code stream block group is not the first control code stream block group, the first encoded content in the code stream block group is 64 bits, the first 8 bits are the BTF portion, and the BTF portion is 0x99. Regardless of the above cases, the 8 bits after the BTF portion are the bits of the data byte contained in the data block, the 6 bits after the data byte are all 0, and the remaining 42 bits are bits 6 through 0 of the last 6 control bytes contained in the data block.

[0112] Case A6: The control block is 0xFC, bits 23 through 16 of the data block are 0xFD, and the LSB is the first bit to be transmitted.

[0113] For example, in case A6, the data block contains two data bytes and six control bytes. If the code stream block group is the first control code stream block group, the first encoded content in the code stream block group is 60 bits, the first 4 bits are the BTF portion, and the BTF portion is 0xA. If the code stream block group is not the first control code stream block group, the first encoded content in the code stream block group is 64 bits, the first 8 bits are the BTF portion, and the BTF portion is 0xAA. Regardless of the above cases, the 16 bits after the BTF portion are the bits of the two data bytes contained in the data block, the 5 bits after the data bytes are all 0, and the remaining 35 bits are bits 6 through 0 of the last 5 control bytes contained in the data block.

[0114] Case A7: The control block is 0xF8, bits 31 through 24 of the data block are 0xFD, and the LSB is the first bit to be sent.

[0115] For example, in case A7, the data block contains 3 data bytes and 5 control bytes. If the code stream block group is the first control code stream block group, the first encoded content in the code stream block group is 60 bits, the first 4 bits are the BTF portion, and the BTF portion is 0x4. If the code stream block group is not the first control code stream block group, the first encoded content in the code stream block group is 64 bits, the first 8 bits are the BTF portion, and the BTF portion is 0xB4. Regardless of the above cases, the 28 bits after the BTF portion are the bits of the 3 data bytes contained in the data block, the 4 bits after the data bytes are all 0, and the remaining 28 bits are bits 6 through 0 of the last 4 control bytes contained in the data block.

[0116] Case A8: The control block is 0xF0, bits 39 through 32 of the data block are 0xFD, and the LSB is the first bit to be sent.

[0117] For example, in case A8, the data block contains 4 data bytes and 4 control bytes. If the code stream block group is the first control code stream block group, the first encoded content in the code stream block group is 60 bits, the first 4 bits are the BTF portion, and the BTF portion is 0xC. If the code stream block group is not the first control code stream block group, the first encoded content in the code stream block group is 64 bits, the first 8 bits are the BTF portion, and the BTF portion is 0xCC. Regardless of the above cases, the 32 bits after the BTF portion are the bits of the 4 data bytes contained in the data block, the 3 bits after the data bytes are all 0, and the remaining 21 bits are bits 6 through 0 of the last 3 control bytes contained in the data block.

[0118] Case A9: The control block is 0xE0, bits 47 through 40 of the data block are 0xFD, and the LSB is the first bit to be sent.

[0119] For example, in case A9, the data block contains 5 data bytes and 3 control bytes. If the code stream block group is the first control code stream block group, the first encoded content in the code stream block group is 60 bits, the first 4 bits are the BTF portion, and the BTF portion is 0x2. If the code stream block group is not the first control code stream block group, the first encoded content in the code stream block group is 64 bits, the first 8 bits are the BTF portion, and the BTF portion is 0xD2. Regardless of the above cases, the 32 bits after the BTF portion are the bits of the 5 data bytes contained in the data block, the 2 bits after the data bytes are all 0, and the remaining 12 bits are bits 6 through 0 of the last 2 control bytes contained in the data block.

[0120] Case A10: The control block is 0xC0, bits 55 through 48 of the data block are 0xFD, and the LSB is the first bit transmitted.

[0121] For example, in case A10, the data block contains 6 data bytes and 2 control bytes. If the code stream block group is the first control code stream block group, the first encoded content in the code stream block group is 60 bits, the first 4 bits are the BTF portion, and the BTF portion is 0x1. If the code stream block group is not the first control code stream block group, the first encoded content in the code stream block group is 64 bits, the first 8 bits are the BTF portion, and the BTF portion is 0xE1. Regardless of the above cases, the 48 bits after the BTF portion are the bits of the 6 data bytes contained in the data block, the 1 bit after the data byte is 0, and the remaining 7 bits are bits 6 through 0 of the last control byte contained in the data block.

[0122] Case A11: The control block is 0x80, bits 63 through 56 of the data block are 0xFD, and the LSB is the first bit to be sent.

[0123] For example, in case A11, the data block contains seven data bytes and one control byte. If the code stream block group is the first control code stream block group, the first encoded content in the code stream block group is 60 bits, the first 4 bits are the BTF portion, and the BTF portion is 0xF. If the code stream block group is not the first control code stream block group, the first encoded content in the code stream block group is 64 bits, the first 8 bits are the BTF portion, and the BTF portion is 0xFF. Regardless of the above cases, the remaining 56 bits are the bits of the seven data bytes contained in the data block.

[0124] Therefore, 2 n In a sequence determined based on control blocks and data blocks within a group of code stream blocks, 2 n The first encoded content in a group of code stream blocks is used as the code block content. Therefore, the target code block can be retrieved based on its type, type indication, and code block content.

[0125] For example, j represents the sequence number of one of the four code stream block groups, where j=0, 1, 2, or 3. TXC_j<7:0> represents the control block of code stream block group j, and tx_payload<251:0> represents the first encoded content in the four code stream block groups. tx_coded<256:0> represents the target code block, and tx_coded <0> This represents the type of target code block, tx_coded<j+1> represents the type indication of the target code block, and tx_coded<256:5> represents the code block content of the target code block. In this case, the bits of tx_coded<256:0> are shown in equations 3 to 5 below. tx_coded <0> =0(Formula 3)

[0126]

number

[0127] tx_coded<256:5>=tx_payload<251:0> (Formula 5)

[0128] In Equation 3, tx_coded <0> =0 indicates that the type is a control block. In Equation 4, if TXC_j<7:0> is not 0x00, the bit of the target code block corresponding to the value of j is 0. Or, if TXC_j<7:0> is 0x00, the bit of the target code block corresponding to the value of j is 1. In Equation 5, tx_coded<(256:5)>=tx_payload<251:0> indicates that multiple bits of the first coded content in the group of four code stream blocks are used as the code block content of multiple bits.

[0129] For example, Figure 5 shows the structure of the target code block, where 0 to 3 represent the sequence numbers of the four code stream block groups, respectively. In Figure 5, the left side shows the types of the four code stream block groups obtained, where C represents a control code stream block and D represents a data code stream block. The right side of Figure 5 shows the structure of the target code block obtained in various cases, where b represents a bit. For example, 1b represents 1 bit, and 4b represents 4 bits. For example, in Case 1 in Figure 5, all four code stream block groups are control code stream blocks, bit 0 of the target code block obtained through the first encoding is 0, and bits 4 through 1 are all 0. Bits 8 through 5 are represented as f_0 and correspond to the BTF portion in the first encoded content of code stream block group 0, and bits 64 through 9 correspond to the other content in the first encoded content of code stream block group 0, i.e., C0. Bits 72 to 65 are represented as BTF1 and correspond to the BTF portion of the first encoded content in code stream block group 1, and bits 128 to 73 correspond to the other content in the first encoded content in code stream block group 1, i.e., C1. Bits 136 to 129 are represented as BTF2 and correspond to the BTF portion of the first encoded content in code stream block group 2, and bits 192 to 137 correspond to the other content in the first encoded content in code stream block group 2, i.e., C2. Then, bits 200 to 193 are represented as BTF3 and correspond to the BTF portion of the first encoded content in code stream block group 3, and bits 256 to 201 correspond to the other content in the first encoded content in code stream block group 4, i.e., C3. The principle of the other cases in Figure 5 is the same as that of Case 1 described above.For example, in Case 2, bits 68 to 5 of the target code block are represented as D0, corresponding to the first encoded content of code stream block group 0; bits 72 to 69 are represented as f_1, corresponding to the BTF portion within the first encoded content of code stream block group 1; and bits 128 to 73 correspond to the other content within the first encoded content of code stream block group 1, i.e., C1. Other cases in Figure 5 are not described further in this specification.

[0130] In possible implementations, the target code block is an error code block, and the error code block contains error indication data. For example, 2 n If one of the groups of code stream blocks does not belong to a data code stream block and does not belong to any of the cases A1 to A11 described above, the code block in question is determined to be an error code block. n The types of the code stream block groups are 2 n The type indication of the target code stream block is obtained based on the control block within the group of code stream blocks, and is 2 n The type of the code stream block group is obtained based on the type, and the type and type indication are used as error indication data within the error code block. For example, bit 0 of the target code block corresponds to the type, bits 1 through 4 correspond to the type indication, bit 0 is set to 0, and bits 1 through 4 are all set to 1.

[0131] For example, if the target code block is an error code block, the structure of the target code block is shown in Figure 6. The left side of Figure 6 shows the types of the four code stream block groups that are acquired, where E represents an error code stream block. The right side of Figure 6 shows the structure of the target code block. Bit 0 of the target code block is 0, bits 1 through 4 are all 1, bits 5 through 64 correspond to the padding content acquired based on code stream block group 1, bits 65 through 128 correspond to the padding content acquired based on code stream block group 2, bits 129 through 192 correspond to the padding content acquired based on code stream block group 3, and bits 193 through 256 correspond to the padding content acquired based on code stream block group 4. For example, each bit of the padding content is 0. For example, the padding content obtained based on code stream block group 1 is represented as E0, the padding content obtained based on code stream block group 2 is represented as E1, the padding content obtained based on code stream block group 3 is represented as E2, and the padding content obtained based on code stream block group 4 is represented as E3.

[0132] According to the encoding method provided in the embodiments of this application, the first encoding can be performed on various types of code stream blocks to obtain the target code block. Therefore, this method is widely applicable.

[0133] In possible implementations, 2 n The step of performing a first encoding on a group of code stream blocks to obtain the target code block includes the following: namely, 2 n Steps to obtain error detection results based on control blocks and data blocks within a group of code stream blocks, and based on the error detection results, n The group of code stream blocks is processed, and the processed 2 nA step of performing a first encoding on a group of code stream blocks to obtain the target code block. In other words, the target code block is obtained based on the error detection result. n The error detection result is obtained by processing a group of code stream blocks, and the result is 2 n It is obtained based on the control blocks and data blocks within a group of code stream blocks.

[0134] For example, 2 n The step of obtaining error detection results based on control blocks and data blocks within a group of code stream blocks includes the following: 2 n Based on control blocks and data blocks within a group of code stream blocks, 2 n The contents and content sequences of the group of coded stream blocks are obtained, and 2 n A step to obtain error detection results based on the content and content sequence of a group of coded stream blocks. For example, 2 n If the content sequence of the group of code stream blocks is at least one case in the first error case set, then 2 n An error occurs in the content sequence of the group of coded stream blocks. n If the content sequence of the individual code stream block group is not any of the cases in the first error case set, then 2 n The content sequence of the group of coded stream blocks is correct. As another example, 2 n If the contents of the group of code stream blocks are at least one case in the second error case set, then 2 n An error occurs in the content of the group of coded stream blocks. 2 n If the contents of the code stream block group are not any of the errors in the second error case set, then 2 n The content of this set of coded stream blocks is correct.

[0135] In possible implementations, two adjacent groups in a code stream block are used as an example for explanation, and the first error case set includes, but is not limited to, the following four cases:

[0136] (1) If the former set of coded stream blocks includes a start control character ( / S / ), the latter set of coded stream blocks includes content other than data bytes.

[0137] (2) If the former set of coded stream blocks contains only data bytes, the latter set of coded stream blocks contains content other than data bytes or termination control characters ( / T / ).

[0138] (3) If the former set of coded stream blocks includes termination control characters, the latter set of coded stream blocks includes content other than idle control characters ( / I / ) or sequence order set control characters ( / O / ).

[0139] (4) If the former group of coded stream blocks includes an idle control character or a sequence order set control character, the latter group of coded stream blocks includes a data byte or a termination control character.

[0140] In possible implementations, one set of code stream blocks is used as an example for explanation, and the second set of error cases includes, but is not limited to, the following four cases:

[0141] (1) In the case of a coded stream block containing a start control character, the start control character is followed by content other than data bytes.

[0142] (2) In the case of a coded stream block containing data bytes, the data bytes are followed by content other than data bytes or termination control characters.

[0143] (3) In the case of a coded stream block containing a termination control character, the termination control character is followed by content other than an idle control character or a sequence order set control character.

[0144] (4) In the case of a coded stream block containing an idle control character or a sequence order set control character, the idle control character or sequence order set control character is followed by a data byte or an end control character.

[0145] For example, the error detection result is 2 n The error block contains a content sequence error or content error in a group of coded stream blocks, and the error block is 2 n Based on a group of code stream blocks containing content sequence errors or code stream blocks with content errors, the first encoding is obtained based on the code stream block having the correct content sequence and correct content, and the second and content. n This is performed on the error blocks within the group of code stream blocks to obtain the target code block. In other words, if the error detection result is 2 n If a group of code stream blocks contains a content sequence error or a content error, the code block in question is considered to have a correct content sequence and correct content, as well as a code stream block with correct content, and 2 n Based on the error blocks within the set of code stream blocks, the first encoding is performed, and the error blocks are 2 n It is obtained based on a content sequence error or a code stream block containing a content error within a group of code stream blocks. For example, an error block may contain an error control character.

[0146] In possible implementations, for a code stream block with a content sequence error or content error, the content of the code stream block is converted to an error control character to obtain the error block. For example, if the code stream block with a content sequence error or content error is the first group of code stream blocks, the content of the code stream block is converted to the first error control character, which is 60 bits long, with the first 4 bits being 0xE and the subsequent 7 bits being 0x1E. As another example, if the code stream block with a content sequence error or content error is at least one of the second, third, or fourth group of code stream blocks, the content of the code stream block is converted to the second error control character, which is 64 bits long, with the first 8 bits being 0x1E and the subsequent 7 bits being 0x1E.

[0147] For example, a coded stream block having a correct content sequence and correct content, and 2 n Performing a first encoding on error blocks within a group of code stream blocks to obtain a target code block includes the following: namely, the type of the target code block is determined to be a control code block. n Identifier values ​​for the group of code stream blocks are obtained, and the identifier value indicates the type of code stream block, 2 n The identifier values ​​of the coded stream block groups are used as type indicators. And the first coding is 2 n In a sequence determined based on control blocks and data blocks within a group of code stream blocks, an error block, and 2 n This process is performed on data blocks of code streams that have the correct content sequence and correct content within a group of code stream blocks, in order to retrieve the code block content.

[0148] For example, the first encoding is 2 n In a sequence determined based on control blocks and data blocks within a group of code stream blocks, 2 n The process is performed on the data blocks of the code stream blocks that have the correct content sequence and correct content within a group of code stream blocks to obtain the code block content that has the correct content sequence and correct content. The target code block is obtained based on the first encoded content in the code stream block that has the correct content sequence and correct content, as well as the error block. For the method of performing the first encoding on the data blocks of the code stream blocks that have the correct content sequence and correct content, please refer to the related content above for performing the first encoding on code stream blocks of type data code stream blocks and code stream blocks of type control code stream blocks. Further details will not be explained again in this specification.

[0149] For example, 2 n If each of the group of code stream blocks is a code stream block with a content sequence error or a content error, the first encoding is 2 n Based on a set of code stream blocks, 2 n This process is executed on each error block to obtain the target code block, which is an error code block.

[0150] The code stream block in which the error occurred is processed in a way that allows the erroneous data to be distinguished from correct data in subsequent data transmissions, thereby ensuring data reliability.

[0151] For example, after a target code block has been acquired, the method further includes the steps of: obtaining first data by performing a second encoding on the target code block based on the FEC code type; and transmitting the first data. The method of performing the second encoding on the target code block based on the FEC code type is not limited to the embodiments of this application. The second encoding is performed on the target code block based on the FEC code type to obtain first data, thereby enabling the receiver to perform error correction on the received first data to ensure data transmission accuracy.

[0152] According to the encoding method provided in the embodiment of this application, the target code block is 2 n Perform 64B / 66B coding on each of the code stream block groups, 2 n To obtain 66-bit code blocks, or 2 n Without the need to convert the code between individual 66-bit code blocks, two control blocks and data blocks are included. n This is achieved by performing a first encoding on a group of code stream blocks. As a result, encoding efficiency is improved, and the delay, power consumption, and chip area occupied by the encoding process are reduced.

[0153] The encoding method provided in the embodiments of this application has been described above. The decoding method provided in the embodiments of this application will be described below. Referring to the implementation scenario shown in Figure 1, the decoding method provided in one embodiment of this application is shown in Figure 7. For example, the decoding method provided in this embodiment of this application is performed by chip 104 in Figure 1, and the method includes, but is not limited to, steps 701 and 702.

[0154] Step 701: Obtain the target code block, which includes the type and data units.

[0155] For example, referring to the implementation scenario in Figure 1, chip 102 transmits first encoded data to chip 104 via channel 105 using the FEC code type. During the data transmission process, an error bit occurs in the first data. The data in which the error bit occurs is called the second data, and chip 104 receives the second data via channel 105.

[0156] In possible implementations, the step of obtaining the target code block includes, but is not limited to, the following methods A and B.

[0157] Method A: A second data is received, which is obtained based on the first data encoded using the FEC code type; and a second decoding is performed on the second data to obtain the target code block, the second decoding being an error correction process.

[0158] For example, the target code block is the error code block obtained when error correction is performed on the second data but fails. For example, the acquisition of the target code block when a second decoding is performed on the second data includes the following: the second data is processed based on the FEC code type to obtain the first codeword, error correction is performed on the first codeword, and the target code block is obtained based on the result of the error correction.

[0159] For example, chip 104 has the function of an FEC decoder. If the FEC decoder determines that the number of error bits exceeds its error correction capability, in other words, if it determines that error correction cannot be performed on the first codeword, it marks all code blocks within the first codeword as error code blocks. Therefore, if the result of the error correction process is that all code blocks within the first codeword are marked as error code blocks, the target code block to be acquired is an error code block.

[0160] For example, if the result of the error correction process is that the error correction of the first codeword is successful, the code block obtained based on the corrected first codeword is used as the code block to be obtained, and the code block obtained based on the corrected first codeword is the code block that has been successfully corrected.

[0161] Method B: A second data is received, which is obtained based on the first data encoded using a forward error-corrected FEC code type; and a second decoding is performed on the second data to obtain a target code block, the second decoding being an error detection process that bypasses error correction.

[0162] For example, the target code block is an error code block obtained through an error detection process on the second data in which error correction is bypassed. For example, the acquisition of the target code block by performing a second decoding on the second data includes: the second data being processed based on the FEC code type to obtain the first codeword, an error detection process in which error correction is bypassed (bypass correction) being performed on the first codeword, and the acquisition of the target code block based on the result of the error detection process in which error correction is bypassed.

[0163] For example, chip 104 has the function of an FEC decoder. When it detects the presence of an error in the first codeword, the FEC decoder marks all code blocks in the first codeword as erroneous code blocks. Therefore, if the result of the error detection process, which bypasses error correction, is that all code blocks in the first codeword are marked as erroneous code blocks, the target code block to be acquired is an erroneous code block.

[0164] For example, if the result of an error detection process that bypasses error correction is that the first codeword is error-free, then the code block obtained based on the first codeword is used as the target code block to be obtained, and the code block obtained based on the first codeword is an error-free code block.

[0165] For example, a frame check sequence (FCS) performed based on the target code block fails. For example, the target code block is 257 bits, the first 5 bits are 01111, and the remaining 252 bits include, but are not limited to, the following three cases: (1) the first 4 bits are 0x1 and every 8 bits in the remaining bits are 0x1E; (2) the first 248 bits are every 8 bits are 0x1E and the last 4 bits are 0x1; (3) each bit is 0.

[0166] Step S702: Based on the type of the target code block and the data unit, perform a first decoding on the target code block, 2 n Obtain n sign stream block sets, where any sign stream block set includes control blocks and data blocks obtained based on type and data units, and n is an integer greater than 1.

[0167] For example, the target code block is 257 bits, and in each code stream block group, the control block is 8 bits and the data block is 64 bits. For the sake of explanation, we will use an example where the first decoding is performed on one target code block to obtain four code stream block groups (n=2). When multiple target code blocks are obtained, the first decoding is performed on each target code block, and 2 nIt is possible to obtain a set of code stream blocks. For example, if two target code blocks are obtained, the first decoding is performed on each of the two code blocks, and four code stream block sets can be obtained. In other words, the first decoding is performed on two target code blocks, and eight code stream block sets can be obtained.

[0168] In possible implementations, a first decoding is performed on the target code block based on the type and data units of the target code block, and then 2 n The step of obtaining a set of code stream blocks includes, but is not limited to, the following decoding methods 1 to 3.

[0169] In decoding method 1, the type of target code block is determined as a data code block based on the type of target code block, and the data units of the target code block each have a length of 8m. n It contains 1 piece of content, and m is a positive integer. And, 2 n The control blocks within the group of code stream blocks are obtained based on the type of the target code block, and the first decoding has a length of 8m each and is included in the data unit, 2 n It is executed separately for each piece of content, 2 n This refers to retrieving data blocks within a group of coded stream blocks.

[0170] For example, if the type indicates that the target code block is a data code block, the first decoding is performed on the target code block in decoding scheme 1, and 2 n Obtain a set of code stream blocks. 2 n The data blocks included in code stream block group i within a group of code stream blocks are obtained in the data unit by performing a first decoding on the content corresponding to code stream block group i, which has a length of 8m, where i is between 1 and 2. n The following integers, or i is greater than or equal to 2. nIt is an integer less than or equal to -1.

[0171] In a possible implementation, the type of the target code block is 1, indicating that the target code block is a data code block, and the data unit of the target code block contains four contents, each with a length of 8m, where one 8m content corresponds to one code stream block group. For example, 8m is 64 bits long. All control blocks within the four code stream block groups are set to 0x00, and the four 64-bit contents are used as the contents of the data blocks within the four code stream block groups, respectively.

[0172] For example, j represents the sequence number of one of the four code stream block groups, where j=0, 1, 2, or 3. RXC_j<7:0> represents the control block within code stream block group j, RXD_j<63:0> represents the data block within code stream block group j, rx_coded<256:0> represents the target code block, and rx_coded <0> represents the type of the target code block, rx_coded<(64j+64):(64j+1)> represents bits (64j+64) to (64j+1) of the target code block, and the contents of RXC_j<7:0> and RXD_j<63:0> are expressed in equations 6 and 7 below. That is, RXC_j<7:0>=0x00, where j=0, 1, 2, or 3 (Equation 6), RXD_j<63:0>=rx_coded<(64j+64):(64j+1)>, where j=0, 1, 2, or 3 (Equation 7).

[0173] In Equation 6, RXC_j<7:0>=0x00 indicates that the control block within each group of code stream blocks is 0x00. In Equation 7, RXD_j<63:0>=rx_coded<(64j+64):(64j+1)> is used as the 64 bits of the data block within one group of code stream blocks.

[0174] For example, if j=0, then RXD_0<63:0>=rx_coded<64:1> means that bits 64 through 1 of the target code block are used as bits 63 through 0 of the data block in code stream block group 0. If j=1, then RXD_1<63:0>=rx_coded<128:65> means that bits 128 through 65 of the target code block are used as bits 63 through 0 of the data block in code stream block group 1. If j=2, then RXD_2<63:0>=rx_coded<192:129> means that bits 192 through 129 of the target code block are used as bits 63 through 0 of the data block in code stream block group 2. If j=3, then RXD_3<63:0>=rx_coded<256:193> means that bits 256 to 193 of the target code block are used as bits 63 to 0 of the data block in the code stream block group 3.

[0175] Decoding method 2: The type of target code block is determined as a control code block based on the type of target code block, and the data unit of the target code block includes a type indicator and code block content, and the type indicator is 2 n It contains 2 bits, n One bit within a set of bits is a group of code stream blocks corresponding to that bit, and 2 n This indicates the type of one code stream block group within a group of code stream blocks, and the code block content is 2 n It includes a set of bits. n The control blocks within a group of code stream blocks are of type 2. n Bits corresponding to a group of code stream blocks, which are bits in the type indication, and 2 n A set of bits corresponding to a set of code stream blocks, which is obtained based on the set of bits in the code block content. And the first decoding is 2 nBits corresponding to a group of code stream blocks, which are bits in the type indication, and 2 n A set of bits corresponding to a set of code stream blocks, which is performed on a set of bits within the code block content, and 2 n This refers to retrieving data blocks within a group of coded stream blocks.

[0176] For example, if the type indicates that the target code block is a control code block, the first decoding is performed on the target code block in decoding scheme 2, n Obtain a set of code stream blocks. 2 n The control blocks included in code stream block group i within a group of code stream blocks are obtained based on the type, the bits corresponding to code stream block group i, which are in the type indicator, and the group of bits corresponding to code stream block group i, which are in the code block content, where i is between 1 and 2. n i is an integer greater than or equal to 2. n It is an integer less than or equal to -1. And 2 n The data blocks contained within code stream block group i in a group of code stream blocks are obtained by performing a first decoding on the set of bits corresponding to code stream block i, which is a set of bits contained within the code block content, based on the bits in the type indication, which is a set of bits corresponding to code stream block i. For example, the set of bits is a set of multiple bits.

[0177] For example, if one bit in the type indication is 1, the type of code stream block obtained based on that bit is a data code stream block, or if one bit in the type indication is 0, the type of code stream block obtained based on that bit is a control code stream block.

[0178] In possible implementations, 2 n The bit groups are the first bit group and the second bit group.n - It includes one second set of bits, and the number of bits in the first set of bits is different from the number of bits in the second set of bits. For example, one bit of the type indicator corresponds to one set of bits in the code block content. For example, the configuration of the target code block shown in Figure 5 is used as an example for explanation. In Case 1, the type indicator includes 4 bits, and the code block content includes 4 sets of bits. The first bit of the type indicator corresponds to the first set of bits, which are bits 5 through 64 of the target code block. The second bit of the type indicator corresponds to one second set of bits, which are bits 65 through 128 of the target code block. The third bit of the type indicator corresponds to one second set of bits, which are bits 129 through 192 of the target code block. The fourth bit of the type indicator corresponds to one second set of bits, which are bits 193 through 256 of the target code block. In Case 2, the type indicator contains 4 bits, and the code block content contains 4 sets of bits. The first bit of the type indicator corresponds to a second set of bits, which corresponds to bits 5 through 67 of the target code block. The second bit of the type indicator corresponds to a first set of bits, which corresponds to bits 68 through 128 of the target code block. The third bit of the type indicator corresponds to a second set of bits, which corresponds to bits 129 through 192 of the target code block. The fourth bit of the type indicator corresponds to a second set of bits, which corresponds to bits 193 through 256 of the target code block. The principles for the other cases are the same as those for Cases 1 and 2 described above. Further details will not be explained further in this specification.

[0179] In possible implementations, for a bit of type indication, if that bit is 1, the control block of the code stream block obtained based on the type, that bit, and the set of bits corresponding to that bit is 0x00, and the content of the data block of the code stream block obtained by performing a first decoding on the set of bits corresponding to that bit is the content of the set of bits. If that bit is 0, the control block and data block of the code stream block obtained based on the position of that bit and the status of the set of bits corresponding to that bit include, but are not limited to, the following cases B1 through B11.

[0180] Case B1: The bit mentioned above is the first bit with a value of 0, and the first 4 bits of the bit group corresponding to that bit are the BTF portion, which is 0x8. Alternatively, the bit is not the first bit with a value of 0, and the first 8 bits of the bit group corresponding to this bit are the BTF portion, which is 0x78.

[0181] For example, in case B1, seven data bytes are included after the BTF portion in the bit group corresponding to that bit. The control block of the sign stream block is 0x01, and the data block of the sign stream block is 64 bits. Bits 7 through 0 of the data block are 0xFB, and the other 56 bits are the bits of the seven data bytes in the bit group corresponding to that bit. LSB is the first bit transmitted.

[0182] Case B2: The bit mentioned above is the first bit with a value of 0, and the first 4 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0xE. Alternatively, the bit is not the first bit with a value of 0, and the first 8 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0x1E.

[0183] For example, in case B2, eight control bit groups are included after the BTF portion in the bit group corresponding to that bit, and each control bit group contains seven bits. The control block of the code stream block is 0xFF, and the data block of the code stream block is 64 bits. The 64 bits of the data block are obtained based on eight control bit groups, with one control bit group for every eight bits of the data block. The method of obtaining each bit of the data block based on each control bit group is not limited to this embodiment of the present application. For example, each bit of the data block is obtained based on each control bit group according to the IEEE 802.3 standard. For example, bits k+7 to k of the data block are at least one of 0x06, 0x07, or 0xFE, and k = 0, 1, 2, 3, 4, 5, 6, or 7. The LSB is the first bit transmitted.

[0184] Case B3: The bit mentioned above is the first bit with a value of 0, and the first 4 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0xB. Alternatively, the bit is not the first bit with a value of 0, and the first 8 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0x4B.

[0185] For example, in case B3, the BTF portion in the bit group corresponding to that bit is followed by three data bytes, one 4-bit O code, and multiple initial padding bits. The control block of the code stream block is 0x01, and the data block of the code stream block is 64 bits. Bits 7 through 0 of the data block are 0x9C, bits 31 through 8 of the data block are bits of three data bytes, and the remaining 32 bits are obtained based on multiple initial padding bits. The LSB is the first bit transmitted. The method of obtaining the remaining 32 bits based on multiple initial padding bits is not limited to this embodiment of the present application.

[0186] Case B4: The above-mentioned bit is the first bit with a value of 0, and the first 4 bits of the bit group corresponding to said bit are the BTF part, and the BTF part is 0x7. Alternatively, said bit is not the first bit with a value of 0, the first 8 bits of the bit group corresponding to said bit are the BTF part, and the BTF part is 0x87.

[0187] For example, for case B4, after the BTF part in the bit group corresponding to said bit, one 7-bit end control character and 7 control bit groups are included, each control bit group includes 7 bits. The control block of the code stream block is 0xFF, and the data block of the code stream block is 64 bits. Bits 7 to 0 of the data block are 0xFD, the remaining 56 bits are obtained based on the 7 control bit groups, and every time 8 bits in the remaining 56 bits are obtained, they are based on one control bit group. The LSB is the bit transmitted first.

[0188] Case B5: The above-mentioned bit is the first bit with a value of 0, and the first 4 bits of the bit group corresponding to said bit are the BTF part, and the BTF part is 0x9. Alternatively, said bit is not the first bit with a value of 0, the first 8 bits of the bit group corresponding to said bit are the BTF part, and the BTF part is 0x99.

[0189] For example, in case B5, after the BTF portion of the bit group corresponding to that bit, there is one data byte, one 6-bit termination control character, and six control bit groups, each containing 7 bits. The control block of the code stream block is 0xFE, and the data block of the code stream block is 64 bits. Bits 7 through 0 of the data block are the bits of the data byte, bits 15 through 8 of the data block are 0xFD, and the remaining 48 bits are obtained based on six control bit groups, with each additional 8 bits obtained in the remaining 48 bits being based on one control bit group. The LSB is the first bit transmitted.

[0190] Case B6: The bit mentioned above is the first bit with a value of 0, and the first 4 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0xA. Alternatively, the bit is not the first bit with a value of 0, and the first 8 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0xAA.

[0191] For example, in case B6, after the BTF portion of the bit group corresponding to that bit, there are two data bytes, one 5-bit termination control character, and five control bit groups, each control bit group containing 7 bits. The control block of the code stream block is 0xFC, and the data block of the code stream block is 64 bits. Bits 15 through 0 of the data block are obtained based on the bits of the two data bytes, bits 23 through 16 of the data block are 0xFD, and the remaining 40 bits are obtained based on five control bit groups, with each additional 8 bits obtained in the remaining 40 bits being based on one control bit group. The LSB is the first bit transmitted.

[0192] Case B7: The bit mentioned above is the first bit with a value of 0, and the first 4 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0x4. Alternatively, the bit is not the first bit with a value of 0, and the first 8 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0xB4.

[0193] For example, in case B7, after the BTF portion of the bit group corresponding to that bit, there are three data bytes, one 4-bit termination control character, and four control bit groups, each control bit group containing 7 bits. The control block of the code stream block is 0xF8, and the data block of the code stream block is 64 bits. Bits 23 through 0 of the data block are obtained based on the bits of the three data bytes, bits 31 through 24 of the data block are 0xFD, and the remaining 32 bits are obtained based on four control bit groups, with one control bit group being used for every 8 bits obtained in the remaining 32 bits. The LSB is the first bit transmitted.

[0194] Case B8: The bit mentioned above is the first bit with a value of 0, and the first 4 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0xC. Alternatively, the bit is not the first bit with a value of 0, and the first 8 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0xCC.

[0195] For example, in case B8, after the BTF portion of the bit group corresponding to that bit, there are four data bytes, one 3-bit termination control character, and three control bit groups, each containing 7 bits. The control block of the sign stream block is 0xF0, and the data block of the sign stream block is 64 bits. Bits 31 through 0 of the data block are obtained based on the bits of the four data bytes, bits 39 through 32 of the data block are 0xFD, and the remaining 24 bits are obtained based on three control bit groups, with each additional 8 bits obtained in the remaining 24 bits being based on one control bit group. The LSB is the first bit transmitted.

[0196] Case B9: The bit mentioned above is the first bit with a value of 0, and the first 4 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0x2. Alternatively, the bit is not the first bit with a value of 0, and the first 8 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0xD2.

[0197] For example, in case B9, after the BTF portion of the bit group corresponding to that bit, there are five data bytes, one 2-bit termination control character, and two control bit groups, each containing 7 bits. The control block of the code stream block is 0xE0, and the data block of the code stream block is 64 bits. Bits 39 through 0 of the data block are obtained based on the bits of the five data bytes, bits 47 through 40 of the data block are 0xFD, and the remaining 16 bits are obtained based on two control bit groups, with each additional 8 bits obtained in the remaining 16 bits being based on one control bit group. The LSB is the first bit transmitted.

[0198] Case B10: The bit mentioned above is the first bit with a value of 0, and the first 4 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0x1. Alternatively, the bit is not the first bit with a value of 0, and the first 8 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0xE1.

[0199] For example, in case B10, after the BTF portion of the bit group corresponding to that bit, there are six data bytes, one 1-bit termination control character, and one 7-bit control bit group. The control block of the code stream block is 0xC0, and the data block of the code stream block is 64 bits. Bits 47 through 0 of the data block are obtained based on the bits of the six data bytes, bits 55 through 48 of the data block are 0xFD, and the remaining 8 bits are obtained based on the control bit group. The LSB is the first bit transmitted.

[0200] Case B11: The bit mentioned above is the first bit with a value of 0, and the first 4 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0xF. Alternatively, the bit is not the first bit with a value of 0, and the first 8 bits of the bit group corresponding to that bit are the BTF portion, and the BTF portion is 0xFF.

[0201] For example, in case B11, seven data bytes are included after the BTF portion of the bit group corresponding to that bit. The control block of the sign stream block is 0x80, and the data block of the sign stream block is 64 bits. Bits 55 through 0 of the data block are obtained based on the bits of the seven data bytes, and bits 63 through 56 of the data block are 0xFD. The LSB is the first bit to be transmitted.

[0202] In some embodiments, 2 n The control blocks within a group of code stream blocks are of type 2.n Bits corresponding to a group of code stream blocks, which are bits in the type indication, and 2 n A set of bits corresponding to a set of code stream blocks, obtained based on a set of bits within the code block content, and the first decoding is 2 n Bits corresponding to a group of code stream blocks, which are bits in the type indication, and 2 n A set of bits corresponding to a set of code stream blocks, which is performed on a set of bits within the code block content, and 2 n Retrieving a data block within a group of coded stream blocks involves the following: namely, 2 n The third set of 64 bits is 2 n To be obtained based on a set of bits. 2 n The control blocks within each code stream block are of type 2. n Bits corresponding to individual code stream blocks, bits within the type indication, and 2 n It is obtained based on a third set of bits. And the first decoding is 2 n Bits corresponding to individual code stream blocks, based on bits in the type indication, 2 n This is performed on the third set of bits, 2 n To retrieve a data block within a given code stream block.

[0203] For example, for the first bit whose value is 0, the set of bits corresponding to that bit includes a 4-bit BTF portion, and based on the 4-bit BTF portion, an 8-bit BTF portion is obtained to obtain a third set of bits. For example, the IEEE 802.3 standard is queried based on the 4-bit BTF portion to obtain the 8-bit BTF portion, or the correspondence table between the 4-bit BTF portion and the 8-bit BTF portion is queried based on the 4-bit BTF portion to obtain the 8-bit BTF portion.

[0204] If the query is successful, specifically if the IEEE 802.3 standard includes an 8-bit BTF portion corresponding to a 4-bit BTF portion, or if the correspondence table includes an 8-bit BTF portion corresponding to a 4-bit BTF portion, the 8-bit BTF portion is used as the retrieved 8-bit BTF portion. If the query fails, specifically if the IEEE 802.3 standard does not include an 8-bit BTF portion corresponding to a 4-bit BTF portion, or if the correspondence table does not include an 8-bit BTF portion corresponding to a 4-bit BTF portion, the 4-bit BTF portion is marked for retrieval of the 8-bit BTF portion. The method for marking the 4-bit BTF portion is not limited to this embodiment of the present application. For example, the 4-bit BTF portion is used as bits 3 through 0, and bits 7 through 4 are all set to 0. For example, if the query fails, the control block of the code stream block retrieved based on the third set of bits is 0xFF and the data block is 0xFEFEFEFE.

[0205] In some other embodiments, obtaining the control block of the code stream block based on the type, the bit, and the set of bits corresponding to that bit for the first bit whose value is 0, and then obtaining the data block of the code stream block by performing a first decoding on the set of bits corresponding to that bit, includes the following: that the 8-bit BTF portion is queried based on the 4-bit BTF portion contained in the set of bits corresponding to that bit; and, if the query fails, the control block of the code stream block is set to 0xFF and the data block of the code stream block is set to 0xFEFEFEFE. The principle of the method of querying the 8-bit BTF portion based on the 4-bit BTF portion is the same as the principle of the query method in the related content described above. Further details are not described herein.

[0206] Decoding method 3: Based on the type of the target code block and the data unit, the type of the target code block is determined to be an error code block. and 2 nThe control blocks and data blocks within the group of code stream blocks are acquired, n All of these code stream block groups are error code stream blocks.

[0207] For example, the data unit includes a type indicator, and the type and type indicator indicate that the target code block is an error code block. n The control blocks included in each group of code stream blocks are the first value, and 2 n The data blocks contained in each group of code stream blocks are the second value, and the first and second values ​​indicate that the code stream block is an error code stream block. For example, the type of the target code block is 0, the type indication is 1111, and the target code block is an error code block. In this case, the 2 obtained through the first decoding are n Each of the code stream block groups contains a control block of 0xFF, and 2 n The data block in each of the group of coded stream blocks is 0xFEFEFEFE.

[0208] According to the decoding method provided in this embodiment of the present application, the first decoding is performed on various types of target code stream blocks, and 2 n It is possible to obtain a group of code stream blocks. Therefore, this method is widely applicable.

[0209] In possible implementations, based on the type and data units of the target code block, a first decoding is performed on the target code block, and then... n The step of obtaining a group of code stream blocks includes the following: obtaining error detection results based on the type and data units of the target code block; and performing a first decoding on the target code block based on the error detection results and the type and data units of the target code block. nacquiring N coded stream block groups; in other words, 2 n the N coded stream block groups are obtained by performing first decoding on the target coded block based on an error detection result, the type of the target coded block and a data unit, and the error detection result is obtained based on the type of the target coded block and the data unit.

[0210] for example, the step of obtaining an error detection result based on the type of the target coded block and the data unit comprises: obtaining content and a content sequence of the target coded block based on the type of the target coded block and the data unit; and obtaining an error detection result based on the content and the content sequence of the target coded block. For example, if the content sequence of the target coded block matches at least one case in a third error case set, an error occurs in the content sequence of the target coded block; or if the content sequence of the target coded block does not match any case in the third error case set, the content sequence of the target coded block is correct. As another example, if the content of the target coded block matches at least one case in a fourth error case set, an error occurs in the content of the target coded block; or if the content of the target coded block does not match any case in the fourth error case set, the content of the target coded block is correct.

[0211] in a possible implementation, an example in which the target coded block is a control coded block and the target coded block comprises four bit groups is used for description. For two adjacent bit groups, the four error case set includes, but is not limited to, the following four cases:

[0212] (1) when the former bit group comprises a start control character ( / S / ), the latter bit group comprises content other than a data byte.

[0213] (2) If the former set of bits contains only data bytes, the latter set of bits contains content other than data bytes or termination control characters ( / T / ).

[0214] (3) If the former set of bits includes a termination control character, the latter set of bits includes content other than an idle control character ( / I / ) or a sequence order set control character ( / O / ).

[0215] (4) If the former set of bits includes an idle control character or a sequence order set control character, the latter set of bits includes a data byte or an end control character.

[0216] For specific meanings and values ​​of control characters in the embodiments of this application, please refer to IEEE 802.3-2018. Further details are not described again in the embodiments of this application.

[0217] In possible implementations, one set of bits is used as an example for illustrative purposes, and the fourth set of error cases includes, but is not limited to, the following four cases:

[0218] (1) For a set of bits containing a start control character, the start control character is followed by content other than data bytes.

[0219] (2) For a set of bits that includes a data byte, the data byte is followed by content other than a data byte or termination control character.

[0220] (3) For a set of bits containing a termination control character, the termination control character is followed by content other than an idle control character or a sequence order set control character.

[0221] (4) For a set of bits that includes an idle control character or a sequence order set control character, the idle control character or sequence order set control character is followed by a data byte or an end control character.

[0222] In possible implementations, the error detection result includes a content sequence error or content error in the target code block, and based on the error detection result, the type of the target code block, and the data unit, a first decoding is performed on the target code block. n The step of obtaining a group of code stream blocks includes the following: a step of transforming the target code block to obtain a second code block; and a step of performing a first decoding on the second code block based on the type and data units of the second code block. n A step to obtain a set of coded stream blocks. In other words, 2 n The code stream block set is obtained by performing a first decoding on the second code block based on the type and data units of the second code block, the second code block being a code block obtained by transforming the target code block, and having the same number of bits as the target code block.

[0223] For example, the step of transforming a target code block to obtain a second code block includes: a step of converting a group of bits in the target code block that have a content sequence error or a content error into an error control character; and a step of obtaining a second code block based on the error control character and a group of bits in the target code block that have the correct content sequence error and the correct content. For example, the first group of bits is converted into a first error control character, and the first group of bits is a group of bits that have a content sequence error or a content error. As another example, the second group of bits is converted into a second error control character, and the second group of bits is a group of bits that have a content sequence error or a content error. In a possible implementation, the second code block obtained through the transformation is a control code block, and the first decoding is performed on the second code block in decoding scheme 2.

[0224] In another possible implementation, the error detection result includes a content sequence error or content error in the target code block, and based on the error detection result, the type of the target code block, and the data unit, a first decoding is performed on the target code block. n The step of obtaining a group of code stream blocks includes the following: Based on the type and data units of the target code block, a first decoding is performed on the target code block, and the first two n Steps to obtain a group of code stream blocks, and the first two n Transform the group of code stream blocks, 2 n A step to obtain a set of coded stream blocks. In other words, 2 n The group of code stream blocks is the first 2 n Obtained by transforming a group of code stream blocks, the first 2 n The set of code stream blocks is obtained by performing a first decoding on the target code block, based on the type and data units of the target code block.

[0225] For example, the first 2 n Transform the group of code stream blocks, 2 n The step of obtaining a group of code stream blocks includes the following: a step of converting a code stream block into an error code stream block, wherein the code stream block is first 2 n A step in which a group of bits within a group of code stream blocks is obtained based on a content sequence error or a group of bits having a content error. For example, in an error code stream block, the control block is 0xFF and each data block is 0xFEFEFEFE. The code block in which the error occurs is processed so that the receiver can distinguish between error data and correct data and ensure data reliability.

[0226] According to the decoding method provided in this embodiment of the present application, two blocks including a control block and a data block are used. n The group of code stream blocks performs a code transformation on the target code block. n Obtain 66-bit code blocks, 2 n This is achieved by performing a first decoding on the target code block without the need to decode individual 66-bit code blocks. Consequently, decoding efficiency is improved, and the delay, power consumption, and chip area occupancy caused by the decoding process are reduced.

[0227] The above describes the encoding method provided in the embodiments of this application. Corresponding to the method described above, embodiments of this application further provide an encoding device. Figure 8 is a schematic diagram of the configuration of an encoding device according to one embodiment of this application. This device is used in a first network device, the first network device being the first network device in the embodiment shown in Figure 1. Based on the following modules shown in Figure 8, the encoding device shown in Figure 8 can perform all or some of the operations performed by the first network device. It should be understood that the device may include more additional modules than those shown, or some of the modules shown may be omitted. This is not limited to these embodiments of this application. As shown in Figure 8, the device is, 2 n An acquisition module 801 configured to acquire a group of code stream blocks, wherein every group of code stream blocks includes control blocks and data blocks, and n is an integer greater than 1. 2 n A first coding module 802 configured to perform a first coding on a group of code stream blocks to obtain a target code block, wherein the target code block is 2 n The type is determined based on the control blocks in the group of code stream blocks, and 2 nIt includes a first encoding module 802 which includes a data unit determined based on control blocks and data blocks in a group of code stream blocks.

[0228] In possible implementations, the type indicates that the target code block is a data code block, and the data units are 2 n In a sequence of two code stream block groups n It is obtained by performing the first encoding on the data blocks in the group of coded stream blocks.

[0229] In possible implementations, the type indicates that the target code block is a control code block, and the data unit contains the type indication and the code block content, and the code block content is 2 n The sequence determined based on the control block and data block in the group of code stream blocks is 2 n The type indication is obtained by performing a first encoding on the data blocks in a group of coded stream blocks, and the type indication is 2 n The type indication is obtained based on the control blocks in each group of code stream blocks, and it indicates the type of each group of code stream blocks.

[0230] In possible implementations, the target code block is an error code block, and the error code block contains error indication data.

[0231] In possible implementations, the target code block is determined based on the error detection result. n The error detection result is obtained by processing a group of code stream blocks, and the result is 2 n It is obtained based on the control blocks and data blocks in a group of code stream blocks.

[0232] In possible implementations, the error detection result is 2 nThe code block in question contains a content sequence error or content error in a group of code stream blocks, and the code stream block has a correct content sequence and correct content, and 2 n It is obtained by performing a first encoding based on the error blocks in a group of code stream blocks, and the error blocks are 2 n This is obtained based on the content sequence error or the code stream block having a content error in a group of code stream blocks.

[0233] In a possible implementation, the control block contains m bits, and the data block contains 8m bits, where m is a positive integer.

[0234] In a possible implementation, the value of n is 2, the value of m is 8, and the target code block is 257 bits.

[0235] In possible implementations, 2 n All of these coded stream blocks are obtained from the media-independent interface MII.

[0236] In a possible implementation, the device further includes a second coding module 803 configured to perform a second coding on a target code block based on a forward error-corrected FEC code type to obtain the first data, and a transmit module 804 configured to transmit the first data.

[0237] According to the encoding device provided in this embodiment of the present application, the target code block is 2 n Perform 64B / 66B encoding on each of the code stream block groups. n Obtain 66-bit code blocks, 2 n Two 66-bit code blocks, including control and data blocks, can be coded without the need for code conversion. nThis is obtained by performing a first encoding on a group of code stream blocks. Therefore, encoding efficiency is improved, and the delay, power consumption, and chip area occupied by the encoding process are reduced.

[0238] The above describes a decoding method provided in embodiments of the present application. Corresponding to the method described above, embodiments of the present application further provide a decoding device. Figure 9 is a schematic diagram of the configuration of a decoding device according to one embodiment of the present application. This device may be used in a second network device, the second network device being the second network device in the embodiment shown in Figure 1. Based on the following modules shown in Figure 9, the decoding device shown in Figure 9 can perform all or some of the operations performed by the second network device. It should be understood that the device may include more additional modules than those shown, or some of the modules shown may be omitted. This is not limited to these embodiments of the present application. As shown in Figure 9, the device includes: namely, An acquisition module 901 configured to acquire a target code block, wherein the target code block includes a type and a data unit. Based on the type and data units of the target code block, a first decoding is performed on the target code block, and 2 n A decoding module 902 configured to acquire n code stream block sets, wherein any code stream block set includes control blocks and data blocks acquired based on type and data units, and n is an integer greater than 1.

[0239] In possible implementations, the type indicates that the target code block is a data code block. And 2 nThe data blocks contained in code stream block group i within a group of code stream blocks are obtained in the data unit by performing a first decoding on the content corresponding to code stream block group i, which has a length of 8m, where m is a positive integer and i is between 1 and 2. n The following integers, or i is greater than or equal to 2. n It is an integer less than or equal to -1.

[0240] In possible implementations, the type indicates that the target code block is a control code block, the data unit contains the type indication and the code block content, and the type indication is 2 n Includes 2 bits n One bit within a bit is a group of code stream blocks corresponding to that bit, 2 n This indicates the type of one code stream block group within a group of code stream blocks, and the code block content is 2 n Contains a set of bits. 2 n The control blocks included in code stream block group i within a group of code stream blocks are obtained based on the type, the bits corresponding to code stream block group i, which are in the type indicator, and the group of bits corresponding to code stream block group i, which are in the code block content, where i is between 1 and 2. n The following integers, or i is greater than or equal to 2. n It is an integer less than or equal to -1. And 2 n The data blocks contained in code stream block group i within a group of code stream blocks are obtained by performing a first decoding on the group of bits corresponding to code stream block group i, which is the group of bits in the code block content, based on the bits in the type indication, which is the bits corresponding to code stream block group i.

[0241] In possible implementations, 2 n The set of bits consists of the first set of bits and 2 nIt includes -1 second set of bits, and the number of bits in the first set of bits is different from the number of bits in the second set of bits.

[0242] In possible implementations, the data unit includes a type indicator, and the type and type indicator indicate that the target code block is an error code block. n The control blocks included in each group of code stream blocks are the first value, and 2 n Each data block in each of the n-numbered code stream block groups is the second value, and the first and second values ​​indicate that the code stream block is an error code stream block.

[0243] In a possible implementation, the acquisition module is configured to: receive a second data, which is acquired based on the first data encoded using a forward error-corrected FEC code type; and perform a second decoding on the second data to acquire the target code block, the second decoding being an error correction process.

[0244] In a possible implementation, the target code block is the code block obtained when error correction is performed on the second data, but the error correction fails.

[0245] In a possible implementation, the acquisition module 901 is configured to: receive a second data, which is acquired based on a first data encoded using a forward error-corrected FEC code type; and perform a second decoding on the second data to acquire a target code block, the second decoding being an error detection process that bypasses error correction.

[0246] In a possible implementation, the target code block is the code block obtained when an error is detected in the second data, but error correction is bypassed.

[0247] In possible implementations, 2 n The code stream block group is obtained by performing a first decoding on the target code block based on the error detection result, the type of the target code block, and the data unit, and the error detection result is obtained based on the type of the target code block and the data unit.

[0248] In possible implementations, the error detection result includes a content sequence error or content error in the target code block, and 2 n The code stream block set is obtained by performing a first decoding on the second code block based on the type and data units of the second code block, the second code block being a code block obtained by transforming the target code block, and having the same number of bits as the target code block.

[0249] In possible implementations, the error detection result includes a content sequence error or content error in the target code block, and 2 n The group of code stream blocks is the first 2 n Obtained by transforming a group of code stream blocks, the first 2 n The set of code stream blocks is obtained by performing a first decoding on the target code block, based on the type and data units of the target code block.

[0250] In a possible implementation, the control block contains m bits and the data block contains 8m bits, where m is a positive integer.

[0251] In a possible implementation, the value of n is 2, the value of m is 8, and the target code block is 257 bits.

[0252] In possible implementations, 2 n All of these coded stream block sets are in the format of the Media Independent Interface (MII).

[0253] According to the decoding device provided in this embodiment of the application, two blocks, including a control block and a data block, are provided. n The group of code stream blocks performs code transformation on the target code block, and then... n To obtain 66-bit code blocks, or 2 n This is achieved by performing a first decoding on the target code block without the need to decode individual 66-bit code blocks. Consequently, decoding efficiency is improved, and the delay, power consumption, and chip area occupancy caused by the decoding process are reduced.

[0254] It should be understood that when the apparatus provided in Figures 8 and 9 implements the functions of this apparatus, the division of the functional modules described above is used merely as an illustrative example. In actual applications, the functions described above may be allocated to different functional modules for implementation based on requirements; in other words, the internal configuration of the apparatus is divided into different functional modules to implement all or part of the functions described above. In addition, the apparatus provided in the embodiments described above and the embodiments of this method belong to the same concept. For their specific implementation processes, please refer to the embodiments of this method. Further details are not described again in this specification.

[0255] For specific hardware configurations in the device in the embodiments described above, please refer to the network device 1500 shown in Figure 10. The network device 1500 includes a transceiver 1501, a processor 1502, and a memory 1503. The transceiver 1501, processor 1502, and memory 1503 are interconnected by using a bus 1504. The transceiver 1501 is configured to receive and transmit packets. The memory 1503 is configured to store instructions or program code. The processor 1502 is configured to call instructions or program code in the memory 1503, enabling the device to execute the relevant processing steps of the first or second network device in the embodiments of the method described above. In particular embodiments, the network device 1500 in this embodiment of the application may correspond to the first or second network device in each of the embodiments of the method described above. The processor 1502 within the network device 1500 reads instructions or program code in the memory 1503, enabling the network device 1500 shown in Figure 10 to perform all or part of the operations performed by the first or second network device.

[0256] The network device 1500 may further correspond to the devices shown in Figures 8 and 9. For example, the acquisition modules 801 and 901 in Figures 8 and 9 are equivalent to the transceiver 1501, and the first acquisition module 802 and decoding module 902 are equivalent to the processor 1502.

[0257] Figure 11 is a schematic diagram showing the configuration of a network device 2000 provided in an exemplary embodiment of this application. The network device 2000 shown in Figure 11 is configured to perform operations related to the encoding method shown in Figure 2 and operations related to the decoding method shown in Figure 7. The network device 2000 is, for example, a switch or a router.

[0258] As shown in Figure 11, the network device 2000 includes at least one processor 2001, memory 2003, and at least one communication interface 2004.

[0259] The processor 2001 is, for example, a central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits configured to implement the solution of this application. For example, the processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or another programmable logic device, a transistor logic device, a hardware component, or any combination thereof. A PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor may implement or execute various logic blocks, modules, and circuits as described with reference to embodiments of the present invention. Alternatively, the processor may be a combination of processors implementing computing functions, for example, a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0260] Optionally, the network device 2000 further includes a bus. The bus is configured to transmit information between components of the network device 2000. The bus may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, and similar. The bus may be classified as an address bus, a data bus, a control bus, and similar. For ease of representation, only a single thick line is used to represent the bus in Figure 11, but this does not mean that only one bus or one type of bus exists. In addition to being connected via a bus, the components of the network device 2000 in Figure 11 may be connected in other ways. In this embodiment of the present invention, the way in which the components are connected is not limited.

[0261] Memory 2003 is, for example, read-only memory (ROM) or another type of static storage device capable of storing static information and instructions; another example being random access memory (RAM) or another type of dynamic storage device capable of storing information and instructions; another example being electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital multipurpose discs, Blu-ray discs, and similar), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to transport or store desired program code in the form of instructions or data structures and that can be accessed by a computer. For example, memory 2003 may exist independently and be connected to processor 2001 via a bus. Alternatively, memory 2003 and processor 2001 may be integrated.

[0262] The communication interface 2004 is configured to communicate with another device or communication network using any device such as a transceiver. The communication network may be Ethernet, a wireless access network (RAN), a wireless local area network (WLAN), and similar. The communication interface 2004 may include a wired communication interface and may further include a wireless communication interface. Specifically, the communication interface 2004 may be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. In this embodiment of the present application, the communication interface 2004 may be used by network equipment 2000 to communicate with another device.

[0263] In a particular implementation, in one embodiment, the processor 2001 may include one or more CPUs, for example, CPU0 and CPU1 shown in Figure 11. Each of the processors may be a single-core processor or a multi-core processor. The processors described herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0264] In a particular implementation, in one embodiment, the network device 2000 may include multiple processors, such as processor 2001 and processor 2005 in Figure 11. Each of the processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. A processor as used herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0265] In certain implementations, in one embodiment, the network device 2000 may further include output devices and input devices. The output device communicates with the processor 2001 and can display information in multiple ways. For example, the output device may be a liquid crystal display (LCD), a light-emitting diode (LED) display device, a cathode ray tube (CRT) display device, a projector, and the like. The input device communicates with the processor 2001 and can receive user input in multiple ways. For example, the input device may be a mouse, a keyboard, a touchscreen device, or a sensing device.

[0266] In some embodiments, memory 2003 is configured to store program code 2010 for executing the solution of the present application, and processor 2001 may execute program code 2010 stored in memory 2003. In other words, network device 2000 may implement the encoding or decoding method provided in embodiments of the present method by using processor 2001 and program code 2010 in memory 2003. Program code 2010 may include one or more software modules. Optionally, processor 2001 may store program code or instructions for executing the solution of the present application.

[0267] In certain embodiments, the network device 2000 in this embodiment of the application may correspond to the first or second network device in each of the embodiments of the method described above. The processor 2001 within the network device 2000 reads program code 2010 in memory 2003, or program code or instructions stored in memory 2001, enabling the network device 2000 shown in Figure 11 to perform all or part of the operations performed by the first or second network device.

[0268] Network device 2000 can further correspond to the devices shown in Figures 8 and 9. Each functional module in the devices shown in Figures 8 and 9 is implemented by using the software of network device 2000. In other words, the functional modules included in the devices shown in Figures 8 and 9 are generated after the processor 2001 in network device 2000 reads the program code 2010 stored in memory 2003. For example, acquisition modules 801 and 901 in Figures 8 and 9 are equivalent to the communication interface 2004, and the first acquisition module 802 and decoding module 902 are equivalent to processor 2001 and / or processor 2005.

[0269] The steps of the method shown in Figures 2 and 7 are completed by using instructions in the form of hardware integrated logic circuits or software in the processor of the network device 2000. The steps of the method disclosed with reference to embodiments of this application may be performed directly by the hardware processor or by using a combination of hardware within the processor and a software module. The software module may be located in a storage medium developed in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. The storage medium is located in memory. The processor reads the information in memory and, in combination with the processor hardware, completes the steps of the method described above. To avoid repetition, further details are not described herein.

[0270] Figure 12 is a schematic diagram showing the configuration of a network device 2100 provided in another exemplary embodiment of this application. The network device 2100 shown in Figure 12 is configured to perform all or part of the operations in the manner shown in Figures 2 and 7. The network device 2100 is, for example, a switch or a router. The network device 2100 may be implemented by a general-purpose bus architecture.

[0271] As shown in Figure 12, the network device 2100 may include a main control board 2110 and an interface board 2130.

[0272] The main control board is sometimes called the main processing unit (MPU) or route processor card. The main control board 2110 is configured to control and manage each component within the network device 2100, including functions for route calculation, device management, device maintenance, and protocol processing. The main control board 2110 includes a central processing unit 2111 and memory 2112.

[0273] Interface board 2130 is line Processing unit (Line Processing Unit, LPU) card It is sometimes called a line card or service board. The interface board 2130 is configured to provide various service interfaces and implement data packet forwarding. The service interfaces include, but are not limited to, Ethernet interfaces and POS (packet over SONET / SDH) interfaces. Ethernet interfaces are, for example, flexible Ethernet clients (FlexE Clients). The interface board 2130 includes, namely, a central processing unit 2131, a network processor 2132, a forwarding entry memory 2134, and a physical interface card (PIC) 2133.

[0274] The central processing unit 2131 on the interface board 2130 is configured to perform the following: control and manage the interface board 2130 and communicate with the central processing unit 2111 on the main control board 2110.

[0275] The network processor 2132 is configured to implement packet transmission processing. The form of the network processor 2132 may be a forwarding chip. The forwarding chip may be a network processor (NP). In some embodiments, the forwarding chip may be implemented using an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 2132 is configured to forward received packets based on a forwarding table stored in the forwarding entry memory 2134. If the destination address of the packet is the address of network equipment 2100, the network processor 2132 sends the packet to the CPU (e.g., a central processing unit 2131) for processing. If the destination address of the packet is not the address of network equipment 2100, the network processor 2132 finds the next hop and the egress interface corresponding to the destination address from the forwarding table based on the destination address and forwards the packet to the egress interface corresponding to the destination address. Processing uplink packets may include: That is, processing the inbound interface of a packet and looking up the forwarding table. Processing downlink packets may include, that is, looking up the forwarding table and so on. In some embodiments, the central processing unit may also perform the functions of a forwarding chip, such as implementing software forwarding based on a general-purpose CPU, thereby eliminating the need for a forwarding chip on the interface board.

[0276] The physical interface card 2133 is configured to implement physical layer interconnection functionality, so that the original traffic enters the interface board 2130 and the processed packets are transmitted from the physical interface card 2133. The physical interface card 2133 may also be called a subcard and may be installed on the interface board 2130, and is involved in converting optical / electrical signals into packets, performing validation checks on the packets, and then forwarding the packets to the network processor 2132 for processing. In some embodiments, the central processing unit 2131 may also perform functions of the network processor 2132, such as implementing software forwarding based on a general-purpose CPU. Therefore, the network processor 2132 is not required by the physical interface card 2133.

[0277] Optionally, the network device 2100 includes multiple interface boards. For example, the network device 2100 further includes an interface board 2140. The interface board 2140 includes a central processing unit 2141, a network processor 2142, a transfer entry memory 2144, and a physical interface card 2143. The functions and implementations of the components within the interface board 2140 are the same as or similar to those of the interface board 2130, and are not described further in this specification.

[0278] Optionally, the network device 2100 further includes a switching board 2120. The switching board 2120 is sometimes called a switch fabric unit (SFU). If the network device has multiple interface boards, the switching board 2120 is configured to perform data exchange between the interface boards. For example, interface boards 2130 and 2140 can communicate with each other by using the switching board 2120.

[0279] The main control board 2110 is coupled to the interface boards. For example, the main control board 2110, interface board 2130, interface board 2140, and switching board 2120 are connected to the system backboard by using the system bus for interaction. In possible implementations, an inter-process communication (IPC) protocol channel is established between the main control board 2110, interface board 2130, and interface board 2140, and the main control board 2110 communicates with interface boards 2130 and 2140 via the IPC channel.

[0280] Logically, the network device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board 2110 and a central processing unit 2111. The forwarding plane includes components that perform forwarding, such as a forwarding entry memory 2134, a physical interface card 2133, and a network processor 2132. The control plane performs router-like functions, namely generating forwarding tables, processing signaling packets and protocol packets, and configuring and maintaining the state of the network device. The control plane delivers the generated forwarding tables to the forwarding plane. On the forwarding plane, the network processor 2132 searches for tables for forwarding packets received by the physical interface card 2133 based on the forwarding tables delivered by the control plane. The forwarding tables delivered by the control plane may be stored in the forwarding entry memory 2134. In some embodiments, the control plane and the forwarding plane may be completely separate and not reside on the same network device.

[0281] It should be noted that there may be one or more main control boards, and if there are multiple main control boards, they may include a primary main control board and a secondary main control board. There may be one or more interface boards. Network devices with more powerful data processing capabilities will provide a larger number of interface boards. One or more physical interface cards may be present on an interface board. Switching boards may or may not be present. If multiple switching boards are present, load balancing and redundant backups may be implemented together. In a centralized forwarding architecture, network devices may not require switching boards, and interface boards perform the function of processing service data for the entire system. In a distributed forwarding architecture, network devices may have at least one switching board, and by using switching boards, data exchange between multiple interface boards is implemented to provide high-capacity data exchange and processing capabilities. Therefore, the data access and processing capabilities of network devices in a distributed architecture are more advanced than those of network devices in a centralized architecture. Optionally, the configuration of network devices may be a single board. In other words, there is no switch fabric board, and the functions of the interface board and main control board are integrated into a single board. In this case, the central processing unit on the interface board and the central processing unit on the main control board can be integrated into a single central processing unit on the single board. The single central processing unit on the board performs the functions of the two central processing units that exist after the two central processing units have been integrated. Network equipment in this form has low data exchange and processing capabilities (e.g., network equipment such as low-end switches or routers). The specific architecture to be used depends on the specific networking deployment scenario, which is not limited herein.

[0282] In certain embodiments, the network device 2100 further corresponds to the device shown in Figures 8 and 9. In some embodiments, the acquisition modules 801 and 901 in the device shown in Figures 8 and 9 are equivalent to the physical interface card 2133 or physical interface card 2143 in the network device 2100. The first encoding module 802 and decoding module 902 in the device shown in Figures 8 and 9 are equivalent to at least one of the central processing unit 2111, network processor 2132, and network processor 2142 in the network device 2100.

[0283] Based on the network equipment shown in Figures 10, 11, and 12, one embodiment of the present application further provides a communication system. The system includes a first network device and a second network device. Optionally, the first network device is network device 1500 shown in Figure 10, network device 2000 shown in Figure 11, or network device 2100 shown in Figure 12, and the second edge network device is network device 1500 shown in Figure 10, network device 2000 shown in Figure 11, or network device 2100 shown in Figure 12.

[0284] For details of the methods performed by the first and second network devices, please refer to the relevant descriptions of the embodiments shown in Figures 1, 2, and 7. Further details are not provided herein.

[0285] It should be understood that the processor may be a central processing unit (CPU), or another general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or another programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or similar. A general-purpose processor may be a microprocessor, any conventional processor, or similar. It should be noted that the processor may be a processor supporting advanced reduced-instruction-set computing machines (ARM).

[0286] Furthermore, in optional embodiments, the memory may include read-only memory and random access memory, and may provide instructions and data to the processor. The memory may further include non-volatile random access memory. For example, the memory may further store device type information.

[0287] The memory may be volatile memory or non-volatile memory, or it may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM) used as an external cache. Rather than being a limitation, it is important to note that numerous forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct rambus random access memory (DR RAM).

[0288] A computer-readable storage medium is further provided. This storage medium stores at least one program instruction or code. When the program instruction or code is loaded and executed by a processor, the computer can implement the encoding method shown in Figure 2 or the decoding method shown in Figure 7.

[0289] This application provides a computer program (product). When the computer program is executed by a computer, the processor or computer becomes capable of performing the corresponding steps and / or procedures in the embodiments of the method described above.

[0290] A chip including a processor is provided. This chip is configured to call and execute instructions stored in memory, thereby enabling the communication device on which the chip is installed to perform the method described above.

[0291] Another chip is provided. This chip includes an input interface, an output interface, a processor, and memory. The input interface, output interface, processor, and memory are connected via an internal connection path. The processor is configured to execute code in memory. Once the code is executed, the processor is configured to perform the method described in the above embodiment.

[0292] Further equipment will be provided. This equipment will include the chip mentioned above. Optionally, this equipment may be network equipment. For example, this equipment may be a router, switch, or server.

[0293] All or part of the embodiments described above may be implemented using software, hardware, firmware, or any combination thereof. When software is used to implement an embodiment, all or part of the embodiment may be implemented in the form of a computer program product. A computer program product includes one or more computer instructions. When a computer program instruction is loaded onto a computer and executed, all or part of the procedures or functions according to this application are generated. The computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired method (e.g., coaxial cable, optical fiber, or digital subscriber line) or by a wireless method (e.g., infrared, radio, or microwave). Computer-readable storage media may be any usable media accessible by a computer, or they may be data storage devices, such as servers or data centers that integrate one or more usable media. Usable media may be magnetic media (e.g., floppy disks, hard disks, or magnetic tapes), optical media (e.g., DVDs), semiconductor media (e.g., solid-state drives (SSDs)), or similar.

[0294] The specific implementation described above provides further details about the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is merely a specific implementation in this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, or similar actions based on the technical solution of this application shall fall within the scope of protection of this application.

[0295] Those skilled in the art will recognize, by referring to the procedures and modules of the methods described in the embodiments disclosed herein, that the procedures and modules of the methods can be implemented by using software, hardware, firmware, or a combination thereof. To clearly illustrate the compatibility between hardware and software, the procedures and configurations of the embodiments are described in the above description in general terms of function. Whether a function is performed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may implement the functions described for each specific application using different methods, but such implementations should not be considered beyond the scope of this application.

[0296] Those skilled in the art will understand that all or part of the steps of this embodiment may be implemented by a program that instructs hardware or related hardware. The program may be stored in a computer-readable storage medium, which may include read-only memory, magnetic disks, or optical disks.

[0297] When software is used to implement an embodiment, all or part of the embodiment may be implemented in the form of a computer program product. A computer program product includes one or more computer program instructions. For example, a method according to an embodiment of this application may be described in the context of machine-executable instructions. For example, machine-executable instructions are contained in a program module within a component for execution on a target real or virtual processor. Generally, a program module includes routines, programs, libraries, objects, classes, components, data structures, and the like, which perform a particular task or implement a particular abstract data structure. In various embodiments, the functions of program modules may be combined or separated among the described program modules. Machine-executable instructions for program modules may be executed locally or within a distributed device. In a distributed device, program modules may reside on both local and remote storage media.

[0298] Computer program code for implementing the methods in embodiments of this application may be written in one or more programming languages. The computer program code may be provided to a processor of a general-purpose computer, a dedicated computer, or another programmable data processing device, so that when the program code is executed by the computer or another programmable data processing device, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code may run entirely on a computer, partially on a computer, as a standalone software package, partially on a computer and partially on a remote computer, or entirely on a remote computer or server.

[0299] In the context of the embodiments of this application, computer program code or associated data may be carried on any suitable carrier, thereby enabling a device, apparatus, or processor to perform the various types of processing and operations described above. Examples of carriers include signals, computer-readable media, and the like.

[0300] Examples of signals may include electrical signals, optical signals, radio signals, audio signals, or other forms of propagating signals such as carrier waves and infrared signals.

[0301] A machine-readable medium may be any tangible medium that contains or stores a program for an instruction execution system, device, or apparatus, or a program relating to an instruction execution system, device, or apparatus. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination thereof. More detailed examples of machine-readable storage media include electrical connections to one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0302] For the sake of convenience and simplicity, it will be readily apparent to those skilled in the art that the detailed working processes of the systems, equipment, and modules described above will be referred to by the corresponding processes in the embodiments of the methods described above. Further details will not be described further herein.

[0303] In some embodiments provided in this application, it should be understood that the systems, devices, and methods disclosed may be implemented in other ways. For example, the embodiments of the devices described are merely examples. For example, the division into modules is simply a division into logical functions, and other modes of division may exist in actual application. For example, multiple modules or components may be combined, integrated into another system, or some characteristics may be ignored or not performed. Furthermore, the mutual or direct coupling or communication connection shown or described may be an indirect coupling or communication connection implemented through some interface, device, or module, or it may be an electrical connection, a mechanical connection, or other form of connection.

[0304] Modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, specifically, they may be located in one location or distributed across multiple network modules. Some or all of the modules may be selected based on actual requirements to implement the objectives of the solutions in embodiments of this application.

[0305] Furthermore, the functional modules in the embodiments of this application may be integrated into a single processing module, or each module may exist physically independently, or two or more modules may be integrated into a single module. The integrated module may be implemented in hardware form or in the form of a software functional module.

[0306] When an integrated module is implemented in the form of a software functional module and sold or used as an independent product, the integrated module may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or a portion that contributes to the prior art, or all or part of the technical solution, may be implemented in the form of a software product. A computer software product is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, server, or network device) to perform all or part of the steps of the method described in embodiments of this application. The storage medium mentioned above includes any medium capable of storing program code, such as a USB flash drive, a removable hard disk, read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0307] In this application, terms such as “first” and “second” are used to distinguish between the same or similar items that have essentially the same function. It should be understood that “first,” “second,” and “nth” do not limit the quantity or execution sequence without having logical or chronological dependencies. In the following description, terms such as “first” and “second” are used to describe various elements, but it should also be understood that these elements should not be limited by the terms described above. These terms are simply used to distinguish one element from another. For example, without deviating from the scope of various examples, a first network device may be called a second network device, and similarly, a second network device may be called a first network device. Both the first and second network devices may be any type of network device, and in some cases may be distinct and different network devices.

[0308] It should be further understood that in the embodiments of this application, the sequence numbers of the processes described above do not mean the execution sequence. The execution sequence of a process should be determined based on the function and internal logic of the process and should not be construed as a limitation to the implementation processes of the embodiments of the present invention.

[0309] In this application, the term "at least one" means one or more, and the term "multiple" means two or more. For example, "multiple second packets" means two or more second packets. The terms "system" and "network" are often used interchangeably in this specification.

[0310] The terms used in the descriptions of the various examples herein are intended to illustrate specific examples and not to impose limitations. As used in the descriptions of the various examples and in the appended claims, the singular forms "one ("a" or "an")" and "the" are also intended to include the plural form unless otherwise explicitly indicated in the context.

[0311] It should be further understood that the term “include” (also known as “includes,” “including,” “comprises,” and / or “comprising” as used herein) identifies the presence of a described feature, integer, procedure, operation, element, and / or component, and does not exclude the presence or addition of one or more other features, integers, procedures, operations, elements, components, and / or such components.

[0312] It should be further understood that the term "if" can be interpreted as meaning "when" or "upon," "depending on the decision," or "depending on the detection." Similarly, depending on the context, "if it is determined that" or "if (the stated condition or event) is detected" can be interpreted as meaning "if it is determined," or "depending on the decision," or "if (the stated condition or event) is detected," or "depending on the detection of (the stated condition or event)."

[0313] It should be understood that determining B based on A does not mean that B is determined solely on A; rather, B may be determined based on A and / or other information.

[0314] It should be further understood that the terms “one embodiment,” “one embodiment,” and “possible implementation” as used throughout this specification mean that certain features, configurations, or characteristics relating to an embodiment or implementation are included in at least one embodiment of this application. Therefore, “in one embodiment,” “in one embodiment,” and “in a possible implementation” as used throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, configurations, or characteristics may be combined into one or more embodiments by using any suitable method.

Claims

1. An encoding method, 2 n A step of obtaining a group of code stream blocks, wherein any group of code stream blocks includes control blocks and data blocks, and n is an integer greater than 1. The above 2 n A step of performing a first encoding on a group of code stream blocks to obtain a target code block, wherein the target code block is the 2 n The type determined based on the control block within the group of code stream blocks, and the 2 n A step including a data unit determined based on the control block and data block within a group of code stream blocks Equipped with, The type indicates that the target code block is a control code block, the data unit includes a type indication and code block content, and the code block content is the 2 n In a sequence determined based on the control block and the data block within a group of code stream blocks, the 2 n Obtained by performing the first encoding on the data blocks within the group of coded stream blocks, The type indication is the 2 n The type indication is obtained based on the control block within the group of code stream blocks, and the type indication consists of a set of bits located at the beginning of the data unit to indicate the type of each group of code stream blocks, with each bit in the set of bits having a value corresponding to either the type of the control block or the data block that constitutes the data unit. method.

2. The method according to claim 1, wherein the target code block is an error code block, and the error code block includes error instruction data.

3. Based on the error detection result, the target code block is determined as follows: n Obtained by processing a group of code stream blocks, The error detection result is obtained based on the two n control blocks and the data blocks in the plurality of code stream block groups, The method according to claim 1 or 2.

4. The error detection result is as follows: n Content sequence errors in a group of coded stream blocks, or containing content errors, The aforementioned target code block is the 2 n Obtained by performing the first encoding based on the code stream blocks having the correct content sequence and correct content, and the error blocks, in a group of code stream blocks. The error block is the 2 n Based on a group of code stream blocks, the following is obtained: The method according to claim 3.

5. The method according to claim 1 or 2, wherein the control block consists of m bits and the data block consists of 8m bits, where m is a positive integer.

6. The method according to claim 5, wherein the value of n is 2, the value of m is 8, and the target code block is 257 bits.

7. The above 2 n The method according to claim 1 or 2, wherein all of the individual code stream block groups are from a media-independent interface MII.

8. After obtaining the aforementioned target code block, A step of obtaining first data by performing a second encoding on the target code block based on a forward error correction (FEC) code type, The step of transmitting the first data mentioned above and The method according to claim 1 or 2, further comprising:

9. An encoding device, 2 n An acquisition module configured to acquire a set of code stream blocks, wherein any set of code stream blocks includes control blocks and data blocks, and n is an integer greater than 1, and the acquisition module The above 2 n A first coding module configured to perform a first coding on a group of code stream blocks to obtain a target code block, wherein the target code block is the 2 n The type determined based on the control block within the group of code stream blocks, and the 2 n A first coding module including a data unit determined based on the control block and data block within a group of code stream blocks, and Equipped with, The type indicates that the target code block is a control code block, the data unit includes a type indication and code block content, and the code block content is the 2 n In a sequence determined based on the control block and the data block within a group of code stream blocks, the 2 n Obtained by performing the first encoding on the data blocks within the group of coded stream blocks, The type indication is the 2 n The type indication is obtained based on the control block within the group of code stream blocks, and the type indication consists of a set of bits located at the beginning of the data unit to indicate the type of each group of code stream blocks, with each bit in the set of bits having a value corresponding to either the type of the control block or the data block that constitutes the data unit. Device.

10. The apparatus according to claim 9, wherein the target code block is an error code block, and the error code block includes error instruction data.

11. Based on the error detection result, the target code block is determined as follows: n Obtained by processing a group of code stream blocks, The error detection result is as follows: n Based on the control block and the data block within the group of code stream blocks, The apparatus according to claim 9 or 10.

12. The error detection result is as follows: n Content sequence errors in a group of coded stream blocks, or containing content errors, The aforementioned target code block is the 2 n Obtained by performing the first encoding based on the code stream blocks having the correct content sequence and correct content, and the error blocks, in a group of code stream blocks. The error block is the 2 n Based on a group of code stream blocks, the following is obtained: The apparatus according to claim 11.

13. The apparatus according to claim 9 or 10, wherein the control block includes m bits and the data block includes 8 m bits, where m is a positive integer.

14. The apparatus according to claim 13, wherein the value of n is 2, the value of m is 8, and the target code block is 257 bits.

15. The above 2 n The apparatus according to claim 9 or 10, wherein all of the individual code stream block groups are from a media-independent interface MII.

16. A second coding module is configured to perform a second coding on the target code block based on a forward error correction (FEC) code type to obtain the first data, A transmitting module configured to transmit the first data and The apparatus according to claim 9 or 10, further comprising:

Images