Light-emitting device

Abstract

To provide a light emitting device capable of suppressing a variation in brightness between pixels due to a variation in the threshold voltage of a transistor.SOLUTION: There is provided a light emitting device including a transistor having a first gate and a second gate that overlap each other via a semiconductor film, a first capacitive element that holds a potential difference between one of the source and drain of the transistor and the first gate, a second capacitive element that holds a potential difference between one of the source and drain of the transistor and the second gate, a switch that controls the conduction state between the second gate of the above transistor and the wires, and a light emitting element to which the drain current of the above transistor is supplied.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a product, a method, or a method of manufacturing; or to a process, a machine , relating to manufacture or composition of matter. In particular One aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a storage device, an information processing device, and The present invention relates to a method for driving these, or a method for manufacturing them. In particular, one aspect of the present invention relates to a semiconductor device Devices, display devices, light-emitting devices, energy storage devices, memory devices, methods for driving them, or manufacturing thereof. Regarding the manufacturing method. [Background technology]

[0002] The active-matrix display device using light-emitting elements has a specific proposed configuration. Although it varies by manufacturer, typically, at least the light-emitting element and the input of the video signal to the pixel are required. The controlling transistor (switching transistor) and the current value supplied to the light-emitting element. A transistor (driving transistor) that controls the movement is provided at each pixel.

[0003] Furthermore, by making all the transistors provided in the pixels have the same polarity, the transistors In the manufacturing process, some steps, such as adding impurity elements to impart conductivity to the semiconductor film, are performed. It can be omitted. Patent Document 1 below describes how pixels can be made using only n-channel transistors. This document describes the light-emitting element type display that is configured within it. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2003-195810 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] By the way, in a light-emitting device, the drain current of the driving transistor is supplied to the light-emitting element. Therefore, if there is variation in the threshold voltage of the driving transistor between pixels, the brightness of the light-emitting element will decrease. This variation is reflected in every step. Therefore, the drive voltage should take into account the variation in threshold voltage. A proposed pixel configuration that can correct the transistor current value improves the image quality of light-emitting devices. This is an important issue in measuring the situation.

[0006] Given the technical background described above, the variation in the threshold voltage of the driving transistors affects the pixels. One of the challenges is to provide a light-emitting device that can suppress variations in brightness between elements.

[0007] Furthermore, one aspect of the present invention aims to provide a novel semiconductor device and the like. The description of these problems does not preclude the existence of other problems. Furthermore, one aspect of the present invention is: It is not necessarily required to solve all of these issues. Other issues are detailed below. This will become clear from the description in the document, drawings, and claims, etc. It is possible to extract other issues from the descriptions in the sections and other documents. [Means for solving the problem]

[0008] A light-emitting device according to one aspect of the present invention comprises a first gate and superimposed on each other via a semiconductor film. A transistor having a second gate, and one of the source and drain of the above transistor a first capacitive element that maintains the potential difference between itself and the first gate, and the transistor's socket A second capacitive element that maintains the potential difference between one of the drain and the second gate. And a switch that controls the conductivity between the second gate of the above transistor and the wiring, The system comprises a light-emitting element to which the drain current of the above-mentioned transistor is supplied. [Effects of the Invention]

[0009] According to one aspect of the present invention, variations in brightness between pixels due to variations in the threshold voltage of transistors We can provide a light-emitting device that can suppress noise.

[0010] Furthermore, according to one aspect of the present invention, a novel semiconductor device and the like can be provided. The description of these effects does not preclude the existence of other effects. Furthermore, one aspect of the present invention is: It is not necessarily required to have all of these effects. Other effects are described in the specification. This will become clear from the description in the drawings, claims, etc., and the specification, drawings, claims From descriptions such as these, it is possible to extract other effects. [Brief explanation of the drawing]

[0011] [Figure 1] A diagram showing the structure of pixels. [Figure 2] A diagram showing the structure of pixels. [Figure 3] A diagram showing the structure of pixels. [Figure 4] A diagram showing the structure of pixels. [Figure 5] A timing chart showing the operation of pixels. [Figure 6] A diagram illustrating the operation of pixels. [Figure 7] A diagram illustrating the operation of pixels. [Figure 8] A timing chart showing the operation of pixels. [Figure 9] A diagram showing the relationship between Vbg and Vth. [Figure 10]A diagram showing the configuration of the pixel area. [Figure 11] A diagram showing the configuration of the pixel section and the selection circuit. [Figure 12] Circuit diagram of the monitor circuit. [Figure 13] A diagram showing the structure of pixels. [Figure 14] A diagram showing the structure of pixels. [Figure 15] A diagram showing the structure of pixels. [Figure 16] A timing chart showing the operation of pixels. [Figure 17] A diagram showing the structure of pixels. [Figure 18] A diagram showing the structure of pixels. [Figure 19] A cross-sectional diagram illustrating the method for manufacturing a light-emitting device. [Figure 20] A cross-sectional diagram illustrating the method for manufacturing a light-emitting device. [Figure 21] A cross-sectional diagram illustrating the method for manufacturing a light-emitting device. [Figure 22] Cross-sectional view of the light-emitting device. [Figure 23] A perspective view of the panel. [Figure 24] A diagram of an electronic device. [Figure 25] A diagram showing the external appearance of a circuit board. [Figure 26] A diagram showing the configuration of an information processing device using a light-emitting device. [Figure 27] A top view showing the structure of a transistor. [Figure 28] A cross-sectional view showing the structure of a transistor. [Figure 29] A top view showing the structure of a transistor. [Figure 30] A cross-sectional view showing the structure of a transistor. [Figure 31] A top view showing the structure of a transistor. [Figure 32] A cross-sectional view showing the structure of a transistor. [Figure 33] A diagram showing the structure of pixels. [Figure 34] A cross-sectional view showing the structure of a transistor. [Figure 35] A diagram showing the structure of pixels. [Figure 36] A diagram showing the structure of pixels. [Figure 37] A diagram showing the structure of pixels. [Figure 38] A diagram showing the structure of pixels. [Figure 39] A diagram showing the structure of pixels. [Figure 40] A diagram showing the configuration of the pixel area. [Figure 41] A diagram showing the configuration of the pixel area. [Figure 42] A diagram showing the characteristics of a transistor. [Figure 43] A diagram illustrating the structure and operation of pixels. [Figure 44] A diagram showing the configuration of a display device. [Figure 45] A diagram showing a photograph of the display on a display device. [Figure 46] A diagram showing the characteristics of a transistor. [Modes for carrying out the invention]

[0012] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the present invention may have forms and characteristics that do not depart from the spirit and scope of the invention. Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents of the embodiments described below.

[0013] In this specification, the light-emitting device refers to a panel in which light-emitting elements are formed on each pixel, and a drive circuit A module in which an IC including a circuit or controller is mounted on the panel, It is included in that category. Furthermore, a light-emitting device according to one aspect of the present invention is a process for manufacturing the light-emitting device. This category includes a device substrate that corresponds to one form of the light-emitting element before it is completed, and The element substrate consists of a transistor and a pixel electrode to which voltage is supplied via the transistor, Each pixel of the number is equipped with it.

[0014] Furthermore, the source of a transistor is the source region, which is a part of the semiconductor film that functions as the active layer. This refers to a region, or a source electrode electrically connected to the above semiconductor film. Similarly, transient The drain of the sta refers to the drain region which is part of the semiconductor film, or the area where electricity flows through the semiconductor film. This refers to the drain electrode, which is connected via gas. The gate, on the other hand, refers to the gate electrode.

[0015] The source and drain of a transistor are provided to the transistor's conductivity type and each terminal. The name changes depending on the potential level. Generally, n-channel transistors In this case, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the slave. It is called a p-channel transistor. Also, in a p-channel transistor, the terminal to which a low potential is applied is called a dove. The terminal to which a high potential is applied is called the source. For convenience, in this specification, Assuming the source and drain are fixed, the connection relationships of the transistor will be explained. In some cases, the terms "source" and "drain" are reversed according to the potential relationship described above. ru.

[0016] Furthermore, if it is explicitly stated in this specification, etc., that X and Y are connected. This refers to the case where X and Y are electrically connected, and the case where X and Y are functionally connected. The cases in which X and Y are directly connected are disclosed in this specification, etc. Therefore, the connection relationships are not limited to predetermined relationships, such as those shown in the diagram or text. Connections other than those shown in the diagram or text are also included as those described in the diagram or text. ru.

[0017] Here, X and Y are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer). (etc.)

[0018] One example of a case where X and Y are directly connected is when an electrical connection between X and Y is possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. If the diode, display element, light-emitting element, load, etc. are not connected between X and Y and elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitors). Without the need for elements such as components, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. This is the case when X and Y are connected.

[0019] One example of a case where X and Y are electrically connected is the ability to make an electrical connection between X and Y possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. One or more devices (such as diodes, display elements, light-emitting elements, and loads) are connected between X and Y. Yes, it is possible. Furthermore, a switch has the function of being controlled to be on or off. In other words, a switch The switch can be in a conductive (on) or non-conductive (off) state, allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which current flows. It has a function to switch between them. Furthermore, if X and Y are electrically connected, X and This includes cases where Y is directly connected to it.

[0020] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (electric (Source circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.) Voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected. When X and Y are functionally connected, the situation is different from when X and Y are directly connected. This includes cases where and are electrically connected.

[0021] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y and When they are electrically connected (i.e., when there is another element or circuit between X and Y) (when connected) and when X and Y are functionally connected (i.e., X and Y are connected) (When functionally connected with another circuit in between) and when X and Y are directly connected In the case of (that is, when X and Y are connected without another element or circuit in between) and However, this shall be as disclosed in this specification, etc. That is, explicitly stated that they are electrically connected. If it is explicitly stated that it is connected, then Similar information is disclosed in this specification, etc.

[0022] <Example of pixel configuration> Figure 1 shows an example of the configuration of a pixel 10 in a light-emitting device according to one aspect of the present invention. The pixel 10 consists of a transistor 11, a switch 16, a capacitive element 13, and a capacitive element 18. It has a light-emitting element 14.

[0023] The light-emitting element 14 is an LED (Light Emitting Diode) or an OLED (O2 Current or voltage, such as in an electromagnetic light-emitting diode. Therefore, elements whose brightness is controlled are included in that category. For example, an OLED has an EL layer and It has at least an anode and a cathode. The EL layer is a single layer placed between the anode and the cathode. It is composed of multiple layers, and among these layers, there is a light-emitting layer containing a light-emitting substance. It also includes the EL layer, where the potential difference between the cathode and anode is less than or equal to the threshold voltage Vthe of the light-emitting element 14. When it is in the upper position, the current supplied produces electroluminescence. Trollinescence involves the emission (fluorescence) that occurs when returning from a singlet excited state to the ground state, and the triplet emission. This includes the emission (phosphorescence) that occurs when returning from an excited state to the ground state.

[0024] Furthermore, the anode and cathode of the light-emitting element 14 function as either one of the pixel electrodes, and the other The latter functions as a common electrode. In Figure 1, the anode of the light-emitting element 14 is used as a pixel electrode, and This diagram illustrates a configuration of a pixel 10 in which the cathode of the optical element 14 is used as a common electrode.

[0025] In addition to the normal gate (first gate), transistor 11 has a semiconductor film in between. It has a second gate that overlaps with the first gate. In Figure 1, the first gate is referred to as G1. The diagram illustrates the second gate, denoted as G2.

[0026] Furthermore, the potential of the first gate of transistor 11 is determined according to the image signal supplied from wiring SL. It is controlled in this way. Switch 16 is connected to the second gate of transistor 11, wiring B It has the function of controlling the supply of potential to L.

[0027] The switch 16 can be configured using one or more transistors. Yes, it is possible. Alternatively, switch 16 can have one or more transistors, plus a capacitive element. It's okay to use it.

[0028] Capacitive element 13 is connected to the second gate of transistor 11 and the source and drain of transistor 11. It has the function of maintaining the potential difference between one side of the rain. Capacitive element 18 is a transistor The potential difference between the first gate of transistor 11 and either the source or drain of transistor 11 is It has the function of holding.

[0029] Figure 1 illustrates the case where transistor 11 is an n-channel type, but in this case, The source and drain of the transistor 11 are electrically connected to the anode of the light-emitting element 14. It is done. And the source and drain of transistor 11 are connected to the wiring VL. They are connected, and the cathode of the light-emitting element 14 is electrically connected to the wiring CL. Furthermore, the potential of wiring VL is determined by the potential of wiring CL and the threshold voltage Vthe of the light-emitting element 14, and the transistor The threshold voltage Vth of the zista 11 is set to be higher than the sum of the two potentials. Therefore, the image signal When the value of the drain current of transistor 11 is determined according to the number, the drain current of the light-emitting element When supplied to the child 14, the light-emitting element 14 enters a state of emitting light.

[0030] If transistor 11 is a p-channel type, then as shown in Figure 35, transistor 11 One of the source and drain of the device is electrically connected to the cathode of the light-emitting element 14. The source and drain of transistor 11 are electrically connected to the wiring VL. Furthermore, the anode of the light-emitting element 14 is electrically connected to the wiring CL. The potential is the potential of the wiring VL, the threshold voltage Vthe of the light-emitting element 14, and the threshold voltage of the transistor 11. The potential is set to be higher than the sum of the voltages Vth and n. Similar to the case of a channel type, when transistor 11 is a p-channel type, the image signal When the value of the drain current of transistor 11 is determined accordingly, the drain current is the light-emitting element. When supplied to 14, the light-emitting element 14 enters a state of emitting light.

[0031] Furthermore, in one aspect of the present invention, the value of the drain current of transistor 11 is changed according to the image signal. Before setting, the current between the source and drain of transistor 11 and the second gate is determined. By controlling the voltage Vbg, the threshold voltage Vth of transistor 11 is corrected, and between pixels 10 This prevents variations in the threshold voltage Vth of transistor 11.

[0032] Specifically, the potential of the wiring BL is transmitted to the second gate of transistor 11 via switch 16. By supplying power, transistor 11 is made into a normally-on state. For example, transistor 11 In the case of an n-channel type, increasing the voltage Vbg shifts the threshold voltage Vth in the negative direction. As a result, transistor 11 becomes normally on. Also, if transistor 11 is p-channel type In this case, lowering the voltage Vbg shifts the threshold voltage Vth in the positive direction, and the transient Sta11 will be Normalion.

[0033] Figure 9 shows the voltage Vbg and threshold voltage Vth when transistor 11 is an n-channel type. Let's show the relationship. When the voltage Vbg is 0, let Vth0 be the threshold voltage Vth of transistor 11. Then, by shifting the voltage Vbg from 0 to the positive direction and setting it to Vbg1, the threshold voltage Vth shifts from Vth0 in the negative direction to Vth1 (Vth1<0).

[0034] Then, with transistor 11 in the normally-marion state, the first gate of transistor 11 and The gate voltage Vgs, which is the potential difference between the source and drain, is kept at a constant value. The drain current of transistor 11 is connected to the second gate and capacitive element 1 of transistor 11. The structure will flow to step 3.

[0035] With the above configuration, the second gate of transistor 11 and the electric charge stored in capacitive element 13 The load shifts, and the potential of either the source or drain of transistor 11 shifts. As the potential of either the source or drain of transistor 11 shifts, the voltage Vb As g changes, the threshold voltage of transistor 11 shifts in the direction of normally-off. For example, if transistor 11 is an n-channel type, the voltage Vbg will be in the negative direction. Because of the shift, the threshold voltage Vth shifts in the positive direction. Also, transistor 11 In the case of a p-channel type, the voltage Vbg shifts in the positive direction, so the threshold voltage Vth is It shifts in the negative direction.

[0036] And finally, the threshold voltage Vth of transistor 11 is kept at a constant value, and the gate voltage As the voltage Vgs approaches zero, the drain current converges to zero, and transistor 11 turns off. Let Vth2 be the threshold voltage Vth of transistor 11 at this time. As shown in Figure 9. When the voltage Vbg becomes Vbg2, the gate voltage Vgs of the transistor is kept at a constant value. The drain current of 11 converges to 0. As a result, the threshold voltage Vth is corrected to Vth2. The above potential difference ΔV0 is held in the capacitive element 13.

[0037] In one aspect of the present invention, the threshold of the transistor 11 generated between pixels 10 is determined by the above configuration. To prevent variations in voltage values ​​from affecting the drain current value of transistor 11. This allows for the suppression of variations in brightness between pixels.

[0038] Note that in Figure 1, the distance between the source and drain of transistor 11 and the second gate is shown. By controlling the voltage Vbg, the threshold voltage Vth of transistor 11 can be corrected. The configuration of the pixel 10 has been shown, but one of the source and drain of the transistor 11 is By controlling the voltage Vgs between the transistor 11 and the first gate, the threshold voltage Vt of the transistor 11 is controlled. It would be good to allow for correction of h.

[0039] Figure 33 shows that the threshold voltage Vth of transistor 11 can be corrected by controlling the voltage Vgs. The configuration of pixel 10 is shown as an example. In the pixel 10 shown in Figure 33, the transistor 11 The potential of the second gate is controlled according to the image signal supplied from wiring SL. 16 controls the supply of potential from the wiring BL to the first gate of transistor 11. It has a function. The capacitive element 13 is connected to the first gate of transistor 11 and transistor 11 The capacitive element 18 has the function of maintaining the potential difference between the source and drain of the capacitor. , the second gate of transistor 11 and one of the source and drain of transistor 11 It has the function of maintaining the potential difference between them. In one aspect of the present invention, the above configuration provides the image signal Before determining the value of the drain current of transistor 11 according to the instructions, the saw of transistor 11 By controlling the voltage Vgs between one of the drains and the first gate, the transient The threshold voltage Vth of transistor 11 is corrected, and the threshold voltage Vth of transistor 11 is corrected between pixels 10. This can prevent variations from occurring.

[0040] <Example 1 of a specific pixel configuration> Figure 2(A) shows an example of the specific configuration of pixel 10 shown in Figure 1.

[0041] The pixel 10 shown in Figure 2(A) consists of a transistor 11, a switch 12, a capacitive element 13, and an oscillator. In addition to the optical element 14, it also has switches 15 to 17 and a capacitive element 18.

[0042] Specifically, in pixel 10 shown in Figure 2(A), the wiring SL transitions via switch 15. It is electrically connected to the first gate of sta 11. Also, wiring SL is connected to switch 15 and The light-emitting element 14 is electrically connected to the pixel electrodes via the switch 12. The transistor 11 has one of its sources and drains electrically connected to the pixel electrode of the light-emitting element 14. The source and drain are connected, and the other is electrically connected to the wiring VL. The second gate of the inverter 11 is electrically connected to the wiring BL via the switch 16. The pixel electrodes of the light-emitting element 14 are electrically connected to the wiring IL via the switch 17. The pair of electrodes of the capacitive element 13 are connected to the second gate of the transistor 11. One end is electrically connected to the other, and the other end is electrically connected to the pixel electrode of the light-emitting element 14. One of the pair of electrodes of the capacitive element 18 is electrically connected to the first gate of the transistor 11. One end is connected to the other, and the other end is electrically connected to the pixel electrode of the light-emitting element 14. The common electrode of 4 is electrically connected to wiring CL.

[0043] Next, Figure 2(B) shows another specific configuration of pixel 10 as shown in Figure 1.

[0044] The pixel 10 shown in Figure 2(B) further has a switch 19, as shown in Figure 2(A). The pixel configuration is different from that of pixel 10.

[0045] Specifically, in pixel 10 shown in Figure 2(B), the wiring SL transitions via switch 15. It is electrically connected to the first gate of sta 11. Also, wiring SL is connected to switch 15. The light-emitting element 14 is electrically connected to the pixel electrodes via switches 12 and 19. The transistor 11 has either its source or drain connected via switch 19. The source and drain are electrically connected to the pixel electrodes of the light-emitting element 14, and the other is the source. It is electrically connected to line VL. The second gate of transistor 11 is connected to switch 16. It is electrically connected to the wiring BL via a switch. The pixel electrodes of the light-emitting element 14 are switches 17 and switch 19 are electrically connected to the wiring IL. Capacitive element 13 has The pair of electrodes are electrically connected to the second gate of transistor 11, with one electrode being the other. The element is electrically connected to the pixel electrode of the light-emitting element 14 via switch 19. The pair of electrodes that 18 has are electrically connected to the first gate of transistor 11. The other end is electrically connected to the pixel electrode of the light-emitting element 14 via switch 19. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

[0046] Next, in the pixel 10 shown in Figure 2(A), when a transistor is used for each switch, Next, we will explain an example of pixel configuration. The pixel 10 shown in Figure 2(A) has a switch 12 and a switch Configuration of the pixel 10 when transistors are used as switches 15 to 17. An example is shown in Figure 3(A).

[0047] The pixel 10 shown in Figure 3(A) has the functions of a transistor 11 and a switch 12. A transistor 12t and a switch 15 to switch 17, respectively. A transistor 15t through a transistor 17t, a capacitive element 13, a capacitive element 18, and a light-emitting element. It has 14 children.

[0048] Specifically, transistor 15t has its gate connected to wiring GLa, and one of its source and drain is The source and drain of the wiring SL are connected to the first gate of transistor 11, respectively. Electrically connected. Transistor 12t has its gate wired to GLB, source and root. One end of the rain is connected to the pixel electrode of the light-emitting element 14, and the other end of the source and drain is connected to transistor 1 Each is electrically connected to the first gate of 1. Transistor 11 has a source and One of the drains is connected to the pixel electrode of the light-emitting element 14, and the other of the source and drain is connected to the wiring VL. They are electrically connected to each other. Transistor 16t has its gate connected to wiring GLB, One of the source and drain wires is connected to wiring BL, and the other source and drain wire is connected to transistor 11. Each is electrically connected to the second gate. Transistor 17t has a gate that The source and drain of the wire GLd are connected to the wiring IL, and the other source and drain are connected to the light-emitting element. Each of these is electrically connected to the pixel electrodes of element 14.

[0049] Furthermore, one of the pair of electrodes of the capacitive element 13 is connected to the second gate of the transistor 11. One end is electrically connected to the other, and the other end is electrically connected to the pixel electrode of the light-emitting element 14. One of the pair of electrodes of element 18 is electrically connected to the first gate of transistor 11. The other end is electrically connected to the pixel electrode of the light-emitting element 14. The common electrode is electrically connected to the wiring CL.

[0050] Next, in the pixel 10 shown in Figure 2(B), when a transistor is used for each switch, Next, we will explain an example of pixel configuration. The pixel 10 shown in Figure 2(B) has a switch 12 and a switch When transistors are used as switches 15 through 17 and switch 19, An example of the configuration of pixel 10 is shown in Figure 3(B).

[0051] The pixel 10 shown in Figure 3(B) has the function of a transistor 11 and a switch 12. A transistor 12t and a switch 15 to switch 17, respectively. A transistor 15t or transistor 17t and a transistor that functions as a switch 19 It comprises a zista 19t, a capacitive element 13, a capacitive element 18, and a light-emitting element 14.

[0052] Specifically, transistor 15t has its gate connected to wiring GLa, and one of its source and drain is The source and drain of the wiring SL are connected to the first gate of transistor 11, respectively. Electrically connected. Transistor 12t has its gate wired to GLB, source and root. One side of the rain is connected to one side of the source and drain of transistor 19t, source and drain The other end is electrically connected to the first gate of transistor 11. Zistor 11 has one of its sources and drains connected to the source and drain of transistor 19t. On one side, the source and the other drain are electrically connected to the wiring VL, respectively. The 16t transistor has its gate connected to wiring GLB, and one of its sources or drains connected to wiring BL. The source and the other drain are electrically connected to the second gate of transistor 11, respectively. Transistor 17t has its gate connected to the wiring GLd, and one of its sources and drains. The wiring IL has the source and drain on the other side, and the source and drain of transistor 19t They are electrically connected to each other. Transistor 19t has a gate wired to GLc The source and the other drain are electrically connected to the pixel electrodes of the light-emitting element 14, respectively. It is.

[0053] Furthermore, one of the pair of electrodes of the capacitive element 13 is connected to the second gate of the transistor 11. They are electrically connected, with the other side electrically connected to one of the source and drain of transistor 19t. It is connected to the first electrode of the transistor 11. It is electrically connected to the gate of the transistor, and the other side is the source and drain of transistor 19t. It is electrically connected to one side. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL. It is being done.

[0054] Next, switch 12 and switches 15 to 17 of pixel 10 shown in Figure 2(B) Figure 4(A) shows another example of the pixel 10 configuration when transistors are used for each component. .

[0055] Pixel 10 shown in Figure 4(A) is where one of the source and drain of transistor 16t is connected to the wiring. Pixel 1 shown in Figure 3(B) is electrically connected to wiring VL, rather than BL. Its configuration is different from that of 0.

[0056] Next, switch 12 and switches 15 to 17 of pixel 10 shown in Figure 2(B) And, another example of pixel 10 configuration when transistors are used as switches 19. This is shown in Figure 4(B).

[0057] In Figure 4(B), pixel 10 has a gate of transistor 17t that is not connected to wiring GLd, but rather to wiring In that it is electrically connected to the line GLa, its configuration differs from that of pixel 10 shown in Figure 3(B). ru.

[0058] <Example of specific pixel operation 1> Next, taking the pixel 10 shown in Figure 3(B) as an example, the image of the light-emitting device according to one embodiment of the present invention Let's explain the basic operation.

[0059] Figure 5 shows the timing chart of the potential input to wiring GLa to wiring GLd, and wiring SL The timing chart of the potential of the image signal Vdata input to the system is shown. Note that Figure 5 shows The timing chart shown is for all transistors in pixel 10 shown in Figure 3(B) that are n This illustrates the case of a channel type. Figures 6 and 7 also show the plots for each period. The operation of element 10 is schematically shown. However, in Figures 6 and 7, the operation of pixel 10 is simplified for clarity. To illustrate this, transistors other than transistor 11 are shown as switches.

[0060] First, during period t1, a low potential is applied to wiring GLa, and a high potential is applied to wiring GLB. A potential is applied to the wire GLc, a low-level potential is applied to the wire GLd, and a high-level potential is applied to the wire GLd. A potential is applied. Therefore, as shown in Figure 6(A), transistor 12t, Transistor 16t and transistor 17t are turned on, and transistor 15t and transistor 17t are turned on. The Zista 19t will be turned off.

[0061] Additionally, wiring VL has a potential Vano, wiring BL has a potential V0, and wiring IL has a potential V1. The wiring CL electrically connected to the common electrode of the light-emitting element 14 has a potential Vcat, respectively. Given. Therefore, the first gate of transistor 11 (indicated as node A) has a potential Given a voltage V1, a potential V0 is applied to the second gate of transistor 11 (indicated as node B). As a result, a potential V1 is obtained at one of the source and drain of transistor 11 (indicated as node C). It is given.

[0062] The potential Vano is determined by the threshold voltage Vthe of the light-emitting element 14 and the potential Vcat, and the transistor 11 It is desirable to make the potential higher than the sum of the threshold voltage Vth and the potential V0. This shifts the threshold voltage Vth of transistor 11 in the negative direction to the extent that node C It is desirable that the potential is sufficiently high relative to the voltage Vb. Specifically, as shown in Figure 9, Let Vth be the threshold voltage Vth of transistor 11 when g is 0, and node B Let Vbg1 be the voltage Vbg corresponding to the potential difference across node C. Then, in period t1, The threshold voltage Vth of transistor 11 becomes Vth1. With the above configuration, Since 11 is normally on, the potential difference between node A and node C, i.e., the transistor Even if the gate voltage of transistor 11 is 0, transistor 11 can still be turned on.

[0063] Furthermore, if transistor 11 is a p-channel type, the potential V0 is the threshold of transistor 11. The potential is low enough relative to node C to shift the value voltage Vth in the positive direction. This is desirable. With the above configuration, transistor 11 becomes normally on, so the node Even if the potential difference between A and node C, i.e., the gate voltage of transistor 11, is 0, You can turn on the 'njista 11'.

[0064] Next, during period t2, a low potential is applied to wiring GLa, and a high potential is applied to wiring GLB. A potential of the bell is applied, a low level potential is applied to wiring GLc, and a low level potential is applied to wiring GLd. The potential of the bell is applied. Therefore, as shown in Figure 6(B), transistor 12t and Transistor 16t turns on, and transistors 15t, 17t, and 16t turn on. The Zista 19t will be turned off.

[0065] Furthermore, the potential Vano is assigned to wiring VL, and the potential V0 is assigned to wiring BL. Therefore, the state in which potential V0 is applied to node B is maintained, and at the start of period t2 The threshold voltage Vth of transistor 11 remains shifted in the negative direction relative to Vth1. Transistor 11 is ON. And during period t2, the power between wiring VL and wiring IL The current path is interrupted by switch 17, so the drain current of transistor 11 The potentials of nodes A and C begin to rise. When the potential of node C rises, node B The voltage Vbg, which corresponds to the potential difference across node C, becomes lower, and the threshold voltage Vt of transistor 11 decreases. h shifts in the positive direction. And finally, the threshold voltage Vt of transistor 11 As h approaches 0, transistor 11 turns off. Threshold voltage of transistor 11 When Vth is 0, the potential difference between node B and node C is V0 - V2.

[0066] That is, when the potential difference between node B and node C is V0-V2, transistor 11 operates. The threshold voltage Vth becomes 0 such that the drain current converges to 0 when the gate voltage is 0. The potential difference V0-V2 between node B and node C is applied to the capacitive element 13. It will be done.

[0067] Next, during period t3, a high potential is applied to wiring GLa, and a low potential is applied to wiring GLB. A potential is applied to the bell, a low potential is applied to wiring GLc, and a high potential is applied to wiring GLd. The potential of the bell is applied. Therefore, as shown in Figure 7(A), transistor 15t and Transistor 17t turns on, and transistors 12t, 16t, and 17t turn on. The Zista 19t will be turned off.

[0068] Additionally, wiring VL contains the potential Vano, and wiring SL contains the potential Vdata, which includes image information. However, each wire IL is given a potential V1. And node B is floating Since it is in a state of [unclear], when node C changes from potential V2 to potential V1, the capacitive element 13 As a result, node B changes from potential V0 to potential V0+V1-V2. Then, the capacitive element 13 Since a potential difference V0-V2 is maintained, the threshold voltage Vth of transistor 11 becomes 0. It is maintained. Also, a potential Vdata is applied to node A, and the gate of transistor 11 The voltage will be Vdata - V1.

[0069] Next, during period t4, a low potential is applied to wiring GLa, and a low potential is applied to wiring GLB. A potential is applied to the bell, a high-level potential is applied to the wiring GLc, and a low-level potential is applied to the wiring GLd. The potential of the bell is applied. Therefore, as shown in Figure 7(B), transistor 19t turns on. As a result, transistor 12t, transistor 15t, transistor 16t, and transistor The 17t will be taken off.

[0070] Furthermore, the wiring VL has a potential Vano, and the wiring is electrically connected to the common electrode of the light-emitting element 14. A potential Vcat is given to CL. During period t4, transistor 19t When it is turned on, the potential of node C changes, and when the potential reaches V3, node A reaches potential Vd Node A is at a potential of V0-V2+V3, and node B is at a potential of V0-V2+V3. Node A, node B, and Even if the potential of node C changes, the potential difference V0-V2 is maintained in the capacitive element 13. The capacitive element 18 holds a potential difference Vdata-V1. Then, wiring VL and wiring C A drain current corresponding to the gate voltage of transistor 11 flows between L and L. The brightness of element 14 is determined according to the value of the drain current described above.

[0071] In the light-emitting device having the pixel 10 shown in Figure 3(B), the source of the transistor 11 and Since the other side of the drain and the second gate of transistor 11 are electrically isolated, Each potential can be controlled individually. Therefore, transistor 11 normally When it is ON, that is, when the original threshold voltage Vth0 of transistor 11 is a negative value If present, during period t2, the power of one of the source and drain of transistor 11 Charge is accumulated in the capacitive element 13 until the potential becomes higher than the potential V0 of the second gate. Yes, it is possible. Therefore, in a light-emitting device according to one aspect of the present invention, the transistor 11 is normally on. Even if, during period t2, the drain current converges to 0 for a gate voltage of 0. This allows the threshold voltage Vth to be corrected to 0.

[0072] Therefore, the source and drain of transistor 11 and the second of transistor 11 The gate and the pixel 1 shown in Figures 3(A), 3(B), and 4(B) are electrically isolated. In a light-emitting device having 0, for example, if an oxide semiconductor is used for the semiconductor film of transistor 11 Even if transistor 11 becomes normally lit, display unevenness can be reduced, resulting in high image quality. It is possible to display this.

[0073] Although Figures 2(A) and 2(B) show examples of circuit configurations, one aspect of the present invention is However, it is not limited to this. For example, switches can be placed in various locations. For example, in the case of Figure 6(A), the configuration is as shown in Figure 36(A), and in the case of Figure 6(B) It has the configuration shown in Figure 36(B), and in the case of Figure 7(A), it is as shown in Figure 37(A). The configuration is as shown in Figure 7(B), and in the case of Figure 7(B), the configuration is as shown in Figure 37(B). That's all you need to do. In each case, set the switch in the appropriate place so that the configuration is as described above. Just place it wherever you like.

[0074] The above describes the correction of the threshold voltage within pixel 10 (hereinafter referred to as internal correction), including the correction of the threshold voltage within pixel 10. This corresponds to an example of operation 0. Next, in addition to internal correction, pixels caused by variations in threshold voltage. When the variation in brightness between 10 points is suppressed by correcting the image signal (hereinafter referred to as external correction) The operation of pixel 10 will now be explained.

[0075] Taking pixel 10 shown in Figure 3(B) as an example, the wiring when external correction is performed in addition to internal correction. A timing chart of the potential input to GLa or wiring GLD, and the potential input to wiring SL Figure 8 shows the timing chart of the potential of the image signal Vdata. Note that the timing chart shown in Figure 8 is The timing chart shows that all the transistors in pixel 10, as shown in Figure 3(B), are n-channel. This is an example of a case where it is of type 'ru'.

[0076] First, from period t1 to period t4, the timing chart is the same as shown in Figure 5, as described above. Pixel 10 operates according to the instructions.

[0077] Next, during period t5, a low potential is applied to wiring GLa, and a low potential is applied to wiring GLB. A potential is applied to the bell, a low potential is applied to wiring GLc, and a high potential is applied to wiring GLd. The potential of the bell is applied. Therefore, transistor 17t turns on, and transistor 12 Transistors t, 15t, 16t, and 19t are turned off.

[0078] Additionally, wiring VL is assigned the potential Vano, and wiring IL is assigned the potential V1. Furthermore, the wiring IL is electrically connected to the monitor circuit.

[0079] As a result of the above operation, the drain current of transistor 11 is transmitted to transistor 17t and wiring IL. It is supplied to the monitor circuit via this. The monitor circuit detects the drain current flowing through the wiring IL. Using this, a signal is generated that includes the value of the drain current as information. And, according to the present invention, In the light-emitting device according to the embodiment, the potential V of the image signal supplied to the pixel 10 is used with the above signal. The values ​​of the data can be corrected.

[0080] Note that the external correction operation performed in period t5 does not always need to be performed after period t4. For example, in a light-emitting device, after repeating the operation of period t1 to period t4 multiple times, It is also possible to perform the operation during interval t5. Alternatively, the operation during period t5 can be performed in one row of pixels 10. After the operation, the image signal corresponding to the minimum grayscale value of 0 is written to the pixel 10 of the row in which the operation was performed. By embedding, the light-emitting element 14 is put into a non-emitting state, and then in the next row of pixels 10, for a period of time. You can also configure it to perform the actions of t5.

[0081] Furthermore, even when external correction is performed without internal correction, the transistors present between pixels 10 In addition to the variation in the threshold voltage of transistor 11, other factors such as mobility of transistor 11 also affect the threshold voltage. It can also correct variations in electrical characteristics. However, in addition to external correction, internal correction is also required. If this is done, the correction for the negative or positive shift of the threshold voltage is performed by internal correction. Therefore, external correction is used for factors other than the threshold voltage at transistor 11, such as mobility. The variation in electrical characteristics should be corrected. Therefore, in addition to external correction, internal correction should also be performed. In this case, compared to performing only external correction, the amplitude of the potential of the image signal after correction is It can be kept small. Therefore, because the amplitude of the potential of the image signal is too large, the grayscale value The potential difference of the image signal between the points becomes large, resulting in a smooth gradient of brightness changes within the image. This prevents situations where it becomes difficult to express things in terms of image quality, and the image quality does not deteriorate. This can prevent it from happening.

[0082] In addition, in the case of pixel 10 shown in Figure 3(A), the wiring GLa and wiring GL shown in Figure 5 or Figure 8 are also used. b, according to the timing chart of the potentials applied to wiring GLd and wiring SL, similarly It can be operated. However, in the case of pixel 10 shown in Figure 3(A), during period t2 The potential V0 is set so that the drain current of transistor 11 does not flow to the light-emitting element 14. The threshold voltage Vthe of element 14 and the threshold voltage Vth of transistor 15t are set to the potential Vca It is desirable to make the potential lower than the potential obtained by adding t.

[0083] Furthermore, in the case of pixel 10 shown in Figure 4(A), the wiring GLa and wiring GL shown in Figure 5 or Figure 8 are also used. b. According to the timing chart of the potentials applied to wiring GLc, wiring GLd, and wiring SL. And it can be made to work in the same way.

[0084] Furthermore, in the case of pixel 10 shown in Figure 4(B), the wiring GLa and wiring GL shown in Figure 5 or Figure 8 are also used. b, according to the timing chart of the potentials applied to wiring GLc and wiring SL, similarly It can be made to work.

[0085] For example, if no external correction is performed, wiring IL can be connected to wiring CL. Good. Alternatively, wiring IL and wiring CL can be combined into a single wire, thereby omitting wiring IL. This may be done. This can reduce the number of wires. For example, in Figure 2(A) An example of the case where wiring IL is omitted is shown in Figure 38(A). Similarly, the same applies to Figure 2(B). An example of this case is shown in Figure 38(B). This can be similarly applied to other drawings.

[0086] <Example of pixel section and selection circuit configuration> Next, Figure 10 shows an example of the configuration of the pixel section of a light-emitting device according to one aspect of the present invention. In Figure 10, the pixel section 40 has a plurality of pixels 10 arranged in a matrix. Furthermore, the pixel section 40 includes wiring GL, wiring SL, wiring VL, wiring BL, wiring IL, and wiring CL It has at least (not shown). Each of the plurality of pixels 10 has at least one of the wiring GL and , at least one of wiring SL, at least one of wiring VL, and at least one of wiring BL Furthermore, it is electrically connected to at least one of the wirings IL and to wiring CL.

[0087] The type and number of the above-mentioned wirings are determined by the configuration, number, and arrangement of the pixels 10. Yes, it is possible. Specifically, in the case of the pixel section 40 shown in Figure 10, the x-column x y-row pixel 10 is a matrix. They are electrically connected in this manner. And multiple wirings GL1 to GLy are shown as wiring GL And, a plurality of wirings SL, indicated by wiring SL1 to wiring SLx, and wiring VL1 to wiring VLx Multiple wirings VL, multiple wirings BL indicated by wirings BL1 to BLx, and wiring IL1 Multiple wirings IL, indicated by wiring ILx, and one wiring CL are arranged within the pixel section 40. This provides examples of situations where this might occur.

[0088] And each wiring GL shown in Figure 10 is wiring GLa, wiring GLB, wiring GLC, or wiring Each of the following must include all or any of the GLd components.

[0089] Furthermore, as shown in Figure 10, if the pixels 10 are connected in a matrix, in a certain row For example, if the actions shown in Figure 6(A), Figure 6(B), and Figure 7(B) are being performed, In the row, for example, the action shown in Figure 7(A) can be performed. Therefore, Figure 6(A) The operations shown in Figure 6(B) and other figures can be performed over a sufficiently long period of time. Therefore, it can be corrected with high precision.

[0090] Note that the actions shown in Figures 6(A) and 6(B), and the actions shown in Figure 7(A), are performed simultaneously on separate lines. If not done, for example, wiring BL may be connected to wiring SL. Or, for example, By combining wiring BL and wiring SL into a single wire, wiring BL can be omitted. This allows for a reduction in the number of wires. As an example, in Figure 2(A), the wiring BL An example of the case where it is omitted is shown in Figure 39(A). Similarly, an example of the case where it is applied to Figure 2(B) is shown. This is shown in Figure 39(B). The same method can be applied to other drawings.

[0091] Furthermore, in Figure 7(A), etc., during the period when the potential Vdata of the image signal is input, As shown in 6(B), the potential difference V0-V2 between node B and node C is applied to the capacitive element 13. Since this operation is not performed, in Figure 7(A), etc., the potential Vdata of the image signal is sequentially set point by point. This allows input to be made to the pixels. An example of this is shown in Figure 40. Switch 60A, Sw Switch 60B, switch 60C, etc. are turned on sequentially while being controlled by circuit 61. As a result, sequential point-by-point driving can be performed. Here, the circuit 61 shifts one by one. It has the function of being able to output a waveform. For example, circuit 61 is a shift register It has the function of a switch. Therefore, switch 60A, switch 60B, switch 6 0C, the circuit 61 can also be said to have a function as a source line driving circuit.

[0092] Alternatively, as another example, in the plurality of wirings SL represented by wirings SL1 to SLx, in the plurality of wirings among them, any one of the wirings may be selected, and the potential Vdata of an image signal may be input sequentially. For example, the wirings SL1 and SL2 are selected by a switch 62A and a switch 62B, and the wirings SL3 and SL4 are selected by a switch 62C and a switch 62 D. FIG. 41 shows an example of this selection. In FIG. 41, when the wiring 63A is selected , the switches 62A and 62C are turned on, and when the wiring 63B is selected , the switches 62B and 62D and the like are turned on. Here, an example in which one wiring is selected from two wirings SL is shown; however, one embodiment of the present invention is not limited to this example. One wiring may be selected from a larger number of wirings SL.

[0093] Next, FIG. 11 shows an example of a connection configuration between a pixel portion 40 and a selection circuit 41 of a light-emitting device having a function of performing external correction. The selection circuit 41 has a function of selecting either a wiring 42 to which a potential V1 is supplied or a connection terminal TER connected to a monitor circuit. The selection circuit 41 can bring either the selected wiring 42 or the connection terminal TER into conduction with a wiring IL.

[0094] Specifically, the selection circuit 41 shown in FIG. 11 includes a switch 43 that controls supply of the potential V1 of the wiring 42 to one wiring IL, and a switch 44 that controls conduction between the one wiring IL and the connection terminal TER.

[0095] <Configuration Example of Monitor Circuit> Next, an example of the configuration of the monitor circuit 45 is shown in Figure 12. The monitor circuit 45 shown in Figure 12 is It has an operational amplifier 46, a capacitive element 47, and a switch 48.

[0096] One of the pair of electrodes of the capacitive element 47 is connected to the inverting input terminal (-) of the operational amplifier 46. The other electrode of the pair of electrodes of the capacitive element 47 is connected to the output terminal of the operational amplifier 46. The switch 48 has the function of releasing the charge stored in the capacitive element 47. Specifically, the device controls the electrical conductivity between the pair of electrodes of the capacitive element 47. It has the capability. The non-inverting input terminal (+) of the operational amplifier 46 is connected to wiring 49, wiring Potential V1 is supplied to 49.

[0097] In one aspect of the present invention, a potential V1 is supplied to the wiring IL of the pixel 10 in order to perform internal correction. In this case, the monitor circuit 45 is made to function as a voltage follower. Specifically, the switch By turning on the 48, the potential V1 supplied to the wiring 49 is transmitted via the monitor circuit 45. It can then be supplied to the wiring IL.

[0098] Furthermore, when extracting current from pixel 10 via wiring IL in order to perform external correction, Furthermore, by making the monitor circuit 45 function as a voltage follower, the potential V is introduced to the wiring IL. After supplying 1, the monitor circuit 45 is made to function as an integrating circuit, and the signal from the pixel 10 is taken The current is converted into voltage. Specifically, by turning on switch 48, wiring 4 The potential V1 supplied to 9 is then supplied to the wiring IL via the monitor circuit 45, and then the switch Turn off switch 48. With switch 48 off, the DRE extracted from pixel 10 When current is supplied to the wiring TER, charge is accumulated in the capacitive element 47, and the capacitive element 47 A voltage is generated between the pair of electrodes. The above voltage is the drain current supplied to the wiring TER. Since it is proportional to the total amount, the wiring OUT connected to the output terminal of op-amp 46 has a predetermined value. A potential corresponding to the total amount of drain current during the period is given.

[0099] <Example of a specific pixel configuration 2> Figure 13(A) shows an example of the specific configuration of pixel 10 shown in Figure 1.

[0100] The pixel 10 shown in Figure 13(A) consists of a transistor 11, a capacitive element 13, and a light-emitting element 14. In addition, it has switches 15 to 17 and a capacitive element 18.

[0101] Specifically, in pixel 10 shown in Figure 13(A), the wiring SL is transmitted via switch 15. It is electrically connected to the first gate of transistor 11. Transistor 11 has a source and One end of the drain is electrically connected to the pixel electrode of the light-emitting element 14, and the source and drain The other end of the input is electrically connected to wiring VL. The second gate of transistor 11 is The pixels of the light-emitting element 14 are electrically connected to the wiring BL via switch 16. The electrodes are electrically connected to the wiring IL via the switch 17. The capacitive element 13 has The pair of electrodes are electrically connected to the second gate of transistor 11, with one electrode being the other. The side is electrically connected to the pixel electrode of the light-emitting element 14. The pair of electrical elements of the capacitive element 18 The poles are electrically connected on one end to the first gate of transistor 11, and on the other end to the light-emitting element. It is electrically connected to the pixel electrode of sub-element 14. The common electrode of light-emitting element 14 is electrically connected to the wiring CL. They are connected by energy.

[0102] Next, FIG. 13(B) shows another example of a specific configuration of the pixel 10 shown in FIG. 1 .

[0103] The pixel 10 shown in FIG. 13(B) differs in configuration from the pixel 10 shown in FIG. 13(A) in that it further includes a switch 19.

[0104] Specifically, in the pixel 10 shown in FIG. 13(B), the wiring SL is electrically connected to the first gate of the transis tor 11 via the switch 15. One of the source and the drain of the transistor 11 is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19. The other of the source and the drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL via the switch 16. The pixel electrode of the light-emitting element 14 is electrically connected to the wiring IL via the switch 17 and the switch 19. One of the pair of electrodes of the capacitive element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19. One of the pair of electrodes of the capacitive element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

[0105] Next, a configuration example of the pixel when transistors are used for each switch in the pixel 10 shown in FIG. 13(A) will be described. The switches 15 to ​​​​Figure 14 shows an example configuration of the pixel 10 when a transistor is used as each switch 17. As shown in A).

[0106] The pixel 10 shown in Figure 14(A) is composed of a transistor 11 and switches 15 to 17. Transistors 15t to 17t, each having the function of, and a capacitive element 1 3. It has a capacitive element 18 and a light-emitting element 14.

[0107] Specifically, transistor 15t has its gate connected to wiring GLa, and one of its source and drain is The source and drain of the wiring SL are connected to the first gate of transistor 11, respectively. They are electrically connected. Transistor 11 has either its source or drain connected to the light-emitting element 1. The source and drain of the 4 pixel electrodes are electrically connected to the wiring VL, respectively. It is there. The 16t transistor has its gate wired to GLB, and one of its sources and drain wired to GLB. In BL, the source and the other drain are connected to the second gate of transistor 11, respectively. They are connected precisely. Transistor 17t has its gate connected to wiring GLd, source and drain One end of the wire is connected to the wiring IL, and the other end of the source and drain is connected to the pixel electrode of the light-emitting element 14. They are electrically connected.

[0108] Furthermore, one of the pair of electrodes of the capacitive element 13 is connected to the second gate of the transistor 11. One end is electrically connected to the other, and the other end is electrically connected to the pixel electrode of the light-emitting element 14. One of the pair of electrodes of element 18 is electrically connected to the first gate of transistor 11. The other end is electrically connected to the pixel electrode of the light-emitting element 14. The common electrode is electrically connected to the wiring CL.

[0109] Next, in the pixel 10 shown in Figure 13(B), when a transistor is used for each switch... An example of the pixel configuration will be explained. The pixel 10 shown in Figure 13(B) has switches 15 to When transistors are used as switch 17 and switch 19, pixel 10 An example of the configuration is shown in Figure 14(B).

[0110] The pixel 10 shown in Figure 14(B) is composed of a transistor 11 and switches 15 to 17. Transistors 15t to 17t, each having the function of, and switch 1 A transistor 19t that functions as 9, a capacitive element 13, a capacitive element 18, and a light-emitting element. It has element 14.

[0111] Specifically, transistor 15t has its gate connected to wiring GLa, and one of its source and drain is The source and drain of the wiring SL are connected to the first gate of transistor 11, respectively. They are electrically connected. Transistor 11 has either its source or drain connected to the transistor One of the source and drain of the 19t is connected to the wiring VL, and the other source and drain is connected to the wiring VL. They are electrically connected. Transistor 16t has its gate connected to wiring GLB, and its source connected to One side of the drain is connected to wiring BL, and the other side of the source and drain is connected to the second side of transistor 11. Each is electrically connected to the gate. Transistor 17t has its gate connected to the wiring GL d, one of the source and drain is connected to wiring IL, and the other of the source and drain is connected to the transistor It is electrically connected to either the source or drain of the 19t transistor. The 19t has its gate connected to the wiring GLc, and the other side of the source and drain is connected to the pixel power of the light-emitting element 14. Each pole is electrically connected to the others.

[0112] Furthermore, one of the pair of electrodes of the capacitive element 13 is connected to the second gate of the transistor 11. They are electrically connected, with the other side electrically connected to one of the source and drain of transistor 19t. It is connected to the first electrode of the transistor 11. It is electrically connected to the gate of the transistor, and the other side is the source and drain of transistor 19t. It is electrically connected to one side. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL. It is being done.

[0113] Next, the switches 15 to 17 of the pixel 10 shown in Figure 13(B) are respectively Figure 15(A) shows another example of the pixel 10 configuration using a transistor.

[0114] Pixel 10 shown in Figure 15(A) is a transistor 16t where one of the source and drain is distributed In that it is electrically connected to wiring VL rather than wire BL, the diagram shown in Figure 14(B) The configuration is different from that of Basic 10.

[0115] Next, the switches 15 to 17 and switch 1 of the pixel 10 shown in Figure 13(B) Figure 15(B) shows another example of the pixel 10 configuration when transistors are used in each case. This will be shown.

[0116] Pixel 10 shown in Figure 15(B) has a gate of transistor 17t that is not connected to wiring GLd, In terms of being electrically connected to the wiring GLa, the configuration is the same as that of pixel 10 shown in Figure 14(B). different.

[0117] <Example of specific pixel operation 2> Next, taking the pixel 10 shown in Figure 14(B) as an example, we will describe a light-emitting device according to one aspect of the present invention. Let's explain how pixels work.

[0118] Figure 16 shows the timing chart of the potential input to wiring GLa to wiring GLd, and wiring S This shows the timing chart of the potential of the image signal Vdata input to L. (Note: Figure 1) The timing chart shown in 6 is for the transistor included in pixel 10 shown in Figure 14(B). This example illustrates the case where all are n-channel type.

[0119] First, during period t1, a high level potential is applied to wiring GLa, and a high level potential is applied to wiring GLB. A potential is applied to the wire GLc, a low-level potential is applied to the wire GLd, and a high-level potential is applied to the wire GLd. A potential is applied to transistor 15t, transistor 16t, and transistor 15t. The zista 17t turns on, and the transistor 19t turns off.

[0120] Additionally, wiring SL has a potential of V4, wiring VL has a potential of Vano, and wiring BL has a potential of V0. The wiring IL has a potential V1, and the wiring CL, which is electrically connected to the common electrode of the light-emitting element 14, has a potential V1. The potentials Vcat are given to each. Therefore, the first gate of transistor 11 ( A potential V4 is applied to node A, and the second gate of transistor 11 (node ​​B) A potential V0 is applied to (as shown), and one of the source and drain of transistor 11 (no A potential V1 is given to point C.

[0121] The potential Vano is determined by the threshold voltage Vthe of the light-emitting element 14 and the potential Vcat, and the transistor 11 It is desirable to make the potential higher than the sum of the threshold voltage Vth and the potential V0. This shifts the threshold voltage Vth of transistor 11 in the negative direction to the extent that node C It is desirable that the potential is sufficiently high relative to the voltage Vb. Specifically, as shown in Figure 9, If the threshold voltage Vth of transistor 11 when g is 0 is Vth0, then the period At t1, the voltage Vbg corresponding to the potential difference between node B and node C is denoted as Vbg1, and Let Vth1 be the threshold voltage Vth of transistor 11. With the above configuration, the transistor Since node 11 is a normalion, the potential difference between node A and node C, i.e., the transient Even if the gate voltage of transistor 11 is V4-V1, transistor 11 can be turned on. Cut.

[0122] Furthermore, if transistor 11 is a p-channel type, the potential V0 is the threshold of transistor 11. The potential is low enough relative to node C to shift the value voltage Vth in the positive direction. This is desirable. With the above configuration, transistor 11 becomes normally on, so the node The potential difference between A and node C, that is, the gate voltage of transistor 11, is V4-V1. This also allows transistor 11 to be turned on.

[0123] Next, during period t2, a low potential is applied to wiring GLa, and a high potential is applied to wiring GLB. A potential of the bell is applied, a low level potential is applied to wiring GLc, and a low level potential is applied to wiring GLd. The potential of the bell is applied. Therefore, transistor 16t turns on, and transistor 15 t, transistor 17t, and transistor 19t are turned off.

[0124] Furthermore, the potential Vano is assigned to wiring VL, and the potential V0 is assigned to wiring BL. Therefore, the state in which potential V0 is applied to node B is maintained, and at the start of period t2 The threshold voltage Vth of transistor 11 remains shifted in the negative direction relative to Vth1. Transistor 11 is ON. And during period t2, the power between wiring VL and wiring IL The current path is interrupted by switch 17, so the drain current of transistor 11 The potentials of nodes A and C begin to rise. When the potential of node C rises, node B The voltage Vbg, which corresponds to the potential difference across node C, becomes lower, and the threshold voltage Vt of transistor 11 decreases. h shifts in the positive direction. And finally, the threshold voltage Vt of transistor 11 As h approaches the gate voltage V4-V1 of transistor 11, transistor 11 Turn it off. When the threshold voltage Vth of transistor 11 is V4-V1, node B and node B The potential difference across C is V0-V2.

[0125] That is, when the potential difference between node B and node C is V0-V2, transistor 11 operates. The threshold voltage Vt is set such that the drain current converges to 0 with respect to the gate voltage V4-V1. h will be corrected to V4-V1. The potential difference V0-V2 between node B and node C is It is applied to the quantitative element 13.

[0126] Next, during period t3, a high potential is applied to wiring GLa, and a low potential is applied to wiring GLB. A potential is applied to the bell, a low potential is applied to wiring GLc, and a high potential is applied to wiring GLd. The potential of the bell is applied. Therefore, transistors 15t and 17t turn on. As a result, transistors 16t and 19t are turned off.

[0127] Additionally, wiring VL contains the potential Vano, and wiring SL contains the potential Vdata, which includes image information. However, each wire IL is given a potential V1. And node B is floating Since it is in a state of [unclear], when node C changes from potential V2 to potential V1, the capacitive element 13 As a result, node B changes from potential V0 to potential V0+V1-V2. Then, the capacitive element 13 Since a potential difference V0-V2 is maintained, the threshold voltage Vth of transistor 11 is V4 It is maintained at -V1. Also, a potential Vdata is applied to node A, and transistor 1 The gate voltage of pin 1 is Vdata - V1.

[0128] Next, during period t4, a low potential is applied to wiring GLa, and a low potential is applied to wiring GLB. A potential is applied to the bell, a high-level potential is applied to the wiring GLc, and a low-level potential is applied to the wiring GLd. The potential of the bell is applied. Therefore, transistor 19t turns on, and transistor 15 t, transistor 16t, and transistor 17t are turned off.

[0129] Furthermore, the wiring VL has a potential Vano, and the wiring is electrically connected to the common electrode of the light-emitting element 14. A potential Vcat is given to CL. During period t4, transistor 19t When it is turned on, the potential of node C changes, and when the potential reaches V3, node A reaches potential Vd Node A is at a potential of V0-V2+V3, and node B is at a potential of V0-V2+V3. Node A, node B, and Even if the potential of node C changes, the potential difference V0-V2 is maintained in the capacitive element 13. The capacitive element 18 holds a potential difference Vdata-V1. Then, wiring VL and wiring C A drain current corresponding to the gate voltage of transistor 11 flows between L and L. The brightness of element 14 is determined according to the value of the drain current described above.

[0130] In the light-emitting device having the pixel 10 shown in Figure 14(B), the source of the transistor 11 And the other side of the drain and the second gate of transistor 11 are electrically isolated. Therefore, each potential can be controlled individually. When it is Rion, that is, when the original threshold voltage Vth0 of transistor 11 is a negative value If such a condition is met, then during period t2, one of the source and drain of transistor 11 Charge is accumulated in the capacitive element 13 until its potential becomes higher than the potential V0 of the second gate. Therefore, in a light-emitting device according to one aspect of the present invention, the transistor 11 is normally Even if this is the case, during period t2, the drain current converges to 0 relative to the gate voltage V4-V1. By bundling them together, the threshold voltage Vth can be corrected to V4-V1.

[0131] Therefore, the source and drain of transistor 11 and the second of transistor 11 The gate and the other are electrically isolated, as shown in Figures 14(A), 14(B), and 15(B). In a light-emitting device having pixels 10, for example, an oxide semiconductor is used for the semiconductor film of the transistor 11. Even if transistor 11 becomes normally on, for example, display unevenness can be reduced, and high It can display images with high resolution.

[0132] The above is an example of the operation of pixel 10, including internal correction. Next, in addition to internal correction, The variation in brightness between pixels 10 caused by variations in threshold voltage is suppressed by external correction. Next, we will explain the operation of pixel 10.

[0133] Taking pixel 10 shown in Figure 14(B) as an example, when external correction is performed in addition to internal correction, the period From t1 to period t4, follow the same timing chart as shown in Figure 16, as described above. So, pixel 10 works.

[0134] Next, in period t5 after period t4, a low potential is applied to wiring GLa, and wiring G A low potential is applied to Lb, a low potential is applied to wiring GLc, and wiring G A high potential is applied to Ld. Therefore, transistor 17t turns on, and the transistor Transistor 15t, transistor 16t, and transistor 19t will be turned off.

[0135] Additionally, wiring VL is assigned the potential Vano, and wiring IL is assigned the potential V1. Furthermore, the wiring IL is electrically connected to the monitor circuit.

[0136] As a result of the above operation, the drain current of transistor 11 is transmitted to transistor 17t and wiring IL. It is supplied to the monitor circuit via this. The monitor circuit detects the drain current flowing through the wiring IL. Using this, a signal is generated that includes the value of the drain current as information. And, according to the present invention, In the light-emitting device according to the embodiment, the potential V of the image signal supplied to the pixel 10 is used with the above signal. The values ​​of the data can be corrected.

[0137] Note that the external correction operation performed in period t5 does not always need to be performed after period t4. For example, in a light-emitting device, after repeating the operation of period t1 to period t4 multiple times, It is also possible to perform the operation during interval t5. Alternatively, the operation during period t5 can be performed in one row of pixels 10. After the operation, the image signal corresponding to the minimum grayscale value of 0 is written to the pixel 10 of the row in which the operation was performed. By embedding, the light-emitting element 14 is put into a non-emitting state, and then in the next row of pixels 10, for a period of time. You can also configure it to perform the actions of t5.

[0138] In addition, in the case of pixel 10 shown in Figure 14(A), the wiring GLa, wiring GLB, and wiring shown in Figure 16 are also used. According to the timing chart of the potentials applied to line GLd and wiring SL, they operate similarly. This can be done. Furthermore, the external correction operation can be performed in the same way as the pixels shown in Figure 14(B). This is possible. However, in the case of pixel 10 shown in Figure 14(A), in period t2, the transient To prevent the drain current of terminal 11 from flowing to the light-emitting element 14, the potential V0 is set to the threshold of the light-emitting element 14. The value voltage Vthe and the threshold voltage Vth of transistor 15t were added to the potential Vcat. It is desirable to keep it lower than the potential.

[0139] Also, in the case of pixel 10 shown in Figure 15(A), wiring GLa, wiring GLB, and wiring shown in Figure 16 are also used. According to the timing chart of the potentials applied to wire GLc, wiring GLd, and wiring SL, It can be operated in the same way. Furthermore, the operation of external correction is the same as that of the pixels shown in Figure 14(B). It can be done in this way.

[0140] Also, in the case of pixel 10 shown in Figure 15(B), wiring GLa, wiring GLb, and wiring shown in Figure 16 are also used. According to the timing chart of the potentials applied to line GLc and wiring SL, they operate similarly. This can be done. Furthermore, the external correction operation can be performed in the same way as the pixels shown in Figure 14(B). It is possible.

[0141] <Transistor Configuration Example 1> Next, in a transistor (OS transistor) where the channel formation region is formed by an oxide semiconductor film. Let me explain about ZISTA.

[0142] Figures 27(A), 27(B), and 27(C) show three transistors with different device structures. The top view (layout diagram) of the ZISTA (TA1, TA2, TB1) and the circuit symbols for each are shown below. Figure 28 shows a cross-sectional view of the transistors (TA1, TA2, TB1). Cross-sectional view of transistor TA1 along lines a1-a2 and b1-b2, and cross-sectional view of transistor TA2 along lines a3- Cross-sectional view using lines a4 and b3-b4, and line a5-a6 of transistor TB1. Cross-sectional views along the b5-b6 line are shown in Figures 28(A) and 28(B). These transistors The cross-sectional structure in the channel length direction is shown in Figure 28(A), and the cross-sectional structure in the channel width direction is This is shown in Figure 28(B).

[0143] As shown in Figures 28(A) and 28(B), the transistors (TA1, TA2, TB1) are They are integrated on the same insulating surface, and these transistors are manufactured using the same manufacturing process. It is possible to do so. Furthermore, in order to clarify the device structure, the following about each transistor is used here. Distribution for supplying potential and power to the gate (G), source (S), and drain (D) Electrical connections to the wires have been omitted.

[0144] Transistors TA1 (Figure 27(A)) and TA2 (Figure 27(B)) are gate transistors. It is a transistor having a gate (G) and a back gate (BG). In the case of BG, one of the gates corresponds to the first gate, and the other corresponds to the second gate. Transistors TA1 and TA2 have a structure in which the back gate is connected to the gate. Transistor TB1 (Figure 27(C)) is a transistor without a backgear. As shown in Figure 28, these transistors (TA1, TA2, TB1) are located on substrate 30. They are formed. The configuration of these transistors will be explained below with reference to Figures 27 and 28. do.

[0145] (Transistor TA1) Transistor TA1 consists of gate electrode GE1, source electrode SE1, drain electrode DE1, and It has a gate electrode BGE1 and an oxide semiconductor film OS1.

[0146] In the following explanation, transistor TA1 will be referred to as TA1, and the back gate as BG. The oxide semiconductor film OS1 is simply called OS1 or film OS1, omitting the names of the device and its components. These terms are sometimes used. Similarly, terms like signals, electric potential, and circuits are sometimes abbreviated.

[0147] Furthermore, in this embodiment, the channel length of the OS transistor is determined by the source electrode and the drain electrode. This is the distance between them. Also, the channel width of the OS transistor is the distance between the oxide semiconductor film and the gate electrode. This is the width of the source electrode or drain electrode in the overlapping region of transistor TA1. The channel length is La1, and the channel width is Wa1.

[0148] The film OS1 overlaps with the electrode GE1 via the insulating film 34. (Top and side views of film OS1) A pair of electrodes (SE1, DE1) are formed in contact with the surface. As shown in Figure 27(A), The membrane OS1 has portions that do not overlap with electrode GE1 and the pair of electrodes (SE1, DE1). The membrane OS1 has a length in the channel length direction that is longer than the channel length La1, and the channel The length in the width direction is longer than the channel width Wa1.

[0149] The insulating film 35 is formed covering the film OS1, electrode GE1, electrode SE1, and electrode DE1. It is there. Electrode BGE1 is formed on insulating film 35. Electrode BGE1 is film OS1 and It is positioned to overlap with electrode GE1. Here, as an example, it is the same shape as electrode GE1. In this configuration, electrodes BGE1 are provided so that they are positioned in the same location. Electrode BGE1 is an insulating film In the opening CG1 that penetrates the insulating film 35 and insulating film 36, the electrode GE1 is in contact with This structure electrically connects the gate and back gate of transistor TA1. .

[0150] By connecting the back gate electrode BGE1 to the gate electrode GE1, the transistor TA1 The on-current can be increased. By providing a back gate BGE1, the transistor The strength of TA1 can be improved. Against deformation such as bending of the substrate 30, the electrode BG E1 acts as a reinforcing element, making transistor TA1 less prone to failure.

[0151] The film OS1, which includes the channel-forming region, has a multilayer structure, and here, as an example, three oxides It has a three-layer structure consisting of semiconductor films (31, 32, 33). The oxide semiconductor film OS1 is composed of The conductive film is preferably a metal oxide film containing at least one identical metal element, In It is particularly preferable to include In, which can constitute a semiconductor film of a transistor. Examples of metal oxides include In-Ga oxide films and In-M-Zn oxide films (where M is Al, Ga, Typical examples include Y, Zr, La, Ce, or Nd. Furthermore, such metal oxide films It is also possible to use films to which other elements or materials have been added.

[0152] '32' is a film that constitutes the channel formation region of transistor TA1. Also, '33 This constitutes the channel formation region of transistors TA2 and TB1, which will be described later. It is also a film that does so. Therefore, it is required for transistors TA2 and TB1. Depending on the electrical characteristics (e.g., field-effect mobility, threshold voltage, etc.), an appropriate oxidation composition is selected. A single-component semiconductor film can be used. For example, an oxide semiconductor film can be used so that a channel is formed in '33'. It is preferable to adjust the composition of the metal elements that are the main components of the conductive films 31-32.

[0153] In transistor TA1, a channel is formed at '32', The flannel formation region can be prevented from contacting the insulating films 34 and 35. By making the body membranes 31-32 metal oxide films containing at least one of the same metal elements, '32 Interfacial scattering is less likely to occur at the interface between ' and '31', and at the interface between '32' and '33'. This makes it possible to increase the field-effect mobility of transistor TA1. It can be made higher than TA2 and transistor TB1, and the drain when on The current (on-current) can be increased.

[0154] (Transistor TA2) Transistor TA2 consists of gate electrode GE2, source electrode SE2, drain electrode DE2, and It has a gate electrode BGE2 and an oxide semiconductor film OS2. The electrode BGE2 is an insulating The electrode GE2 is in contact with the aperture CG2 that penetrates the film 34 to the insulating film 36. Transistor TA2 is a modified version of transistor TA1, and film OS2 is an oxide semiconductor film 33. It differs from transistor TA1 in that it has a single-layer structure, but is otherwise similar. So, the channel length La2 and channel width Wa2 of transistor TA2 are... The channel length La1 and channel width Wa1 are set to be equal to channel 1.

[0155] (Transistor TB1) Transistor TB1 consists of a gate electrode GE3, a source electrode SE3, a drain electrode DE3, and It has an oxide semiconductor film OS3. Transistor TB1 is a modified form of transistor TA2. Similar to transistor TA2, the film OS3 has a single-layer structure consisting of an oxide semiconductor film 33. Yes, it does. It differs from the transistor TA2 in that it does not have a back gate electrode. Also, it is film The layout of OS3 and electrodes (GE3, SE3, DE3) is different. (See Figure 27(C)) Similarly, in the region of membrane OS3 that does not overlap with electrode GE3, electrode SE3 or electrode DE It overlaps with one of the three. Therefore, the channel width Wb1 of transistor TB1 is film O It is determined by the width of S3. The channel length Lb1 is determined by the electrode SE, similar to transistor TA2. Determined by the distance between 3 and electrode DE3, here is the channel length La2 of transistor TA2. It's longer than that.

[0156] [sulfonamide] Insulating film 34, insulating film 35, and insulating film 36 are in contact with the transistors (TA1, TA2) of the substrate 30. This is a film formed over the entire region where TB1) is formed. Insulating film 34, insulating film 35, and The insulating film 36 is formed of a single layer or multiple layers of insulating film. The insulating film 34 is a transistor This is the film that constitutes the gate insulating film of (TA1, TA2, TB1). Also, insulating film 35 and The insulating film 36 is located on the back channel side gate of the transistors (TA1, TA2, TB1). This is a film that constitutes the insulating film. Furthermore, the uppermost insulating film 36 is formed on the substrate 30. It is preferable to form it with a material that functions as a protective film for the zista. The insulating film 36 is as appropriate. It should be provided to insulate the third layer electrode BGE1 from the second layer electrodes (SE1, DE1). Furthermore, it is sufficient that at least one insulating film layer exists between these layers.

[0157] The insulating films 34 to 36 are formed as single-layer insulating films or as multilayer insulating films of two or more layers. This is possible. The insulating films that make up these insulating films 34 and 36 are aluminum oxide. Aluminum, magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, nitriding Silicon oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, Examples include films made of lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. These insulating films are produced by sputtering, CVD, MBE, ALD, or It can be formed using the PLD method.

[0158] [Oxide semiconductor film] This section describes the oxide semiconductor film that constitutes the semiconductor film of an OS transistor. When a semiconductor film has a multilayer structure like OS1, the oxide semiconductor films that make up these layers are small Preferably, the metal oxide film contains at least one identical metal element, and preferably contains In. preferable.

[0159] For example, if '31' is an In-Ga oxide film, the atomic ratio of In is greater than the atomic ratio of Ga. Make it smaller. In-M-Zn oxide film (where M is Al, Ga, Y, Zr, La, Ce, or In the case of Nd, the atomic ratio of In is made smaller than the atomic ratio of M. In this case, the atoms of Zn It is possible to make the numerical ratio as large as possible.

[0160] For example, if '32' is an In-Ga oxide film, the atomic ratio of In is greater than the atomic ratio of Ga. To increase the size. In the case of an In-M-Zn oxide film, the atomic ratio of In should be greater than the atomic ratio of M. In an In-M-Zn oxide film, the atomic ratio of In is greater than the atomic ratio of M and Zn. It is preferable to make it larger.

[0161] For example, if '33' is an In-Ga oxide film, the atomic ratio of In is the same as the atomic ratio of Ga. To make it larger or smaller. In the case of an In-M-Zn oxide film, the atomic ratio of In is the same as the atomic ratio of M. Make the numerical ratio the same. In this case, the atomic ratio of Zn can be greater than that of In and M. Yes, it is possible. Here, '33' refers to the transistors TA2 and TB1, which will be discussed later. It is also a membrane that constitutes the channel-forming region.

[0162] The atomic ratio of oxide semiconductor films 31 to 33 is determined by the sputtering method. In such cases, this can be achieved by adjusting the atomic ratio of the target's constituent materials. When forming films by method, this can be done by adjusting the flow rate ratio of the raw material gas, etc. The following describes oxides. As semiconductor films 31 to oxide semiconductor films 33, In-M-Zn oxide is produced by sputtering. Using the example of forming a film, we will describe the targets used for film deposition. To form the film, a target made of In-M-Zn oxide is used.

[0163] Let the atomic ratio of the target metal elements in '31' be In:M:Zn = x1:y1:z1. and 、 x1 / y1 is preferably 1 / 6 or more and less than 1. Also, z1 / y1 is 1 / It is preferable that the value is between 3 and 6, and more preferably between 1 and 6.

[0164] Typical examples of atomic ratios of target metal elements include In:M:Zn = 1:3:2, In :M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4: 6, In:M:Zn=1:4:7, In:M:Zn=1:4:8, In:M:Zn=1: 5:5, In:M:Zn=1:5:6, In:M:Zn=1:5:7, In:M:Zn= Examples include 1:5:8 and In:M:Zn=1:6:8.

[0165] Let the atomic ratio of the metal elements in the target '32' be In:M:Zn = x2:y2:z2. and 、 It is preferable that x² / y² is greater than 1 and less than or equal to 6. Also, z² / y² is less than or equal to 1. It is preferable that it is greater than or equal to 6. Examples of the atomic ratio of target metal elements are given below. is In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Z n=2:1:3, In:M:Zn=3:1:2, In:M:Zn=3:1:3, In:M Examples include Zn=3:1:4.

[0166] Let's assume the atomic ratio of the metal elements in the target of '33' is In:M:Zn = x3:y3:z3. and 、 x3 / y3 is preferably between 1 / 6 and 1. Also, z3 / y3 is 1 / The original value of the target metal element is preferably 3 or more and 6 or less, and more preferably 1 or more and 6 or less. Typical examples of the ratio of offspring are In:M:Zn=1:1:1 and In:M:Zn=1:1:1. 2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1: 3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:4, In:M:Zn= 1:4:5, In:M:Zn=1:4:6, In:M:Zn=1:4:7, In:M:Z n=1:4:8, In:M:Zn=1:5:5, In:M:Zn=1:5:6, In:M :Zn=1:5:7, In:M:Zn=1:5:8, In:M:Zn=1:6:8, and so on .

[0167] In a target for depositing an In-M-Zn oxide film, when the atomic ratio of metal elements is In:M: Zn = x:y:z, setting 1 ≤ z / y ≤ 6 is preferable because this facilitates the formation of a CAAC-OS film as the In-M-Zn oxide film . Note that the CAAC-OS film will be described later.

[0168] As the oxide semiconductor film 31 to oxide semiconductor film 33, an oxide semiconductor film with low carrier density is used. For example, as the oxide semiconductor film 31 to oxide semiconductor film 33, the carrier density is 1×10 17 ions / cm 3 or less, preferably 1×10 15 ions / cm 3 or less, and more preferably is 1×10 13 ions / cm 3 or less oxide semiconductor film is used. In particular, the oxide semiconductor film 31 to oxide semiconductor film 33 has a carrier density of 8×10 11 ions / cm 3 less than, more preferably 1×10 11 ions / cm 3 less than, still more preferably less than 1×10 10 ions / cm 3 , it is less than , and it is preferable to use an oxide semiconductor film with carrier density of 1×10 -9 ions / cm 3 or more.

[0169] The oxide semiconductor films 31 to 33 have a low impurity concentration and a low defect level density. By using low-temperature oxide semiconductor films, transistors with even better electrical characteristics can be created. It can be manufactured in a way that has a low impurity concentration and a low defect level density (low oxygen deficiency). The term "high-purity intrinsic" or "substantially high-purity intrinsic" refers to a substance that is (not) intrinsic or substantially high-purity intrinsic. Oxide semiconductors, being of intrinsic purity, have few carrier sources, thus resulting in a low carrier density. In some cases, this is possible. Therefore, when channel regions are formed in the oxide semiconductor film, The inverter exhibits an electrical characteristic where the threshold voltage is negative (also known as normalion). It is rare for this to happen. Also, oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic are Because the defect level density is low, the trap level density may also be low. Furthermore, high-purity intrinsic... Alternatively, an oxide semiconductor film that is substantially high-purity intrinsic has a remarkably low off-current and a wide channel width. is 1 x 10 6 Even with a device with a channel length L of 10 μm, the source electrode and drain electrode When the voltage between the electrodes (drain voltage) is in the range of 1V to 10V, the off-current is in the semiconductor parallel Below the measurement limit of the meter analyzer, i.e., 1 × 10⁻⁶ -13 Obtain the characteristic of being A or less. This is possible. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film is electrically This results in a transistor with small fluctuations in gas characteristics and high reliability. Impurities include hydrogen and nitrogen. These include elements, alkali metals, or alkaline earth metals.

[0170] Hydrogen contained in oxide semiconductor films reacts with oxygen bonded to metal atoms to form water, and also acid An oxygen vacancy is formed in the lattice where an element has been removed (or in the area where oxygen has been removed). When hydrogen enters, electrons, which act as carriers, are sometimes generated. Also, some of the hydrogen In some cases, by bonding with oxygen atoms that bond with metal atoms, electrons, which act as carriers, can be generated. Therefore, transistors using oxide semiconductors containing hydrogen exhibit normally-on characteristics. It's easy to understand.

[0171] Therefore, the oxide semiconductor films 31 to 33 produce hydrogen along with oxygen vacancies. It is preferable that it be reduced as much as possible. Specifically, oxide semiconductor film 31 to oxide semiconductor In membrane 33, secondary ion mass spectrometry (SIMS) was performed. The hydrogen concentration obtained by ss Spectrometry is 5 × 10 19 atoms / cm 3 More preferably 1 × 10 19 atoms / cm 3 Below, 5 x 10 18 at oms / cm 3 Less than 1 × 10 18 atoms / cm 3 The following is more 5 x 10 17 atoms / cm 3 More preferably 1 × 10 16 atoms / cm 3 The following applies:

[0172] The oxide semiconductor films 31 to 33 contain silicon and carbon, which are among the Group 14 elements. When acid is present, oxygen deficiency in the membrane increases, causing these membranes to become n-type. The concentration of silicon and carbon in the oxide semiconductor film 31 to the oxide semiconductor film 33 (secondary ionic properties) The concentration obtained by quantitative analysis is 2 × 10 18 atoms / cm 3 The following are preferably 2 ×1017 atoms / cm 3 The following applies:

[0173] Furthermore, in oxide semiconductor films 31 to 33, secondary ion mass spectrometry is used The concentration of alkali metals or alkaline earth metals obtained is 1 × 10⁻⁶ 18 ate / c m 3 The following is preferably 2 × 10 16 atoms / cm 3 The following applies: Alkali metals and A Lucali earth metals can generate carriers when they bond with oxide semiconductors, and transients The off-current of the sta may increase. Therefore, the oxide semiconductor film 31 to oxide It is preferable to reduce the concentration of alkali metals or alkaline earth metals in the semiconductor film 33.

[0174] If nitrogen is present in oxide semiconductor films 31 to 33, the carriers will be As offspring are produced, the carrier density increases, and it becomes easier for it to become n-type. Therefore, oxides containing nitrogen are used. Since transistors using semiconductors tend to exhibit normally-on characteristics, the oxide semiconductor film 31 Alternatively, it is preferable that the nitrogen content of the oxide semiconductor film 33 be reduced as much as possible, for example Then, the nitrogen concentration obtained by secondary ion mass spectrometry is 5 × 10⁻⁶ 18 atoms / cm 3 Below It is preferable to place it downwards.

[0175] The above describes oxide semiconductor films 31 to 33, but is not limited to these. , the semiconductor characteristics and electrical characteristics of the transistor required (field-effect mobility, threshold voltage) Depending on the requirements, an oxide semiconductor film with an appropriate composition may be used. To obtain the semiconductor properties and electrical properties of the oxide semiconductor film 31 to oxide semiconductor film 3 3. Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density It is preferable to set the degree and other parameters appropriately.

[0176] Transistor TA1 is Ga or M (where M is Al, Ga, Y, Zr, La, Ce, or In oxide semiconductor film 32, where the atomic ratio of In is greater than the atomic ratio of Nd, channels are formed. Therefore, the field effect mobility can be increased. Typically, the field effect mobility is , 10cm 2 / Larger than Vs, 60cm 2 / Vs less than, preferably 15cm 2 / Vs or more 50cm 2 It is less than / Vs. Therefore, the circuit of the active matrix display device is affected. The TA1 inverter is suitable for drive circuits that require high-speed operation.

[0177] Furthermore, it is preferable to place transistor TA1 in a light-shielded region. By providing a transistor TA1 with effective mobility in the drive circuit, the drive frequency can be increased. This allows for the creation of higher-resolution display devices.

[0178] Transistors TA2 and TB1, in which the channel formation region is formed by an oxide semiconductor film 33, It has a lower field-effect mobility than the TA1 transistor, and its size is 3 cm. 2 / Vs or more 10 cm 2 It is approximately / Vs or less. Transistors TA2 and TB1 have an oxide semiconductor film 32. Because it does not have this feature, it is less susceptible to degradation from light than transistor TA1, and is not turned off by light irradiation. The increase in current is small. Therefore, the channel formation region is formed by the oxide semiconductor film 33. Transistors TA2 and TB1 are suitable for pixel areas that are illuminated by light.

[0179] Compared to transistor TA2, which does not have an oxide semiconductor film 32, When light is shone on it, the current in the off state tends to increase. Transistor TA1 is in the pixel area This is why it is more suitable for peripheral drive circuits, which are less affected by light, than for pixel areas, where light shielding is not sufficient. It is one of them. Also, of course, transistors with configurations such as transistor TA2, TB1 It is also possible to install a t-type component in the drive circuit.

[0180] The above describes transistors (TA1, TA2, TB1) and oxide semiconductor films 31 to oxide semiconductors. Although film 33 has been described, it is not limited to these, and the semiconductor characteristics of the transistor required and The transistor configuration can be changed according to its electrical characteristics. For example, the back gate electrode. Presence or absence, layered structure of oxide semiconductor film, oxide semiconductor film, terminal electrode, source electrode and The shape and arrangement of the rain electrodes can be changed as needed.

[0181] (Structure of oxide semiconductors) Next, we will explain the structure of oxide semiconductors.

[0182] In this specification, "parallel" means that two straight lines are aligned at an angle of -10° to 10°. It refers to the state in which something is placed. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "Approximately parallel" refers to a state where two straight lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state where two straight lines are positioned at an angle of 80° to 100°. It refers to the state. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "approximately perpendicular" means This refers to a state in which two straight lines are positioned at an angle between 60° and 120°.

[0183] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0184] Oxide semiconductor films are divided into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. For example, oxide semiconductors can be divided into crystalline oxide semiconductors and amorphous oxide semiconductors. ru.

[0185] Furthermore, as a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned) Crystalline Oxide Semiconductor, Polycrystalline Oxide These include semiconductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors. Also, crystalline oxide semiconductors... The materials include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides. Examples include semiconductors.

[0186] First, let's explain the CAAC-OS membrane.

[0187] CAAC-OS film is an oxide semiconductor film having multiple c-axis oriented crystalline regions.

[0188] Transmission Electron Microscope (TEM) A composite analysis image of the CAAC-OS film's bright-field image and diffraction pattern (using a scope) Also known as a high-resolution TEM image, multiple crystalline regions can be identified by observing it. On the other hand, high-resolution TEM images also clearly show the boundaries between crystalline parts, i.e., grain boundaries. Also called boundary.) It is not possible to confirm. Therefore, the CAAC-OS membrane is This means that a decrease in electron mobility due to grain boundaries is less likely to occur.

[0189] When observing a high-resolution TEM image of the cross-section of the CAAC-OS film from a direction approximately parallel to the sample surface, In the crystalline region, it can be confirmed that the metal atoms are arranged in layers. Each layer of metal atoms is: The surface (also called the film-forming surface) or the top surface of the CAAC-OS film reflects the unevenness of the surface on which the film is formed. It has a specific shape and is arranged parallel to the surface or top surface of the CAAC-OS film to be formed.

[0190] On the other hand, a high-resolution TEM image of the CAAC-OS film plane was observed from a direction approximately perpendicular to the sample surface. This confirms that in the crystalline region, the metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions.

[0191] X-ray diffraction (XRD) applied to the CAAC-OS film. When structural analysis is performed using this method, for example, a CAAC-OS film having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is approximately aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing vertically.

[0192] Furthermore, the out-of-plane method for CAAC-OS films containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 36° 2θ indicate c-axis orientation in a portion of the CAAC-OS film. This indicates that it contains crystals that do not have [the specified characteristic]. The CAAC-OS film has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0193] CAAC-OS films are oxide semiconductor films with low impurity concentrations. The impurities include hydrogen, carbon, These are elements other than silicon and transition metal elements, which are the main components of oxide semiconductor films. In particular, silicon Elements such as ions, which have a stronger bonding force with oxygen than the metal elements that make up oxide semiconductor films, By removing oxygen from the material semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a certain atomic radius. Because of its large molecular radius, when it is contained within an oxide semiconductor film, the oxide semiconductor film This disrupts the atomic arrangement and reduces crystallinity. Furthermore, these impurities are present in oxide semiconductor films. Objects can sometimes act as carrier traps or carrier sources.

[0194] Furthermore, CAAC-OS films are oxide semiconductor films with a low defect level density. For example, oxide Oxygen vacancies in semiconductor films can act as carrier traps or capture hydrogen. It can be a source of carrier activity.

[0195] A low impurity concentration and low defect level density (few oxygen vacancies) is referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film Because there are fewer carrier sources, the carrier density can be kept low. Therefore, The transistor using this oxide semiconductor film exhibits an electrical characteristic in which the threshold voltage becomes negative. Also called normally-on.) It rarely becomes high-purity intrinsic or substantially high-purity. Highly intrinsic oxide semiconductor films have few carrier traps. Transistors using body membranes exhibit less variation in electrical characteristics and are highly reliable. Furthermore, the charge trapped in the carrier trap of the oxide semiconductor film requires time to be released. It can remain dormant for a long time, behaving almost like a fixed charge. Therefore, the impurity concentration Transistors using oxide semiconductor films with high defect level density have unstable electrical properties. It can happen.

[0196] Furthermore, transistors using CAAC-OS films exhibit electrical characteristics under irradiation with visible light and ultraviolet light. The fluctuations are small.

[0197] Next, we will explain microcrystalline oxide semiconductor films.

[0198] Microcrystalline oxide semiconductor films have areas where crystalline regions can be confirmed in high-resolution TEM images. It has regions where a clear crystalline structure cannot be observed, and regions where a clear crystalline structure cannot be identified. Microcrystalline oxide semiconductor film The crystalline portion contained therein is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, the minute particles are between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having nanocrystals (nc) which are crystalline, -OS(nanocrystalline oxide semiconductor) It is called a film. Furthermore, nc-OS films, for example, clearly show grain boundaries in high-resolution TEM images. There may be cases where it cannot be recognized.

[0199] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). The atomic arrangement has periodicity in the region of 3 nm or less. Also, the nc-OS film is different No regularity in crystal orientation is observed between the crystalline regions. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where this is not possible. For example, when using X-rays with a diameter larger than that of the crystalline region on an nc-OS film, XR When structural analysis is performed using instrument D, the out-of-plane method shows that the crystal plane No peaks indicating this are detected. Also, for the nc-OS film, probes larger than the crystalline region are detected. Electron diffraction (also called limited-area electron diffraction) using an electron beam with a diameter (e.g., 50 nm or more) When this is done, a diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS films... Nanobeam electron beams with a probe diameter close to or smaller than the size of the crystal region are used. When diffraction is performed, spots are observed. Furthermore, nanobeam electron diffraction is performed on nc-OS films. When this is done, a region of high brightness may be observed in a circular (ring-shaped) pattern. Also, When nanobeam electron diffraction is performed on an nc-OS film, multiple spots are observed within a ring-shaped region. It may be observed.

[0200] nc-OS films are oxide semiconductor films with higher orderliness than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, In nc-OS films, no regularity is observed in the crystal orientation between different crystalline regions. Therefore, nc-O The S film has a higher defect level density compared to the CAAC-OS film.

[0201] Next, we will explain amorphous oxide semiconductor films.

[0202] Amorphous oxide semiconductor films have an irregular atomic arrangement within the film and do not contain crystalline regions. These are physical semiconductor films. One example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0203] In amorphous oxide semiconductor films, crystalline regions cannot be observed in high-resolution TEM images.

[0204] When structural analysis of amorphous oxide semiconductor films is performed using an XRD device, out-of-p Analysis using the Lane method did not detect any peaks indicating crystal planes. Furthermore, amorphous oxide semi-crystalline materials were found. When electron diffraction is performed on a conductive film, a halo pattern is observed. Furthermore, amorphous oxide semiconductors... When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is not seen. It is observed.

[0205] Furthermore, oxide semiconductor films exhibit physical properties between nc-OS films and amorphous oxide semiconductor films. It may have such a structure. Oxide semiconductor films having such a structure are particularly amorphous-like oxide Amorphous-like Oxide Semiconductor (a-like OS) It is called a conductor film.

[0206] In a-like OS films, porosity (also called voids) is observed in high-resolution TEM images. In some cases, the crystalline portion can be clearly identified in high-resolution TEM images. It has regions and regions where the crystalline portion cannot be observed. The a-like OS film is Crystallization occurs and crystalline growth is observed even with minute electron irradiation, such as that seen by TEM. This can sometimes occur. On the other hand, with a high-quality nc-OS film, even trace amounts of electricity, such as those observed by TEM, are not detected. Crystallization due to subirradiation is hardly observed.

[0207] Furthermore, the size of the crystalline portion of a-like OS films and nc-OS films was measured using high-resolution T This can be done using EM imaging. For example, the crystal of InGaZnO4 has a layered structure, The unit cell of the InGaZnO4 crystal has two Ga-Zn-O layers between the In-O layers. It has three In-O layers and six Ga-Zn-O layers, for a total of nine layers arranged in the c-axis direction. It has a structure that is layered in a staggered manner. Therefore, the spacing between these adjacent layers is the (009) plane. It is approximately the same as the lattice plane spacing (also called the d-value), and its value, as determined by crystal structure analysis, is 0.29 nm. Therefore, we are focusing on the grid lines in high-resolution TEM images, and the spacing of the grid lines. In areas where the wavelength is between 0.28 nm and 0.30 nm, each lattice fringe is InG This corresponds to the ab-plane of the aZnO4 crystal.

[0208] Furthermore, oxide semiconductor films may have different densities depending on their structure. For example, a certain oxide semiconductor If the composition of the body membrane is known, then by comparing it with the density of a single crystal with the same composition, The structure of the oxide semiconductor film can be estimated. For example, with respect to the density of a single crystal, a- The density of the OS film is between 78.6% and 92.3%. Also, for example, single crystal Compared to the density of the nc-OS film and the CAAC-OS film, the density of the nc-OS film is 92.3% or higher. It will be less than 0%. Furthermore, an oxide semiconductor film with a density of less than 78% of the density of a single crystal is... Deposition of the film itself is difficult.

[0209] The above will be explained using a concrete example. For example, In:Ga:Zn=1:1:1[atom In an oxide semiconductor film satisfying the [number ratio], a single crystal InGaZnO4 having a rhombohedral structure. The density is 6.357 g / cm³ 3Therefore, for example, In:Ga:Zn=1:1:1 In an oxide semiconductor film satisfying the [atomic ratio], the density of the a-like OS film is 5.0 g. / cm 3 More than 5.9g / cm 3 It becomes less than. Also, for example, In:Ga:Zn=1:1: In an oxide semiconductor film satisfying 1 [atomic ratio], the density of the nc-OS film and CAAC- The density of the OS film is 5.9 g / cm³. 3 More than 6.3g / cm 3 It will be less than.

[0210] Note that single crystals with the same composition may not exist. In that case, different compositions may be found in arbitrary proportions. By combining single crystals, it is possible to calculate the density corresponding to a single crystal with a desired composition. Yes, it is possible. The density of a single crystal of the desired composition depends on the ratio of single crystals with different compositions combined. It can be calculated using a weighted average. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate by combining the two factors.

[0211] Furthermore, oxide semiconductor films include, for example, amorphous oxide semiconductor films, a-like OS films, and microcrystalline films. The film may be a multilayer film having two or more types of crystalline oxide semiconductor films and CAAC-OS films.

[0212] As explained above, OS transistors can achieve extremely excellent off-current characteristics.

[0213] [Circuit board 30] Various types of substrates can be used for the substrate 30, and it is not limited to any particular type. Examples of substrates 30 include semiconductor substrates (e.g., single crystal substrates or silicon substrates), SOI Substrates, glass substrates, quartz substrates, plastic substrates, metal substrates, stainless steel substrates, Substrates with stainless steel foil, tungsten substrates, tungsten foil Substrates, flexible substrates, laminated films, paper containing fibrous materials, or base material films Examples include barium borosilicate glass and aluminobodium. Examples include sodium-lime glass or soda-lime glass. Flexible substrates, laminated films, base Examples of material films include the following: For example, polyethylene tereol PET, polyethylene naphthalate (PEN), polyethersulfone ( There are plastics such as PES. Alternatively, as an example, synthetic resins such as acrylic. It contains oil, etc. Or, as an example, polypropylene, polyester, polyvinyl fluoride Examples include polyvinyl chloride, or polyamide, polyimide, These include aramid, epoxy, inorganic vapor-deposited films, and paper. In particular, semiconductor substrates and single-layered materials. By manufacturing transistors using a crystalline substrate or SOI substrate, characteristics, size, etc., can be improved. Transistors with minimal variation in size or shape, high current capacity, and small size. It can be manufactured. When a circuit is constructed using such transistors, the circuit's power consumption is reduced. This allows for reduced power consumption or increased circuit integration.

[0214] Before forming the gate electrodes (GE1, GE2, GE3), an underlayer insulating film is formed on the substrate 30. This may be done. As the undercoat insulating film, silicon oxide, silicon oxide nitride, silicon nitride, nitrile Silicon oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide Examples include aluminum oxide nitride, etc. Furthermore, silicon nitride, gallium oxide, etc., are used as the underlayer insulating film. By using materials such as hafnium oxide, yttrium oxide, and aluminum oxide, the substrate 30 From impurities (typically alkali metals, water, hydrogen, etc.) into oxide semiconductor films (OS1-OS3) This can suppress the spread to ).

[0215] [Gate field (GE1, GE2, GE3)] The gate electrodes (GE1, GE2, GE3) consist of a single conductive film or two or more conductive films stacked together. It is a layered, multilayered film. It is formed as a gate electrode (GE1, GE2, GE3). The conductive film is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten. A selected metal element, or an alloy containing the above-mentioned metal elements, or the above-mentioned metal elements It can be formed using a combination of alloys, etc. Also, manganese, zirconium A metallic element selected from one or more of the following may be used. In addition, aluminum may be used. Choose from tan, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. An alloy film or nitride film, which is a combination of one or more of these films, may also be used. Indium oxide containing tungsten oxide, indium oxide containing tungsten oxide Indium oxide containing zinc oxide, titanium oxide containing indium tin oxide, and titanium oxide containing indium tin oxide. Translucent oxides, indium zinc oxide, indium tin oxide including silicon oxide, etc. It is also possible to apply conductive materials.

[0216] For example, as the gate electrodes (GE1, GE2, GE3), an aluminum film containing silicon. This can be formed when the gate electrodes (GE1, GE2, GE3) have a two-layer structure. For example, forming a titanium film on an aluminum film, or forming a titanium film on a titanium nitride film. To form a tungsten film on a titanium nitride film, a tantalum nitride film or tungsten nitride film A tungsten film can be formed on the tungsten film. Also, the gate electrode (GE1, GE2, GE 3) If the structure is made into a three-layer structure, for example, a titanium film and an aluminum film on top of the titanium film The layers can be stacked, and then a titanium film can be formed on top of them.

[0217] By sputtering, vacuum deposition, pulsed laser deposition (PLD), thermal CVD, etc. They form gate electrodes (GE1, GE2, GE3).

[0218] Furthermore, tungsten films can be deposited using a film deposition apparatus that utilizes ALD. In this process, WF6 gas and B2H6 gas are sequentially and repeatedly introduced to form an initial tungsten film. Subsequently, WF6 gas and H2 gas are introduced simultaneously to form a tungsten film. SiH4 gas may be used instead of 2H6 gas.

[0219] In addition to the above formation method, the gate electrodes GE1-GE3 can be formed by electroplating, printing, and ink. This can be done using methods such as the Quetz method.

[0220] [Insulating film 34 (gate insulating film)] The insulating film 34 is formed by covering the gate electrodes GE1-GE3. The insulating film 34 is a single layer of insulation. It is an insulating film or a multilayer insulating film with two or more layers. The insulating film formed as insulating film 34 is Examples include oxide insulating films, nitride insulating films, oxide-nitriding insulating films, and nitride-oxide insulating films. In this specification, an oxidized nitride is a material in which the oxygen content is higher than the nitrogen content. A oxide is defined as a material in which nitrogen content is higher than oxygen content.

[0221] Examples of insulating films formed as insulating film 34 include silicon oxide and silicon oxide nitride. silicon nitride, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide Alternatively, an insulating film made of a Ga-Zn metal oxide can be formed. As an insulating film, hafnium silicate (HfSiO x ), Hafniu with added nitrogen Musilicate (HfSi x O y N z ), nitrogen-added hafnium aluminate (Hf Al x O y N z ), a film made of high-k materials such as hafnium oxide and yttrium oxide. It is possible to form a transistor gate leak by using high-k material. It can be reduced.

[0222] Since the insulating film 34 is a film that constitutes the gate insulating film, the oxide semiconductor film (OS1, OS2, To improve the interfacial properties between OS3) and the gate insulating film, these layers in insulating film 34 The regions in contact with (OS1, OS2, OS3) are formed with an oxide insulating film or an oxidnitriding insulating film. It is preferable to do so. For example, the uppermost layer of the insulating film 34 is a silicon oxide film or an oxide film. A silicon nitride film would suffice.

[0223] The thickness of the insulating film 34 may be, for example, 5 nm to 400 nm. More preferably, the wavelength is between 10 nm and 300 nm, and more preferably between 50 nm and 250 nm. That is the case.

[0224] When forming oxide semiconductor films (OS1, OS2, OS3) by sputtering, plasma The power supply for generating the signal may include an RF power supply, AC power supply, DC power supply, etc., as appropriate. It can be used.

[0225] Sputtering gases include a noble gas (typically argon) atmosphere, an oxygen atmosphere, and a noble gas and Use an appropriate mixture of oxygen gases. In the case of a mixture of noble gases and oxygen, use the appropriate amount for the noble gas. It is preferable to increase the oxygen gas ratio.

[0226] Furthermore, the target is determined by the composition of the oxide semiconductor film (OS1, OS2, OS3) to be formed. Then, you can choose as appropriate.

[0227] Furthermore, when using the sputtering method to form oxide semiconductor films (OS1, OS2, OS3) In addition, the substrate temperature is set to 150°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower, further Preferably, the temperature is set to 200°C or higher and 350°C or lower, so that the oxide semiconductor films 31-32 are A CAAC-OS film can be formed.

[0228] Furthermore, it is preferable to apply the following conditions for forming the CAAC-OS film.

[0229] By suppressing the inclusion of impurities during film formation, it is possible to prevent the disruption of the crystalline state due to impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, and nitrogen, etc.) present in the deposition chamber can be reduced. It should be reduced. Also, the impurity concentration in the film-forming gas should be reduced. Specifically, the dew point should be reduced. A film-forming gas with a temperature of 80°C or lower, preferably -100°C or lower, is used.

[0230] Furthermore, by increasing the oxygen content in the deposition gas and optimizing the power, plasma damage during film deposition can be reduced. It is preferable to reduce this. The oxygen content in the film-forming gas is preferably 30% by volume or more, and 100 parts Product percentage is preferable.

[0231] By depositing an oxide semiconductor film while heating it, or after forming an oxide semiconductor film, By performing a heat treatment, the hydrogen concentration of the oxide semiconductor film is increased to 2 × 10⁻⁶. 20 atoms / cm 3 Below Below, preferably 5 × 10 19 atoms / cm 3 More preferably 1 × 10 19 at oms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than 1 × 10 18 a toms / cm 3 The following is more preferable: 5 x 10 17 atoms / cm 3 Below, further good Mashiku is 1 x 10 16 atoms / cm 3 The following is possible:

[0232] Furthermore, the heat treatment should be performed at a temperature higher than 350°C but 650°C or lower, preferably 450°C to 600°C. By performing the process as described below, the CAAC conversion rate, as described later, will be 70% or more and less than 100%, preferably 80%. More than 100%, preferably 90% or more and less than 100%, more preferably 95% or more and 98% An oxide semiconductor film with a content of less than % can be obtained. In addition, the content of hydrogen, water, etc. can be reduced. It is possible to obtain oxide semiconductor films with low impurity concentrations and low defect level density. It is possible to form oxide semiconductor films with low properties.

[0233] Oxide semiconductor films can be formed using a film deposition apparatus that utilizes ALD. For example, InG aZnO X (X>0) When forming a film, In(CH3)3 gas and O3 gas are sequentially used. The gas is repeatedly introduced to form an InO2 layer, and then Ga(CH3)3 gas and O3 gas are introduced simultaneously. After introducing the gas to form a GaO layer, and then simultaneously introducing Zn(CH3)2 gas and O3 gas, Then a ZnO layer is formed. Note that the order of these layers is not limited to this example. Also, these layers Mixing in InGaO2, InZnO2, GaInO, ZnInO, and GaZnO A mixed compound layer, such as a layer, may be formed. Alternatively, an inert gas such as Ar can be used instead of O3 gas. While bubbling H2O gas can be used, it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, In(C2H5)3 gas may be used. Alternatively, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Also, Z n(CH3)2 gas may also be used.

[0234] The oxide semiconductor film 32 and the oxide semiconductor film 33 form the channels of the transistor. It is a film whose thickness can be between 3 nm and 200 nm. Preferably, the wavelength is 3 nm to 100 nm, and more preferably 30 nm to 50 nm. The following applies: The thickness of the oxide semiconductor film 31 shall be, for example, 3 nm or more and 100 nm or less. This is possible, preferably with a wavelength of 3 nm to 30 nm, and more preferably with a wavelength of 3 nm to 15 nm. The following applies: The oxide semiconductor film 31 is thinner than the oxide semiconductor film 32 and the oxide semiconductor film 33. It is preferable to form it in a certain way.

[0235] Here, as oxide semiconductor films 31, 32, and 33, In-Ga-Zn films are sputtered The film is deposited using the G method. The atomic ratio of the target metal elements used in these films (In:G) a:Zn) For example, oxide semiconductor film 31 is 1:3:6 and oxide semiconductor film 32 is The ratio is 3:1:2, and the oxide semiconductor film 33 is 1:1:1.2 or 1:1:1. This is possible. Also, the thicknesses of the oxide semiconductor films 31, 32, and 33 are 5 nm and 35 nm, respectively. The nm can be set to 35nm.

[0236] [Source electrode, drain electrode] The electrodes (SE1, DE1, SE2, DE2, SE3, DE3) are gate electrodes (GE1, GE 2. It can be formed in the same way as GE3.

[0237] For example, a copper-manganese alloy film with a thickness of 50 nm, a copper film with a thickness of 400 nm, and a copper film with a thickness of 100 nm By stacking these films in the order of m copper-manganese alloy films using the sputtering method, Forming a three-layer electrode structure (SE1, DE1, SE2, DE2, SE3, DE3) can.

[0238] Transistors used in drive circuits for light-emitting devices, etc., are designed to operate at high speeds. The sta is a transistor (TA1, TA2), or a transistor (TA3, TA4, It is preferable to shorten the channel length, as in TC1). The channel length is preferably less than 2.5 μm. For example, it is preferable to have it be 2.2 μm or less. i. In the transistor of this embodiment, the channel length is the distance between the source electrode and the drain electrode. Therefore, the minimum channel length is determined by the electrodes (SE1, DE1, SE2, DE2, S The precision required to process the conductive film (E3, DE3) is limited. Transistor of this embodiment For example, the channel length can be 0.5 μm or more, or 1.0 μm or more. ru.

[0239] [Insulating film 35, 36] For example, with '35', a two-layer insulating film structure can be formed. Here, '3 The first layer of film 5 will be called insulating film 35a, and the second layer will be called insulating film 35b.

[0240] The insulating film 35a is, for example, an oxide insulating film made of silicon oxide, or a nitrogen-containing film. Furthermore, it is possible to form an oxide insulating film with a low defect rate. It contains nitrogen and has a low defect rate. Typical examples of oxide insulating films with low emissions include silicon oxide nitride films and aluminum oxide nitride films. These include:

[0241] Oxide insulating films with few defects exhibit spectra obtained by measuring at ESR below 100K. The first signal is when the g value is between 2.037 and 2.039, and the second signal is when the g value is between 2.001 and 2. A second signal below 003, and a third signal with a g value between 1.964 and 1.966. A signal is observed. Furthermore, the split width of the first signal and the second signal, and the second signal... The split width of the first signal and the third signal is approximately 5m in the X-band ESR measurement. It is T. Also, the first signal is when the g value is between 2.037 and 2.039, and the g value is 2.0 A second signal between 01 and 2.003, and a g value between 1.964 and 1.966. The sum of the spin densities of a third signal is 1 × 10⁻¹⁰ 18 spins / cm 3 Less than Typical examples include 1 x 10 17 spins / cm 3 The above 1 x 10 18 spins / cm 3 less than That is the case.

[0242] Furthermore, in ESR spectra below 100K, the g value is between 2.037 and 2.039. The first signal, the second signal with a g value between 2.001 and 2.003, and the g value of 1. The third signal, between 964 and 1.966, represents nitrogen oxides (NOx, where x is between 0 and 2). This corresponds to a signal originating from (preferably 1 or more and 2 or less). Typical examples of nitrogen oxides include: These include nitric oxide, nitrogen dioxide, etc. That is, the first one has a g value of 2.037 or more and 2.039 or less. A signal, a second signal with a g value between 2.001 and 2.003, and a g value of 1.96 The smaller the sum of the spin densities of the third signal, which is between 4 and 1.966, the less likely it is to be an oxide. It can be said that the nitrogen oxide content in the insulating film is low.

[0243] Because the insulating film 35a is a film with a low nitrogen oxide content, the insulating film 35a and the layer (OS It is possible to reduce carrier trapping at the interface with OS2 and OS3. As a result, it is possible to reduce the threshold voltage shift of the transistor, This can reduce variations in the electrical characteristics of the zista.

[0244] Furthermore, to improve the reliability of the transistor, the insulating film 35a is SIMS (Secondary The nitrogen concentration measured by (Ion Mass Spectrometry) is 6 × 10 2 0 / cm 3 The following is preferable: During the transistor fabrication process, the insulating film 35 This is because nitrogen oxides are less likely to be produced in state a.

[0245] As an example of an oxide insulating film containing nitrogen and having a low defect rate, CV A silicon oxidoxide-nitride film can be formed by method D. In this case, the raw material gas is: It is preferable to use a silicon-containing depositing gas and an oxidizing gas. Typical examples of oxidative gases include silanes, disilanes, trisilanes, and silane fluorides. Examples of gaseous substances include nitrous oxide and nitrogen dioxide.

[0246] Furthermore, the ratio of oxidizing gas to sedimentary gas is greater than 20 times but less than 100 times, preferably 40 times. The ratio should be between 2 and 80 times, and the pressure inside the processing chamber should be less than 100 Pa, preferably 50 Pa or less. By using the CVD method, the insulating film 35a is made of nitrogen and has a low defect content. A material insulating film can be formed.

[0247] As the insulating film 35b, for example, an oxide containing more oxygen than satisfies the stoichiometric composition. It can be formed using a material insulating film. More oxygen than satisfactorily satisfying the stoichiometric composition. In oxide insulating films containing [a certain substance], some of the oxygen is removed upon heating. Oxide insulating films containing more oxygen than those with a higher oxygen content, when analyzed by TDS, show a higher oxygen content in terms of oxygen atoms. Desorption amount is 1.0 × 10 18 atoms / cm 3 Preferably 3.0 × 10 20 ato ms / cm 3 The above describes the oxide insulating film. Note that the surface of the film during the above TDS analysis. The preferred temperature range is between 100°C and 700°C, or between 100°C and 500°C. It's nice.

[0248] The insulating film 35b has a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more. Silicon oxide, silicon oxide nitride, etc., with a wavelength of 00 nm or less can be used. Insulating film 35 As b, an oxide insulating film containing more oxygen than satisfactorily satisfying the stoichiometric composition is used to form When formed, oxygen is used as an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition A silicon oxynitride film can be formed by a CVD method.

[0249] In the case of forming a silicon oxide film or a silicon oxynitride film as the insulating film 35b, the following Film formation can be performed under the following conditions. A substrate placed in an evacuated processing chamber of a plasma CVD apparatus is held at a temperature of 180°C or higher and 280°C or lower, more preferably 200°C or higher and 240°C or lower , a source gas is introduced into the processing chamber, and the pressure in the processing chamber is adjusted to 100 Pa or more and 250 P a or less, more preferably 100 Pa or more and 200 Pa or less, and an electrode provided in the processing chamber is applied with 0.17 W / cm 2 or more and 0.5 W / cm 2 or less, more preferably 0.25 W / cm 2 or more and 0.35 W / cm 2 or less of high-frequency power.

[0250] As the insulating film 36, a film having at least a blocking effect against hydrogen and oxygen is used . More preferably, it has a blocking effect against oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. Typically, a nitride insulating film such as silicon nitride may be formed. Nitro In addition to silicon nitride films, silicon oxynitride films, aluminum nitride films, and aluminum oxynitride films etc. can also be used.

[0251] Further, as a film constituting the insulating film 36, a film having a blocking effect against oxygen, hydrogen, water, etc. is An oxide insulating film may be provided. Examples of such an oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride Examples include yttrium, hafnium oxide, and hafnium oxide-nitride.

[0252] Furthermore, the thickness of the insulating film 36 may be 50 nm or more and 300 nm or less, preferably 100 It is between 200 nm and 300 nm. It has a blocking effect on oxygen, hydrogen, water, etc. By forming the edge film 36, acid can escape from the oxide semiconductor film 31 to the oxide semiconductor film 33 to the outside. It prevents the diffusion of elements and also prevents hydrogen and water from entering the oxide semiconductor film 31 to oxide semiconductor film 33 from the outside. This can prevent intrusion by means of such as [unclear text].

[0253] When forming a silicon nitride film as the insulating film 36 by plasma CVD, the silicon content It is preferable to use sedimentary gases, nitrogen, and ammonia as raw material gases. By using a raw material gas, ammonia dissociates in the plasma, generating active species. The species are silicon and hydrogen bonds in silicon-containing sedimentary gases, and the triple bond of nitrogen. The bond is broken. As a result, the bond between silicon and nitrogen is promoted, and the bond between silicon and hydrogen is also promoted. It is possible to form a dense silicon nitride film with fewer impurities and fewer defects. On the other hand, the raw materials In gases, when the amount of ammonia relative to nitrogen is high, silicon-containing sedimentary gases and nitrogen The decomposition of each element did not proceed properly, leaving silicon and hydrogen bonds intact, resulting in an increase in defects. Furthermore, a rough silicon nitride film is formed. For these reasons, in the source gas, ammonia The nitrogen flow rate ratio to nitrogen is set to 5 to 50, preferably 10 to 50. preferable.

[0254] After forming the insulating film 35, a heat treatment may be performed. The temperature of the heat treatment is typically: 150°C or higher but below the substrate strain point, preferably 200°C or higher and 450°C or lower, more preferably 3 The temperature shall be between 00°C and 450°C. This heat treatment shall cause the acid constituting the second layer of the insulating film 35 to Oxygen contained in the oxide insulating film is moved to the oxide semiconductor film 31 or oxide semiconductor film 33. This can reduce the oxygen deficiency contained in these materials. Heat treatment can be performed, for example, with nitrogen and acid The heating should be done in a mixed gas atmosphere containing the element, at a temperature of 350°C for 1 hour.

[0255] Furthermore, after forming the insulating film 36, hydrogen etc. is released from the oxide semiconductor film 31 to the oxide semiconductor film 33. Heat treatment may be performed for the purpose of releasing nitrogen. This heat treatment may involve, for example, nitrogen The heating should be done in a mixed gas atmosphere containing oxygen, at a temperature of 350°C for 1 hour.

[0256] [Back to the destination] The back gate electrodes (BGE1, BGE2) are the same as the gate electrodes (GE1, GE2, GE3). It can be formed in such a way.

[0257] The following are some other examples of transistor configurations.

[0258] (Transistors TA3, TA4) Figures 29(A) and 29(B) show transistors TA3 and TA4, respectively. The top view (layout diagram) and its circuit symbol are shown. Figures 30(A) and 30(B) show the transistors. Cross-sectional view of transistor TA3 along lines a7-a8 and b7-b8, and transistor T A cross-sectional view is shown along lines a9-a10 and b9-b10 on A4 paper.

[0259] Transistor TA3 consists of gate electrode GE4, oxide semiconductor film OS4, source electrode SE4, It has a drain electrode DE4 and a back gate electrode BGE4. Transistor TA3 is This is a modified version of transistor TA1, where electrode BGE4 is located at two apertures CG4 and CG5. However, it differs from transistor TA1 in that it is in contact with electrode GE4, and otherwise it is the same as transistor TA This is the same as in 1. As shown in Figure 30(B), in the channel width direction, the membrane OS4 is connected to the electrode GE4 It is surrounded by electrode BGE4, which can further improve the strength of transistor TA3. ru.

[0260] Transistor TA4 consists of gate electrode GE5, oxide semiconductor film OS5, source electrode SE5, It has a drain electrode DE5 and a back gate electrode BGE5. Transistor TA4 is This is a modified version of transistor TA2, where electrode BGE5 is not connected to electrode GE5, and electrode BG E5 allows different signals or potentials to be input to electrode GE5. For example, when a transistor is input to electrode GE5... A signal is input to control the conduction state of transistor TA4, and electrode BGE5 is connected to transistor TA4. It is possible to input signals or potentials that correct the threshold voltage.

[0261] (Transistors TC1, TB2, TD1) Figures 31(A), 31(B), and 31(C) show transistor TC1 and transistor TC1, respectively. A top view (layout diagram) of transistor TB2 and transistor TD1, and their circuit symbols. Figures 32(A) and 32(B) show the a11-a12 line and b of transistor TC1. Cross-sectional view using line 11b12, lines a13-a14 and b13-b1 of transistor TB2 Cross-sectional view using 4 lines, and lines a15-a16 and b15-b16 of transistor TD1. A cross-sectional view is shown using lines.

[0262] Transistor TC1 consists of gate electrode GE6, oxide semiconductor film OS6, source electrode SE6, It has a drain electrode DE6 and a back gate electrode BGE6. Electrode BGE6 has an aperture C At G6, it is in contact with electrode GE6. Transistor TC1 is a change of transistor TA1. This is an example, where the OS6 membrane has a two-layer structure. The OS6 membrane consists of '32' and '33'. Similar to transistor TA1, transistor TC1 also has a channel formation region of '32'. It is a transistor that is made up of transistor TC1 and transistor TA1. These are transistors with similarly high field-effect mobility, typically those with a field-effect mobility of 10c. m 2 / Larger than Vs, 60cm 2 / Vs less than, preferably 15cm 2 / Vs or more 50cm 2 It is a transistor with a voltage of less than / Vs. Therefore, transistor TC1 and transistor TA1 Similarly, it is suitable for transistors that operate at high speeds, such as in drive circuits.

[0263] Transistor TB2 consists of a gate electrode GE7, an oxide semiconductor film OS7, and a source electrode SE7. It has a drain electrode DE7 and a back gate electrode BGE7. Electrode BGE7 has an aperture C At G7, it is in contact with electrode GE7. Transistor TB2 is a change of transistor TB1. This is an example and differs from transistor TB2 in that it has electrode BGE7. Since 2 has electrode BGE7 connected to electrode GE7, it is more efficient than transistor TB1. It also has a high on-current and improved mechanical strength.

[0264] Transistor TD1 consists of gate electrode GE8, oxide semiconductor film OS8, source electrode SE8, and has a drain electrode DE8. Transistor TD1 is a variation of transistor TB1. This is an example where the entire film OS8 overlaps the electrode GE8, and the part outside the edge of electrode GE8 It does not have a fraction. Thus, transistor TD1 has film OS8 and transistor TB1 Because it has a structure that is less exposed to light than other structures, it is suitable for transistors in the pixel section.

[0265] The film constituting transistors TA1, TA2, and TB1 (Insulating films, oxide semiconductor films, metal oxide films, conductive films, etc.) are produced by sputtering and chemical vapor deposition. Formed using CVD (Chemical Vapor Deposition), vacuum deposition, or pulsed laser deposition (PLD). This can be done. Alternatively, it can be formed by coating or printing methods. As for film formation methods, spa While the tarring method and plasma chemical vapor deposition (PECVD) are typical methods, thermal CVD is also used. This is also good. Examples of thermal CVD methods include MOCVD (organometallic chemical deposition) and ALD (atomic layer deposition). A membrane method may also be used.

[0266] Thermal CVD is a method in which the chamber is subjected to atmospheric pressure or reduced pressure, and the raw material gas and oxidizer are simultaneously processed. The film is formed by sending the material into a chamber, reacting it near or on the substrate, and depositing it onto the substrate. Thus, since thermal CVD is a film deposition method that does not generate plasma, It has the advantage of not generating defects through damage.

[0267] Furthermore, the ALD method involves maintaining atmospheric pressure or reduced pressure inside the chamber, and sequentially supplying the raw material gases for the reaction. Next, the gas is introduced into the chamber, and the film deposition process is carried out by repeating this gas introduction sequence. For example, Switching between each switching valve (also called a high-speed valve) allows for the use of two or more raw materials. The gases are supplied to the chamber in sequence, and the first raw material gas and the other gases are supplied in order to prevent the mixing of multiple raw material gases. Simultaneously or afterward, an inert gas (such as argon or nitrogen) is introduced to the second raw material. Introducing the gas. Note that if an inert gas is introduced simultaneously, the inert gas will be used as a carrier gas. Furthermore, an inert gas may be introduced simultaneously when introducing the second raw material gas. Instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation, and then the second A raw material gas may be introduced. The first raw material gas is adsorbed onto the surface of the substrate to form a first single atomic layer. The first single layer forms a film and reacts with a second source gas introduced later, forming a second single layer on top of the first single layer. A thin film is formed by stacking layers.

[0268] By controlling the gas introduction sequence and repeating this process multiple times until the desired thickness is achieved, the step-level coverage can be improved. A thin film with excellent properties can be formed. The thickness of the thin film depends on the number of times the gas introduction sequence is repeated. Because it can be adjusted, precise film thickness control is possible, and miniature transistors can be created. It is suitable for manufacturing.

[0269] <Example 3 of a specific pixel configuration>

[0270] Figure 17 shows an example of the specific configuration of pixel 10 shown in Figure 1. Pixel shown in Figure 17 Pixel 10 is located in a different position from the pixel 10 shown in Figure 4(A), and transistor 19t is located in a different position. Specifically, In pixel 10 shown in Figure 17, transistor 19t is connected to wiring VL, and transistor 11 is connected to the saw The other side of the source and drain, and the connection between the source and drain of transistor 16t. In terms of the connection between the elements, its configuration differs from that of pixel 10 shown in Figure 4(A).

[0271] Figure 18 shows an example of the specific configuration of pixel 10 shown in Figure 1. Pixel shown in Figure 18 In Figure 15(A), the position of pixel 10 is different from that of transistor 19t. Specifically In the pixel 10 shown in Figure 18, transistor 19t is connected to wiring VL, and transistor 11 is connected to the socket. Between the other side of the source and drain of transistor 16t, and between the source and drain of transistor 16t In terms of the points of connection, its configuration differs from that of pixel 10 shown in Figure 15(A).

[0272] Furthermore, in the pixel 10 of the light-emitting device according to one aspect of the present invention, transistors other than transistor 11 The zistor only needs to have a gate on at least one side of the semiconductor film, but the semiconductor film It may also have another gate that overlaps with the gate in question. If a transistor other than ZISTA11 has a pair of gates, then one of the pair of gates If we use a back gate, then the same potential is applied to the normal gate and the back gate. It's fine if it's present, or if only the back gate is supplied with a fixed potential such as ground potential. The threshold voltage of the transistor is controlled by controlling the height of the potential applied to the back gate. This is possible. In addition, by providing a back gate, the channel formation area increases, and drain This allows for an increase in current. Furthermore, by providing a back gate, air bubbles can be created in the semiconductor film. This makes it easier for a thin layer to form, thus improving the S value.

[0273] <Transistor Configuration Example 2> The transistor used in the light-emitting device according to one aspect of the present invention is amorphous, microcrystalline, or polycrystalline. Alternatively, a single crystal semiconductor film or semiconductor substrate such as silicon or germanium, It may also have a channel formation region. In addition, the thin film was fabricated using a vapor phase growth method such as plasma CVD or a sputtering method. Amorphous silicon, and amorphous silicon, are crystallized by processes such as laser annealing. Polycrystalline silicon and single-crystal silicon wafers are subjected to hydrogen ions and other substances to exfoliate the surface layer. Crystalline silicon and other materials can be used.

[0274] Figure 34 shows a thin silicon film that can be used in a light-emitting device according to one aspect of the present invention. An example of a cross-sectional view of the transistor used is shown. Figure 34 shows an n-channel type transistor 70 This shows a p-channel type transistor 71.

[0275] The transistor 70 has a conductive film 73 that functions as a gate on a substrate 72 having an insulating surface. The insulating film 74 on the conductive film 73 and the semiconductor superimposed on the conductive film 73 with the insulating film 74 in between. A film 75, an insulating film 76 on the semiconductor film 75, and superimposed on the semiconductor film 75 with the insulating film 76 in between. Furthermore, conductive films 77a and 77b function as gates, and conductive films 77a and insulating film 78 on conductive film 77b, insulating film 79 on insulating film 78, insulating film 78 and insulating film 7 An opening in 9 is electrically connected to the semiconductor film 75, and is also a source or It has conductive films 80 and 81 that function as drains.

[0276] The conductive film 77b has a shorter width in the channel length direction than the conductive film 77a, and the conductive film 77a and The conductive film 77b is stacked sequentially from the insulating film 76 side. The semiconductor film 75 is conductive A channel-forming region 82 is placed in a position where it overlaps with the membrane 77b, and another channel-forming region 82 is placed in between. A pair of LDD (Light Doped Drain) regions 83 located in the U, and channel It has a pair of impurity regions 84 positioned between the pulp-forming region 82 and the LDD region 83. The pair of impurity regions 84 function as either a source region or a drain region. Also, L The DD region 83 and the impurity region 84 are impurity sources that impart an n-type conductivity to the semiconductor film 75. Elements such as boron (B), aluminum (Al), and gallium (Ga) are added. ru.

[0277] Furthermore, the transistor 71 is a conductive material that functions as a gate on a substrate 72 having an insulating surface. A film 85, an insulating film 74 on the conductive film 85, and a film superimposed on the conductive film 85 with the insulating film 74 in between. A semiconductor film 86, an insulating film 76 on the semiconductor film 86, and the semiconductor film 86 with the insulating film 76 in between. Conductive films 87a and 87b superimpose on each other and also function as gates, and conductive film 87 a and insulating film 78 on conductive film 87b, insulating film 79 on insulating film 78, insulating film 78 and insulating film 78 An opening in the edge film 79 is electrically connected to the semiconductor film 86, and also a source Alternatively, it has conductive films 88 and 89 that function as drains.

[0278] The conductive film 87b has a shorter width in the channel length direction than the conductive film 87a, and the conductive film 87a and The conductive film 87b is stacked sequentially from the insulating film 76 side. The semiconductor film 75 is conductive A channel-forming region 90 is placed in a position where it overlaps with membrane 87b, and another channel-forming region 90 is placed in between. It has a pair of impurity regions 91 located in the source region. This region functions as a drain region. In addition, the impurity region 91 controls the p-type conductivity of the semiconductor film 86. Impurity elements, such as phosphorus (P) and arsenic (As), are added to the material.

[0279] Furthermore, the semiconductor film 75 or the semiconductor film 86 may be crystallized by various techniques. Crystallization methods include laser crystallization using laser light and crystallization using catalytic elements. Alternatively, a combination of crystallization methods using catalytic elements and laser crystallization methods can also be used. It can be done. Also, when using a substrate with excellent heat resistance such as quartz as the substrate 72, an electric furnace Thermal crystallization method using infrared light, lamp annealing crystallization method using catalytic elements, A crystallization method combining crystallization with high-temperature annealing at around 950°C may also be used.

[0280] <Method for fabricating a light-emitting device 1> Next, Figures 19 and 20 show a method for manufacturing a light-emitting device 400 according to one aspect of the present invention. We will explain using this method.

[0281] First, an insulating film 420 is formed on the substrate 462, and a first element layer 410 is formed on the insulating film 420. This is achieved (see Figure 19(A)). A semiconductor element is provided in the first element layer 410. Alternatively, the first element layer 410 may include, in addition to semiconductor elements, display elements or pixel electrodes, etc. It is acceptable for some of the display elements to be provided.

[0282] The substrate 462 must have at least enough heat resistance to withstand subsequent heat treatment. There are. For example, glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., substrate 4 It may also be used as 62.

[0283] When a glass substrate is used for substrate 462, a silica oxide film is placed between substrate 462 and insulating film 420. When insulating films such as silicon oxide film, silicon nitride film, silicon nitride film, and silicon nitride film are formed, This is preferable because it prevents contamination from the substrate.

[0284] The insulating film 420 can be, for example, epoxy resin, aramid resin, acrylic resin, or polyimide resin. Organic resin films such as lipids, polyamide resins, and polyamide-imide resins can be used. Polyimide resin is preferable because it has high heat resistance. For example, as the insulating film 420, When using polyimide resin, the film thickness of the polyimide resin is preferably 3 nm to 20 μm. The thickness is between 500 nm and 2 μm. Polyimide resin is used as the insulating film 420. In such cases, the surface is formed using methods such as spin coating, dip coating, or doctor blade coating. This is possible. For example, when using polyimide resin as the insulating film 420, doctor blade By removing a portion of the film made of the polyimide resin according to the law, a film with the desired thickness can be obtained. An insulating film 420 can be obtained.

[0285] Furthermore, the temperature during the manufacturing process of the first element layer 410 is between room temperature and 300°C. This is preferable. For example, the first element layer 410 may contain an insulating film or conductive film made of an inorganic material. The film is formed at a temperature of 150°C to 300°C, and even more specifically, at 200°C to 270°C. It is preferable that this is done. Furthermore, the first element layer 410 contains an organic resin material. Insulating films and the like are preferably formed at a film deposition temperature of room temperature or higher and 100°C or lower.

[0286] Furthermore, the oxide semiconductor film of the transistor included in the first element layer 410 contains the aforementioned CA It is preferable to use AC-OS. CAAC-OS is used for the oxide semiconductor film of the transistor. Using S, for example, when bending the light-emitting device 400, cracks will form in the channel-forming region. This makes it difficult for imperfections to enter, and improves resistance to bending.

[0287] Furthermore, the conductive film included in the first element layer 410 is indium with silicon oxide added. When tin oxide is used, cracks may form in the conductive film when the light-emitting device 400 is bent. This is preferable because it makes it more difficult.

[0288] Next, the first element layer 410 and the temporary support substrate 466 are bonded together using a release adhesive 464. Then, the insulating film 420 and the first element layer 410 are peeled off from the substrate 462. Layers 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see Figure 19(B)). .

[0289] The temporary support substrate 466 can be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, A metal substrate or the like can be used. Furthermore, the heat resistance that can withstand the processing temperature of this embodiment is A plastic substrate may be used, or a flexible substrate such as a film may be used. .

[0290] The release adhesive 464 can be soluble in water or solvents, or it can be plasticized by irradiation with ultraviolet light or the like. It is possible to do so by separating the temporary support substrate 466 and the element layer 410 when necessary. Use an adhesive that can be separated scientifically or physically.

[0291] Furthermore, various methods can be used as appropriate for the transfer process to the temporary support substrate 466. , the side of the substrate 462 where the insulating film 420 is not formed, i.e., the lower side shown in Figure 19(B) By irradiating the insulating film 420 with laser light 468, the insulating film 420 is weakened. This allows the substrate 462 and the insulating film 420 to be separated. Also, irradiation with the laser light 468 By adjusting the energy density, regions with high adhesion between the substrate 462 and the insulating film 420, and the base Alternatively, areas with low adhesion between the plate 462 and the insulating film 420 may be created before peeling.

[0292] In this embodiment, the method for peeling at the interface between the substrate 462 and the insulating film 420 is described below. The examples given are not limited to these. For example, the boundary between the insulating film 420 and the first element layer 410. It may be peeled off in a surface area.

[0293] Furthermore, the liquid is permeated into the interface between the substrate 462 and the insulating film 420, allowing the insulating film 42 to penetrate from the substrate 462. Layer 0 may be peeled off. Alternatively, a liquid may be permeated into the interface between the insulating film 420 and the first element layer 410. The first element layer 410 may be peeled off from the insulating film 420. The above liquid may be, for example, Alternatively, water, polar solvents, etc., can be used. The interface that peels off the insulating film 420, specifically the base A liquid is injected into the interface between plate 462 and insulating film 420 or the interface between insulating film 420 and first element layer 410. By allowing the body to penetrate, electrostatic discharge is generated on the first element layer 410 due to delamination. It can suppress the influence of energy and other factors.

[0294] Next, the first substrate 401 is bonded to the insulating film 420 using the adhesive layer 418 (Figure 19( See C).

[0295] Next, the release adhesive 464 is dissolved or plasticized to remove the release adhesive from the first element layer 410. Remove the adhesive 464 and the temporary support substrate 466 (see Figure 19(D)).

[0296] Furthermore, the surface of the first element layer 410 is exposed by applying the release adhesive 464 with water or a solvent. It is preferable to remove it.

[0297] As a result, the first element layer 410 can be fabricated on the first substrate 401.

[0298] Next, the second substrate 4 is formed using the same formation method as shown in Figures 19(A) to 19(D). 05, the adhesive layer 412 on the second substrate 405, the insulating film 440 on the adhesive layer 412, and the second The element layer 411 and are formed (see Figure 20(A)).

[0299] The insulating film 440 of the second element layer 411 is made of the same material as the insulating film 420, where It can be formed using organic resin.

[0300] Next, a sealing layer 432 is filled between the first element layer 410 and the second element layer 411, and the first The element layer 410 and the second element layer 411 are bonded together (see Figure 20(B)).

[0301] The sealing layer 432 allows for, for example, solid sealing. However, the sealing layer 432 is Therefore, a flexible configuration is preferred. As the sealing layer 432, for example, glass frit Glass materials such as glass, two-component resins that harden at room temperature, and photocurable resins. Resin materials such as thermosetting resins can be used.

[0302] Based on the above, the light-emitting device 400 can be manufactured.

[0303] <Method for fabricating a light-emitting device 2> Next, another method for manufacturing a light-emitting device 400 according to one aspect of the present invention will be described using Figure 21. Let me explain. Note that in Figure 21, inorganic insulating films are used as insulating film 420 and insulating film 440. Let me explain the configuration.

[0304] First, a release layer 463 is formed on the substrate 462. Next, an insulating film 420 is applied to the release layer 463. The first element layer 410 is formed on the insulating film 420 (see Figure 21(A)).

[0305] Examples of materials for the release layer 463 include tungsten, molybdenum, titanium, tantalum, and niobium. Nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, os An element selected from iridium, iridium, and silicon, an alloy material containing the element, or the element Compound materials containing elements can be used, and single-layer or laminated structures can be employed. In the case of a layer containing silicon, the crystal structure of the silicon-containing layer may be amorphous, microcrystalline, or polycrystalline. Either crystal or single crystal is acceptable.

[0306] The release layer 463 can be formed by sputtering, PECVD, coating, printing, or the like. The coating method includes spin coating, droplet dispensing, and dispensing.

[0307] If the release layer 463 has a single-layer structure, it may contain tungsten, molybdenum, or tungsten and molybdenum. It is preferable to form a layer containing a butene mixture. Alternatively, tungsten oxide or This is a layer containing oxidized nitride, a layer containing molybdenum oxide or oxidized nitride, or tang A layer containing an oxide or oxidized nitride of a mixture of stainless steel and molybdenum may be formed. Oh, a mixture of tungsten and molybdenum is, for example, an alloy of tungsten and molybdenum. It corresponds to this.

[0308] Furthermore, the release layer 463 is the sum of a layer containing tungsten and a layer containing tungsten oxide. When forming a layered structure, a layer containing tungsten is formed, and an oxide layer is formed on top of it. By forming an insulating layer, tungsten oxide is formed at the interface between the tungsten layer and the insulating layer. The formation of a tungsten-containing layer may also be utilized. Alternatively, the surface of the tungsten-containing layer may be treated with hot acid. Oxidizing treatments such as chemical treatment, oxygen plasma treatment, nitrous oxide (N2O) plasma treatment, and ozonated water A layer containing tungsten oxide may be formed by treatment with a strong solution. Zuma treatment and heat treatment are performed using oxygen, nitrogen, nitrous oxide alone, or a combination of these gases and other gases. This may be carried out in a mixed gas atmosphere. By the above plasma treatment or heat treatment, the peeled layer 463 By changing the surface state, the adhesion between the release layer 463 and the insulating film 420 that is formed later is improved. It is possible to control it.

[0309] The insulating film 420 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxide nitride film, or a silicon oxide nitride film. Low-permeability inorganic insulating films such as ricon film and aluminum oxide film can be used. The inorganic insulating film can be formed, for example, using sputtering, PECVD, etc. Cut.

[0310] Next, the first element layer 410 and the temporary support substrate 466 are bonded together using a release adhesive 464. Then, the insulating film 420 and the first element layer 410 are peeled off from the peeling layer 463. The film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see Figure 21(B)). ).

[0311] Furthermore, various methods can be used as appropriate for the transfer process to the temporary support substrate 466. If a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal By weakening the oxide film through crystallization, the insulating film 420 can be peeled off from the peeling layer 463. Furthermore, if the release layer 463 is formed with a tungsten film, ammonia water and hydrogen peroxide are used. The tungsten film may be removed while etching it with a water-based solution.

[0312] Furthermore, by permeating the interface between the release layer 463 and the insulating film 420 with liquid, the insulating film is released from the release layer 463. 420 may be peeled off. As the above liquid, for example, water, a polar solvent, etc. can be used. It can be done. At the interface where the insulating film 420 is peeled off, specifically at the interface between the peeling layer 463 and the insulating film 420. By permeating the liquid, static electricity generated during peeling is applied to the first element layer 410. It can suppress the effects of electricity, etc.

[0313] Next, the first substrate 401 is bonded to the insulating film 420 using the adhesive layer 418 (Figure 21(C)). reference).

[0314] Next, the release adhesive 464 is dissolved or plasticized to remove the release adhesive from the first element layer 410. Remove the adhesive 464 and the temporary support substrate 466 (see Figure 21(D)).

[0315] Furthermore, the surface of the first element layer 410 is exposed by applying the release adhesive 464 with water or a solvent. It is preferable to remove it.

[0316] As a result, the first element layer 410 can be fabricated on the first substrate 401.

[0317] Next, the second substrate 4 is formed using the same formation method as shown in Figures 21(A) to 21(D). 05, the adhesive layer 412 on the second substrate 405, the insulating film 440 on the adhesive layer 412, and the second The element layer 411 and the second element layer 411 are formed. Then between the first element layer 410 and the second element layer 411 A sealing layer 432 is filled into the first element layer 410 and the second element layer 411 are bonded together. ru.

[0318] Finally, attach the anisotropic conductive film 380 and FPC408 to the connecting electrode 360. IC chips or similar components may be mounted on the device.

[0319] Based on the above, the light-emitting device 400 can be manufactured.

[0320] <Cross-sectional structure of a light-emitting device> Figure 22 shows, as an example, the cross-sectional structure of the pixel portion of a light-emitting device according to one aspect of the present invention. In Figure 22, the pixel 10 shown in Figure 3(A) has a transistor 11, a capacitive element 18, The cross-sectional structure of the light-emitting element 14 is also illustrated.

[0321] Specifically, the light-emitting device shown in Figure 22 has a transistor 11 and a capacitive element 18 on a substrate 500. The transistor 11 has a conductive film 501 that functions as the first gate, and a conductive film An insulating film 502 on 501 and a semiconductor film superimposed on the conductive film 501 with the insulating film 502 in between. 503 and a guide that functions as a source or drain electrically connected to the semiconductor film 503. The dielectric film 504 and the conductive film 505, and the insulating film on the semiconductor film 503, conductive film 504 and conductive film 505 The edge film 550 and the conductive film 501 are superimposed with the insulating film 550 in between, and the second gate is formed It has a conductive film 551 that can perform certain functions.

[0322] The capacitive element 18 has a conductive film 501 that functions as an electrode, and an insulating film 502 on the conductive film 501. The conductive film overlaps with the conductive film 501 with an insulating film 502 in between, and also functions as an electrode. It has 504.

[0323] Insulating film 502 includes aluminum oxide, magnesium oxide, silicon oxide, and silicon oxide nitride. Silicon nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, oxide Zirconium, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide (one of these) The insulating film, including the above, may be used as a single layer or in a laminated configuration. In this specification, Oxiditrides refer to materials whose composition contains more oxygen than nitrogen, and nitride oxides. This refers to a material whose composition contains more nitrogen than oxygen.

[0324] Furthermore, an insulating film 511 is provided on the semiconductor film 503, the conductive film 504, and the conductive film 505. When an oxide semiconductor is used as the semiconductor film 503, the insulating film 511 is the semiconductor film 5 It is desirable to use a material that can supply oxygen to O3. The above material is used as an insulating film 5 By using it in 11, the oxygen contained in the insulating film 511 can be moved to the semiconductor film 503. This is possible, and the amount of oxygen vacancy in the semiconductor film 503 can be reduced. The insulating film 511 contains The transfer of oxygen to the semiconductor film 503 occurs after the insulating film 511 is formed by performing a heat treatment. This can be done efficiently.

[0325] An insulating film 520 is provided on the insulating film 511, and a conductive film 524 is provided on the insulating film 520. It is provided. The conductive film 524 is provided in the openings provided in the insulating film 511 and the insulating film 520. It is connected to the conductive film 504.

[0326] An insulating film 525 is provided on the insulating film 520 and the conductive film 524. The insulating film 525 is It has an opening in a position that overlaps with the conductive film 524. Also, on the insulating film 525, the insulating film 5 An insulating film 526 is provided at a different location from the 25 openings. And insulating film 525 And on the insulating film 526, the EL layer 527 and the conductive film 528 are arranged to be stacked in order. The conductive film 524 and conductive film 528 overlap with the EL layer 527 in between. However, it functions as a light-emitting element 14. And, conductive film 524 and conductive film 528, one of which is positive One pole functions as the electrode, and the other functions as the cathode.

[0327] Furthermore, the light-emitting device has a substrate 530 facing the substrate 500 with the light-emitting element 14 in between. On the substrate 530, that is, on the surface of the substrate 530 that is close to the light-emitting element 14, light is shielded. A shielding film 531 is provided which has the function of shielding the light-emitting element 1. It has an opening in the region that overlaps with 4. In the opening that overlaps with the light-emitting element 14, the substrate 53 A colored layer 532 that transmits visible light in a specific wavelength range is provided on the 0.

[0328] <Exterior view of the light-emitting device> Figure 23(A) is a perspective view showing an example of the external appearance of a light-emitting device according to one aspect of the present invention. The light-emitting device shown in 23(A) consists of a panel 1601, a controller, a power supply circuit, and an image processing circuit. It has a circuit board 1602 on which a path, image memory, CPU, etc. are provided, and a connection part 1603. Panel 1601 has a pixel section 1604 with multiple pixels, and a section that moves the multiple pixels. The drive circuit 1605 selects and controls the input of the image signal Sig to the pixels in the selected row. It has a drive circuit 1606 that controls it.

[0329] From the circuit board 1602, various signals and the power supply potential are transmitted via the connection part 1603 to the panel. Input is sent to 1601. Connection part 1603 is FPC (Flexible Printer). d Circuits, etc., can be used. A chip mounted on an FPC is called a CO It is called F tape, and using COF tape allows for higher density mounting in a smaller area. This is possible. Also, when COF tape is used in the connection part 1603, the circuit board 1602 Some circuits, or parts of drive circuits 1605 and 1606 of panel 1601 These are formed on a separately prepared chip, and the COF (Chip On Film) method is used. The chip can also be connected to the COF tape.

[0330] Figure 23(B) shows a perspective view illustrating an example of the appearance of a light-emitting device using COF tape 1607. This will be shown.

[0331] Chip 1608 is a semiconductor bare chip (IC, LSI) with terminals such as bumps on its surface. Furthermore, CR components can also be mounted on the COF tape 1607, and the circuit board 1602 Area reduction is also possible. The wiring pattern on the flexible circuit board corresponds to the terminals of the chip to be mounted. Multiple chips are formed. The chip 1608 has a wiring pattern, formed by a bonder device or the like. It is mounted by positioning and placing it on a flexible substrate and then heat-pressing it.

[0332] Figure 23(B) shows an example of a COF tape 1607 with one chip 1608 mounted on it. However, it is not limited to the above. Multiple rows of chips on one or both sides of a single COF tape 1607 It is possible to implement the chip, but in order to reduce costs, the number of chips to be implemented will be reduced. It is preferable to arrange them in a single row, and more preferably to arrange them individually.

[0333] <Example of circuit board configuration> Figure 25 shows an external view of circuit board 2003. Circuit board 2003 has a slit 2211. Bluetooth (registered trademark, IEEE 802.15.1) is available on the FPC2201. Same as above.) Communication device 2101, microcontroller 2102, storage device 2103, FPGA2 104, DA converter 2105, charge control IC 2106, and level shifter 2107 are provided. The circuit board 2003 has the following configuration. Furthermore, the present invention is connected via the input / output connector 2108. It is electrically connected to a light-emitting device according to one embodiment. Also, the FPC2201 has a slit 2211 By providing this feature, the flexibility of the circuit board 2003 using FPC2201 is increased.

[0334] By using a flexible substrate in a light-emitting device according to one aspect of the present invention, the circuit board 200 Along with 3, the light-emitting device can also be bent. Therefore, light emission using a flexible substrate The device and the circuit board 2003 can be repeatedly deformed to match the shape of the mounting site. Therefore, it is suitable for use in electronic devices that can be worn on the body, such as on the arms or legs.

[0335] <Example of information processing device configuration> Figure 26(A) is a schematic diagram illustrating the external appearance of an information processing device 1000 according to one embodiment of the present invention. Figure 26(B) illustrates the cross-sectional structure along the cutting line X1-X2 shown in Figure 26(A). This is a view. Also, Figures 26(C) and 26(D) show an information processing device 1 according to one embodiment of the present invention. Figure 26(E) is a schematic diagram illustrating the appearance of 000, and Figures 26(C) and 26(D) are schematic diagrams illustrating the appearance of 000. Figure 26(C) is a cross-sectional view illustrating the structure of the cross-section at the cutting line X3-X4 shown in the diagram. This is a schematic diagram illustrating the front view of the information processing device 1000. Figure 26(D) shows the information processing device 10 This is a schematic diagram illustrating the back of 00.

[0336] As shown in Figures 26(C) and 26(D), the position input unit 1001 or the display unit 1002 Furthermore, it may be provided not only on the front of the information processing device 1000, but also on the sides and back. The position input unit 1001 or the display unit 1002 is provided on the upper surface of the information processing device 1000. It may also be the position input unit 1001 or the display unit 1002. It may be located at the base of 0.

[0337] In addition to the position input section 1001, the surface of the housing 1003 also has hardware buttons and external connections. It may have connecting terminals, etc.

[0338] This configuration allows for a configuration parallel to the front of the housing 1003, unlike conventional information processing devices. In addition to displaying on the surface, it is also possible to display on the side of the casing 1003. Furthermore, by providing display areas along two or more sides of the housing 1003, the diversity of the display is increased. Therefore, it is preferable.

[0339] Display area positioned along the front of the information processing device, and each display area positioned along the side These may be used as independent display areas to display different images, etc., or any two of them may be used A single image or the like may be displayed across multiple display areas. For example, the correct display of an information processing device. Images to be displayed in display areas arranged along the surface are provided along the side of the information processing device. They may be displayed continuously in a display area or similar.

[0340] Furthermore, the arithmetic unit 1005 is located inside the housing 1003. In Figure 26(B), The arithmetic unit 1005 is located at a distance from the display unit 1002. In Figure 26(E) The arithmetic unit 1005 is positioned to overlap with the display unit 1002.

[0341] The position input unit 1001 includes, for example, a first region 1001(1) and a first region 100 A second region 1001(2) opposite to 1(1), and the first region 1001(1) and the second Fold so that a third region 1001(3) is formed between region 1001(2). It has the flexibility to do so (see Figure 26(B)). Another example is the first region Region 1001(1), the third region 1001(3), and the region opposite the third region 1001(3) A fourth region 1001(4) and a flexible material that can be bent so as to form (See Figure 26(E)).

[0342] Another example is the third region 1001(3), the fifth region 1001(5), and the A fourth region 1001(4) opposite region 3 1001(3) is formed by folding. It may also have flexibility that allows it to be bent.

[0343] The arrangement of the second region 1001(2) opposite the first region 1001(1) is as follows: The arrangement is not limited to one directly facing region 1001(1), but also includes arrangements with an inclination toward the first region 1001(1). This also includes arrangements where they face each other. Furthermore, the fourth territory opposite the third territory 1001(3) The arrangement of region 1001(4) is not limited to an arrangement that directly faces the third region 1001(3), but also the third This also includes arrangements that face each other with an inclination in region 1001(3).

[0344] The display unit 1002 comprises at least a first region 1001(1), a second region 1001(2), It is positioned to overlap with a portion of the third region 1001(3) or the fourth region 1001(4). It will be done.

[0345] The information processing device 1000 has a flexible position input unit 100 that detects objects that are nearby or in contact with it. It is composed of including 1. And the position input unit 1001 is, for example, the first region 1001 ( 1) and a second region 1001(2) opposite the first region, and the first region 1001(1) and a third region 1001(3) overlapping with the display unit 1002 between the second region 1001(2) ) and can be bent so that a shape is formed. This allows for, for example, the palm or hand Either of the fingers is in either the first region 1001(1) or the second region 1001(2), etc. It is possible to determine how close it is. As a result, a human interface with excellent operability We can provide chairs. Or, we can provide a novel information processing device with excellent operability.

[0346] A resin with a thickness sufficient to be flexible can be used as the substrate for the display unit 1002. Examples of resins include polyester, polyolefin, polyamide, polyimide, and Examples include lamidopolymers, epoxy resins, polycarbonates, or acrylic resins. In addition, typical substrates that do not have flexibility include glass substrates, quartz substrates, and semiconductor substrates. You can use [this].

[0347] <Examples of electronic device configurations> A light-emitting device according to one aspect of the present invention is a display device, a notebook personal computer, and a recording medium Image playback device equipped with a body (typically DVD: Digital Versatile DVD) (Used in a device that plays back recording media such as ISC and has a display capable of displaying the images.) In addition, electronic devices that can use the light-emitting device according to one aspect of the present invention As devices, mobile phones, portable game consoles, personal digital assistants, e-books, video cameras, digital cameras Cameras such as rustil cameras, goggle-type displays (head-mounted displays) Navigation systems, sound playback devices (car audio, digital audio players) (e.g., photocopiers, fax machines, printers, multifunction printers, ATMs) Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 24. .

[0348] Figure 24(A) shows a display device, which includes a housing 5001, a display unit 5002, a support base 5003, etc. The light-emitting device according to one aspect of the present invention can be used in the display unit 5002. Display devices include all types of information, such as those for personal computers, TV broadcast reception, and advertising displays. It includes a display device for information display.

[0349] Figure 24(B) shows a portable information terminal, consisting of a housing 5101, a display unit 5102, and operation keys 5103. The present invention has the following features. A light-emitting device according to one aspect of the present invention can be used in the display unit 5102.

[0350] Figure 24(C) shows a display device, which has a curved housing 5701, a display unit 5702, etc. By using a flexible substrate in a light-emitting device according to one aspect of the present invention, a curved housing can be used. The light-emitting device can be used in the display unit 5702 supported by the body 5701, and flex We can provide a lightweight, user-friendly display device.

[0351] Figure 24(D) shows a portable game console, consisting of a casing 5301, casing 5302, display unit 5303, Display unit 5304, microphone 5305, speaker 5306, operation keys 5307, stand It has illustration 5308, etc. A light-emitting device according to one aspect of the present invention has a display unit 5303 or a display unit 5303 or It can be used in the display unit 5304. The present invention can be used in the display unit 5303 or the display unit 5304. By using the light-emitting device described in this embodiment, the user experience is superior and quality degradation is less likely to occur. A portable game console can be provided. Note that the portable game console shown in Figure 24(D) is... It has two display units 5303 and 5304, but a portable game console has The number of display units is not limited to this.

[0352] Figure 24(E) is an e-book, which has a housing 5601, a display unit 5602, etc. One of the present inventions The light-emitting device according to the embodiment can be used in the display unit 5602. And it has flexibility By using a substrate, the light-emitting device can be made flexible, and We can provide lightweight and user-friendly ebooks.

[0353] Figure 24(F) shows a mobile phone, with a housing 5901 containing a display unit 5902, a microphone 5907, and a microphone. The speaker 5904, camera 5903, external connection unit 5906, and operation buttons 5905 are provided. It is provided. A light-emitting device according to one aspect of the present invention can be used in the display unit 5902. Furthermore, when a light-emitting device according to one aspect of the present invention is formed on a flexible substrate, Figure 24( The light-emitting device can be applied to a display unit 5902 having a curved surface as shown in F). ru.

[0354] <Examples> This embodiment describes a display device fabricated using the pixels shown in the above embodiment. .

[0355] First, the characteristics of the transistors used in the pixels were measured. The transistors used in the pixels are CA The OS transistor is formed using an AC-OS film, and the CAAC-OS film is made of In-Ga -Formed using Zn oxide.

[0356] FIG. 42(A) shows the measurement results of the I-V characteristics of an OS transistor. Here, the source- drain voltage (Vds) is set to 0.1 V and 10 V, and the measurement results are shown herein. Note that the channel length L of the OS transistor is 6 μm, and the channel width W is 6 μm . In addition, the OS transistor is provided with a back gate, and the voltage between the back gate and the source (Vbgs) is 0 V when the measurement is performed.

[0357] The measurement is performed at 20 points on the same substrate. The OS transistor obtained by the measurement has a median threshold voltage of 4.38 V, and the variation in threshold voltage is 3σ=0.88 V .

[0358] Note that providing a back gate reduces the DIBL (Drain Induced Ba rrier Lowering) effect. In a single gate structure that does not use a back gate structure, the channel length modulation coefficient is approximately 0.05 V -1 , whereas when a back gate is used, the channel length modulation coefficient is approximately 0.009 V -1 , which indicates improved saturation characteristics.

[0359] Next, the measurement results of the Vbgs dependency of the threshold voltage Vth of an OS transistor are shown in FIG. 42(B) below. FIG. 42(B) is obtained by, with the source potential of the OS transistor fixed, varying Vbgs to measure the I-V characteristics, then calculating the threshold voltage from the measurement results and plotting the same in a grap h. Note that FIG. 42(B) shows the measurement results when Vds=10 V.

[0360] It can be seen that when Vbgs changes to the positive side, the threshold voltage shifts to the negative side, and when Vbgs changes to the negative side, the threshold voltage shifts to the positive side. Furthermore, Vth is V It can be seen that it is shifted linearly with respect to BGS. Note that the amount of the threshold voltage shift is... It also depends on the thickness of the interlayer film between the flannel section and the back gate section, and the dielectric constant of the interlayer film. The thicker the film thickness and the lower the dielectric constant, the smaller the influence of Vbgs on the threshold voltage. Yes.

[0361] The pixels were constructed using the OS transistors described above. Figure 43(A) shows the circuit configuration of the pixels. This is shown. Note that the pixels shown in Figure 43(A) correspond to pixels 10 shown in Figures 3(B) and 4(B). Then, the pixels shown in Figure 43(A) are processed according to the timing chart shown in Figure 43(B). The threshold voltage was corrected by driving it in this way. The threshold voltage correction operation was performed as described above. The description of the form can be taken into consideration. In addition, during period I, G3 was high level. Tr4 is in the ON state, and the source potential of the drive transistor DrTr is CATHODE The threshold Vth of the OLED is at this position. OLED The resulting potential is the sum of these two factors.

[0362] Table 1 shows the specifications of the display device fabricated using the above pixels. The resolution of the display device is 302. The ppi was 61%, and the aperture ratio was 61%. The scan driver was also embedded on the glass. The source driver uses COF.

[0363] [Table 1]

[0364] The display device is a top-emission type using white EL elements and color filters (CF). The structure of the display device is shown in Figure 44(A).

[0365] Furthermore, the white EL element had a stacked structure as shown in Figure 44(B). The white EL element is blue A light-emitting unit using colored fluorescent materials and a light-emitting unit using green and red phosphorescent materials are connected in series. A tandem element structure with two connected layers was adopted.

[0366] Figure 45 shows a photograph of the display of the actual manufactured display device. The photograph shows no display inconsistencies, It appears to be displaying correctly.

[0367] Figure 46 shows the results when the threshold voltage of the drive transistor DrTr shown in Figure 43(A) is changed. The calculation results are shown. Here, ΔVth, which is the horizontal axis of the graph, represents the Vth after the threshold voltage correction. This represents the amount of shift. Also, the vertical axis of the graph, Vgs-Vth, corresponds to period IV in Figure 43(B). From the Vgs of the drive transistor DrTr during the light emission period, the drive transistor after threshold voltage correction... This is the value obtained by subtracting the threshold voltage of the transistor DrTr. If the threshold voltage correction is performed correctly... Therefore, since the Vgs-Vth value does not depend on the threshold voltage, the slope of the graph is 0.

[0368] From the calculation results shown in Figure 46, Vgs when ΔVth is in the range of -1.5V to +1.5V The variation in the value of -Vth is kept to about 10% of the value of Vgs-Vth at ΔVth=0. It can be seen that it is being obtained.

[0369] In addition, in the pixel shown in Figure 43(A), the threshold of the OLED is set to Vth OLED Therefore, If the threshold voltage Vth of the dynamic transistor DrTr is a positive value, then Vth = 0 to V0 -(Cathode+Vth OLED Corrects up to the range where the potential is shifted to the positive side by the amount of ) It is possible, and if the threshold voltage of the drive transistor DrTr is a negative value, Vt The threshold voltage range from h=0 to the negative side by the potential of Anode-V0. This can correct for variations in the threshold voltage of the drive transistor DrTr. If the value falls within the positive range, the V0 power supply can be used as the Anode. In this case, the number of power lines V0 within a pixel can be reduced by one.

[0370] As described above, by using the present invention, the threshold voltage is corrected and display unevenness is reduced. The device can be manufactured. [Explanation of Symbols]

[0371] 10 pixels 11 transistors 12 switches 12t transistor 13 Capacitive elements 14 Light-emitting elements 15 switches 15t transistor 16 switches 16t transistor 17 Switches 17t transistor 18 Capacitive elements 19 switches 19t transistor 30 circuit boards 31 Oxide semiconductor film 31-32 Oxide semiconductor film 32 Oxide semiconductor film 33 Oxide semiconductor film 34 Insulating Film 35 Insulating film 35a insulating film 35b insulating film 36 Insulating Film 40-pixel section 41 Selection Circuit 42 Wiring 43 switches 44 switches 45 Monitor Circuit 46 Op-amps 47 Capacitive elements 48 switches 49 Wiring 60A switch 60B switch 60C switch 61 circuits 62A switch 62B switch 62C switch 63A Wiring 63B Wiring 70 transistors 71 transistors 72 circuit boards 73 Conductive film 74 Insulating Film 75 Semiconductor film 76 insulating film 77a Conductive film 77b Conductive film 78 insulating film 79 Insulating film 80 Conductive film 81 Conductive film 82 Channel formation region 83 LDD area 84 Impurity region 85 Conductive film 86 Semiconductor film 87a Conductive film 87b Conductive film 88 Conductive film 89 Conductive film 90 Channel formation region 91 Impurity region 360 connecting electrodes 380 Anisotropic conductive film 400 Light-emitting devices 401 circuit board 405 circuit board 408 FPC 410-element layer 411-element layer 412 Adhesive layer 418 Adhesive layer 420 insulating film 432 Sealing layer 440 insulating film 462 circuit boards 463 Delamination layer 464 Release Adhesive 466 Temporary support board 468 Laser light 500 circuit boards 501 Conductive film 502 Insulating film 503 Semiconductor film 504 Conductive film 505 Conductive film 511 Insulating Film 520 Insulating film 524 Conductive film 525 Insulating film 526 Insulating film 527 EL layer 528 Conductive film 530 circuit boards 531 Shielding membrane 532 Colored layer 550 insulating film 551 Conductive film 802 IEEE 1000 Information Processing Devices 1001 Position input section 1001(1) First Domain 1001(2) Second area 1001(3) Third Domain 1001(4) The fourth area 1002 Display section 1003 Casing 1005 Arithmetic equipment 1601 Panel 1602 Circuit board 1603 Connection part 1604 pixel section 1605 Drive Circuit 1606 Drive Circuit 1607 COF Tape 1608 chips 2003 Circuit board 2101 Communication equipment 2102 Microcontroller 2103 Storage device 2104 FPGA 2105 DA converter 2106 Charging control IC 2107 Level Shifter 2108 Input / Output Connector 2201 FPC 2211 Slit 5001 enclosure 5002 Display section 5003 Support stand 5101 enclosure 5102 Display section 5103 Operation Keys 5301 enclosure 5302 enclosure 5303 Display section 5304 Display section 5305 Microphone 5306 Speaker 5307 Operation Keys 5308 Stylus 5601 enclosure 5602 Display section 5701 enclosure 5702 Display section 5901 enclosure 5902 Display section 5903 Camera 5904 Speaker 5905 Button 5906 External connection section 5907 Mike

Claims

1. A light-emitting device comprising a transistor, a first to fifth switch, a first capacitive element and a second capacitive element, and a light-emitting element, The transistor has a first gate and a second gate having a region that overlaps with the first gate via a semiconductor film of the transistor. The first switch has one terminal electrically connected to the first wiring and the other terminal electrically connected to the first gate of the transistor. The transistor has either its source or drain electrically connected to the second wiring, and the other source or drain electrically connected to one of the terminals of the fifth switch. The second switch has one terminal electrically connected to the first gate of the transistor, and the other terminal electrically connected to one terminal of the fifth switch. The third switch has one terminal electrically connected to the first wiring and the other terminal electrically connected to the second gate of the transistor. The fourth switch has one terminal electrically connected to the third wiring, and the other terminal electrically connected to one terminal of the fifth switch. The first capacitive element has a first electrode electrically connected to the first gate of the transistor, and a second electrode electrically connected to the other of the source or drain of the transistor. The second capacitive element has a first electrode electrically connected to the second gate of the transistor, and a second electrode electrically connected to the other of the source or drain of the transistor. The fifth switch has the other terminal electrically connected to the first electrode of the light-emitting element. The light-emitting element has a second electrode electrically connected to the third wiring. A first period in which the third switch is in the ON state and the fourth switch is in the OFF state, The system includes a second period in which the third switch is in the off state and the fourth switch is in the on state, The first wiring has the function of supplying an image signal, The second wiring has the function of supplying the first potential, The third wiring is a light-emitting device having the function of supplying a second potential.

2. A light-emitting device comprising a transistor, a first to fifth switch, a first capacitive element and a second capacitive element, and a light-emitting element, The transistor has a first gate and a second gate having a region that overlaps with the first gate via a semiconductor film of the transistor. The first switch has one terminal electrically connected to the first wiring and the other terminal electrically connected to the first gate of the transistor. The transistor has either its source or drain electrically connected to the second wiring, and the other source or drain electrically connected to one of the terminals of the fifth switch. The second switch has one terminal electrically connected to the first gate of the transistor, and the other terminal electrically connected to one terminal of the fifth switch. The third switch has one terminal electrically connected to the first wiring and the other terminal electrically connected to the second gate of the transistor. The fourth switch has one terminal electrically connected to the third wiring, and the other terminal electrically connected to one terminal of the fifth switch. The first capacitive element has a first electrode electrically connected to the first gate of the transistor, and a second electrode electrically connected to the other of the source or drain of the transistor. The second capacitive element has a first electrode electrically connected to the second gate of the transistor, and a second electrode electrically connected to the other of the source or drain of the transistor. The fifth switch has the other terminal electrically connected to the first electrode of the light-emitting element. The light-emitting element has a second electrode electrically connected to the third wiring. A first period in which the third switch is in the ON state and the fourth switch is in the OFF state, The system includes a second period in which the third switch is in the off state and the fourth switch is in the on state, The first wiring has the function of supplying an image signal, The second wiring has the function of supplying the first potential, The third wiring has the function of supplying a second potential, The semiconductor film is a light-emitting device having an oxide semiconductor film in a channel-forming region.

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