Indication device

Abstract

The display device may include first, second, and third sub-pixels adjacent to each other, each including a storage capacitor, a scan line extending in a first direction and selectively transmitting a scan signal and a control signal to each of the first, second, and third sub-pixels, a data line extending in the second direction intersecting the first direction and transmitting a data signal to each of the first, second, and third sub-pixels, and a first power line electrically connected to each of the first, second, and third sub-pixels and supplied with a first driving power voltage. The first power line may be located between the storage capacitor and the data line.

Description

Technical Field

[0001] The present invention relates to a display device.

Background Art

[0002] In recent years, as interest in information displays has increased, research and development relating to display devices have been continuously carried out.

Summary of Invention

Problem to be Solved by the Invention

[0003] The present invention can provide a display device with improved reliability.

Means for Solving the Problem

[0004] A display device according to an embodiment comprises: first, second, and third sub-pixels adjacent to each other, each provided with a storage capacitor; a scan wiring that selectively transmits a scan signal and a control signal to each of said first to third sub-pixels, and extends in a first direction; a data wiring that transmits a data signal to each of said first, second, and third sub-pixels, and extends in a second direction intersecting said first direction; and a first power supply wiring electrically connected to each of said first, second, and third sub-pixels, and supplied with a first driving power supply voltage. Said first power supply wiring may be located between said storage capacitor and said data wiring.

[0005] In the embodiment, the display device may further include a substrate; a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially arranged on the substrate; a second power supply wiring supplied with a second driving power supply voltage different from the first driving power supply voltage; and an initialization power supply wiring supplied with an initialization power supply voltage. The first power supply wiring may include a first vertical power supply wiring configured as a first conductive layer arranged on the substrate and a first horizontal power supply wiring configured as a second conductive layer arranged on the second insulating layer. Viewed in plan, the first vertical power supply wiring may be located between the storage capacitors and data wiring of the first, second, and third sub-pixels, respectively.

[0006] In the embodiment, each of the first, second, and third subpixels may include: a light-emitting element; a first transistor for controlling the current of the light-emitting element; a second transistor connected between the data wiring and the gate electrode of the first transistor and turned on by the scan signal; a third transistor connected between the initialization power wiring and the source electrode of the first transistor and turned on by the control signal; and a storage capacitor including a lower electrode electrically connected to the gate electrode of the first transistor and the source electrode of the second transistor, and an upper electrode electrically connected to the source electrode of the first transistor and the source electrode of the third transistor.

[0007] In this embodiment, the first, second, and third transistors can be located on one side of the storage capacitor.

[0008] In the embodiment, the second power supply wiring may include a second vertical power supply wiring configured as the first conductive layer and a second horizontal power supply wiring configured as the second conductive layer. When viewed in a planar view, the storage capacitor may be located between the second vertical power supply wiring and the first vertical power supply wiring.

[0009] In this embodiment, when viewed in plan view, the initialization power supply wiring can be located between the first vertical power supply wiring and the data wiring.

[0010] In the embodiment, the gate electrodes of the first transistors of each of the first, second, and third subpixels may be located between the storage capacitor and the first vertical power supply wiring.

[0011] In this embodiment, the lower electrode is placed on the substrate, and the upper electrode is placed on the first insulating layer and can be superimposed on the lower electrode with the first insulating layer in between.

[0012] In the embodiment, the upper electrode may be placed on the same layer as the active patterns of the first, second, and third transistors, respectively.

[0013] In the embodiment, the upper electrode may be formed integrally with the source electrode of the first transistor and the source electrode of the third transistor.

[0014] In the embodiment, the light-emitting element may include a first electrode configured as a third conductive layer disposed on the fourth insulating layer; a light-emitting layer disposed on the first electrode; and a second electrode disposed on the light-emitting layer.

[0015] In the embodiment, the first electrode may be electrically connected to the source electrode of the first transistor via a contact portion that penetrates the second to fourth insulating layers.

[0016] In this embodiment, when viewed in plan view, the initialization power supply wiring can be located between the second vertical power supply wiring and the storage capacitor.

[0017] In this embodiment, when viewed in a plan view, the initialization power supply wiring can be located on one side of the storage capacitor, and the first vertical power supply wiring can be located on the other side of the storage capacitor.

[0018] In this embodiment, when viewed in a planar view, the third transistor among the first, second, and third transistors may be located on one side of the storage capacitor, and the first and second transistors may be located on the other side of the storage capacitor.

[0019] In the embodiment, each of the first, second, and third subpixels may further include a sealing layer disposed on the light-emitting element; a color filter layer disposed on the sealing layer; and an overcoat layer disposed on the color filter layer.

[0020] The display device according to the embodiment may include: a substrate; first, second, third, and fourth insulating layers sequentially laminated on the substrate; first, second, and third sub-pixels each including a storage capacitor and a pixel circuit including first, second, and third transistors, and a light-emitting element electrically connected to the pixel circuit, respectively; scan wiring disposed on the substrate for selectively transmitting scan signals and control signals to the first, second, and third sub-pixels; data wiring for transmitting data signals to the first, second, and third sub-pixels; a first power supply wiring supplied with a first power supply voltage; a second power supply wiring supplied with a second power supply voltage different from the first power supply voltage; and an initialization power supply wiring supplied with an initialization power supply voltage different from the first and second power supply voltages. The gate electrode of the first transistor may be located between the storage capacitor and the first power supply wiring.

[0021] In the embodiment, the first power wiring may include a first vertical power wiring disposed on the substrate and a first horizontal power wiring disposed on the second insulating layer. The first vertical power wiring may be located between the storage capacitor and the data wiring.

[0022] In this embodiment, the first, second, and third transistors can be located on one side of the storage capacitor when viewed in a planar view.

[0023] In an embodiment, when viewed in a plan view, the storage capacitor may be located between the initialization power supply line and the first vertical power supply line.

Effects of the Invention

[0024] According to an embodiment, the first vertical power supply line is arranged between the storage capacitor of each sub-pixel and the data line, so that the area of the gate electrode of the first transistor (or drive transistor) of each sub-pixel can be reduced, and the area of the storage capacitor can be secured.

[0025] According to an embodiment, a display device with improved reliability can be provided by increasing the capacitance of the storage capacitor of each sub-pixel.

[0026] Effects according to the embodiment are not limited to the contents exemplified above, and various other effects are included in the present specification.

Brief Description of the Drawings

[0027] [Figure 1] FIG. 1 is a schematic plan view showing a display device according to an embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view showing the display panel of FIG. 1. [Figure 3] FIG. 3 is a schematic circuit diagram showing the electrical connection relationship of components included in each of the pixels shown in FIG. 1. [Figure 4] FIG. 4 is a schematic plan view showing a pixel according to an embodiment. [Figure 5] FIG. 5 is a schematic plan view showing a pixel according to an embodiment. [Figure 6] FIG. 6 is a schematic plan view showing only the configuration included in the first conductive layer in the pixel of FIG. 5 [Figure 7] FIG. 7 is a schematic plan view showing only the configuration included in the transistor and the second conductive layer in the pixel of FIG. 5. [Figure 8] FIG. 8 is a schematic cross-sectional view taken along line I-I' of FIG. 5. [Figure 9] FIG. 9 is a schematic cross-sectional view taken along line II-II' of FIG. 5. [Figure 10] This is a schematic cross-sectional view along lines II to II' in Figure 5. [Figure 11] This shows a pixel according to one embodiment, and is a schematic cross-sectional view corresponding to lines I to I' in Figure 5. [Figure 12] This is a schematic plan view showing pixels according to one embodiment. [Figure 13] This is a schematic plan view showing only the components included in the first conductive layer in the pixels of Figure 12. [Figure 14] Figure 12 is a schematic plan view showing only the components included in the transistor and the second conductive layer in the pixel. [Figure 15] This is a schematic cross-sectional view along lines III to III' in Figure 12. [Modes for carrying out the invention]

[0028] While the present invention is subject to numerous modifications and can be implemented in various forms, only specific embodiments are illustrated in the drawings and described based on these embodiments. However, the present invention is not limited to such specific embodiments, and all modifications, equivalents, or substitutions that fall within the technical scope of the present invention should be understood as being included within the present invention.

[0029] In the descriptions of each drawing, similar components are referred to by the same reference numerals. In the attached drawings, the dimensions of the structures are shown enlarged for the purpose of clarifying the invention. Terms such as "first," "second," etc., are used to describe various components, but the components should not be limited by such terms. Such terms are used solely for the purpose of distinguishing one component from another. For example, without going beyond the scope of the rights of this disclosure, the first component may be called the second component, and similarly, the second component may be called the first component.

[0030] In this application, terms such as “includes” or “have” should be understood to indicate the presence of features, numbers, stages, actions, components, parts, or combinations thereof described in the specification, without prejudice to the possibility of the presence or addition of one or more other features, numbers, stages, actions, components, parts, or combinations thereof. Furthermore, when a layer, film, region, plate, etc. is said to be “on” another part, this includes not only when it is “directly on” the other part, but also when other parts are located between them. Also, in this specification, when a layer, film, region, plate, etc. is formed on another part, the direction of formation is not limited to the upward direction, but also includes formation in the side or downward direction. Conversely, when a layer, film, region, plate, etc. is said to be “below” another part, this includes not only when it is “directly below” the other part, but also when other parts are located between them.

[0031] In this application, where it is stated that “a component (e.g., ‘the first component’) is “operally or communicatively coupled with / to” or “connected to” another component (e.g., ‘the second component’), it should be understood that the first component may be directly connected to the other component or connected via another component (e.g., ‘the third component’). On the other hand, where it is stated that a component (e.g., ‘the first component’) is “directly connected” or “directly connected” to another component (e.g., ‘the second component’), it can be understood that there is no other component (e.g., ‘the third component’) between the first component and the other component.

[0032] The following description details preferred embodiments of the present invention and other matters necessary for those skilled in the art to easily understand the invention, with reference to the attached drawings. In the following description, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0033] Figure 1 is a schematic plan view showing a display device DD according to one embodiment, and Figure 2 is a schematic cross-sectional view showing the display panel DP of Figure 1.

[0034] In Figures 1 and 2, for convenience, the structure of the display device DD, particularly the display panel DP provided on the display device DD, is simplified and shown with the display area DA on which the image is displayed as the center.

[0035] Referring to Figures 1 and 2, for convenience, the structure of the display device DD, and in particular the display panel DP provided on the display device DD, is simplified and shown with respect to the display area DA where the image is displayed.

[0036] Referring to Figures 1 and 2, the display panel DP (or display device DD) according to the embodiment can be provided in various shapes. For example, the display panel DP may be provided in the form of a rectangular plate having two pairs of parallel sides. However, it is not limited to this. When the display panel DP is provided in the form of a rectangular plate, one of the two pairs of sides may be longer than the other pair.

[0037] The display panel DP may have flexibility in at least a portion of it, and may be folded in the flexible portion, but is not limited thereto.

[0038] The display panel DP can display images. The display panel DP may be a self-emissive display panel such as an organic light-emitting display panel (OLED panel) using organic light-emitting diodes as light-emitting elements, a micro-LED or nano-LED display panel using micro-LEDs as light-emitting elements, or a quantum dot organic light-emitting display panel (QD OLED panel) using quantum dots and organic light-emitting diodes. Alternatively, the display panel DP may be a non-emissive display panel such as a liquid crystal display panel (LCD panel), an electrophoretic display panel (EPD panel), or an electro-wetting display panel (EWD panel). When a non-emissive display panel is used as the display panel DP, the display device DD may be equipped with a backlight unit to supply light to the display panel DP. In this embodiment, the display panel DP may be an organic light-emitting display panel.

[0039] The display panel DP may include a substrate SUB and pixels PXL provided on the substrate SUB.

[0040] The substrate SUB may, but is not limited to, contain a transparent insulating material that allows light to pass through. The substrate SUB may be a rigid substrate or a flexible substrate.

[0041] The rigid substrate may be, for example, one of the following: a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate.

[0042] The flexible substrate may be one of a film substrate containing a polymeric organic material and a plastic substrate. For example, the flexible substrate may contain at least one of the following: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, or cellulose acetate propionate.

[0043] One area of ​​the substrate SUB may be provided as a display area DA on which pixels PXL are arranged, and the remaining area of ​​the substrate SUB may be provided as a non-display area NDA. For example, the substrate SUB may include a display area DA that includes a pixel area PXA on which each pixel PXL is arranged, and a non-display area NDA that is arranged around (or adjacent to) the display area DA.

[0044] The non-display area (NDA) may be located adjacent to the display area (DA). The non-display area (NDA) may be provided on at least one side of the display area (DA). For example, the non-display area (NDA) may surround (or border) the display area (DA). The non-display area (NDA) may be provided with wiring connected to each pixel PXL and drive units connected to the wiring for driving the pixel PXL.

[0045] Each pixel PXL may be provided within the display area DA of the substrate SUB. A pixel PXL may include a light-emitting element that emits white and / or color light and a pixel circuit for driving the light-emitting element. The pixel circuit may include at least one transistor electrically connected to the light-emitting element. Each pixel PXL may emit light of one of the following colors: red, green, and blue. Each pixel PXL may emit light of one of the following colors: cyan, magenta, yellow, and white.

[0046] Multiple pixel PXLs may be provided and arranged in a matrix configuration along a pixel row extending in a first direction DR1 and a pixel column extending in a second direction DR2 intersecting the first direction DR1. The arrangement configuration of the pixel PXLs is not particularly limited, and the pixel PXLs may be arranged in various configurations. According to the embodiment, when multiple pixel PXLs are provided, they may be provided to have different areas (or sizes) from each other. For example, in the case of pixel PXLs that emit light of different colors, each color pixel PXL may be provided with a different area (or size) or a different shape.

[0047] The drive unit can control the driving of each pixel PXL by providing a predetermined signal and a predetermined voltage to each pixel PXL via the wiring unit.

[0048] Each display panel DP (or pixel PXL) may include a pixel circuit layer PCL, a display element layer DPL, and a encapsulation layer TFE, all located on a substrate SUB.

[0049] The pixel circuit layer (PCL) is provided on a substrate (SUB) and may include transistors and signal wiring connected to the transistors. For example, the transistor may be configured such that an active pattern (or semiconductor pattern), a gate electrode, a source electrode, and a drain electrode are stacked in sequence with an insulating layer in between. The semiconductor pattern may include amorphous silicon, polysilicon, low-temperature polysilicon, organic semiconductors, and / or oxide semiconductors. The gate electrode, source electrode, and drain electrode may include, but are not limited to, one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo). For example, the pixel circuit layer (PCL) may include at least one insulating layer.

[0050] A display element layer (DPL) may be arranged on the pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements. The light-emitting elements may be, for example, organic light-emitting diodes, but are not limited thereto. According to the embodiment, the light-emitting elements may be inorganic light-emitting elements containing inorganic light-emitting materials or light-emitting elements that emit light by changing the wavelength of emitted light using quantum dots.

[0051] A sealing layer TFE may be placed on the display element layer DPL. The sealing layer TFE may be a sealing substrate or a sealing film consisting of multiple layers. If the sealing layer TFE is in the form of a sealing film, it may include an inorganic film and / or an organic film. For example, the sealing layer TFE may be in the form of an inorganic film, an organic film, and an inorganic film stacked in sequence. The sealing layer TFE can prevent external air and moisture from penetrating the display element layer DPL and the pixel circuit layer PCL.

[0052] Figure 3 is a schematic circuit diagram showing the electrical connection relationships of the components included in each of the pixel PXLs shown in Figure 1.

[0053] In Figure 3, for convenience, the pixel PXL located at the i-th pixel row (or the i-th horizontal line) and the j-th pixel column is shown (where i and j are natural numbers).

[0054] Referring to Figures 1 to 3, a pixel PXL may include an EMU (Emitting Mass Unit) that generates light with a brightness corresponding to the data signal. For example, a pixel PXL may further include a pixel circuit PXC (Picture Circuit) for driving the EMU.

[0055] The light-emitting unit EMU may include a light-emitting element LD connected between a first power supply wiring PL1 supplied with a first drive power supply voltage VDD and a second power supply wiring PL2 supplied with a second drive power supply voltage VSS. As an example, the light-emitting unit EMU may include a light-emitting element LD that includes a first electrode AE ​​connected to the first drive power supply voltage VDD via the pixel circuit PXC and the first power supply wiring PL1, and a second electrode CE connected to the second drive power supply voltage VSS via the second power supply wiring PL2. The first electrode AE ​​may be an anode, and the second electrode CE may be a cathode. The first drive power supply voltage VDD and the second drive power supply voltage VSS may have different potentials. In this case, the potential difference between the first and second drive power supply voltages VDD and VSS may be set to be greater than or equal to the threshold voltage of the light-emitting element LD during the light-emitting period of the pixel PXL.

[0056] If a pixel PXL (or subpixel) is located in the i-th pixel row and j-th pixel column in the display area DA, the pixel circuit PXC of the pixel PXL (or subpixel) may be electrically connected to the i-th scan line Si and the j-th data line Dj. The pixel circuit PXC may also be electrically connected to the i-th control line CLi and the j-th sensing line SENj.

[0057] The aforementioned pixel circuit PXC may include first to third transistors T1, T2, and T3 and a storage capacitor Cst.

[0058] The first transistor T1 is a drive transistor for controlling the drive current applied to the light-emitting element LD, and may be electrically connected between the first drive power supply voltage VDD and the light-emitting element LD. Specifically, the first terminal of the first transistor T1 may be electrically connected to the first drive power supply voltage VDD via the first power supply wiring PL1, the second terminal of the first transistor T1 may be electrically connected to the second node N2, and the gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 can control the amount of drive current applied to the light-emitting element LD from the first drive power supply voltage VDD via the second node N2 in accordance with the voltage applied to the first node N1. In this embodiment, the first terminal of the first transistor T1 may be the drain electrode, and the second terminal of the first transistor T1 may be the source electrode, but is not limited thereto. According to this embodiment, the first terminal may be the source electrode, and the second terminal may be the drain electrode.

[0059] The second transistor T2 may be electrically connected between the data trace Dj (for example, the j-th data trace) and the first node N1 as a switching transistor that selects and activates the pixel PXL in response to the scan signal. The first terminal of the second transistor T2 may be electrically connected to the data trace Dj, the second terminal of the second transistor T2 may be electrically connected to the first node N1 (or the gate electrode of the first transistor T1), and the gate electrode of the second transistor T2 may be electrically connected to the scan trace Si (or the i-th scan trace). The first and second terminals of the second transistor T2 may be different terminals; for example, the first terminal may be the drain electrode and the second terminal may be the source electrode.

[0060] Such a second transistor T2 is turned on when a scan signal of gate-on voltage (for example, a high-level voltage) is supplied from the scan trace Si, and can electrically connect the data trace Dj and the first node N1. The first node N1 is the point where the second terminal of the second transistor T2 is connected to the gate electrode of the first transistor T1, and the second transistor T2 can transmit a data signal to the gate electrode of the first transistor T1.

[0061] The third transistor T3 can acquire a sensing signal via the sensing line SENj (for example, the j-th sensing line) by electrically connecting the first transistor T1 to the sensing line SENj, and use the sensing signal to detect the characteristics of the pixel PXL, including the threshold voltage of the first transistor T1. Information regarding the characteristics of the pixel PXL may be used to transform the video data so that characteristic deviations between pixels PXL can be compensated for. The second terminal of the third transistor T3 can be electrically connected to the second terminal of the first transistor T1, the first terminal of the third transistor T3 can be electrically connected to the sensing line SENj, and the gate electrode of the third transistor T3 may be electrically connected to a control line CLi (for example, the i-th control line). The first terminal may be a drain electrode, and the second terminal may be a source electrode.

[0062] The third transistor T3 is an initialization transistor that can initialize the second node N2, and can be turned on when a sensing control signal is supplied from the control line CLi to transmit the initialization power supply voltage to the second node N2. As a result, the storage capacitor Cst electrically connected to the second node N2 may be initialized.

[0063] A storage capacitor Cst may include a lower electrode LE (or first storage electrode) and an upper electrode UE (or second storage electrode). The lower electrode LE may be electrically connected to a first node N1, and the upper electrode UE may be electrically connected to a second node N2. Such a storage capacitor Cst charges a data voltage corresponding to the data signal supplied to the first node N1 for one frame period. This allows the storage capacitor Cst to store a voltage corresponding to the difference between the voltage at the gate electrode of the first transistor T1 and the voltage at the second node N2.

[0064] Figure 3 shows an embodiment in which all of the first to third transistors T1, T2, and T3 are N-type transistors, but the invention is not limited to this. For example, at least one of the first to third transistors T1, T2, and T3 described above may be replaced with a P-type transistor.

[0065] The structure of the pixel circuit PXC can be modified in various ways.

[0066] In the following examples, for the sake of explanation, the lateral direction (X-axis direction or horizontal direction) on a plane is indicated by the first direction DR1, the vertical direction (Y-axis direction or perpendicular direction) on a plane is indicated by the second direction DR2, and the vertical direction on a cross-section is indicated by the third direction DR3.

[0067] Figures 4 and 5 are schematic plan views showing a pixel PXL according to one embodiment; Figure 6 is a schematic plan view showing only the components included in the first conductive layer C1 in the pixel PXL of Figure 5; and Figure 7 is a schematic plan view showing only the components included in the transistors T1, T2, T3 and the second conductive layer C2 in the pixel PXL of Figure 5.

[0068] The pixel PXL shown in Figure 5 further shows the first light emission region EMA1 of the first subpixel SPX1, the second light emission region EMA2 of the second subpixel SPX2, and the third light emission region EMA3 of the third subpixel SPX3 in the pixel PXL of Figure 4.

[0069] Referring to Figures 1 to 7, the pixel PXL in the embodiment may be located in a pixel area PXA, which is a region of the display area DA. The pixel area PXA (or display area DA) may include a wiring area LA. For example, the wiring area LA may be located between two pixels PXL arranged adjacent to each other in the same pixel row. In the embodiment, the wiring area LA may be a region where signal wiring extending in the first direction DR1 is located. For example, the wiring area LA may contain, but is not limited to, a first horizontal power wiring PL1b, a scan wiring SC, and a second horizontal power wiring PL2b extending in the first direction DR1 (or horizontal direction).

[0070] A pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 may include a first pixel circuit PXC1 and a first light-emitting element (see “LD1” in Figure 8) driven by the first pixel circuit PXC1. The second sub-pixel SPX2 may include a second pixel circuit PXC2 and a second light-emitting element (see “LD2” in Figure 8) driven by the second pixel circuit PXC2. The third sub-pixel SPX3 may include a third pixel circuit PXC3 and a third light-emitting element (see “LD3” in Figure 8) driven by the third pixel circuit PXC3. Each of the first to third pixel circuits PXC1, PXC2, and PXC3 may be a pixel circuit PXC as described with reference to Figure 3, and each of the first to third light-emitting elements LD1, LD2, and LD3 may be a light-emitting element LD as described with reference to Figure 3.

[0071] The pixel region PXA may include a first light-emitting region EMA1, a second light-emitting region EMA2, and a third light-emitting region EMA3. The pixel region PXA may also include a non-light-emitting region NEA surrounding the first to third light-emitting regions EMA1, EMA2, and EMA3. A pixel definition film (see "PDL" in Figure 8) that defines the first to third light-emitting regions EMA1, EMA2, and EMA3 may be placed in the non-light-emitting region NEA.

[0072] The first light-emitting region EMA1 may be the region from which light is emitted from the first light-emitting element LD1 of the first subpixel SPX1. For example, the first light-emitting region EMA1 may correspond to the region in which the first light-emitting layer EML1 of the first light-emitting element LD1 is located.

[0073] The second light-emitting region EMA2 may be the region from which light is emitted from the second light-emitting element LD2 of the second subpixel SPX2. For example, the second light-emitting region EMA2 may correspond to the region in which the second light-emitting layer EML2 of the second light-emitting element LD2 is located.

[0074] The third light-emitting region EMA3 may be the region from which light is emitted from the third light-emitting element LD3 of the third subpixel SPX3. For example, the third light-emitting region EMA3 can correspond to the region in which the third light-emitting layer EML3 of the third light-emitting element LD3 is located.

[0075] Signal wiring electrically connected to the first to third sub-pixels SPX1, SPX2, and SPX3 may be arranged in the pixel area PXA. For example, scan wiring SC, data wiring D1, D2, and D3, power wiring PL, initialization power wiring IPL, etc., may be arranged in the pixel area PXA, but are not limited to these.

[0076] The scan wiring SC is located in the wiring region LA and may extend in the first direction DR1. The scan wiring SC may selectively supply scan signals and sensing control signals. The scan wiring SC may be configured as a second conductive layer C2. The second conductive layer C2 may be formed as a single or multiple film consisting of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and oxides or alloys thereof.

[0077] The scan wiring SC may include a first sub-scan wiring SSL1 extending in a second direction DR2. The first sub-scan wiring SSL1 may be configured as a second conductive layer C2 and formed integrally with the scan wiring SC. In this case, the first sub-scan wiring SSL1 may be a region of the scan wiring SC.

[0078] The first subscan wiring SSL1 may be formed integrally with the second gate electrode GE2 of the second transistor T2 of the first to third pixel circuits PXC1, PXC2, and PXC3, respectively. For example, a portion of the first subscan wiring SSL1 may be the second gate electrode GE2 of the second transistor T2 of the first to third pixel circuits PXC1, PXC2, and PXC3, respectively.

[0079] For example, the first subscan wiring SSL1 may be formed integrally with the third gate electrode GE3 of the third transistor T3 of the first to third pixel circuits PXC1, PXC2, and PXC3, respectively. As an example, the other part of the first subscan wiring SSL1 may be the third gate electrode GE3 of the third transistor T3 of the first to third pixel circuits PXC1, PXC2, and PXC3, respectively.

[0080] The scan wiring SC can supply a scan signal to the second gate electrode GE2 of the second transistor T2 of each of the first to third pixel circuits PXC1, PXC2, and PXC3 during the drive period of the light-emitting element LD, and supply a sensing control signal to the third gate electrode GE3 of the third transistor T3 of each of the first to third pixel circuits PXC1, PXC2, and PXC3 during the sensing period.

[0081] Data routes D1, D2, and D3 may include a first data route D1, a second data route D2, and a third data route D3 that extend along a second direction DR2 and are arranged in the first direction DR1. Each of the first to third data routes D1, D2, and D3 may be supplied with data signals.

[0082] The first data wiring D1 may be electrically connected to the second transistor T2 of the first pixel circuit PXC1 (or first sub-pixel SPX1), the second data wiring D2 may be electrically connected to the second transistor T2 of the second pixel circuit PXC2 (or second sub-pixel SPX2), and the third data wiring D3 may be electrically connected to the second transistor T2 of the third pixel circuit PXC3 (or third sub-pixel SPX3). Each of the first to third data wirings D1, D2, and D3 may constitute the first conductive layer C1. The first conductive layer C1 may contain the same material as the second conductive layer C2 described above, or may contain one or more suitable (or selected) materials from the materials exemplified as constituent materials of the second conductive layer C2, but is not limited thereto.

[0083] A power supply wiring PL may include a first power supply wiring PL1 and a second power supply wiring PL2.

[0084] The first power supply wiring PL1 may be supplied with the first drive power supply voltage VDD. The first power supply wiring PL1 may include the first vertical power supply wiring PL1a and the first horizontal power supply wiring PL1b.

[0085] The first vertical power wiring PL1a may extend along the second direction DR2 and, when viewed in plane, may be located between the first to third storage capacitors Cst1, Cst2, Cst3 and the data wirings D1, D2, D3. For example, the first vertical power wiring PL1a may be located between the first to third storage capacitors Cst1, Cst2, Cst3 and the initialization power wiring IPL adjacent to the first data wiring D1. The first vertical power wiring PL1a may be configured as the first conductive layer C1. The first vertical power wiring PL1a may be electrically connected to the first horizontal power wiring PL1b located in a different layer via corresponding contact holes.

[0086] The first horizontal power wiring PL1b is located in the wiring area LA and may extend in the first direction DR1. The first horizontal power wiring PL1b may be configured as the second conductive layer C2. The first vertical power wiring PL1a, configured as the first conductive layer C1, and the first horizontal power wiring PL1b, configured as the second conductive layer C2, may be electrically connected to each other via corresponding contact holes. The first power wiring PL1 may have a mesh structure due to the first vertical power wiring PL1a and the first horizontal power wiring PL1b being electrically connected to each other.

[0087] The second power supply wiring PL2 may be supplied with the second drive power supply voltage VSS. The second power supply wiring PL2 may include the second vertical power supply wiring PL2a and the second horizontal power supply wiring PL2b.

[0088] The second vertical power wiring PL2a may extend along the second direction DR2 and, when viewed in plane, may be located on one side (for example, the left side) of the first to third storage capacitors Cst1, Cst2, and Cst3. The second vertical power wiring PL2a may be configured as the first conductive layer C1. The second vertical power wiring PL2a may be electrically connected to an additional conductive pattern ACP located in a different layer via corresponding contact holes.

[0089] The additional conductive pattern ACP is configured as a second conductive layer C2 and can extend in the second direction DR2 so as to overlap with the second vertical power wiring PL2a. The second vertical power wiring PL2a may be electrically connected to the additional conductive pattern ACP located in a different layer via corresponding contact holes to realize a double-layer structure. This can reduce the wiring resistance of the second vertical power wiring PL2a.

[0090] The second horizontal power wiring PL2b is located in the wiring area LA and may extend in the first direction DR1. The second horizontal power wiring PL2b may be configured as the second conductive layer C2. The second vertical power wiring PL2a, configured as the first conductive layer C1, and the second horizontal power wiring PL2b, configured as the second conductive layer C2, may be electrically connected to each other via corresponding contact holes. The second power wiring PL2 may have a mesh structure due to the electrically connected second vertical power wiring PL2a and second horizontal power wiring PL2b.

[0091] The initialization power wiring IPL extends in the second direction DR2 and may be configured as the first conductive layer C1. When viewed in plan, the initialization power wiring IPL may be positioned between the first vertical power wiring PL1a and the data wirings D1, D2, D3. The first vertical power wiring PL1a, the initialization power wiring IPL, and the data wirings D1, D2, D3 may be spaced apart in the first direction DR1. The initialization power wiring IPL may be the sensing line SENj as described with reference to Figure 3. The initialization power wiring IPL may supply an initialization voltage. The initialization power wiring IPL may be electrically connected to the third transistor T3 of each of the first to third pixel circuits PXC1, PXC2, PXC3 (or the first to third sub-pixels SPX1, SPX2, SPX3).

[0092] The first pixel circuit PXC1 of the first sub-pixel SPX1, the second pixel circuit PXC2 of the second sub-pixel SPX2, and the third pixel circuit PXC3 of the third sub-pixel SPX3 can have substantially similar or identical structures. In the following, the first pixel circuit PXC1 will be described in detail, and the descriptions of the second pixel circuit PXC2 and the third pixel circuit PXC3 will be simplified.

[0093] The first pixel circuit PXC1 may include first to third transistors T1, T2, and T3 and a first storage capacitor Cst1.

[0094] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, and a first drain electrode DE1.

[0095] The first gate electrode GE1 may be electrically connected to the second source electrode SE2 of the second transistor T2 via a corresponding contact hole. The first gate electrode GE1 may be configured as the second conductive layer C2. In the embodiment, the first gate electrode GE1 may be electrically connected to the lower metal pattern BML via a corresponding contact hole. In the embodiment, the first gate electrode GE1 may be located between the first storage capacitor Cst1 and the first vertical power supply wiring PL1a.

[0096] The lower metal pattern BML (or first lower metal pattern) is configured as the first conductive layer C1 and can be superimposed on the first transistor T1. The lower metal pattern BML may be electrically connected to the first gate electrode GE1 via corresponding contact holes. By electrically connecting the lower metal pattern BML to the first gate electrode GE1, floating of the lower metal pattern BML is prevented, and the wiring resistance of the first gate electrode GE1 can be reduced.

[0097] The first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be configured as semiconductor patterns made of polysilicon, amorphous silicon, oxide semiconductors, etc. The first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be formed from semiconductor layers that are either undoped with impurities or doped with impurities. For example, the first source electrode SE1 and the first drain electrode DE1 may be doped with impurities to be conductive, while the first active pattern ACT1 may consist of an intrinsic semiconductor layer that is not doped with impurities.

[0098] The first active pattern ACT1 is located below the first gate electrode GE1, which is configured as the second conductive layer C2, and can be superimposed on the first gate electrode GE1. The first active pattern ACT1 can constitute the channel region of the first transistor T1.

[0099] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. The first source electrode SE1 can be doped with impurities in an impurity doping process that is carried out after the formation of the second conductive layer C2 to become conductive. In the embodiment, the first source electrode SE1 may be formed integrally with the third source electrode SE3 of the third transistor T3 and connected to the third source electrode SE3.

[0100] The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1. The first drain electrode DE1 can be made conductive by being doped with impurities in an impurity doping process that is carried out after the formation of the second conductive layer C2. The first drain electrode DE1 may be electrically connected to the first conductive pattern CP1 via a corresponding contact hole.

[0101] The first conductive pattern CP1 is configured as a second conductive layer C2 and can be superimposed on the first drain electrode DE1 and the first vertical power supply wiring PL1a. A portion of the first conductive pattern CP1 may be electrically connected to the first drain electrode DE1 via a corresponding contact hole. Another portion of the first conductive pattern CP1 may be electrically connected to the first vertical power supply wiring PL1a via the same contact hole. The first drain electrode DE1 and the first vertical power supply wiring PL1a may be electrically connected to each other via the first conductive pattern CP1.

[0102] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0103] The second gate electrode GE2 may be formed integrally with the first subscan wiring SSL1 and may be configured as the second conductive layer C2. The second gate electrode GE2 can be superimposed on the second active pattern ACT2.

[0104] The second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be configured as semiconductor patterns made of polysilicon, amorphous silicon, oxide semiconductors, etc. The second source electrode SE2 and the second drain electrode DE2 may be doped with impurities to be conductive, while the second active pattern ACT2 may consist of an intrinsic semiconductor layer that is not doped with impurities.

[0105] The second active pattern ACT2 can be located below the second gate electrode GE2 and superimposed on the second gate electrode GE2. The second active pattern ACT2 can constitute the channel region of the second transistor T2.

[0106] The second source electrode SE2 may be connected to one end of the second active pattern ACT2. The second source electrode SE2 can be made conductive by being doped with impurities in an impurity doping process that is carried out after the formation of the second conductive layer C2. The second source electrode SE2 may be electrically connected to the first gate electrode GE1 via a corresponding contact hole.

[0107] The second drain electrode DE2 may be connected to the other end of the second active pattern ACT2. The second drain electrode DE2 can be doped with impurities in an impurity doping process that is carried out after the formation of the second conductive layer C2 to become conductive. The second drain electrode DE2 may be electrically connected to the second conductive pattern CP2 via a corresponding contact hole.

[0108] The second conductive pattern CP2 is configured as a second conductive layer C2 and can be superimposed on the first data wiring D1 and the second drain electrode DE2. A portion of the second conductive pattern CP2 may be electrically connected to the second drain electrode DE2 via a corresponding contact hole. The other portion of the second conductive pattern CP2 may be electrically connected to the first data wiring D1 via the same contact hole. The second drain electrode DE2 and the first data wiring D1 may be electrically connected via the second conductive pattern CP2.

[0109] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3.

[0110] The third gate electrode GE3 may be configured as the second conductive layer C2 and may be formed integrally with the first subscan wiring SSL1. The third gate electrode GE3 can be superimposed on the third active pattern ACT3.

[0111] The third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be configured as semiconductor patterns made of polysilicon, amorphous silicon, oxide semiconductors, etc. The third source electrode SE3 and the third drain electrode DE3 may be doped with impurities to be conductive, while the third active pattern ACT3 may be configured as an intrinsic semiconductor layer that is not doped with impurities.

[0112] The third active pattern ACT3 can be superimposed on the third gate electrode GE3. The third active pattern ACT3 can constitute the channel region of the third transistor T3.

[0113] The third source electrode SE3 may be connected to one end of the third active pattern ACT3. The third source electrode SE3 can be made conductive by being doped with impurities in an impurity doping process that is carried out after the formation of the second conductive layer C2. The third source electrode SE3 may be formed integrally with the first source electrode SE1 and connected to the first source electrode SE1. By forming the third source electrode SE3 and the first source electrode SE1 integrally, a separate first connecting member for connecting the third source electrode SE3 and the first source electrode SE1 may be omitted.

[0114] The third drain electrode DE3 may be connected to the other end of the third active pattern ACT3. The third drain electrode DE3 can be made conductive by being doped with impurities in an impurity doping process that is carried out after the formation of the second conductive layer C2. The third drain electrode DE3 may be electrically connected to the third conductive pattern CP3 via a corresponding contact hole.

[0115] The third conductive pattern CP3 can be superimposed on the initialization power wiring IPL and the third drain electrode DE3. A portion of the third conductive pattern CP3 may be electrically connected to the third drain electrode DE3 via a corresponding contact hole. Another portion of the third conductive pattern CP3 may be electrically connected to the initialization power wiring IPL via the same contact hole. The third drain electrode DE3 and the initialization power wiring IPL may be electrically connected to each other via the third conductive pattern CP3.

[0116] The first storage capacitor Cst1 may include a first lower electrode LE1 and a first upper electrode UE1. The first storage capacitor Cst1 may be the storage capacitor Cst described with reference to Figure 3.

[0117] The first lower electrode LE1 is configured as the first conductive layer C1 and may be formed integrally with the lower metal pattern BML. The first lower electrode LE1 (or lower metal pattern BML) may be positioned between the second vertical power supply wiring PL2a and the first vertical power supply wiring PL1a when viewed in plan. In the embodiment, the first lower electrode LE1 may be electrically connected to the first gate electrode GE1 and the second source electrode SE2 via corresponding contact holes.

[0118] The first upper electrode UE1 may be formed integrally with the first source electrode SE1 and the third source electrode SE3 and connected to the first source electrode SE1 and the third source electrode SE3. The first upper electrode UE1 is configured as a semiconductor pattern made of polysilicon, amorphous silicon, oxide semiconductor, etc., and can be conductive after being doped with impurities. The first upper electrode UE1 is superimposed on the first lower electrode LE1 and may be similar in size (or area) to the first lower electrode LE1 or larger than the first lower electrode LE1, but is not limited thereto.

[0119] In this embodiment, the first upper electrode UE1 may be positioned so as not to overlap with the first gate electrode GE1. Viewed in a planar plane, the first upper electrode UE1 may be positioned between the second vertical power supply wiring PL2a and the first vertical power supply wiring PL1a.

[0120] In the first pixel circuit PXC1 having the configuration described above, the first source electrode SE1, the third source electrode SE3, and the first upper electrode UE1, which are integrally formed, may be electrically connected to the first-1 electrode AE1 (or first anode) via a contact portion CNT.

[0121] The first electrode AE1 may be configured as a third conductive layer C3. The third conductive layer C3 and the second conductive layer C2 may contain the same material. The third conductive layer C3 may contain, but is not limited to, one or more suitable materials from those exemplified as constituent materials of the second conductive layer C2. The first electrode AE1 can be superimposed on a part of the configuration of the first pixel circuit PXC1, for example, the first transistor T1 and the first storage capacitor Cst1. For example, the first electrode AE1 can be superimposed on a part of the signal wiring electrically connected to the first pixel circuit PXC1. In the embodiment, the first electrode AE1 can be superimposed on a first light-emitting layer EML1 corresponding to a first light-emitting region EMA1. If the first sub-pixel SPX1 is a red pixel, the first light-emitting layer EML1 may, but is not limited to, emit red light.

[0122] The second pixel circuit PXC2 may include the first to third transistors T1, T2, and T3 and the second storage capacitor Cst2.

[0123] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, and a first drain electrode DE1.

[0124] The first gate electrode GE1 may be electrically connected to the second source electrode SE2 of the second transistor T2 via a corresponding contact hole. The first gate electrode GE1 may be configured as a second conductive layer C2 and electrically connected to the lower metal pattern BML (or second lower electrode LE2) via the contact hole. In this embodiment, the first gate electrode GE1 may be located between the second storage capacitor Cst2 and the first vertical power supply wiring PL1a.

[0125] The lower metal pattern BML (or second lower metal pattern) is configured as the first conductive layer C1 and can be superimposed on the first transistor T1. Alternatively, the lower metal pattern BML may be formed integrally with the second lower electrode LE2 of the second storage capacitor Cst2.

[0126] The first active pattern ACT1 can be superimposed on the first gate electrode GE1. The first active pattern ACT1 can constitute the channel region of the first transistor T1.

[0127] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. In this embodiment, the first source electrode SE1 may be formed integrally with the third source electrode SE3 of the third transistor T3 and connected to the third source electrode SE3.

[0128] The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1. The first drain electrode DE1 may also be electrically connected to the fourth conductive pattern CP4 via a corresponding contact hole.

[0129] The fourth conductive pattern CP4 is configured as the second conductive layer C2 and can be superimposed on the first drain electrode DE1 and the first vertical power supply wiring PL1a. A portion of the fourth conductive pattern CP4 may be electrically connected to the first drain electrode DE1 via a corresponding contact hole. Another portion of the fourth conductive pattern CP4 may be electrically connected to the first vertical power supply wiring PL1a via the same contact hole. The first drain electrode DE1 and the first vertical power supply wiring PL1a may be electrically connected to each other via the fourth conductive pattern CP4.

[0130] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0131] The second gate electrode GE2 may be formed integrally with the first subscan wiring SSL1 and constitute the second conductive layer C2.

[0132] The second active pattern ACT2 can constitute the channel region of the second transistor T2.

[0133] The second source electrode SE2 may be connected to one end of the second active pattern ACT2. The second source electrode SE2 may also be electrically connected to the first gate electrode GE1 via a corresponding contact hole.

[0134] The second drain electrode DE2 may be connected to the other end of the second active pattern ACT2. The second drain electrode DE2 may also be electrically connected to the fifth conductive pattern CP5 via a corresponding contact hole.

[0135] The fifth conductive pattern CP5 is configured as the second conductive layer C2 and can be superimposed on the second data wiring D2 and the second drain electrode DE2. A portion of the fifth conductive pattern CP5 may be electrically connected to the second drain electrode DE2 via a corresponding contact hole. Another portion of the fifth conductive pattern CP5 may be electrically connected to the second data wiring D2 via the same contact hole. The second drain electrode DE2 and the second data wiring D2 may be electrically connected via the fifth conductive pattern CP5.

[0136] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3.

[0137] The third gate electrode GE3 may be configured as the second conductive layer C2 and may be formed integrally with the first subscan wiring SSL1.

[0138] The third active pattern ACT3 can constitute the channel region of the third transistor T3.

[0139] The third source electrode SE3 may be connected to one end of the third active pattern ACT3. The third source electrode SE3 may be formed integrally with the first source electrode SE1 and connected to the first source electrode SE1. By forming the third source electrode SE3 and the first source electrode SE1 integrally, another second connecting member for connecting the third source electrode SE3 and the first source electrode SE1 may be omitted.

[0140] The third drain electrode DE3 may be connected to the other end of the third active pattern ACT3. The third drain electrode DE3 may also be electrically connected to the sixth conductive pattern CP6 via a corresponding contact hole.

[0141] The sixth conductive pattern CP6 is configured as the second conductive layer C2 and can be superimposed on the third drain electrode DE3 and the initialization power wiring IPL. A portion of the sixth conductive pattern CP6 may be electrically connected to the third drain electrode DE3 via a corresponding contact hole. Another portion of the sixth conductive pattern CP6 may be electrically connected to the initialization power wiring IPL via the same contact hole. The third drain electrode DE3 and the initialization power wiring IPL may be electrically connected to each other via the sixth conductive pattern CP6.

[0142] The second storage capacitor Cst2 may include a second lower electrode LE2 and a second upper electrode UE2. The second storage capacitor Cst2 may be the storage capacitor Cst described with reference to Figure 3.

[0143] The second lower electrode LE2 may be configured as the first conductive layer C1 and may be formed integrally with the lower metal pattern BML. The second lower electrode LE2 (or lower metal pattern BML) may be positioned between the second vertical power wiring PL2a and the first vertical power wiring PL1a when viewed in plan. In the embodiment, the second lower electrode LE2 may be electrically connected to the first gate electrode GE1 and the second source electrode SE2 via corresponding contact holes.

[0144] The second upper electrode UE2 may be formed integrally with the first source electrode SE1 and the third source electrode SE3 and connected to the first source electrode SE1 and the third source electrode SE3. The second upper electrode UE2 may superimpose on the second lower electrode LE2 and may be similar in size (or area) to the second lower electrode LE2 or larger than the second lower electrode LE2, but is not limited thereto.

[0145] In this embodiment, the second upper electrode UE2 may be positioned so as not to overlap with the first gate electrode GE1. Viewed in a planar plane, the second upper electrode UE2 may be positioned between the second vertical power supply wiring PL2a and the first vertical power supply wiring PL1a.

[0146] In the second pixel circuit PXC2 having the configuration described above, the first source electrode SE1, the third source electrode SE3, and the second upper electrode UE2, which are integrally formed, may be electrically connected to the first-to-second electrode AE2 (or second anode) via a contact portion CNT.

[0147] The first-to-second electrode AE2 may be configured as a third conductive layer C3. The first-to-second electrode AE2 can be superimposed on a part of the configuration of the second pixel circuit PXC2, for example, the first transistor T1 and the second storage capacitor Cst2. For example, the first-to-second electrode AE2 can be superimposed on a part of the signal wiring electrically connected to the second pixel circuit PXC2. In this embodiment, the first-to-second electrode AE2 can be superimposed on the second light-emitting layer EML2 corresponding to the second light-emitting region EMA2. If the second sub-pixel SPX2 is a green pixel, the second light-emitting layer EML2 can emit green light, but is not limited to this.

[0148] The third sub-pixel PXC3 may include the first to third transistors T1, T2, and T3 and the third storage capacitor Cst3.

[0149] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, and a first drain electrode DE1.

[0150] The first gate electrode GE1 may be electrically connected to the second source electrode SE2 of the second transistor T2 via a corresponding contact hole. The first gate electrode GE1 may be configured as a second conductive layer C2 and electrically connected to the lower metal pattern BML (or third lower electrode LE3) via the contact hole. In this embodiment, the first gate electrode GE1 may be located between the third storage capacitor Cst3 and the first vertical power supply wiring PL1a.

[0151] The lower metal pattern BML (or third lower metal pattern) is configured as the first conductive layer C1 and can be superimposed on the first transistor T1. For example, the lower metal pattern BML may be formed integrally with the third lower electrode LE3 of the third storage capacitor Cst3.

[0152] The first active pattern ACT1 can be superimposed on the first gate electrode GE1. The first active pattern ACT1 can constitute the channel region of the first transistor T1.

[0153] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. In this embodiment, the first source electrode SE1 may be formed integrally with the third source electrode SE3 of the third transistor T3 and connected to the third source electrode SE3.

[0154] The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1. The first drain electrode DE1 may also be electrically connected to the seventh conductive pattern CP7 via a corresponding contact hole.

[0155] The seventh conductive pattern CP7 is configured as the second conductive layer C2 and can be superimposed on the first drain electrode DE1 and the first vertical power supply wiring PL1a. A portion of the seventh conductive pattern CP7 may be electrically connected to the first drain electrode DE1 via a corresponding contact hole. Another portion of the seventh conductive pattern CP7 may be electrically connected to the first vertical power supply wiring PL1a via the same contact hole. The first drain electrode DE1 and the first vertical power supply wiring PL1a may be electrically connected to each other via the seventh conductive pattern CP7.

[0156] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0157] The second gate electrode GE2 may be formed integrally with the first subscan wiring SSL1 and constitute the second conductive layer C2.

[0158] The second active pattern ACT2 can constitute the channel region of the second transistor T2.

[0159] The second source electrode SE2 may be connected to one end of the second active pattern ACT2. The second source electrode SE2 may also be electrically connected to the first gate electrode GE1 via a corresponding contact hole.

[0160] The second drain electrode DE2 may be connected to the other end of the second active pattern ACT2. The second drain electrode DE2 may also be electrically connected to the eighth conductive pattern CP8 via a corresponding contact hole.

[0161] The eighth conductive pattern CP8 is configured as the second conductive layer C2 and can be superimposed on the third data wiring D3 and the second drain electrode DE2. A portion of the eighth conductive pattern CP8 may be electrically connected to the second drain electrode DE2 via a corresponding contact hole. Another portion of the eighth conductive pattern CP8 may be electrically connected to the third data wiring D3 via the same contact hole. The second drain electrode DE2 and the third data wiring D3 may be electrically connected via the eighth conductive pattern CP8.

[0162] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3.

[0163] The third gate electrode GE3 may be configured as the second conductive layer C2 and may be formed integrally with the first subscan wiring SSL1.

[0164] The third active pattern ACT3 can constitute the channel region of the third transistor T3.

[0165] The third source electrode SE3 may be connected to one end of the third active pattern ACT3. The third source electrode SE3 may be formed integrally with the first source electrode SE1 and connected to the first source electrode SE1. By forming the third source electrode SE3 and the first source electrode SE1 integrally, another third connecting member for connecting the third source electrode SE3 and the first source electrode SE1 may be omitted.

[0166] The third drain electrode DE3 may be connected to the other end of the third active pattern ACT3. The third drain electrode DE3 may also be electrically connected to the ninth conductive pattern CP9 via a corresponding contact hole.

[0167] The ninth conductive pattern CP9 is configured as the second conductive layer C2 and can be superimposed on the third drain electrode DE3 and the initialization power wiring IPL. A portion of the ninth conductive pattern CP9 may be electrically connected to the third drain electrode DE3 via a corresponding contact hole. Another portion of the ninth conductive pattern CP9 may be electrically connected to the initialization power wiring IPL via the same contact hole. The third drain electrode DE3 and the initialization power wiring IPL may be electrically connected to each other via the ninth conductive pattern CP9.

[0168] The third storage capacitor Cst3 may include a third lower electrode LE3 and a third upper electrode UE3. The third storage capacitor Cst3 may be the storage capacitor Cst described with reference to Figure 3.

[0169] The third lower electrode LE3 may be configured as the first conductive layer C1 and may be formed integrally with the lower metal pattern BML. The third lower electrode LE3 (or lower metal pattern BML) may be positioned between the second vertical power supply wiring PL2a and the first vertical power supply wiring PL1a when viewed in plan. In the embodiment, the third lower electrode LE3 may be electrically connected to the first gate electrode GE1 and the second source electrode SE2 via corresponding contact holes.

[0170] The third upper electrode UE3 may be formed integrally with the first source electrode SE1 and the third source electrode SE3 and connected to the first source electrode SE1 and the third source electrode SE3. The third upper electrode UE3 may superimpose on the third lower electrode LE3 and may be similar in size (or area) to the third lower electrode LE3 or larger than the third lower electrode LE3, but is not limited thereto.

[0171] In this embodiment, the third upper electrode UE3 may be positioned so as not to overlap with the first gate electrode GE1. Viewed in a planar plane, the third upper electrode UE3 may be positioned between the second vertical power supply wiring PL2a and the first vertical power supply wiring PL1a.

[0172] In the third pixel circuit PXC3 having the configuration described above, the first source electrode SE1, the third source electrode SE3, and the third upper electrode UE3, which are integrally formed, may be electrically connected to the first-to-third electrodes AE3 (or third anode) via the contact portion CNT.

[0173] The first-to-third electrodes AE3 may be configured as a third conductive layer C3. The first-to-third electrodes AE3 can be superimposed on a part of the configuration of the third pixel circuit PXC3, for example, the first transistor T1 and the third storage capacitor Cst3. For example, the first-to-third electrodes AE3 can be superimposed on a part of the signal wiring electrically connected to the third pixel circuit PXC3. In this embodiment, the first-to-third electrodes AE3 can be superimposed on a third light-emitting layer EML3 corresponding to a third light-emitting region EMA3. If the third sub-pixel SPX3 is a blue pixel, the third light-emitting layer EML3 can emit blue light, but is not limited to this.

[0174] In the embodiment described above, the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 can be arranged along the second direction DR2 and positioned on the same line. In the pixel region PXA, the first to third storage capacitors Cst1, Cst2, and Cst3 can be positioned between the second vertical power supply wiring PL2a and the first vertical power supply wiring PL1a. For example, the second vertical power supply wiring PL2a can be located on one side (for example, the left side) of the first to third storage capacitors Cst1, Cst2, and Cst3 in the pixel region PXA, and the first vertical power supply wiring PL1a can be located on the other side (for example, the right side) of the first to third storage capacitors Cst1, Cst2, and Cst3 in the pixel region PXA.

[0175] If the first vertical power supply wiring PL1a is located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, then the first transistor T1 of each of the first to third pixel circuits PXC1, PXC2, and PXC3, which are electrically connected to the first vertical power supply wiring PL1a, can be located to the right of the storage capacitor of the corresponding pixel circuit. For example, the first transistor T1 of the first pixel circuit PXC1 can be located between the right side of the first storage capacitor Cst1 and the first vertical power supply wiring PL1a, the first transistor T1 of the second pixel circuit PXC2 can be located between the right side of the second storage capacitor Cst2 and the first vertical power supply wiring PL1a, and the first transistor T1 of the third pixel circuit PXC3 can be located between the right side of the third storage capacitor Cst3 and the first vertical power supply wiring PL1a. In this case, the first gate electrode GE1 of the first transistor T1 of the first pixel circuit PXC1 is located between the right side of the first storage capacitor Cst1 and the first vertical power supply wiring PL1a, the first gate electrode GE1 of the first transistor T1 of the second pixel circuit PXC2 is located between the right side of the second storage capacitor Cst2 and the first vertical power supply wiring PL1a, and the first gate electrode GE1 of the first transistor T1 of the third pixel circuit PXC3 is located between the right side of the third storage capacitor Cst3 and the first vertical power supply wiring PL1a.

[0176] For example, in the embodiment described above, the initialization power wiring IPL and the first to third data wirings D1, D2, D3, which are electrically connected to the first to third pixel circuits PXC1, PXC2, PXC3, may be located to the right of the first to third storage capacitors Cst1, Cst2, Cst3, and spaced apart from the first vertical power wiring PL1a. In the pixel region PXA, the second vertical power wiring PL2a, the first to third storage capacitors Cst1, Cst2, Cst3, the first vertical power wiring PL1a, the initialization power wiring IPL, the first data wiring D1, the second data wiring D2, and the third data wiring D3 may be arranged in that order along the first direction DR1.

[0177] If the initialization power wiring IPL is located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the third transistor T3 of each of the first to third pixel circuits PXC1, PXC2, and PXC3, which are electrically connected to the initialization power wiring IPL, may be located to the right of the storage capacitor of the corresponding pixel circuit. For example, the third transistor T3 of the first pixel circuit PXC1 can be located between the right side of the first storage capacitor Cst1 and the initialization power wiring IPL, the third transistor T3 of the second pixel circuit PXC2 can be located between the right side of the second storage capacitor Cst2 and the initialization power wiring IPL, and the third transistor T3 of the third pixel circuit PXC3 can be located between the right side of the third storage capacitor Cst3 and the initialization power wiring IPL.

[0178] If the first data wiring D1 is located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the second transistor T2 of the first pixel circuit PXC1, which is electrically connected to the first data wiring D1, may be located to the right of the first storage capacitor Cst1. If the second data wiring D2 is located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the second transistor T2 of the second pixel circuit PXC2, which is electrically connected to the second data wiring D2, may be located to the right of the second storage capacitor Cst2. If the third data wiring D3 is located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the second transistor T2 of the third pixel circuit PXC3, which is electrically connected to the third data wiring D3, may be located to the right of the third storage capacitor Cst3.

[0179] As described above, the first to third transistors T1, T2, and T3 of the first pixel circuit PXC1 can be located to the right of the first storage capacitor Cst1, the first to third transistors T1, T2, and T3 of the second pixel circuit PXC2 can be located to the right of the second storage capacitor Cst2, and the first to third transistors T1, T2, and T3 of the third pixel circuit PXC3 can be located to the right of the third storage capacitor Cst3. In this case, in each of the first to third sub-pixels SPX1, SPX2, and SPX3, the electrical connection between the first gate electrode GE1 and the second source electrode SE2 (or the corresponding data wiring) may be made to the right of the storage capacitor of the corresponding sub-pixel. This reduces or prevents the electrical connection between the first gate electrode GE1 and the second source electrode SE2 from affecting each of the first to third storage capacitors Cst1, Cst2, and Cst3. In this case, in each of the first to third sub-pixels SPX1, SPX2, and SPX3, the area (or size) of the first gate electrode GE1 of the first transistor T1 can be reduced, and the area of ​​the storage capacitor for the corresponding sub-pixel can be secured by the reduced area (or size) of the first gate electrode GE1. For example, in the first sub-pixel SPX1, the area of ​​the first gate electrode GE1 of the first transistor T1 can be reduced, and the area of ​​the first lower electrode LE1 and the first upper electrode UE1 can be increased by the reduced area of ​​the first gate electrode GE1, thereby further securing the superposition area of ​​the first lower electrode LE1 and the first upper electrode UE1 and improving the capacitance of the first storage capacitor Cst1. In the second sub-pixel SPX2, the area of ​​the first gate electrode GE1 of the first transistor T1 can be reduced, and the area of ​​the second lower electrode LE2 and the second upper electrode UE2 can be increased by the reduced area of ​​the first gate electrode GE1, thereby further securing the superposition area of ​​the second lower electrode LE2 and the second upper electrode UE2 and improving the capacitance of the second storage capacitor Cst2.In the third sub-pixel SPX3, the area of ​​the first gate electrode GE1 of the first transistor T1 can be reduced, and the area of ​​the third lower electrode LE3 and the third upper electrode UE3 can be increased by the same amount as the reduced area of ​​the first gate electrode GE1, thereby further securing the superposition area of ​​the third lower electrode LE3 and the third upper electrode UE3 and improving the capacitance of the third storage capacitor Cst3.

[0180] According to the embodiment described above, the reliability of the pixel PXL (or display device DD) can be improved by increasing the capacitance of each of the first to third storage capacitors Cst1, Cst2, and Cst3.

[0181] As described above, in each of the first to third pixel circuits PXC1, PXC2, and PXC3, the first source electrode SE1 of the first transistor T1 and the third source electrode SE3 of the third transistor T3 are integrally formed, thereby eliminating the need for connecting members (for example, contact holes and conductive patterns) for electrically connecting the first source electrode SE1 and the third source electrode SE3. This allows for further securing of the area of ​​the first storage capacitor Cst1 in the first pixel circuit PXC1, thereby increasing the capacitance of the first storage capacitor Cst1; further securing of the area of ​​the second storage capacitor Cst2 in the second pixel circuit PXC2, thereby increasing the capacitance of the second storage capacitor Cst2; and further securing of the area of ​​the third storage capacitor Cst3 in the third pixel circuit PXC3, thereby increasing the capacitance of the third storage capacitor Cst3.

[0182] According to the embodiment described above, by positioning the first vertical power supply wiring PL1a to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the first to third transistors T1, T2, and T3 of the first to third pixel circuits PXC1, PXC2, and PXC3 can be positioned to the right of the storage capacitor of the corresponding pixel circuit. This makes it easy to form the first to third transistors T1, T2, and T3 to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, respectively, and reduces the design constraints imposed by the position of the first to third transistors T1, T2, and T3.

[0183] The following explanation will focus on the stacked structure (or cross-sectional structure) of the pixel PXL according to the previously described embodiment, with reference to Figures 8 to 10.

[0184] Figure 8 is a schematic cross-sectional view along lines I to I' in Figure 5, and Figures 9 and 10 are schematic cross-sectional views along lines II to II' in Figure 5.

[0185] Figure 10 shows a modified example of the embodiment in Figure 9, with respect to the position of the second insulating layer INS2, etc.

[0186] Figures 8 to 10 show a simplified representation of the pixel PXL stacking structure, such as showing each electrode as a single-layer electrode and each insulating layer as a single-layer insulating layer, but the structure is not limited to this.

[0187] To avoid redundant explanations regarding the embodiments shown in Figures 8 to 10, we will primarily describe the differences from the embodiments described above.

[0188] Referring to Figures 1 to 10, the pixel PXL according to the embodiment can include a first subpixel SPX1, a second subpixel SPX2, and a third subpixel SPX3 that are adjacent to each other.

[0189] The first subpixel SPX1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA surrounding the first light-emitting region EMA1. The second subpixel SPX2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA surrounding the second light-emitting region EMA2. The third subpixel SPX3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA surrounding the third light-emitting region EMA3.

[0190] Each of the first to third sub-pixels SPX1, SPX2, and SPX3 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and a encapsulation layer TFE.

[0191] The substrate SUB may contain a transparent insulating material and be capable of transmitting light. The substrate SUB may be a rigid substrate or a flexible substrate.

[0192] The pixel circuit layer PCL may contain circuit elements (for example, first to third transistors T1, T2, and T3) and signal wiring electrically connected to the circuit elements. The display element layer DPL may contain light-emitting elements (see "LD" in Figure 3) electrically connected to the circuit elements of the first to third sub-pixels SPX1, SPX2, and SPX3, respectively.

[0193] At least one insulating layer may be placed on the substrate SUB. For example, a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, and a fourth insulating layer INS4 may be placed on the substrate SUB, sequentially stacked along a third direction DR3. For example, at least one conductive layer may be placed on the substrate SUB. For example, the conductive layer may include a first conductive layer C1 placed between the substrate SUB and the first insulating layer INS1, a second conductive layer C2 placed on the second insulating layer INS2, and a third conductive layer C3 placed on the fourth insulating layer INS4.

[0194] The first conductive layer C1 may include a first vertical power wiring PL1a, a second vertical power wiring PL2a, an initialization power wiring IPL, first to third data wirings D1, D2, D3, a lower metal pattern BML, and first to third lower electrodes LE1, LE2, LE3. The second conductive layer C2 may include a first horizontal power wiring PL1b, a second horizontal power wiring PL2b, an additional conductive pattern ACP, first to ninth conductive patterns CP1 to CP9, first to third gate electrodes GE1, GE2, GE3, a scan wiring SC, and a first subscan wiring SSL1. The third conductive layer C3 may include a first-to-first electrode AE1, a first-to-second electrode AE2, and a first-to-third electrode AE3.

[0195] The pixel circuit layer PCL may be placed on the substrate SUB. The first to fourth insulating layers INS1, INS2, INS3, and INS4 described above may be placed on the pixel circuit layer PCL.

[0196] The first insulating layer INS1 (or buffer layer) may be distributed over the entire substrate SUB. The first insulating layer INS1 can prevent the diffusion of impurities to the first to third transistors T1, T2, and T3. The first insulating layer INS1 may be an inorganic insulating film containing an inorganic material. The first insulating layer INS1 may contain at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or at least one of metal oxides such as aluminum oxide (AlxOy). The first insulating layer INS1 may be provided as a single film, or as a multilayer film of at least two or more layers. If the first insulating layer INS1 is provided as a multilayer film, each layer may be formed of the same material as the others, or of different materials as the others. The first insulating layer INS1 may be omitted depending on the material and process conditions of the substrate SUB.

[0197] The second insulating layer INS2 (or gate insulating layer) may be disposed entirely on the first insulating layer INS1. The second insulating layer INS2 may contain the same material as the first insulating layer INS1 described above, or may contain a suitable (or selected) material from the materials exemplified as constituent materials of the first insulating layer INS1. For example, the second insulating layer INS2 may contain an inorganic insulating film containing an inorganic material. In the embodiment, the second insulating layer INS2 may be disposed partially on the first insulating layer INS1, as shown in Figure 10. For example, the second insulating layer INS2 may be etched together with the base material of the second conductive layer C2 during the manufacturing process of the second conductive layer C2 so that it is disposed only below the second conductive layer C2. In this case, the second insulating layer INS2 may, but is not limited to, have the same width as the second conductive layer C2 located above it.

[0198] The third insulating layer INS3 (or interlayer insulating layer) may be provided and / or formed entirely on the second insulating layer INS2. The third insulating layer INS3 may contain the same material as the first insulating layer INS1, or may contain one or more suitable (or selected) materials from those exemplified as constituent materials of the first insulating layer INS1. As an example, the third insulating layer INS3 may be an inorganic insulating film containing an inorganic material.

[0199] The fourth insulating layer INS4 (or via layer) may be provided and / or formed entirely on the third insulating layer INS3. The fourth insulating layer INS4 may be an inorganic insulating film containing an inorganic material or an organic insulating film containing an organic material. The inorganic insulating film may include, for example, at least one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlxOy). The organic insulating film may include, for example, at least one of polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, unsaturated polyesters resin, polyphenylene ethers resin, polyphenylene sulfides resin, and benzocyclobutene resin. In the examples, the fourth insulating layer INS4 may be an organic insulating film containing an organic material.

[0200] Each of the aforementioned second to fourth insulating layers INS2, INS3, and INS4 can be partially opened to include contact portion CNTs (or contact holes). The contact portion CNTs may also be connection points for electrically connecting each of the first to third pixel circuits PXC1, PXC2, and PXC3 to the respective light-emitting LDs of the first to third sub-pixels SPX1, SPX2, and SPX3.

[0201] The pixel circuit layer PCL of the first to third sub-pixels SPX1, SPX2, and SPX3 can include first to third transistors T1, T2, and T3 and a storage capacitor, which are arranged on the first insulating layer INS1. For example, the pixel circuit layer PCL of the first sub-pixel SPX1 can include first to third transistors T1, T2, and T3 and a first storage capacitor Cst1, which are arranged on the first insulating layer INS1. The pixel circuit layer PCL of the second sub-pixel SPX2 can include first to third transistors T1, T2, and T3 and a second storage capacitor Cst2, which are arranged on the first insulating layer INS1. The pixel circuit layer PCL of the third sub-pixel SPX3 can include first to third transistors T1, T2, and T3 and a third storage capacitor Cst3, which are arranged on the first insulating layer INS1.

[0202] The first transistor T1 may include a first active pattern ACT1, a first source electrode SE1, a first drain electrode DE1, and a first gate electrode GE1, which are located on a first insulating layer INS1. A lower metal pattern BML may be located below the first transistor T1. The lower metal pattern BML is configured as a first conductive layer C1 located between the substrate SUB and the first insulating layer INS1, and may be formed integrally with the corresponding lower electrode among the first to third lower electrodes LE1, LE2, and LE3.

[0203] The second transistor T2 may include a second active pattern ACT2 arranged on the first insulating layer INS1, a second source electrode SE2, a second drain electrode DE2, and a second gate electrode GE2 arranged on the second insulating layer INS2.

[0204] The third transistor T3 may include a third active pattern ACT3, a third source electrode SE3, a third drain electrode DE3, and a third gate electrode GE3, which are located on the second insulating layer INS2, all of which are located on the first insulating layer INS1.

[0205] The first storage capacitor Cst1 may include a first lower electrode LE1 disposed between the substrate SUB and the first insulating layer INS1, and a first upper electrode UE1 superimposed on the first lower electrode LE1 with the first insulating layer INS1 in between. The first lower electrode LE1 is configured as a first conductive layer C1, and the first upper electrode UE1 is disposed between the first insulating layer INS1 and the second insulating layer INS2, and may be configured as a conductive semiconductor pattern doped with impurities. In the first subpixel SPX1, the first lower electrode LE1 may be formed integrally with the lower metal pattern BML, and the first upper electrode UE1 may be formed integrally with the first source electrode SE1 and the third source electrode SE3. The first upper electrode UE1 may be electrically connected to a part of the display element layer DPL, for example, the 1-1 electrode AE1, via a corresponding contact portion CNT.

[0206] The second storage capacitor Cst2 may include a second lower electrode LE2 positioned between the substrate SUB and the first insulating layer INS1, and a second upper electrode UE2 superimposed on the second lower electrode LE2 with the first insulating layer INS1 in between. The second lower electrode LE2 may be configured as a first conductive layer C1, and the second upper electrode UE2 may be positioned between the first insulating layer INS1 and the second insulating layer INS2 and configured as a conductive semiconductor pattern doped with impurities. In the second subpixel SPX2, the second lower electrode LE2 may be formed integrally with the lower metal pattern BML, and the second upper electrode UE2 may be formed integrally with the first source electrode SE1 and the third source electrode SE3. The second upper electrode UE2 may be electrically connected to a part of the display element layer DPL, for example, the first-to-second electrode AE2, via a corresponding contact portion CNT.

[0207] The third storage capacitor Cst3 may include a third lower electrode LE3 disposed between the substrate SUB and the first insulating layer INS1, and a third upper electrode UE3 superimposed on the third lower electrode LE3 with the first insulating layer INS1 in between. The third lower electrode LE3 may be configured as a first conductive layer C1, and the third upper electrode UE3 may be disposed between the first insulating layer INS1 and the second insulating layer INS2, and may be configured as a semiconductor pattern doped with impurities to be conductive. In the third subpixel SPX3, the third lower electrode LE3 may be formed integrally with the lower metal pattern BML, and the third upper electrode UE3 may be formed integrally with the first source electrode SE1 and the third source electrode SE3. The third upper electrode UE3 may be electrically connected to a part of the display element layer DPL, for example, the first to third electrodes AE3, via a contact portion CNT.

[0208] A third insulating layer INS3 and a fourth insulating layer INS4 may be continuously provided and / or formed on the aforementioned first to third transistors T1, T2, T3 and first to third storage capacitors Cst1, Cst2, Cst3.

[0209] A display element layer DPL may be provided and / or formed on the fourth insulating layer INS4.

[0210] The display element layer DPL may include a first light-emitting element LD1, a second light-emitting element LD2, a third light-emitting element LD3, and a pixel definition film PDL. The first light-emitting element LD1 may be located in the display element layer DPL of the first sub-pixel SPX1 and electrically connected to the first pixel circuit PXC1. The second light-emitting element LD2 may be located in the display element layer DPL of the second sub-pixel SPX2 and electrically connected to the second pixel circuit PXC2. The third light-emitting element LD3 may be located in the display element layer DPL of the third sub-pixel SPX3 and electrically connected to the third pixel circuit PXC3. Each of the first to third light-emitting elements LD1, LD2, and LD3 may be the light-emitting elements LD described with reference to Figure 3.

[0211] The first light-emitting element LD1 may include a first-to-first electrode AE1, a first light-emitting layer EML1, and a second electrode CE. The second light-emitting element LD2 may include a first-to-second electrode AE2, a second light-emitting layer EML2, and a second electrode CE. The third light-emitting element LD3 may include a first-to-third electrode AE3, a third light-emitting layer EML3, and a second electrode CE.

[0212] The first-first electrode AE1, the first-second electrode AE2, and the first-third electrode AE3 may be configured as a third conductive layer C3 provided and / or formed on the fourth insulating layer INS4 of the subpixel. The first-first electrode AE1, the first-second electrode AE2, and the first-third electrode AE3 may be spaced apart from each other on the fourth insulating layer INS4. The first-first electrode AE1 may be the anode of the first light-emitting element LD1, the first-second electrode AE2 may be the anode of the second light-emitting element LD2, and the first-third electrode AE3 may be the anode of the third light-emitting element LD3.

[0213] The first electrode AE1 may be electrically connected to the first upper electrode UE1 of the first storage capacitor Cst1 via a corresponding contact portion CNT. The first-second electrode AE2 may be electrically connected to the second upper electrode UE2 of the second storage capacitor Cst2 via a corresponding contact portion CNT. The first-third electrode AE3 may be electrically connected to the third upper electrode UE3 of the third storage capacitor Cst3 via a corresponding contact portion CNT.

[0214] Each of the first electrode AE1, first electrode AE2, and first electrode AE3 may be composed of a conductive substance (or material). The conductive substance may include opaque metals. Examples of opaque metals include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. However, the materials of each of the first electrode AE1, first electrode AE2, and first electrode AE3 are not limited to the embodiments described above. According to the embodiments, the first electrode AE1, first electrode AE2, and first electrode AE3 may include transparent conductive substances (or materials). Examples of transparent conductive materials include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), as well as conductive polymers such as PEDOT (poly(3,4-ethylenedioxythiophene)). If the first-first electrode AE1, the first-second electrode AE2, and the first-third electrode AE3 contain transparent conductive materials, another conductive layer made of an opaque metal may be added to reflect the light emitted from the first, second, and third light-emitting layers EML1, EML2, and EML3 in the image display direction of the display device DD (or towards the top of the sealing layer TFE).

[0215] The first electrode AE1 may be located at least in the first light-emitting region EMA1, the first-second electrode AE2 may be located at least in the second light-emitting region EMA2, and the first-third electrode AE3 may be located at least in the third light-emitting region EMA3.

[0216] The pixel definition film PDL is provided on the pixel circuit layer PCL in the non-emitting region NEA and can define (or partition) the first emitting region EMA1, the second emitting region EMA2, and the third emitting region EMA3. The pixel definition film PDL may include an organic insulating film made of an organic material. Examples of organic materials include acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. According to the examples, the pixel definition film PDL may contain a light-absorbing substance or be coated with a light-absorbing agent to absorb light entering from the outside. For example, the pixel definition film PDL may, but is not limited to, a carbon-based black pigment.

[0217] The pixel definition film PDL is partially open to include an aperture OP that exposes one region each of the first-1 electrode AE1, the first-2 electrode AE2, and the first-3 electrode AE3, and can protrude in the third direction DR3 from the fourth insulating layer INS4 along the periphery of the first to third light-emitting regions EMA1, EMA2, and EMA3, respectively.

[0218] A first light-emitting layer EML1 may be placed on the first-first electrode AE1 exposed by an aperture OP of the pixel definition film PDL, a second light-emitting layer EML2 may be placed on the first-second electrode AE2 exposed by another aperture OP of the pixel definition film PDL, and a third light-emitting layer EML3 may be placed on the first-third electrode AE3 exposed by yet another aperture OP of the pixel definition film PDL.

[0219] The first light-emitting layer EML1 may be located only on the first-first electrode AE1 within the aperture OP of the pixel-defining film PDL, the second light-emitting layer EML2 may be located only on the first-second electrode AE2 within another aperture OP of the pixel-defining film PDL, and the third light-emitting layer EML3 may be located only on the first-third electrode AE3 within yet another aperture OP of the pixel-defining film PDL. Each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may be supplied to the target region of the corresponding subpixel (for example, the upper part of a region of the first electrode (see "AE" in Figure 3) exposed by the aperture OP of the pixel-defining film PDL) by an inkjet printing method, but is not limited to this.

[0220] Each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may have a multilayer thin film structure including a light-generation layer that generates light. For example, the first light-emitting layer EML1 may include a light-generation layer that generates and emits red light, the second light-emitting layer EML2 may include a light-generation layer that generates and emits green light, and the third light-emitting layer EML3 may include a light-generation layer that generates and emits blue light, but is not limited to this. According to the embodiment, each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may include a light-generation layer that generates and emits white light, in which case a color conversion layer for converting the white light (or light of a first color) into light of a specific color (or light of a second color) may be provided.

[0221] A second electrode CE may be provided and / or formed on the first light-emitting layer EML1, the second light-emitting layer EML2, the third light-emitting layer EML3, and the pixel definition film PDL.

[0222] The second electrode CE may be a common layer provided in common to the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3. The second electrode CE may, but is not limited to, be provided in plate form across the entire area of ​​the display region DA.

[0223] The second electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3, respectively. The second electrode CE may be formed of a metallic material or a transparent conductive material to have a relatively thin thickness. For example, the second electrode CE may be composed of various transparent conductive materials. The second electrode CE may include at least one of various transparent conductive materials, including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide, and may be realized to be substantially transparent or translucent to satisfy a predetermined light transmittance. This allows light emitted from the first, second, and third light-emitting layers EML1, EML2, and EML3, located below the second electrode CE, to pass through the second electrode CE and be emitted upward toward the sealing layer TFE.

[0224] For example, the second electrode CE may be electrically connected to the second power supply wiring PL2.

[0225] A sealing layer TFE may be provided and / or formed over the entire surface of the second electrode CE.

[0226] The encapsulation layer TFE may include a first incapsulation layer ENC1, a second incapsulation layer ENC2, and a third incapsulation layer ENC3, which are sequentially located on the second electrode CE. The first incapsulation layer ENC1 is formed on the display element layer DPL (or the second electrode CE) and may be located over at least a portion of the display area DA and the non-display area NDA. The second incapsulation layer ENC2 is formed on the first incapsulation layer ENC1 and may be located over at least a portion of the display area DA and the non-display area NDA. The third incapsulation layer ENC3 is formed on the second incapsulation layer ENC2 and may be located over at least a portion of the display area DA and the non-display area NDA. According to the embodiment, the third incapsulation layer ENC3 may be located over the entire display area DA and the non-display area NDA.

[0227] The first and third incapsulation layers ENC1 and ENC3 can each consist of an inorganic film containing an inorganic material, and the second incapsulation layer ENC2 can consist of an organic film containing an organic material. The inorganic film may include, for example, silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). The organic film may include organic insulating materials such as acrylic resin (polyacrylates resin), epoxy resin (epoxy resin), phenolic resin (phenolic resin), polyamide resin (polyamides resin), polyimide resin (polyimides resin), unsaturated polyester resin (polyphenylene resin), polyphenylene sulfide resin (polyphenylenesulfides resin), or benzocyclobutene (BCB).

[0228] According to the examples, a color filter layer and / or a color conversion layer may be selectively provided and / or formed on the sealing layer TFE, which emits light from the first to third light-emitting elements LD1, LD2, and LD3 as light with excellent color reproducibility.

[0229] Figure 11 shows a pixel PXL according to one embodiment, and is a schematic cross-sectional view corresponding to lines I to I' in Figure 5.

[0230] To avoid redundant explanations regarding the embodiment shown in Figure 11, we will primarily describe the differences from the previously mentioned embodiment.

[0231] Referring to Figures 1 to 5 and Figure 11, the pixel PXL according to the embodiment may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, a encapsulation layer TFE, a color filter layer CFL, and an overcoat layer OC.

[0232] The color filter layer CFL may be formed on top of the sealing layer TFE through a continuous process. The color filter layer CFL may include a color filter CF and a light-shielding pattern BM. The color filter CF may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0233] The first color filter CF1 may be placed on one surface of the third incapsulation layer ENC3 of the encapsulating layer TFE so as to correspond to the first light-emitting layer EML1. The second color filter CF2 may be placed on one surface of the third incapsulation layer ENC3 of the encapsulating layer TFE so as to correspond to the second light-emitting layer EML2. The third color filter CF3 may be placed on one surface of the third incapsulation layer ENC3 of the encapsulating layer TFE so as to correspond to the third light-emitting layer EML3.

[0234] The light-shielding pattern BM can be positioned adjacent to the first to third color filters CF1, CF2, and CF3 on one surface of the third incapsulation layer ENC3 of the sealing layer TFE. For example, the light-shielding pattern BM may be positioned on one surface of the third incapsulation layer ENC3 in the non-emitting region NEA to correspond to the pixel definition film PDL. The light-shielding pattern BM may include a light-shielding material. As an example, the light-shielding pattern BM may be a black matrix, but is not limited thereto. According to the embodiment, the light-shielding pattern BM is configured to include at least one light-shielding material and / or a reflective material, and can improve the light emission efficiency by causing the light emitted from each of the first to third light-emitting layers EML1, EML2, and EML3 to proceed further in the image display direction of the display device DD. The light-shielding pattern BM can prevent color mixing of the light emitted from the first to third light-emitting layers EML1, EML2, and EML3.

[0235] Each of the first, second, and third color filters CF1, CF2, and CF3 may contain a colorant such as a dye or pigment that absorbs wavelengths other than the corresponding color wavelength. The first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter. In the drawings, an example is shown in which adjacent color filters CF are arranged so as to be separated from each other with a light-shielding pattern BM in between, but adjacent color filters CF may be at least partially superimposed on the light-shielding pattern BM. According to the embodiment, the first to third color filters CF1, CF2, and CF3 can be arranged so as to be superimposed on each other in the non-emitting region NEA and used as a light-shielding member to block light interference between adjacent subpixels. In this case, the light-shielding pattern BM can be omitted.

[0236] An overcoat layer OC may be placed on the aforementioned color filter layer CFL.

[0237] The overcoat layer OC is positioned on the color filter layer CFL and can cover the lower components, including the color filter layer CFL. The overcoat layer OC can prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color filter layer CFL. For example, the overcoat layer OC can prevent the colorants of the color filter layer CFL from diffusing into other components. The overcoat layer OC may, but is not limited to, include an inorganic insulating film containing inorganic materials.

[0238] Figure 12 is a schematic plan view showing a pixel PXL according to one embodiment; Figure 13 is a schematic plan view showing only the components included in the first conductive layer C1 in the pixel PXL of Figure 12; Figure 14 is a schematic plan view showing only the components included in the transistors T1, T2, T3 and the second conductive layer C2 in the pixel PXL of Figure 12; and Figure 15 is a schematic cross-sectional view along lines III to III' in Figure 12.

[0239] The embodiment shown in Figure 12 illustrates a modified version of Figure 4, particularly regarding the location of the initialization power supply wiring IPL.

[0240] Regarding the embodiments shown in Figures 12 to 15, in order to avoid redundant explanations, we will mainly describe the differences from the embodiments described above.

[0241] Referring to Figures 1 to 3 and 12 to 15, the pixel PXL according to the embodiment may include a first sub-pixel SPX1 containing a first pixel circuit PXC1, a second sub-pixel SPX2 containing a second pixel circuit PXC2, and a third sub-pixel SPX3 containing a third pixel circuit PXC3. Each of the first to third pixel circuits PXC1, PXC2, and PXC3 may include first to third transistors T1, T2, and T3, and a storage capacitor Cst.

[0242] In the pixel region PXA where the pixel PXL is provided, signal wiring electrically connected to the first to third pixel circuits PXC1, PXC2, and PXC3 may be arranged. For example, scan wiring SC, first to third data wiring D1, D2, and D3, power wiring PL, and initialization power wiring IPL may be arranged in the pixel region PXA.

[0243] The scan wiring SC may be configured as a second conductive layer C2 extending along a first direction DR1 and positioned on a second insulating layer INS2. The scan wiring SC may include first and second subscan wirings SSL1 and SSL2 extending in a second direction DR2. The first subscan wiring SSL1 may be formed integrally with the second gate electrode GE2 of the second transistor T2 of each of the first to third pixel circuits PXC1, PXC2, and PXC3. The second subscan wiring SSL2 may be formed integrally with the third gate electrode GE3 of the third transistor T3 of each of the first to third pixel circuits PXC1, PXC2, and PXC3.

[0244] The first data wiring D1 may be electrically connected to the second transistor T2 of the first pixel circuit PXC1, the second data wiring D2 may be electrically connected to the second transistor T2 of the second pixel circuit PXC2, and the third data wiring D3 may be electrically connected to the second transistor T2 of the third pixel circuit PXC3.

[0245] The power wiring PL may include a first power wiring PL1 and a second power wiring PL2. The first power wiring PL1 may include a first vertical power wiring PL1a and a first horizontal power wiring PL1b, which are located on different layers and electrically connected via corresponding contact holes. The second power wiring PL2 may include a second vertical power wiring PL2a and a second horizontal power wiring PL2b, which are located on different layers and electrically connected via corresponding contact holes. In this embodiment, the first vertical power wiring PL1a may be located between the first to third storage capacitors Cst1, Cst2, and Cst3 and the first data wiring D1.

[0246] The initialization power supply wiring IPL may be positioned between the second vertical power supply wiring PL2a and the first to third storage capacitors Cst1, Cst2, and Cst3 when viewed in plan. In this case, the second vertical power supply wiring PL2a is located on one side (for example, the left side) of the initialization power supply wiring IPL, and each of the first to third storage capacitors Cst1, Cst2, and Cst3 can be located on the other side (for example, the right side) of the initialization power supply wiring IPL.

[0247] In this embodiment, the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 can be arranged along the second direction DR2 and located on the same line. The first to third storage capacitors Cst1, Cst2, and Cst3 can be located between the initialization power supply wiring IPL and the first vertical power supply wiring PL1a. In this case, the initialization power supply wiring IPL can be located on one side (for example, the left side) of the first to third storage capacitors Cst1, Cst2, and Cst3, and the first vertical power supply wiring PL1a can be located on the other side (for example, the right side) of the first to third storage capacitors Cst1, Cst2, and Cst3.

[0248] If the first vertical power supply wiring PL1a is located to the right of the first to third storage capacitors Cst1, Cst2, and Cst3, the first transistor T1 of each of the first to third pixel circuits PXC1, PXC2, and PXC3, which are electrically connected to the first vertical power supply wiring PL1a, may be located to the right of the storage capacitor of the corresponding pixel circuit. In this embodiment, the first to third data wirings D1, D2, and D3 can be located away from the first vertical power supply wiring PL1a along a first direction DR1 from one side of the first vertical power supply wiring PL1a (for example, the right side). If the first to third data wirings D1, D2, and D3 are each located to the right of the first vertical power wiring PL1a, then the second transistor T2 of the first pixel circuit PXC1 electrically connected to the first data wiring D1, the second transistor T2 of the second pixel circuit PXC2 electrically connected to the second data wiring D2, and the second transistor T2 of the third pixel circuit PXC3 electrically connected to the third data wiring D3 may be located to the right of the storage capacitor of the corresponding pixel circuit.

[0249] If the initialization power wiring IPL is located to the left of the first to third storage capacitors Cst1, Cst2, and Cst3, the third transistor T3 of each of the first to third pixel circuits PXC1, PXC2, and PXC3, which are electrically connected to the initialization power wiring IPL, may be located to the left of the storage capacitor of the corresponding pixel circuit.

[0250] As mentioned above, the first and second transistors T1 and T2 may be positioned to the right of each of the first to third storage capacitors Cst1, Cst2, and Cst3, and the third transistor T3 may be positioned to the left of each of them. In this case, the electrical connection between the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 can be reduced or prevented from directly affecting each of the first to third storage capacitors Cst1, Cst2, and Cst3. This makes it possible to reduce the area (or size) of the first gate electrode GE1 of the first transistor T1 in each of the first to third pixel circuits PXC1, PXC2, PXC3 (or the first to third sub-pixels SPX1, SPX2, SPX3), and to further secure the area of ​​the storage capacitor of the corresponding sub-pixel by the reduced area (or size) of the first gate electrode GE1, thereby increasing the capacitance of the storage capacitor.

[0251] As described above with reference to preferred embodiments of the present invention, a person skilled in the art or a person with ordinary knowledge of the art will understand that the present invention can be modified and altered in various ways without departing from the technical domain of the present invention as described in the claims below.

[0252] Therefore, the technical scope of the present invention is not limited to what is described in the detailed description of the specification, but should be defined by the claims.

Claims

1. First, second, and third subpixels are adjacent to each other and each has a light-emitting element and a storage capacitor, respectively. A scan signal and a control signal are selectively transmitted to each of the first to third subpixels, and a scan wiring extending in the first direction is provided. A data wiring is provided that transmits a data signal to each of the first to third subpixels and extends in a second direction intersecting the first direction, The first power supply wiring is electrically connected to each of the first, second, and third subpixels and supplies a first drive power supply voltage to the first electrode, which is the anode of the light-emitting element, The storage capacitor comprises a first storage capacitor, a second storage capacitor, and a third storage capacitor, each corresponding to the first, second, and third subpixels, and arranged adjacent to each other along the second direction. The first power supply wiring is located between the storage capacitor and the data wiring. Each of the first, second, and third subpixels is: A first transistor that controls the current of the light-emitting element, A second transistor is connected between the data wiring and the gate electrode of the first transistor, and is turned on by the scan signal supplied from the scan wiring during the driving period of the light-emitting element, A third transistor connected to the source electrode of the first transistor and turned on by the control signal supplied from the scan wiring during the sensing period, A display device comprising a storage capacitor including a lower electrode electrically connected to the gate electrode of the first transistor and the source electrode of the second transistor, and an upper electrode electrically connected to the source electrode of the first transistor and the source electrode of the third transistor.

2. circuit board and A first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer are sequentially arranged on the substrate, A second power supply wiring supplies a second drive power supply voltage, different from the first drive power supply voltage, to the second electrode of the light-emitting element, The invention further includes an initialization power supply wiring that supplies an initialization power supply voltage for initializing a node connected to the first electrode of the light-emitting element, The first power wiring includes a first vertical power wiring configured as a first conductive layer placed on the substrate and a first horizontal power wiring configured as a second conductive layer placed on the second insulating layer. Viewed in a plane, the first vertical power supply wiring is located between the storage capacitors and data wiring of the first, second, and third sub-pixels, respectively. The third transistor is connected between the initialization power supply wiring and the source electrode of the first transistor. The initialization power supply voltage is supplied to the first electrode of the light-emitting element during the sensing period. The display device according to claim 1, wherein the first drive power supply voltage is supplied to the first electrode of the light-emitting element during the driving period of the light-emitting element.

3. The display device according to claim 2, wherein the first, second, and third transistors are located on one side of the storage capacitor.

4. The second power supply wiring includes a second vertical power supply wiring configured as the first conductive layer and a second horizontal power supply wiring configured as the second conductive layer. The display device according to claim 2, wherein, when viewed in a planar view, the storage capacitor is located between the second vertical power supply wiring and the first vertical power supply wiring.

5. The display device according to claim 4, wherein, when viewed in a planar view, the initialization power supply wiring is located between the first vertical power supply wiring and the data wiring.

6. The display device according to claim 5, wherein the gate electrodes of the first transistors of each of the first, second, and third subpixels are located between the storage capacitor and the first vertical power supply wiring.

7. The display device according to claim 2, wherein the lower electrode is disposed on the substrate, and the upper electrode is disposed on the first insulating layer and superimposed on the lower electrode with the first insulating layer in between.

8. The display device according to claim 7, wherein the upper electrode is arranged in the same layer as the active patterns of the first, second, and third transistors, respectively.

9. The display device according to claim 8, wherein the upper electrode is formed integrally with the source electrode of the first transistor and the source electrode of the third transistor.

10. The light-emitting element is The first electrode, which is configured as a third conductive layer disposed on the fourth insulating layer, A light-emitting layer disposed on the first electrode, The display device according to claim 2, further comprising the second electrode disposed on the light-emitting layer.

11. The display device according to claim 10, wherein the first electrode is electrically connected to the source electrode of the first transistor via a contact portion that penetrates the second to fourth insulating layers.

12. The display device according to claim 4, wherein, when viewed in a planar view, the initialization power supply wiring is located between the second vertical power supply wiring and the storage capacitor.

13. The display device according to claim 12, wherein, when viewed in a planar view, the initialization power supply wiring is located on one side of the storage capacitor and the first vertical power supply wiring is located on the other side of the storage capacitor.

14. The display device according to claim 13, wherein, when viewed on a plane, the third transistor among the first, second, and third transistors is located on one side of the storage capacitor, and the first and second transistors are located on the other side of the storage capacitor.

15. Each of the first, second, and third subpixels is: A sealing layer disposed on the light-emitting element, A color filter layer disposed on the sealing layer, The display device according to claim 2, further comprising an overcoat layer disposed on the color filter layer.

16. circuit board and The first, second, third, and fourth insulating layers are sequentially laminated on the substrate, The substrate includes a storage capacitor and a pixel circuit including first, second, and third transistors, and first, second, and third subpixels, each including a light-emitting element electrically connected to the pixel circuit, A scan wiring is arranged on the substrate and selectively transmits scan signals and control signals to the first, second, and third subpixels. Data wiring for transmitting data signals to the first, second, and third subpixels, A first power supply wiring that supplies a first drive power supply voltage to the first electrode which is the anode of the light-emitting element, A second power supply wiring supplies a second drive power supply voltage, different from the first drive power supply voltage, to the second electrode of the light-emitting element, It includes an initialization power supply wiring that supplies an initialization power supply voltage different from the first and second drive power supply voltages, and for initializing a node connected to the first electrode of the light-emitting element, The storage capacitor comprises a first storage capacitor, a second storage capacitor, and a third storage capacitor, each corresponding to the first, second, and third subpixels, and arranged adjacent to one another. The gate electrode of the first transistor is located between the storage capacitor and the first power supply wiring. The first transistor controls the current of the light-emitting element, The second transistor is connected between the data wiring and the gate electrode of the first transistor, and is turned on by the scan signal supplied from the scan wiring during the drive period of the light-emitting element. The third transistor is connected between the initialization power supply wiring and the source electrode of the first transistor, and is turned on by the control signal supplied from the scan wiring during the sensing period. The storage capacitor includes a lower electrode electrically connected to the gate electrode of the first transistor and the source electrode of the second transistor, and an upper electrode electrically connected to the source electrode of the first transistor and the source electrode of the third transistor. The initialization power supply voltage is supplied to the first electrode of the light-emitting element during the sensing period. The first drive power supply voltage is supplied to the first electrode of the light-emitting element during the driving period of the light-emitting element in a display device.

17. The first power wiring includes a first vertical power wiring arranged on the substrate and a first horizontal power wiring arranged on the second insulating layer. The display device according to claim 16, wherein the first vertical power supply wiring is located between the storage capacitor and the data wiring.

18. The display device according to claim 17, wherein, when viewed in a planar view, the first, second, and third transistors are located on one side of the storage capacitor.

19. The display device according to claim 17, wherein, when viewed in a planar view, the storage capacitor is located between the initialization power supply wiring and the first vertical power supply wiring.

Images