How to avoid processor stalls when accessing low-power coherent memory devices.

Abstract

To provide a system, a method, a program, and a storage medium for memory power supply management for executing management in a coherent lower power state.SOLUTION: A memory subsystem provided with a memory managed by using coherent access manages a page table entry so as to enable the memory to be in a lower power state. Memory control can change the page table entry of the memory before triggering the memory so as to be entered to the low power state. The change to the page table entry causes a page fault to the next access to the memory. The page fault triggers processing using a fault routine to the access to the memory, and avoids synchronization delay to the memory which occurs in the case of being normal access.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The description generally relates to computer systems, and more specifically relates to avoiding processor stalls when accessing coherent memory devices. [Background Art]

[0002] Devices connected via PCIe (Peripheral Component Interconnect Express) or NVMe (Nonvolatile Memory Express) have a low-power link state, and can enter a low-power state while the system is active. PCIe is inherently non-coherent and is managed by a host driver. A device driver can process I / O (Input / Output) operations that are transmitted when the power is turned off. Alternatively, I / O operations can also be processed by the bus automatically returning to hardware. Exiting a low-power state (whether it is a link state or a device state) usually incurs a delay, but this delay inherently does not affect the host processor's processing of other activities or handling of interrupts when the memory is non-coherent. The non-coherent nature of such links allows this operation to be processed asynchronously and in a non-blocking manner.

[0003] When coherent memory wakes from a low-power state to process an I / O operation, it may cause a stall in the host processor. CXL (Compute Express Link) is a PCIe-based protocol that defines the CXL.mem interface for coherent memory connections. Using CXL.mem or another coherent memory interconnect makes the memory interface coherent. The host processor waits for the completion of I / O operations to the coherent memory.

[0004] If coherent memory is allowed to enter a low-power state, it could potentially stall the host processor, leading to a decrease in system performance. One mechanism to reduce latency is to prevent the memory from entering a low-power state that could stall the host processor. However, while preventing coherent memory from entering a low-power state reduces the impact of latency, it comes at the cost of increased energy usage. Due to the "always-on" nature of coherent memory, a considerable amount of energy is wasted, reducing the system's battery life. This energy waste could also potentially lead to failure to meet energy compliance regulations. [Brief explanation of the drawing]

[0005] The following description includes a discussion of figures with examples given as illustrations of one implementation. These figures should be understood as illustrations and not as limitations. In this specification, references to one or more examples should be understood as describing a particular function, structure, or feature included in at least one implementation of the invention. Expressions such as "in one example" or "in an alternative example" appearing herein are providing examples of implementations relating to the invention, and not all refer to the same implementation. However, such expressions are not necessarily mutually exclusive.

[0006] [Figure 1] This is a block diagram of an example of a multilevel memory system with coherent memory that can enter a low-power state without stalling the host processor.

[0007] [Figure 2] This is a block diagram illustrating an example of a system that can modify page table entries before placing coherent memory into a low-power state.

[0008] [Figure 3]This is a flowchart illustrating an example of a process for reducing the power consumption of coherent memory.

[0009] [Figure 4] This is a flowchart illustrating an example of a process for waking coherent memory from low power.

[0010] [Figure 5] This is a block diagram of an example of a memory subsystem in which coherent low-power state management can be performed.

[0011] [Figure 6] This is a block diagram of an example of a computing system in which coherent low-power state management can be performed.

[0012] [Figure 7] This is a block diagram of an example of a mobile device in which coherent low-power state management can be implemented.

[0013] A description of some details and implementation examples follows, which may include figures illustrating some or all of the embodiments and a non-limiting description of other possible implementation examples. [Modes for carrying out the invention]

[0014] As described herein, a memory subsystem with memory managed using coherent access can manage page table entries to enable the memory to enter a low-power state. Memory control can modify the page table entries of memory before triggering the memory to enter a low-power state. Memory control can include a host operating system (OS) memory manager and memory drivers. Modifications to page table entries will result in a page fault for the next access to memory. The page fault triggers processing using a fault routine for memory access, avoiding the synchronization delay to memory that would occur with normal access.

[0015] Systems containing coherent memory are often secondary or auxiliary memory rather than main system memory. Therefore, if coherent memory is the second-tier memory in a multilevel memory (MLM) system, or remote memory for a NUMA (non-uniform memory access) architecture node, the system accesses main memory. Ori coherent memory devices but Used attitude do not have There may be time Therefore, there may be periods when it is more rational to trigger the device to enter a low-power state. An MLM system refers to a system that has primary memory as near memory and secondary memory as far memory, where near memory access is faster (less latency) than far memory access. A NUMA architecture refers to a system with one or more memory buses, where hopping to distant memory requires crossing memory bus boundaries. Therefore, distant memory has higher latency (slower access) than local memory.

[0016] In any case, coherent memory is always Used attitude It's not necessarily the case. ThereforeConsidering the workload requirements, coherent memory is given an opportunity to enter a low-power mode. It's fine to do so By managing coherent memory page table entries, it may be possible for coherent memory to enter a low-power state without affecting system performance. As described herein, if the host is not using the address range of coherent memory, the system can reduce device power while the system is active. In one example, the OS can put coherent memory into a low-power state after invalidating page table entries, such as through a memory manager or operating system driver. With invalid page table entries, the system will trigger a page fault routine instead of stalling the processor and waiting for the device to wake from the low-power state. A processor stall can also lead to other system error conditions, such as CPU (Central Processing Unit) timeouts, hardware errors, and OS crashes.

[0017] Instead of waiting for the device to wake up, the host processor can continue handling other processes, such as threads, or interrupts. This is not possible when waiting for coherent memory access to complete. While the host processor is performing other tasks, the coherent memory can wake up from its low-power state and handle memory I / O operations from the host processor.

[0018] Accordingly, coherent memory can utilize low-power states without directly impacting the host processor. The ability to enable low-power states can result in a significant reduction in energy consumption, thereby extending the battery life of the device. The ability to use low-power states can enable support for CXL (Compute Express Link: a trademark registered by the CXL Consortium) on platforms with strict regulatory requirements that might otherwise not be able to support CXL without this capability. CXL may refer to the CXL 2.0 specification first released by the CXL Consortium in November 2020, or the currently under consideration CXL 3.0 specification.

[0019] The ability to modify a page table before putting a memory device into a low-power state allows the system, for example via the OS, to perform power management on coherent devices such as memory with a CXL.mem interface. In one example, modifying the page table is invalidating references within the page table, and does not remove references from the page table. Requests to a sleeping coherent device will incur a fault. This in turn triggers a fault routine to obtain the invalid reference.

[0020] Figure 1 is a block diagram of an example multi-level memory system including coherent memory that can enter a low-power state without stalling the host processor. Specifically, system 100 shows a multi-level memory system capable of performing power management for coherent devices.

[0021] SOC 110 represents an example of a processor die or a processor SOC package. SOC 110 includes a processor 112 (i.e., a single-core processor or a multi-core processor) that can include one or more cores 120 for executing instructions. In one example, core 120 includes a processor-side cache 122, and this cache includes cache control circuitry and cache data storage. Cache 122 can represent any type of cache on the processor side. In one example, each individual core 120 includes local cache resources 122 that are not shared with other cores. In one example, a plurality of cores 120 share the cache resources 122.

[0022] In one example, SOC 110 includes a system fabric 130 that interconnects the respective components of the processor system. System fabric 130 may be or may include interconnections between components such as processor 112, peripheral control 132, one or more memory controllers including an integrated memory controller (iMC) 150 that manages access to a main memory 190 and an iMC 140 that manages access to a secondary memory 170, I / O control (not specifically shown), and a graphics subsystem (not specifically shown). System fabric 130 enables the exchange of data signals between these components. While system fabric 130 is generally shown as connecting the respective components, it will be understood that system 100 does not necessarily show interconnections between all components. System fabric 130 can represent interconnection topologies such as one or more mesh connections, a central switching mechanism, ring connections, or a hierarchical fabric structure.

[0023] In one example, the SOC 110 includes one or more peripheral controllers 132 that connect to peripheral components or peripheral devices outside the SOC 110. In one example, the peripheral controllers 132 represent a hardware interface to the platform controller 160 and include one or more components or circuits for controlling interconnections on the hardware platform or system board or motherboard of the system 100 to interconnect peripherals to the processor 112. Peripherals are represented by components 162. Components 162 represent any type of chip, interface or hardware element that connects to the processor 112 via the platform controller 160.

[0024] In one example, SOC110 has a common substrate or board on which each component of the SOC is located. For example, each component of SOC110 may be an individual component mounted on a common board or substrate, or may include such components. In one example, each component of SOC110 may be a circuit integrated on the same semiconductor substrate, or may include such circuits. In one example, each component of SOC110 may include a plurality of components on a common semiconductor substrate and one or more additional components mounted on the semiconductor substrate or mounted on a common board together with the common semiconductor substrate.

[0025] In one example, SOC110 includes iMC150, which represents control logic connected to main memory 190 and managing access to main memory 190. iMC150 may include hardware circuitry and software or firmware control logic. In one example, SOC110 includes iMC140, which represents control logic connected to secondary memory 170 and managing access to secondary memory 170. Secondary memory 170 represents one or more memory devices with longer access latency compared to main memory 190. Secondary memory 170 may alternatively be called auxiliary memory. iMC140 may include hardware circuitry and software or firmware control logic. In one example, iMC140 may be integrated into processor 112. In one example, iMC150 may be integrated into processor 112. In one example, iMC140 is part or a subset of the control logic of the memory controller represented by iMC150.

[0026] In one example, system 100 includes an NVM (Non-Volatile Medium) 180 coupled to SOC 110 via a platform controller 160. The NVM 180 represents non-volatile memory, including a medium 182 (which is the NVM medium) and a controller 184 that controls access to the medium 182. In one example, the NVM 180 is a memory device coupled to SOC 110 by peripheral connections such as PCIe (Peripheral Component Interconnect Express) or NVMe (Non-Volatile Memory Express). PCIe may conform to PCI Express Basic Specification Revision 4.0, first released by PCI-SIG in October 2017, PCI Express Basic Specification Revision 5.0, first released by PCI-SIG in May 2019, or a variation thereof. NVMe may conform to the NVMe Express Basic Specification, first released by NVM Express Inc. in June 2019, or a variation thereof.

[0027] In one example, system 100 includes main memory 190, which provides primary system memory. Main memory 190 typically includes a volatile medium 196 for storing data in a non-volatile manner. In one example, main memory 190 includes an NVM medium 192 and a controller 194 that controls access to the NVM medium 192 or the volatile medium 196, or access to both the NVM medium 192 and the volatile medium 196. Controller 194 represents a memory-side controller that manages operations on memory in response to the receipt of commands or I / O (input / output) operations.

[0028] In one example, secondary memory 170 contains byte-addressable non-volatile memory managed by a coherent interface. In another example, iMC 140 connects to secondary memory 170 via a CXL.mem interface such as the CXL Cache / Memory Protocol Interface (CPI) standard, such as CXL2.0 or CXL3.0. Medium 172 represents the storage medium of secondary memory 170. Controller 174 represents the memory-side controller that manages operations on memory in response to command reception or I / O operations.

[0029] The multilevel memory system of System 100 may be configured in one of several ways, depending on which memory resources are included and how those memory resources are used. Not all implementation examples of System 100 include all the memory types shown. System 100 shows various possible variations of memory that can be used in a multilevel system.

[0030] In one example, a reference to an NVM medium may refer to a block-addressable or byte-addressable memory device, such as a three-dimensional crosspoint memory device or other non-volatile memory device. In one example, an NVM medium may include a non-volatile block-addressable or byte-addressable medium that stores data based on the resistive state or phase of a memory cell. In one example, the memory device may use a chalcogenide-based phase-change material (e.g., chalcogenide glass). In one example, the memory device may be, or include, a single-level or multi-level phase-change memory (PCM) or switched phase-change memory (PCMS), resistive random-access memory, nanowire memory, ferroelectric transistor random-access memory (FeTRAM), magnetoresistive random-access memory (MRAM) incorporating memristor technology, or spin-transfer-to-reverse (STT) MRAM, or any combination of the above.

[0031] Generally, when the secondary memory 170 of system 100 is used as higher-level or second-level memory (e.g., 2LM implementation), system 100 primarily stores data in main memory 190, and while the secondary memory 170 can be useful for expanding the storage capacity of system memory, it may have potentially slower access times or longer latency compared to main memory 190.

[0032] In one example, secondary memory 170 represents an NVDIMM (Non-Volatile Dual In-Line Memory Module) containing a non-volatile medium interfaced with the system memory bus. The NVDIMM may contain any type of byte-addressable or block-addressable medium. In one example, secondary memory 170 represents a 3D crosspoint (3DXP) memory device. In another example, secondary memory 170 represents an Optane DIMM. Optane is a registered trademark of Intel Corporation. Optane contains memory that can be accessed by the system bus as byte-addressable memory.

[0033] As described above, in one example, secondary memory 170 can interface with SOC 110 via a coherent interface such as a coherent CXL.mem interface. Processor 112 may represent the CPU (Central Processing Unit) of the computing device. Due to the CPU's MOV instruction or SFENCE, the processor will wait for data or data commitment from the coherent CXL.mem device. The CPU core 120 cannot handle interrupts while waiting for the completion of those instructions. Therefore, as a coherent device in a low link state (e.g., a link state with a high termination delay) and a low device power state (including low power states such as the D3 state) the processor 112 Secondary memory 170 Load or SFENCE Departure If you do, Conventional This would cause processor 112 to stall or encounter a runtime error. If the device state is shallow (e.g., a low-latency termination state), a stall will not occur due to synchronous access by processor 112, and the device will be retrained or woken to process requests from processor 112.

[0034] In one example, processor 112 runs a memory manager (MEM MGR) 128 as part of the host OS. In another example, processor 112 runs a memory driver (MEM DRVR) 124. Together, the memory manager 128 and memory driver 124 provide memory control to a coherent memory device. The memory driver 124 represents a driver or software run by processor 112 to manage the hardware interface of memory. In one example, the memory driver 124 includes control logic to interface with secondary memory 170 as a coherent memory device. Processor 112 also includes a driver (DRVR) 126, which represents one or more other device drivers run by processor 112. Driver 126 may represent a driver for another coherent device included in system 100.

[0035] In one example, the memory manager 128 and memory driver 124 manage the low-power state of a coherent device or coherent device link. More specifically, memory control can modify the page table entry for the address space of secondary memory 170 (or other coherent memory in system 100). A modification of the page table entry may trigger a page fault, which involves fault handling by the processor 112 for the next request to secondary memory 170. Instead of synchronously waiting for secondary memory 170 to wake up and process the request, the processor 112 can asynchronously wait for secondary memory 170 to wake up based on fault handling. Such an operation would free up the processor 112 to perform other operations while secondary memory 170 is awake, thus avoiding a processor stall.

[0036] In one example, the memory manager 128 can determine the expected delay for a low-power state of coherent secondary memory 170. In another example, the memory manager 128 can determine whether the wake delay exceeds a configurable threshold. In yet another example, if the wake delay is less than the threshold, the memory manager 128 can determine that secondary memory 170 enters and exits a low-power state. As usual It may be possible to enable this. If the wake delay exceeds the threshold, the memory manager 128 can power-manage the low-power state by triggering a page fault for waking the device.

[0037] Figure 2 is a block diagram of an example system in which page table entries can be modified before coherent memory is placed in a low-power state. System 200 represents a system based on an example of System 100. System 200 shows multiple CPU cores, labeled CPU 210. The CPU or CPU core accesses memory 240, which represents memory with a coherent interface for access.

[0038] Details for only one CPU 210 are shown. Other CPUs may have the same or similar components as those shown in the detail diagram of one CPU. In one example, CPU 210 runs one or more application (APP) instances 212. An application instance 212 may contain any application that generates requests for data stored in memory 240. An application instance 212 can make resource requests, such as requests for access to memory 240, via an API (Application Programming Interface) 214.

[0039] In one example, a request from an application instance 212 using API 214 would result in one or more instances of driver 216. Driver 216 may include a user-mode driver for user data and a kernel-mode driver for system information. Driver 216 can manage access to memory 240, including access from low-power device states or low-power link states. The CPU 210 may be communicatively coupled to memory 240 by bus 230, which represents a high-speed communication connection between the CPU 210 and memory 240.

[0040] Memory 240 can store data for application instances 212, or for the operating system (OS) 220, or components or agents of the OS. Memory 240 can also store operational code and data resources for performing operations within the CPU 210. Operational code and data resources refer to the data and code that the CPU 210 needs to access to run the application or the OS 220. The OS 220 provides a software platform, including system hardware interface management and drivers, enabling applications to run while the OS accesses hardware resources in the computing environment. Drivers 216 represent drivers that run under the OS. In one example, the OS 220 includes a memory manager (MGR) 222 that manages the state of memory 240. The memory manager 222 can prevent the CPU 210 from stalling by determining when access to memory 240 can enter a low-power state through interface processing.

[0041] In one example, memory 240 includes a memory interface 242. In another example, the memory interface 242 is a CXL.mem interface. As a coherent memory device, the CPU 210 will wait for I / O operations to be completed by the memory before performing any other operations. The controller 244 of memory 240 represents the controller of the memory device and manages memory device-specific operations. Array 246 represents the storage array for memory 240. In one example, array 246 provides byte-addressable memory. In another example, array 246 represents volatile memory. In yet another example, array 246 represents non-volatile memory.

[0042] The CPU 210's page table 224 represents information managed by the OS 220, such as the file system or memory manager 222, and indicates the location of data and code stored in memory. More specifically, the page table 224 indicates the state of data in memory. The page table can indicate whether a reference is available for the data, and whether the data is available or whether the access descriptor needs to be refreshed for the data.

[0043] The TLB (Translation Lookaside Buffer) 226 represents the logic that provides address translation to the OS and applications of the CPU 210. The translation can indicate how handles for data in the OS are mapped to the address space of memory 240. In one example, the translation may include a mapping table to the physical addresses of the requested data. The TLB 226 can perform translations for virtual memory interfaces.

[0044] In one example, driver 216 includes a memory driver that manages access to coherent memory 240. In one example, memory manager 222 can modify page table 224 before triggering memory 240 to enter a low-power state. In one example, driver 216 does not put memory 240 into a low-power state without first determining whether memory manager 222 needs to modify the page table.

[0045] In the following examples, CXL.mem will be used as an example of a coherent memory interface. These examples are for illustrative purposes only, and it should be understood that coherent interfaces are not limited to CXL.mem. In one example, OS220 can determine, through memory manager 222 and driver 216, whether low-power state management by CXL.mem is required.

[0046] In one example, the memory manager 222 determines whether the low-power state satisfies a given termination delay criterion. If the low-power state satisfies this delay criterion, the memory manager 222 determines when memory 240 enters and exits this state. As usual It is permissible to allow this. Therefore, memory 240 will be woken up by PCIe / CXL access without any changes to page table 224.

[0047] In one example, the memory manager 222 determines whether a low-power state has an unacceptable termination delay for the system 200, because such a delay can lead to a stall of the CPU 210. In one example, the memory manager 222 always determines that an "off" state, such as the D3 state, has an unacceptable termination delay. For device states that would cause undesirable CPU delays, the memory manager 222 may modify the entries in the page table 224 before putting the memory 240 into a low-power state.

[0048] In general, a change to page table 224 can be considered a change that will trigger or generate a fault in response to the next access to memory 240. In one example, memory manager 222 invalidates an entry in page table 224 and then puts memory 240 into a low-power state. When the entry is invalidated, there is no translation for the address range of memory 240, which triggers a page fault. Memory manager 222 then calls the page fault handler, Originally Asynchronous operations of the synchronous interface may be enabled. An entry in page table 224 can be disabled without deleting the entry from page table 224.

[0049] In one example, the memory manager 222 determines that memory 240 has been idle for at least a threshold period and decides to allow memory 240 to enter a low-power state. The threshold period may be a period set by an OS policy. In one example, this period is configurable. This period may vary depending on the device and system configuration. Typically, memory traffic is not visible to software or drivers. In one example, the driver 216 periodically polls or queries memory 240 via a management interface (for example, the device reports the elapsed time since the last memory access) to determine how long the memory has been idle.

[0050] In one example, the memory manager 222 checks if any pages in the HPA (Host Physical Address) range of CXL.mem are locked. These pages may be locked for purposes such as DMA (Direct Memory Access). In one example, if any pages are locked, the memory manager 222 performs a low-power operation. Entering Stop the process and leave the device in a high-power state. In such cases, a shallow low-power state is acceptable, but a deep low-power state is not permitted.

[0051] In one example, memory manager 222 invalidates the HPA page table for CXL.mem in page table 224. In another example, memory manager 222 simply invalidates entries without deleting these tables. In another example, memory manager 222 performs a TLB shootdown with respect to addresses contained in TLB 226 corresponding to invalid addresses. In one example, system 200 maintains the first level or first-level page table entries of system memory. In another example, the OS clears the "current" bit in the table through memory manager 222. By clearing the "current" bit, the system forces a fault if the memory address space is being referenced, following the next access request to the address space of memory 240 by CPU 210. The A reference occurs.

[0052] In one example, the memory manager 222 edits one or more page table entries (PTEs). In one example, page table 224, Address for memory access Final physical address and flag give This represents the final stage of the page table hierarchy. Flags may include, for example, a flag for the valid bit. Disabling the PTE allows the address to remain in page table 224, thus preserving the page's physical address mapping table. Disabling a page does not delete the mapping table and require its creation; it simply invalidates the mapping table, which can then be re-enabled to allow access after the device awakens from low power.

[0053] The OS memory manager is Ma First-tier memory of multilevel memory inside Manages the first level of the full page table for CXL.mem Having an explicit policy (for example, from system startup) This is possible. Therefore, for example, the system may maintain a page table 224 in system memory, such as system memory 190 of system 100. The first level of host memory is page To check the table to Memory 240 fart access What to do HPA of CXL.mem to Access To prevent it from happening This can be ensured. After modifying page table 224, the memory manager 222 can instruct memory 240 to enter a low-power state (e.g., link state, device state, D3). In one example, OS220 saves the state of the CXL.mem object as being in a low-power state for future reference.

[0054] In one example, to wake memory 240 from a low-power state on the next or the next access to a memory address range, driver 216 can reference the CXL.mem virtual address which maps to the HPA of memory 240 in a low-power state. Without a valid translation for the HPA, the reference will result in a fault. In one example, erasing the current bit for a first-level page table entry will cause the reference to the address range to lead to a fault. In another example, the combination of no translation and the erased or reset current bit will trigger a fault. This fault occurs before the instruction is executed by CPU 210, thus preventing CPU 210 from stalling. The address that caused the fault will not be executed until the fault is handled. Therefore, CPU 210 can continue other work or handle interrupts. In one example, CPU 210 time-slices other operations along with fault handling.

[0055] In one example, a fault handler checks a low-power state flag. Low power state flag This may be saved by the OS memory manager, and the OS memory manager will store the flag Save 、 In the first level of system memory at Manage data. In one example, if the device is not low power, the memory manager can handle page table updates for page table 224. Such a process can be carried out according to normal page table service operations.

[0056] In one example, if the device is in a low-power state, the fault handler of the memory manager 222 requests the driver 216 to wake up memory 240. In another example, if memory 240 is in a powered-off state such as state D3, the driver 216, either the CXL.mem driver or the bus driver (driver for bus 230), calls an ACPI (Advanced Configuration and Power Interface) method to cause the platform to restore power to memory 240. After power is restored to memory 240, the memory manager 222 sets the PMCSR (Power Management Control and Status Register) to an active state. In one example, in conjunction with setting memory 240 to an active state, the memory manager 222 may re-enumerate powered-off devices to an active state (e.g., transition from D3 to D0). Once fully powered on, the decoder and interface hardware are reinitialized, and the system can notify the CPU 210 of a fault, allowing this CPU to handle the fault exception.

[0057] If memory 240 is in an ultra-low power link state or ultra-low power device state but is not powered off, in one example, driver 216 will Show A management wake command can be issued. For example, driver 216 can interrupt Completed by Completed to cause You can issue commands that do nothing or arbitrary management commands. Management, such as fault handling, is understood as an asynchronous management interface.

[0058] By triggering the asynchronous management interface, the expected synchronization of the coherent interface is achieved. behavior Therefore, this behavior is removed. An example of an asynchronous management interface may be a CXL management process with MSI-X (Extended Message Signaled Interrupt) enabled. Using an asynchronous management command interface, the fault handler is (For example, via the CXL driver) , Requesting an administrative command,By means of an interrupt The until the completion of an operation is notified, system can be perform Letting go ed child . An interrupt can trigger the CPU to access the memory 240 again.

[0059] In response to an interrupt, the memory 240 will be considered to be in a fully awake state together with an active link, active device power, an active interface, and the like. Then the memory 240 enters a state where it can respond to requests. In one example, a fault handling event is set, and the remaining fault handling by the memory manager occurs. In one example, the driver 216 indicates to the CPU 210 that a fault exception has been handled, and the CPU can start processing the memory access.

[0060] It has been described above that pages are locked for DMA. It will be understood that the fault handling that triggers an asynchronous operation functions when the CPU 210 generates an access. However, DMA generally does not generate a fault. Therefore, when a page is mapped to DMA for a CXL device, in one example, the system 200 does not allow the CXL device to enter a low power state. The system 200 may also reject DMA access to the CXL device, or may allow DMA to the CXL device, but does not allow the CXL device to enter a low power state.

[0061] The DMA engine typically wakes the device naturally, and the DMA engine has a timeout. If a device has a very long termination delay, it may take too long to wake up, which can cause a DMA failure. Since DMA operations are not CPU blocking events, DMA operations add a delay to termination delays within the DMA engine's timeout window without stalling the CPU. In normal CXL operations, the OS has complete control over access to the HPA range of CXL.mem, and the OS hides CXL.mem for its own system-wide useful purposes. Therefore, the content exchanged with the address range is left to the discretion of the OS and memory manager.

[0062] Figure 3 is a flowchart illustrating an example of a process for reducing the power consumption of coherent memory. Process 300 represents the process of placing a coherent device, such as memory, into a low-power state. Process 300 represents a process that may be executed by the system 200.

[0063] These operations are shown as being performed by components such as the host operating system's memory manager, drivers, and memory devices. In one example, the memory manager can be separated into various components, and different operations can be performed by the different components within the memory manager. In one example, one or more components shown for the memory manager may be performed by system components such as drivers.

[0064] In one example, the memory manager determines at 302 whether the memory has reached the idle threshold. In one example, if the idle threshold has not been reached, the process proceeds to the NO branch at 304, and since this operation can be returned to the start at 306, the process proceeds to the end of the operation. If the threshold has been reached, the process proceeds to the YES branch at 304, and in one example, the memory manager determines at 308 whether any pages for memory are locked.

[0065] If there are locked pages, the process proceeds to the YES branch at 310, and in one example, the memory manager can return to the start at 312, so the process proceeds to the end. If there are no locked pages, the process proceeds to the NO branch at 310, and in one example, the memory manager modifies the page table entry at 314 and invalidates that entry. The driver can then send a command at 316 to the memory device entering a low-power state.

[0066] The host (memory manager and driver) completes the operation to put the memory into a low-power state. At 318, the memory receives a power-down command or low-power command from the driver. The memory can then enter the low-power state at 320 according to the command.

[0067] Figure 4 is a flowchart illustrating an example of a process for waking coherent memory from a low-power state. Process 400 represents the process for waking a coherent device, such as memory, from a low-power state. Process 400 represents a process that may be executed by the system 200.

[0068] These operations are shown as being performed by components such as the host operating system's memory manager, drivers, and memory devices. In one example, the memory manager can be separated into various components, and different operations can be performed by the different components within the memory manager. In one example, one or more components shown for the memory manager may be performed by system components such as drivers.

[0069] In one example, the memory manager receives a request from the host processor at 402 and accesses coherent memory in a low-power state. In one example, if this access does not result in a page fault, the process proceeds to the NO branch at 404, and in one example, the memory manager can return to the start at 406 and proceed to the end of the processing operation. If this access results in a page fault, the process proceeds to the YES branch at 404, and in one example, the memory manager can check the device state at 408.

[0070] If the device is in an active state, branch 410 proceeds to the YES branch, and in one example, the memory manager performs normal fault handling at branch 412 to deal with the fault. The normal fault handling then executes the operation, and the process can proceed to its end. If the memory device is not in an active state, branch 410 proceeds to the NO branch, and in one example, the memory manager determines whether the device is in an ultra-low power state or simply a low power state.

[0071] If the device is not in an ultra-low power state (i.e., only in a low power state), the process proceeds to the NO branch at 414, and in one example, the driver issues a command at 416 to complete the interrupt handling. Interrupt handling complete means that the fault handler handles the access, which gives the device enough time to wake from the low power state. This process then proceeds to 412. keruThe system can then proceed to normal fault handling.

[0072] If the device is in an ultra-low power state, the process proceeds to the YES branch at 414. In one example, the driver performs a power management operation at 418 to power down or wake the memory from the ultra-low power state. In another example, the driver issues a command to the memory, and the memory receives this command and wakes from the low power state at 420. If the driver issues a command to the memory, processing proceeds to 412. keru The system can then proceed to normal fault handling.

[0073] Figure 5 is a block diagram of an example memory subsystem in which coherent low-power state management can be performed. System 500 includes the processor and memory subsystem elements within the computing device. System 500 is an example of a system, such as System 100 or System 200.

[0074] In one example, system 500 includes a CXL control 590, which represents power management control for a coherent implementation of memory device 540. The CXL control 590 can represent a memory manager and memory driver as in any of the examples described above. The CXL control 590 can manage a page table to trigger a page fault on the next access to memory device 540. Therefore, The Memory access may be handled by a fault routine. After modifying the page table, the CXL control 590 may trigger the memory device 540 to enter a low-power state, according to one of the examples herein.

[0075] The processor 510 represents the processing unit of a computing platform capable of running an operating system (OS) and applications, and is sometimes collectively referred to as the memory host or user. The OS and applications perform operations that result in memory access. The processor 510 may include one or more separate processors. Each separate processor may include a single processing unit, a multi-core processing unit, or a combination thereof. The processing unit may be a primary processor such as a CPU (Central Processing Unit), a peripheral processor such as a GPU (Graphics Processing Unit), or a combination thereof. Memory access may also be initiated by a device such as a network controller or a hard disk controller. Such a device may be integrated with the processor, connected to the processor via a bus (e.g., PCI Express), or a combination thereof, depending on the system. The system 500 may be implemented as a system-on-a-chip (SOC) or as multiple standalone components.

[0076] References to memory devices can apply to various memory types. Often, memory devices refer to volatile memory technology. Volatile memory is memory whose state (and therefore the data stored within it) becomes uncertain when the power supply to the device is cut off. Non-volatile memory is memory whose state remains certain even when the power supply to the device is cut off. Dynamically volatile memory requires refreshing the data stored in the device to maintain its state. One example of dynamically volatile memory includes DRAM (Dynamic Random Access Memory) or some derivative of synchronous DRAM (SDRAM). Memory subsystems described herein include DDR4 (Double Data Rate Version 4, JESD79-4: first published in September 2012 by JEDEC (Joint Council of Electronic Device Technology, now JEDEC Solid State Technology Association)), LPDDR4 (Low Power DDR Version 4, JESD209-4: first published in August 2014 by JEDEC), and WIO2 (Wide I / O). It may be compatible with several memory technologies, such as WideIO2 (JESD229-2: first published by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235A: first published by JEDEC in November 2015), DDR5 (DDR version 5: first published by JEDEC in July 2020), LPDDR5 (LPDDR version 5, JESD209-5: first published by JEDEC in February 2019), HBM2 (HBM version 2, JESD235C: first published by JEDEC in January 2020), or HBM3 (HBM version 3, currently under consideration by JEDEC), or combinations of these memory technologies, and technologies based on derivative or extended versions of such specifications.

[0077] In addition to volatile memory, or instead, in one example, the memory module may be a persistent memory DIMM or non-volatile system memory, which refers to non-volatile memory connected to a system memory bus. Such memory devices may include three-dimensional crosspoint (3DXP) memory devices. 3DXP can operate as a byte-addressable or block-addressable non-volatile memory device. The memory device may include a non-volatile byte-addressable or block-addressable medium that stores data based on the resistive state of the memory cells or the phase of the memory cells. In one example, the memory device may use a chalcogenide phase-change material (e.g., chalcogenide glass). In one example, the system memory device may be, or may include, a memory such as NAND flash memory for persistent random access memory, NOR flash memory for persistent random access memory, single-level or multi-level phase-change memory (PCM) or switched phase-change memory (PCMS), resistive random-access memory, nanowire memory, ferroelectric transistor random-access memory (FeTRAM), magnetoresistive random-access memory (MRAM) incorporating memristor technology, or spin-transfer-to-reverse (STT) MRAM, or any combination of the above.

[0078] The memory controller 520 represents one or more memory controller circuits or devices of the system 500. The memory controller 520 represents control logic that generates memory access commands in response to operations performed by the processor 510. The memory controller 520 accesses one or more memory devices 540. The memory devices 540 may be DRAM devices as described above. In one example, the memory devices 540 are organized and managed as various channels. Each channel is coupled to buses and signal lines coupled in parallel to multiple memory devices. Each channel can operate independently. Thus, each channel is accessed and controlled independently, with separate timing, data transfer, command and address exchange, and other operations for each channel. Coupling may refer to electrical coupling, communicative coupling, physical coupling, or a combination thereof. Physical coupling may include direct contact. Electrical coupling includes interfaces or interconnections that enable the flow of electricity between components, or enable signaling between components, or both. Communicative coupling includes connections, including wired or wireless, that enable data exchange between components.

[0079] In one example, channel-specific settings are controlled by register settings, such as separate mode registers. In one example, each memory controller 520 manages a separate memory channel, but the system 500 can be configured to have multiple channels managed by a single controller, or to have multiple controllers on a single channel. In one example, the memory controller 520 is part of the host processor 510, such as being implemented on the same die as the processor or as logic implemented in the same package space.

[0080] The memory controller 520 includes I / O interface logic 522 coupled to a memory bus such as the memory channel described above. The I / O interface logic 522 (and the I / O interface logic 542 of the memory device 540) may include hardware such as pins, pads, connectors, signal lines, wiring, or wires, or a combination thereof, that connect the devices to each other. The I / O interface logic 522 may include a hardware interface. As shown, the I / O interface logic 522 includes at least a driver / transceiver for the signal lines. Generally, wires in an integrated circuit interface are coupled to pads, pins, or connectors to interface wires such as signal lines or wiring between devices. The I / O interface logic 522 may include circuitry such as drivers, receivers, transceivers, or terminators, or a combination of circuits, that exchange signals on the signal lines between devices. Signal exchange includes at least one of transmission or reception. Although I / O 522 is shown to connect from the memory controller 520 to the I / O 542 of the memory device 540, in one implementation example of system 500 where a group of memory devices 540 are accessed in parallel, it will be understood that multiple memory devices may have I / O interfaces to the same interface of the memory controller 520. In one implementation example of system 500 including one or more memory modules 570, I / O 542 may include the interface hardware of the memory modules in addition to the interface hardware of the memory devices themselves. Other memory controllers 520 would have separate interfaces to other memory devices 540.

[0081] The bus between the memory controller 520 and the memory device 540 may be implemented as a set of signal lines connecting the memory controller 520 to the memory device 540. The bus may typically include at least a clock (CLK) 532, a command / address (CMD) 534, write data (DQ) and read data (DQ) 536, and zero or more other signal lines 538. In one example, the bus or connection between the memory controller 520 and the memory may be called the memory bus. In one example, the memory bus is a multidrop bus. The signal lines for CMD may be called the "C / A bus" (or ADD / CMD bus, or whatever other name indicates the transfer of command (C or CMD) and address (A or ADD) information), and the signal lines for write DQ and read DQ may be called the "data bus". In one example, each independent channel has a different clock signal, C / A bus, data bus, and other signal lines. Therefore, system 500 may be considered to have multiple “buses,” in the sense that independent interface paths may be considered separate buses. It will be understood that a bus may include, in addition to the explicitly indicated lines, at least one of the following signal lines, or combinations thereof, such as strobe signal lines, alert lines, and auxiliary lines. It will also be understood that serial bus technology may be used for the connection between the memory controller 520 and the memory device 540. An example of serial bus technology is 5B10B encoding and high-speed data transmission using an embedded clock in each direction via a single differential pair of signals. In one example, CMD534 represents signal lines shared in parallel with multiple memory devices. In one example, multiple memory devices share the encoding command signal lines of CMD534, each having a separate chip selection (CS_n) signal line for selecting individual memory devices.

[0082] In the example of system 500, it will be understood that the bus between the memory controller 520 and the memory device 540 includes an auxiliary command bus CMD 534 and an auxiliary bus DQ 536 for carrying write and read data. In one example, the data bus may include bidirectional lines for read data and write / command data. In another example, the auxiliary bus DQ 536 may include unidirectional write signal lines for writing from the host to memory and for data, and unidirectional lines for reading data from memory to the host. Depending on the selected memory technology and system design, other signals 538 may accompany the bus or subbus, such as the strobe line DQS. Based on the design of system 500, or the implementation examples if a design example supports multiple implementation examples, the data bus may have some bandwidth per memory device 540. For example, the data bus can support memory devices having any of the following interfaces: x4 interface, x8 interface, x16 interface, etc. In the conventional expression "xW," W is an integer representing the interface size or interface width of the memory device 540, which represents the number of signal lines that exchange data with the memory controller 520. The interface size of the memory device is a control factor regarding how many memory devices can be used simultaneously per channel of the system 500, or how many can be coupled in parallel on the same signal line. For example, high-bandwidth memory devices, wide interface devices, or stacked memory configurations, or a combination thereof, can enable wider interfaces such as data bus interface widths like x128, x256, x512, and x1024 interfaces.

[0083] In one example, memory devices 540 and memory controller 520 exchange data over a data bus in bursts or in sequences of continuous data transfers. A burst corresponds to a number of transfer cycles, and a transfer cycle is related to the bus frequency. In one example, a transfer cycle may be the entire clock cycle of transfers occurring on the same clock or strobe signal edge (e.g., rising edge). In one example, all clock cycles referencing the system clock cycle are separated into multiple unit intervals (UIs), each UI being a transfer cycle. For example, a double data rate transfer is triggered on both edges of the clock signal (e.g., rising and falling). A burst can last for a set number of UIs, which may be a configuration stored in a register or a configuration triggered at runtime. For example, a sequence of eight consecutive transfer periods may be considered a burst length of 8 (BL8), and each memory device 540 can transfer data in each UI. Therefore, an x8 memory device operating on BL8 can transfer 64 bits of data ([8 data signal lines] × [8 data bits transferred per line during a burst]). It should be understood that this simple example is merely illustrative and not limiting.

[0084] The memory devices 540 represent the memory resources of the system 500. In one example, each memory device 540 is a separate memory die. In another example, each memory device 540 may interface with multiple (e.g., two) channels per device or die. Each memory device 540 includes I / O interface logic 542, which has a bandwidth (e.g., x16 or x8 or some other interface bandwidth) determined by the device implementation. The I / O interface logic 542 enables the memory device to interface with the memory controller 520. The I / O interface logic 542 may include a hardware interface, which on the memory device side may follow the I / O 522 of the memory controller. In one example, multiple memory devices 540 are connected in parallel to the same command bus and data bus. In another example, multiple memory devices 540 are connected in parallel to the same command bus and to different data buses. For example, the system 500 may consist of multiple memory devices 540 connected in parallel, each memory device responding to commands and accessing its own internal memory resources 560. During a write operation, each memory device 540 can write a portion of the entire data word, and during a read operation, each memory device 540 can fetch a portion of the entire data word. The remaining bits of this word will be provided or received in parallel by other memory devices.

[0085] In one example, the memory device 540 is located directly on the motherboard or host system platform of the computing device (e.g., the PCB (printed circuit board) on which the processor 510 is located). In one example, these memory devices 540 may be organized into a memory module 570. In one example, the memory module 570 represents a dual inline memory module (DIMM). In another example, the memory module 570 represents another organization of multiple memory devices that share at least some of their access or control circuits, and this circuit may be a separate circuit, a separate device, or a separate board from the host system platform. The memory module 570 may contain multiple memory devices 540, and the memory module may include support for multiple separate channels to the memory devices located and contained therein. In another example, the memory device 540 may be incorporated into the same package as the memory controller 520 by means of techniques such as a multi-chip module (MCM), package-on-package, through-silicon vibrator (TSV), or a combination thereof. Similarly, in one example, multiple memory devices 540 may be incorporated into a memory module 570, and these memory devices themselves may be incorporated into the same package as the memory controller 520. In those implementations and other implementations, it will be understood that the memory controller 520 may be part of the host processor 510.

[0086] Each memory device 540 contains one or more memory arrays 560. Each memory array 560 represents an addressable memory location or storage location for data. Typically, a memory array 560 is managed as rows of data accessed by the control of word lines (rows) and bit lines (individual bits within a row). A memory array 560 may be organized as separate channels, ranks, and banks of memory. A channel may refer to an independent control path to a storage location within the memory device 540. A rank may refer to a location common across multiple parallel memory devices (e.g., the same row address across different devices). A bank may refer to a subarray of memory locations within the memory device 540. In one example, a bank of memory may be divided into multiple subbanks, each having at least some shared circuitry (e.g., drivers, signal lines, control logic) to enable separate addressing and access. It will be understood that memory location organization, such as channels, ranks, banks, subbanks, and bank groups, and combinations of these organization, may overlap when applying them to physical resources. For example, the same physical memory location may be accessed as a specific bank on a specific channel, and this bank may also belong to a rank. Therefore, the organization of memory resources will be understood in an inclusive rather than exclusive manner.

[0087] In one example, the memory device 540 includes one or more registers 544. The registers 544 represent one or more storage devices or storage locations that provide configuration or settings for the operation of the memory device. In one example, the registers 544 may provide storage locations in the memory device 540 that store data accessed by the memory controller 520 as part of a control or management operation. In one example, the registers 544 include one or more mode registers. In another example, the registers 544 include one or more multipurpose registers. Configurations of locations within the registers 544 allow the memory device 540 to be configured to operate in various "modes." Based on these modes, command information can trigger various operations within the memory device 540. Alternatively, the various modes can also trigger various operations from signal lines, such as address information, depending on the mode. The settings in the registers 544 can indicate configurations of I / O settings (e.g., I / O settings such as timing, terminators or ODTs (on-die terminators) 546, and driver configurations).

[0088] In one example, memory device 540 includes ODT546 as part of the interface hardware associated with I / O 542. The ODT546, configured as described above, can provide impedance settings applied to the interface to specified signal lines. In one example, the ODT546 is applied to the DQ signal line. In another example, the ODT546 is applied to the command signal line. In yet another example, the ODT546 is applied to the address signal line. In yet another example, the ODT546 can be applied to any combination of the above. The ODT setting may be modified based on whether the memory device is a selectable or excluded device for access operations. The ODT546 setting may affect the timing and reflection of signaling at the termination lines. Precise control by the ODT546 can improve the matching of applied impedance with the load, potentially enabling faster operation. The ODT546 may be applied to specific signal lines of I / O interfaces 542, 522 (e.g., ODT for DQ lines or ODT for CA lines), but not necessarily to all signal lines.

[0089] The memory device 540 includes a controller 550, which represents the control logic within the memory device that controls internal operations within the memory device. For example, the controller 550 decodes commands sent by the memory controller 520 and generates internal operations that execute or satisfy those commands. The controller 550 is sometimes called an internal controller and is separate from the host memory controller 520. The controller 550 determines which mode is selected based on register 544 and, based on the selected mode, can configure the internal execution of operations such as operations that access memory resources 560. The controller 550 generates control signals to control the routing of bits within the memory device 540, providing an appropriate interface to the selected mode and sending commands to the appropriate memory location or address. The controller 550 includes command logic 552, which can decode command encodings received on the command signal line and address signal line. Thus, the command logic 552 may be a command decoder or include one. Using the command logic 552, the memory device can identify commands and generate internal operations that execute the requested commands.

[0090] Referring again to the memory controller 520, the memory controller 520 includes command (CMD) logic 524, which represents logic or circuitry that generates commands to send to the memory device 540. Command generation can refer to commands before scheduling, or preparing a queue command to be sent. In general, signaling in a memory subsystem includes address information in or accompanying a command to indicate or select one or more memory locations where the memory device should execute the command. In response to scheduling for transactions of the memory device 540, the memory controller 520 can issue commands via I / O 522 to cause the memory device 540 to execute the commands. In one example, the controller 550 of the memory device 540 receives and decodes the command and address information received from the memory controller 520 via I / O 542. Based on the received command and address information, the controller 550 can control the timing of the operation of the logic and circuitry within the memory device 540 to execute the command. The controller 550 is responsible for ensuring compliance with standards or specifications within the memory device 540, such as timing and signaling requirements. The memory controller 520 can enforce compliance with standards or specifications by scheduling and controlling access.

[0091] The memory controller 520 includes a scheduler 530, which represents logic or circuitry that generates and sequentially sends transactions to the memory device 540. From one perspective, the primary function of the memory controller 520 is sometimes said to be scheduling memory access to the memory device 540 and other transactions. Such scheduling may include generating the transactions themselves to carry out data requests by the processor 510 and maintaining data integrity (e.g., using refresh-related commands). A transaction may consist of one or more commands and may result in the transfer of commands or data, or both, in one or more timing cycles, such as a clock cycle or a unit interval. A transaction may be for access, such as a read command or a write command or related commands or a combination thereof, and other transactions may include memory management commands for configuration, setting, data integrity, or a combination thereof.

[0092] The memory controller 520 typically includes logic such as a scheduler 530 that enables the selection and ordering of transactions to improve the performance of the system 500. Thus, the memory controller 520 can select which of the pending transactions should be sent to the memory device 540 and in what order, which is usually achieved with logic far more complex than a simple first-in, first-out algorithm. The memory controller 520 manages the sending of transactions to the memory device 540 and manages the timing associated with transactions. In one example, a transaction has deterministic timing, which is managed by the memory controller 520 and may be used when determining how to schedule the transaction in the scheduler 530.

[0093] In one example, the memory controller 520 includes refresh (REF) logic 526. Because the refresh logic 526 is volatile, it may be used for memory resources that need to be refreshed to maintain a deterministic state. In one example, the refresh logic 526 indicates the location of the refresh and the type of refresh to perform. The refresh logic 526 can trigger a self-refresh within the memory device 540, or it can perform an external refresh (sometimes called an automatic refresh command) by sending a refresh command, or a combination of both. In one example, the controller 550 within the memory device 540 includes refresh logic 554 that applies a refresh within the memory device 540. In one example, the refresh logic 554 generates an internal operation to perform a refresh according to an external refresh received from the memory controller 520. The refresh logic 554 can determine whether the refresh targets the memory device 540 and which memory resources 560 should be refreshed in response to the command.

[0094] Figure 6 is a block diagram of an example of a computing system in which coherent low-power state management can be performed. System 600 represents a computing device according to any example herein, which may be an electronic device such as a laptop computer, desktop computer, tablet computer, server, game or entertainment control system, or embedded computing device.

[0095] System 600 represents a system according to an example of System 100 or System 200. In one example, System 600 includes a CXL control 690, which represents power management control of a coherent implementation of memory 630. The CXL control 690 can represent a memory manager and memory driver according to any of the examples described above. The CXL control 690 manages the page table so that a page fault can be triggered on the next access to memory 630. Thus, memory access can be handled by a fault routine. After modifying the page table, the CXL control 690 can trigger memory 630 to enter a low-power state according to any example herein.

[0096] System 600 includes a processor 610, which may include processing hardware such as any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or a combination thereof, and brings about the processing or execution of instructions of System 600. Processor 610 may be a host processor device. Processor 610 controls the overall operation of System 600 and may be, or include, one or more programmable general-purpose microprocessors or dedicated microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or a combination of such devices.

[0097] System 600 includes Boot / Setup 616, which represents system-level hardware operating outside the host OS, such as boot code (e.g., Basic Input / Output System (BIOS)), storage for configuration settings, and security hardware (e.g., Trusted Platform Module (TPM)). Boot / Setup 616 may also include non-volatile storage devices such as read-only memory (ROM) and memory devices such as flash memory.

[0098] In one example, system 600 includes an interface 612 coupled to processor 610, which may represent a high-speed or high-throughput interface to system components requiring higher bandwidth connectivity, such as a memory subsystem 620 or a graphics interface component 640. Interface 612 represents an interface circuit, which may be a standalone component or integrated on the processor die. Interface 612 may be integrated as a circuit on the processor die or as a component on the system-on-chip. If present, graphics interface 640 interfaces to a graphics component that provides a visual display to the user of system 600. Graphics interface 640 may be a standalone component or integrated on the processor die or on the system-on-chip. In one example, graphics interface 640 may drive a high-definition (HD) or ultra-high-definition (UHD) display that provides output to the user. In one example, this display may include a touchscreen display. In one example, the graphics interface 640 generates a display based on data stored in memory 630, or based on operations performed by the processor 610, or both.

[0099] The memory subsystem 620 represents the main memory of the system 600 and provides storage for code executed by the processor 610 or for data values ​​used when executing routines. The memory subsystem 620 may include one or more memory devices 630, such as read-only memory (ROM), flash memory, DRAM, one or more different random access memories (RAM), 3DXP (3D Crosspoint), or a combination of such devices. Memory 630, among other things, stores and hosts the operating system (OS) 632, providing a software platform for executing instructions in the system 600. Furthermore, applications 634 may be executed from memory 630 on the software platform of OS 632. An application 634 represents a program with its own operational logic that performs one or more functions. A process 636 represents an agent or routine that provides auxiliary functions to OS 632 or one or more applications 634, or a combination thereof. OS 632, applications 634, and processes 636 provide the software logic that provides each function to the system 600. In one example, the memory subsystem 620 includes a memory controller 622, which is a memory controller that generates commands and issues those commands to memory 630. It will be understood that the memory controller 622 may be a physical part of the processor 610 or a physical part of interface 612. For example, the memory controller 622 may be an integrated memory controller that is integrated into the circuit with the processor 610, such as being integrated on the processor die or system-on-chip.

[0100] Although not specifically indicated, it will be understood that System 600 may include one or more buses or bus systems between devices, such as a memory bus, graphics bus, and interface bus. Signal lines such as buses can connect components to each other either communicatively or electrically, or can connect components both communicatively and electrically. These buses may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or combinations thereof. These buses may include one or more of the following buses or combinations thereof, such as a system bus, Peripheral Component Interconnect (PCI) bus, Hypertransport or Industry Standard Architecture (ISA) bus, Small Computer System Interface (SCSI) bus, Universal Serial Bus (USB), etc.

[0101] In one example, system 600 includes interface 614, which may be coupled to interface 612. Interface 614 may be a slower interface than interface 612. In one example, interface 614 represents an interface circuit, which may include standalone components and integrated circuits. In one example, multiple user interface components or peripheral components, or both, are coupled to interface 614. Network interface 650 provides system 600 with the ability to communicate with remote devices (e.g., computing devices such as servers) over one or more networks. Network interface 650 may include wired or wireless standard-based interfaces or dedicated interfaces such as Ethernet® adapters, wireless interconnect components, cellular network interconnect components, and USB (Universal Serial Bus). Network interface 650 can exchange data with remote devices, and data exchange may include sending data stored in memory or receiving data stored in memory.

[0102] In one example, system 600 includes one or more input / output (I / O) interfaces 660. The I / O interfaces 660 may include one or more interface components through which the user interacts with system 600 (e.g., audio, alphanumeric, tactile / touch interface connections). Peripheral interfaces 670 may include any hardware interfaces not specifically described above. Peripheral devices generally refer to devices that are dependently connected to system 600. A dependent connection is one in which system 600 provides a software platform, a hardware platform, or both, on which operations are performed, and on which the user interacts.

[0103] In one example, system 600 includes a storage subsystem 680 for storing data in a non-volatile manner. In one example, in several system implementations, at least some components of storage 680 may overlap with components of memory subsystem 620. Storage subsystem 680 includes a storage device 684, which may be or include any conventional medium, such as one or more magnetic media, solid media, 3DXP media, or optical-based disks, or a combination thereof, for storing large amounts of data in a non-volatile manner. Storage 684 holds code or instructions and data 686 in a persistent state (i.e., its values ​​are retained even if power to system 600 is cut off). Storage 684 is often considered "memory," but memory 630 is typically execution memory or operating memory that provides instructions to processor 610. While storage 684 is non-volatile, memory 630 may include volatile memory (i.e., the values ​​or state of data become indeterminate if power to system 600 is cut off). In one example, the storage subsystem 680 includes a controller 682 that interfaces with the storage 684. In another example, the controller 682 may be a physical part of the interface 614 or the processor 610, or it may include circuitry or logic in both the processor 610 and the interface 614.

[0104] Power supply 602 supplies power to each component of system 600. More specifically, power supply 602 typically interfaces with one or more power supply devices 604 of system 600 to supply power to each component of system 600. In one example, power supply device 604 includes an AC / DC (alternating current / direct current) adapter that plugs into a wall outlet. Such an AC power source may also be power supply 602 powered by renewable energy (e.g., solar energy). In one example, power supply 602 includes a DC power source, such as an external AC / DC converter. In one example, power supply 602 or power supply device 604 includes wireless charging hardware that charges by being brought near a charging station. In one example, power supply 602 may include a built-in battery or fuel cell power source.

[0105] Figure 7 is a block diagram of an example of a mobile device in which coherent low-power state management can be implemented. System 700 represents a mobile computing device such as a computing tablet, mobile phone or smartphone, wearable computing device, or embedded computing device. Some components are shown in general terms, and it will be understood that not all components of such a device are shown in System 700. System 700 is one example of a system that can incorporate a system compatible with System 100 or System 200.

[0106] In one example, the memory subsystem 760 includes memory 762, which may include one or more coherent memory resources identified as coherent memory 792. In another example, the system 700 includes OS 790 with CXL control 794, which represents power management control of coherent memory 792. CXL control 794 can represent a memory manager and memory driver according to any of the examples described above. CXL control 794 manages a page table so that a page fault is triggered on the next access to coherent memory 792. Thus, memory access can be handled by a fault routine. After modifying the page table, CXL control 794 can trigger coherent memory 792 to enter a low-power state according to any of the examples herein.

[0107] System 700 includes a processor 710, which performs the main processing operations of System 700. The processor 710 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, or programmable logic device. Processing operations performed by the processor 710 include the execution of an operating platform or operating system on which applications and device functions are executed. Processing operations include operations related to I / O (input / output) with human users or other devices, operations related to power management, operations related to connecting System 700 to other devices, or a combination thereof. Processing operations may also include operations related to interface connections, such as audio I / O and display I / O, or a combination thereof. The processor 710 can execute data stored in memory. The processor 710 can write data to memory or edit data stored in memory.

[0108] In one example, system 700 includes one or more sensors 712. Sensor 712 represents an interface to an embedded sensor or an external sensor, or a combination thereof. Sensor 712 enables system 700 to monitor or detect one or more conditions relating to the environment or device in which system 700 is implemented. Sensor 712 may include environmental sensors (such as temperature sensors, motion detectors, photodetectors, cameras, chemical sensors (e.g., carbon monoxide sensors, carbon dioxide sensors, etc.)), pressure sensors, accelerometers, gyroscopes, medical sensors, or physiological sensors (e.g., biosensors, sensors that detect physiological attributes such as heart rate monitors), or combinations thereof. Sensor 712 may also include sensors for biometric authentication systems, such as fingerprint recognition systems, face detection systems, or facial recognition systems, which detect or recognize user features. Sensor 712 should be understood broadly and not limited to the many different types of sensors that may be implemented using system 700. In one example, one or more sensors 712 are coupled to the processor 710 via a front-end circuit integrated with the processor 710. In another example, one or more sensors 712 are coupled to the processor 710 via another component of the system 700.

[0109] In one example, system 700 includes an audio subsystem 720, which represents the hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. Audio functionality may include output through speakers or headphones and input through a microphone. Devices for such functionality may be integrated into system 700 or connected to system 700. In one example, a user interacts with system 700 by providing audio commands that are received and processed by processor 710.

[0110] The display subsystem 730 represents hardware components (e.g., display devices) and software components (e.g., drivers) that provide a visual display to present to the user. In one example, the display includes tactile components or touchscreen elements for the user to interact with the computing device. The display subsystem 730 includes a display interface 732, which includes a specific screen or hardware device used to provide a display to the user. In one example, the display interface 732 includes logic (such as a graphics processor) separate from the processor 710 that performs at least some display-related processing. In one example, the display subsystem 730 includes a touchscreen device that provides both output and input to the user. In one example, the display subsystem 730 includes a high-definition (HD) or ultra-high-definition (UHD) display that provides output to the user. In one example, the display subsystem includes or drives a touchscreen display. In one example, the display subsystem 730 generates display information based on data stored in memory, or based on operations performed by the processor 710, or both.

[0111] The I / O controller 740 represents hardware devices and software components related to user interaction. The I / O controller 740 can operate to manage hardware that is part of the audio subsystem 720 or the display subsystem 730, or both. Furthermore, the I / O controller 740 indicates connection points for additional devices that connect to the system 700, through which the user can interact with the system. For example, devices that may connect to the system 700 may include other I / O devices such as microphone devices, speakers or stereo systems, display devices such as video systems, keyboards or keypad devices, buttons / switches, or card readers used with specific applications.

[0112] As described above, the I / O controller 740 can interact with the audio subsystem 720, the display subsystem 730, or both. For example, it can provide input or commands to one or more applications or functions of the system 700 via an audio device such as a microphone. Furthermore, audio outputs may be provided instead of, or in addition to, the display outputs. In another example, if the display subsystem includes a touchscreen, the display device may also function as an input device and may be managed at least partially by the I / O controller 740. The system 700 may also have additional buttons or switches to provide I / O functions managed by the I / O controller 740.

[0113] In one example, the I / O controller 740 manages devices such as hardware or sensors 712 that may be included in system 700, including environmental sensors such as accelerometers, cameras, and light sensors, as well as gyroscopes and the Global Positioning System (GPS). Inputs can be part of direct user interaction, as well as environmental inputs that affect system operation (such as filtering noise, adjusting the display for brightness detection, or applying a flash to a camera).

[0114] In one example, system 700 includes a power management unit 750 that manages functions related to battery power usage, battery charging, and power-saving operations. Power management unit 750 manages power from a power supply unit 752 that powers each component of system 700. In one example, power supply unit 752 includes an AC / DC (alternating current / direct current) adapter that plugs into a wall outlet. Such an AC power supply may be renewable energy (e.g., solar energy, motion-based energy). In one example, power supply unit 752 includes only DC power, which may be supplied by an external DC power supply such as an AC / DC converter. In one example, power supply unit 752 includes wireless charging hardware that charges by being brought close to a charging area. In one example, power supply unit 752 may include a built-in battery or fuel cell power supply.

[0115] The memory subsystem 760 includes a memory device 762 for storing information in the system 700. The memory subsystem 760 may include non-volatile (the state of which does not change when power to the memory device is cut off) or volatile (the state of which becomes uncertain when power to the memory device is cut off) memory devices, or a combination thereof. In addition to data such as application data, user data, music, photographs, and documents, the memory 760 can store system data (whether long-term or temporary) related to the execution of applications and functions of the system 700. In one example, the memory subsystem 760 includes a memory controller 764 (which may be considered part of the control unit of the system 700, and potentially part of the processor 710). The memory controller 764 includes a scheduler that generates and issues commands to control access to the memory device 762.

[0116] Connectivity 770 includes hardware devices (e.g., wireless or wired connectors and communication hardware, or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) that enable System 700 to communicate with external devices. External devices may be separate devices, such as other computing devices, wireless access points or base stations, or peripheral devices such as headsets or printers. In one example, System 700 exchanges data with an external device for storage in memory or for display on a display device. The exchanged data may include data to be stored in memory for reading, writing, or editing, or data already stored in memory.

[0117] Connectivity 770 may include several different types of connectivity. For generalization, system 700 is shown together with cellular connectivity 772 and wireless connectivity 774. Cellular connectivity 772 generally refers to cellular network connectivity provided by a wireless carrier, such as GSM® (Global System for Mobile Communications) or its variations or derivatives, CDMA (Code Division Multiple Access) or its variations or derivatives, TDM (Time Division Multiplexing) or its variations or derivatives, LTE (Long-Term Evolution, also known as "4G"), and 5G, provided by cellular service standards. Wireless connectivity 774 refers to wireless connectivity that is not cellular, and may include wireless communication such as personal area networks (such as Bluetooth®), local area networks (such as WiFi®), or wide area networks (such as WiMAX®), or a combination thereof. Wireless communication refers to the transfer of data using modulated electromagnetic radiation over a non-solid medium. Wired communication is performed over a solid communication medium.

[0118] Peripheral connections 780 include not only hardware interfaces and connectors, but also software components (e.g., drivers, protocol stacks) for making peripheral connections. It will be understood that system 700 can be both a peripheral device to other computing devices ("outside" 782) and a peripheral device connected to system 700 ("outside" 784). System 700 generally has a "docking" connector for connecting to other computing devices for purposes such as managing the content of system 700 (e.g., downloading, uploading, modifying, synchronizing). Furthermore, the docking connector may allow system 700 to connect to several peripheral devices that enable system 700 to control content output to systems such as audiovisual systems.

[0119] In addition to proprietary connection hardware such as dedicated docking connectors, System 700 can form peripheral connections 780 via common or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of several different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), and High Definition Multimedia Interface (HDMI®).

[0120] In general, in relation to the description herein, in one example, the apparatus includes a substrate and host hardware on the substrate, the host hardware performing memory control to manage access to a memory device, the memory control modifying the page table entry of the memory device to cause a page fault for the next access to the memory device, and triggering the memory device to enter a low-power state after the modification of the page table entry.

[0121] In one example of this device, the memory device has a byte-addressable memory device. In any of the aforementioned examples of this device, the memory device has a non-volatile memory device. In any of the aforementioned examples of this device, the memory device has a memory device compatible with the CXL (Compute Express Link) Cache / Memory Protocol Interface (CPI) standard. In any of the aforementioned examples of this device, the memory device has a three-dimensional crosspoint (3DXP) memory device. In any of the aforementioned examples of this device, memory control that modifies the page table includes memory control that invalidates the entry without removing the entry from the page table. In any of the aforementioned examples of this device, memory control that invalidates an entry includes memory control that clears the current bit indicator for the memory address range in the page table. In any of the aforementioned examples of this device, the memory control modifies the page table entry in response to a determination that the memory device has been idle for a threshold period. In any of the aforementioned examples of this device, before modifying the page table, the memory control determines whether the low-power state of the memory device has a wake delay that would stall the host processor, and modifies the page table in response to a determination that this low-power state has a wake delay that would stall the host processor. In any of the aforementioned examples relating to this device, before modifying the page table, memory control determines whether the memory device stores data associated with the locked page, and modifies the page table only in response to the determination that the memory device does not store data associated with the locked page.

[0122] In general, in relation to the description herein, one example includes a system that includes a memory device managed using coherent access and host hardware for performing memory control that manages access to the memory device, the memory control modifies the page table entry of the memory device to cause a page fault for the next access to the memory device, and triggers the memory device to enter a low-power state after the modification of the page table entry.

[0123] In one example of this system, the memory device has a byte-addressable memory device. In any of the aforementioned examples of this system, the memory device has a non-volatile memory device. In any of the aforementioned examples of this system, the memory device has a memory device compatible with the CXL (Compute Express Link) Cache / Memory Protocol Interface (CPI) standard. In any of the aforementioned examples of this system, the memory device has a three-dimensional crosspoint (3DXP) memory device. In any of the aforementioned examples of this system, memory control that modifies the page table includes memory control that invalidates the entry without removing the entry from the page table. In any of the aforementioned examples of this system, memory control that invalidates an entry includes memory control that clears the current bit indicator for the memory address range in the page table. In any of the aforementioned examples of this system, the memory control modifies the page table entry in response to a determination that the memory device has been idle for a threshold period. In any of the aforementioned examples of this system, before modifying the page table, the memory control determines whether the low-power state of the memory device has a wake delay that would stall the host processor, and modifies the page table in response to a determination that this low-power state has a wake delay that would stall the host processor. In any of the aforementioned examples relating to this system, before modifying the page table, memory control determines whether the memory device stores the data associated with the locked page, and modifies the page table only in response to the determination that the memory device does not store the data associated with the locked page. In any of the aforementioned examples relating to this system, the host hardware includes one or more of the following: a host processor, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or an interface to a battery that powers the system.

[0124] In general, in relation to the description herein, one example of a method for putting a memory device into a low-power state includes the steps of: determining that a memory device managed using coherent access is idle for a threshold period; modifying the page table entry of the memory device to cause a page fault for the next access to the memory device; and triggering the memory device to enter a low-power state after the modification of the page table entry.

[0125] In one example of this method, the memory device is a byte-addressable memory device. In any of the examples described above of this method, the memory device is a non-volatile memory device. In any of the examples described above of this method, the memory device is a memory device compatible with the CXL (Compute Express Link) Cache / Memory Protocol Interface (CPI) standard. In any of the examples described above of this method, the memory device is a three-dimensional crosspoint (3DXP) memory device. In any of the examples described above of this method, the step of modifying the page table includes a step of invalidating an entry without deleting the entry from the page table. In any of the examples described above of this method, the step of invalidating an entry includes a step of clearing the current bit indicator for a memory address range in the page table. In any of the examples described above of this method, before the step of modifying the page table, there is a step of determining whether the low-power state of the memory device has a wake delay that would stall the host processor, and modifying the page table in response to the determination that this low-power state has a wake delay that would stall the host processor. In any of the aforementioned examples relating to this method, there is a step before the step of modifying the page table in which it is determined whether the memory device stores data associated with the locked page, and the page table is modified only in response to the determination that the memory device does not store data associated with the locked page.

[0126] In general, in relation to the description herein, one example includes a computer-readable storage medium containing instructions stored in the computer-readable storage medium that, when executed by a processor, cause the processor to perform the method described in either of the two preceding paragraphs.

[0127] Each flowchart presented herein provides an example of a sequence of various process operations. These flowcharts may also show physical operations in addition to operations performed by software or firmware routines. A flowchart may illustrate an example of an implementation of a finite state machine (FSM), which can be implemented in hardware and / or software. The order of operations is shown in a specific sequence or order, but can be changed unless otherwise specified. Therefore, the diagrams shown should be understood as examples only, and this process may occur in a different order, and some operations may be performed in parallel. Furthermore, one or more operations may be omitted, and therefore not all implementation examples perform all operations.

[0128] To the extent that various operations or functions are described herein, such operations or functions may also be described or specified as software code, instructions, configurations, and / or data. Content may be a directly executable file ("object" format or "executable file" format), source code, or differential code ("delta" code or "patch" code). Software content relating to what is described herein may be provided through the product in which the content is stored, or by operating a communication interface to send data through the communication interface. Machine-readable storage media include any mechanism that can cause a machine to perform the described functions or operations and stores information in a format accessible to a machine (e.g., a computing device, an electronic system, etc.), such as write-once / write-once media (e.g., read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that interfaces to any hardwired medium, wireless medium, optical medium, etc., for communication with another device, such as a memory bus interface, processor bus interface, internet connection, disk controller, etc. A communication interface may be configured to provide data signals describing software content by providing configuration parameters and / or by sending signals to prepare the communication interface. A communication interface may be accessed via one or more commands or signals sent to the communication interface.

[0129] The various components described herein may be means for performing the operations or functions described herein. Each component described herein may include software, hardware, or a combination thereof. Each component may be implemented as a software module, a hardware module, dedicated hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), an embedded controller, a hardwired circuit, etc.

[0130] In addition to what is described herein, various modifications can be made to the disclosed and implemented examples of the invention without departing from their scope. Therefore, the descriptions and examples herein should be interpreted as illustrative, not restrictive. The scope of the invention should be determined solely by reference to the following claims. [Other possible items] (Item 1) circuit board and The host hardware on the aforementioned board and A device comprising: the host hardware performing memory control to manage access to the memory device; the memory control modifying the page table entry of the memory device to cause a page fault for the next access to the memory device; and triggering the memory device to enter a low-power state after the modification of the page table entry. (Item 2) The apparatus according to item 1, wherein the memory device has a byte-addressable memory device. (Item 3) The apparatus according to item 2, wherein the memory device has a non-volatile memory device. (Item 4) The apparatus described in item 2, wherein the memory device has a memory device compatible with the CXL (Compute Express Link) Cache / Memory Protocol Interface (CPI) standard. (Item 5) The apparatus according to item 2, wherein the memory device has a three-dimensional crosspoint (3DXP) memory device. (Item 6) The apparatus according to item 1, wherein the memory control that modifies the page table includes the memory control that disables the entry without deleting the entry from the page table. (Item 7) The apparatus according to item 6, wherein the memory control that invalidates the entry includes the memory control that clears the current bit indicator for the memory address range in the page table. (Item 8) The apparatus according to item 1, wherein the memory control modifies the page table entry in response to a determination that the memory device is idle during a threshold period. (Item 9) The apparatus according to item 1, wherein, before changing the page table, the memory control determines whether the low-power state of the memory device has a wake delay that would stall the host processor, and changes the page table in response to the determination that the low-power state has a wake delay that would stall the host processor. (Item 10) The apparatus according to item 1, wherein, before changing the page table, the memory control determines whether the memory device stores data associated with a locked page, and changes the page table only in response to the determination that the memory device does not store data associated with a locked page. (Item 11) Memory devices managed using coherent access, Host hardware for performing memory control to manage access to the aforementioned memory device, and A system comprising: a memory control that modifies the page table entry of the memory device in order to cause a page fault for the next access to the memory device, and triggers the memory device to enter a low-power state after the modification of the page table entry. (Item 12) The system according to item 11, wherein the memory device is a non-volatile byte-addressable memory device. (Item 13) The system described in item 12, wherein the memory device has a memory device compatible with the CXL (Compute Express Link) Cache / Memory Protocol Interface (CPI) standard. (Item 14) The system according to item 12, wherein the memory device has a three-dimensional crosspoint (3DXP) memory device. (Item 15) The system according to item 11, wherein the memory control that modifies the page table includes the memory control that disables the entry without deleting the entry from the page table. (Item 16) The system according to item 11, wherein the memory control modifies the page table entry in response to a determination that the memory device is idle during a threshold period. (Item 17) The aforementioned host hardware Host processor, A display that is communicatively coupled to the host processor. A network interface that is communicatively coupled to the host processor, or Interface to the battery that supplies power to the aforementioned system A system as described in item 11, which includes one or more of the following. (Item 18) A method for putting a memory device into a low-power state, The stage of determining whether a memory device managed using coherent access is idle during the threshold period, The steps include modifying the page table entry of the memory device in order to cause a page fault for the next access to the memory device, A step of triggering the memory device to enter a low-power state after modifying the page table entry. A method for providing this. (Item 19) The method according to item 18, wherein the memory device has a memory device compatible with the CXL (Compute Express Link) Cache / Memory Protocol Interface (CPI) standard. (Item 20) The method according to item 18, wherein the step of modifying the page table includes a step of disabling the entry without deleting the entry from the page table.

Claims

1. Memory devices managed using coherent access, Host hardware configured to perform memory control for managing access to the aforementioned memory device, A memory power management system comprising: The memory control is performed by changing the page table entry for the memory device, thereby causing a page fault for the next access to the memory device, and changing the next access to the memory device from a synchronous access to an asynchronous access, wherein in the asynchronous access, the host processor does not wait for the memory device to wake up from the low-power state, and after the change to the page table entry, the memory device is triggered to enter the low-power state. Before modifying the page table entry, the memory control determines whether the low-power state of the memory device has a wake delay that would stall the host processor, and modifies the page table entry in response to the determination that the low-power state has a wake delay that would stall the host processor.

2. The system according to claim 1, further comprising: when the page fault occurs, the memory control issues a management command to wake the memory device which is in a low-power state, and does not resume the execution of the next access that caused the page fault until the completion of the management command is notified by an interrupt.

3. The system according to claim 1 or 2, wherein the memory device has a byte-addressable memory device.

4. The system according to claim 3, wherein the memory device has a non-volatile memory device.

5. The system according to claim 3, wherein the memory device is a memory device compatible with the CXL (Compute Express Link) Cache / Memory Protocol Interface (CPI) standard.

6. The system according to claim 3, wherein the memory device has a three-dimensional crosspoint (3DXP) memory device.

7. The system according to any one of claims 1 to 6, wherein the memory control modifies the page table entry, and the memory control invalidates the page table entry without deleting the page table entry from the page table.

8. The system according to claim 7, wherein the memory control invalidating the page table entry includes clearing the current bit indicator for a memory address range in the page table.

9. The system according to any one of claims 1 to 8, wherein the memory control modifies the page table entry in response to a determination that the memory device is idle during a threshold period.

10. Memory devices managed using coherent access, Host hardware for performing memory control to manage access to the aforementioned memory device, and Equipped with, The memory control modifies the page table entry of the memory device to cause a page fault for the next access to the memory device, and triggers the memory device to enter a low-power state after the modification of the page table entry. A memory power management system, wherein, before modifying the page table entry, the memory control determines whether the low-power state of the memory device has a wake delay that would stall the host processor, and modifies the page table entry in response to the determination that the low-power state has a wake delay that would stall the host processor.

11. The system according to any one of claims 1 to 10, wherein, before modifying the page table entry, the memory control determines whether the memory device stores data associated with a locked page, and modifies the page table entry only in response to the determination that the memory device does not store data associated with a locked page.

12. Memory devices managed using coherent access, Host hardware for performing memory control to manage access to the aforementioned memory device, and Equipped with, The memory control modifies the page table entry of the memory device to cause a page fault for the next access to the memory device, and triggers the memory device to enter a low-power state after the modification of the page table entry. A memory power management system wherein, before modifying the page table entry, the memory control determines whether the memory device stores data associated with the locked page, and modifies the page table entry only in response to the determination that the memory device does not store data associated with the locked page.

13. The aforementioned host hardware Host processor, A display, which is communicatively coupled to the host processor, A network interface that is communicatively coupled to the host processor, or Interface to the battery that supplies power to the aforementioned system The system according to any one of claims 1 to 12, comprising one or more of the above.

14. A method for putting a memory device into a low-power state, The steps include determining that the memory device managed using coherent access is idle during the threshold period, A step of modifying the page table entry for the memory device to cause a page fault for the next access to the memory device, thereby changing the next access to the memory device from a synchronous access to an asynchronous access, wherein in the asynchronous access, the host processor does not wait for the memory device to wake up from the low-power state. The steps include: after modifying the page table entry, triggering the memory device to enter the low-power state; Equipped with, The method further comprises a step of determining whether the low-power state of the memory device has a wake delay that would stall the host processor, prior to the step of modifying the page table entry, and the step of modifying the page table entry is performed in response to the determination that the low-power state has a wake delay that would stall the host processor.

15. The method according to claim 14, wherein the memory device is a byte-addressable memory device.

16. The method according to claim 15, wherein the memory device has a non-volatile memory device.

17. The method according to claim 15, wherein the memory device is a memory device compatible with the CXL (Compute Express Link) Cache / Memory Protocol Interface (CPI) standard.

18. The method according to claim 15, wherein the memory device has a three-dimensional crosspoint (3DXP) memory device.

19. The method according to any one of claims 14 to 18, wherein the step of modifying the page table entry includes a step of disabling the page table entry without deleting the page table entry from the page table.

20. The method according to claim 19, wherein the step of invalidating the page table entry includes the step of clearing the current bit indicator for a memory address range in the page table.

21. A method for putting a memory device into a low-power state, The stage of determining whether a memory device managed using coherent access is idle during the threshold period, The steps include determining whether the low-power state of the memory device has a wake delay that would cause the host processor to stall, In response to the determination that the low-power state has a wake delay that would stall the host processor, the step of modifying the page table entry of the memory device in order to cause a page fault for the next access to the memory device, A method comprising the step of triggering the memory device to enter the low-power state after modifying the page table entry.

22. The method according to any one of claims 14 to 21, further comprising the step of determining whether the memory device stores data associated with a locked page, prior to the step of modifying the page table entry, and the step of modifying the page table entry is performed only in response to the determination that the memory device does not store data associated with a locked page.

23. A method for putting a memory device into a low-power state, The stage of determining whether a memory device managed using coherent access is idle during the threshold period, The steps include determining whether the memory device stores data associated with the locked page, A step of modifying the page table entry of the memory device in order to cause a page fault for the next access to the memory device, in response only to the determination that the memory device does not store data associated with a locked page, A method comprising the step of triggering the memory device to enter a low-power state after modifying the page table entry.

24. A computer program for causing a computing device to perform the method according to any one of claims 14 to 23.

25. A computer-readable storage medium for storing the computer program described in claim 24.

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