Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device which is less damaged during processing and in which the generation of interface states on the crystal surface or junction interface is suppressed, thereby obtaining good device characteristics.SOLUTION: A semiconductor device includes a semiconductor layer having a groove-shaped opening, and the semiconductor layer is made of β-Ga2O3 crystals, the crystal plane orientation of the first main surface of the semiconductor layer is (001), the longitudinal direction of the groove is parallel to the intersection of the plane orientation of the first main surface and the (100) plane, the longitudinal sidewall of the groove is a (100) facet plane, and the bottom of the groove has a single (-101) plane orientation where the groove width is greater than 0 μm and less than 2.0 μm.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] β-Ga2O3 has a wider bandgap (approximately 4.6 eV) than SiC and GaN, and a breakdown field strength about 20 times that of Si, making it a promising material for use, particularly in power semiconductors. β-Ga2O3 single crystal substrates can be manufactured using methods such as FZ (floating zone), CZ (Czochralaki), VB (Vertical Bridgeman), and EFG (Edge-Defined Film-Fed Growth), with high-quality 6-inch substrates being commercially available, particularly using the EFG method.

[0003] For this reason, research and development of Schottky barrier diodes (SBDs) and metal oxide semiconductor transistors (MOSFETs) using β-Ga2O3 material is actively underway. In this research, efforts are being made to improve the breakdown voltage of these devices in principle, and to investigate structures such as trenches and fins that enable normally-off operation even with β-Ga2O3, a unipolar semiconductor. As can be seen in Non-Patent Documents 1 and 2, many prototype results have been reported.

[0004] Currently, these structures are formed by anisotropic dry etching (reactive ion etching). However, it has been pointed out that using anisotropic dry etching to form trenches and fins in β-Ga2O3 power devices presents problems related to damage and defects, as described below.

[0005] (1) When dry etching is used, the sidewall surfaces of the formed trenches and fins are subjected to processing damage. Therefore, after dry etching, it is necessary to remove the damage using a wet process with alkali or acid. (2) The sidewalls formed by dry etching do not reflect crystal facets, and thus have a high density of dangling bonds. This leads to an increase in crystal surface states and junction interface state density, and degrades device characteristics. [Prior Art Documents] [Non-Patent Literature]

[0006] [Non-Patent Literature 1] F. Otsuka et al., Appl. Phys. Express, 15, 016501(2022) https: / / doi.org / 10.35848 / 1882-0786 / ac4080 [Non-Patent Literature 2] W. Li et al., IEEE International Electron Devices Meeting(IEDM), (2019) https: / / doi.org / 10.1109 / IEDM19573.2019.8993526 [Summary of the Invention] [Problem to be Solved by the Invention]

[0007] An object of the present invention is to solve the above-mentioned problems of conventional β-Ga₂O₃ semiconductor devices having trenches or fin structures, and provide a semiconductor device using β-Ga₂O₃ semiconductor suitable for microfabrication, which has less processing damage, suppresses generation of interface states at crystal surfaces and bonding interfaces, and can achieve favorable device characteristics, and particularly provide a power device utilizing the characteristics of β-Ga₂O₃ semiconductor and a method for manufacturing the same. [Means for Solving the Problem]

[0008] The configuration of the present invention is shown below. (Configuration 1) comprises a semiconductor layer having a trench, the semiconductor layer is formed of a β-Ga₂O₃ crystal, the crystal plane orientation of the first main surface of the semiconductor layer is (001), The longitudinal direction of the groove is parallel to the intersection line of the surface orientation of the first main surface and the (100) plane. The longitudinal side walls of the groove are (100) faceted surfaces, A semiconductor device wherein the bottom of the groove has a surface orientation of (-101) in the area where the width of the groove is greater than 0 μm and less than or equal to 2.0 μm. (Configuration 2) The semiconductor device according to configuration 1, wherein the bottom of the groove has surface orientations of (-101) and (001) in places where the width of the groove is 2.0 μm or more. (Composition 3) The semiconductor device according to configuration 1 or 2, wherein the longitudinal side walls of the groove are inclined at 13.7° with respect to the vertical plane of the first main surface. (Composition 4) A semiconductor layer having grooves, The aforementioned semiconductor layer is made of β-Ga2O3 crystal. The crystal orientation of the first main surface of the semiconductor layer is (-102). The longitudinal direction of the groove is parallel to the intersection line of the surface orientation of the first main surface and the (100) plane. A semiconductor device wherein at least one of the longitudinal side walls of the groove is a (100) facet surface and is perpendicular to the first main surface. (Composition 5) A semiconductor layer having grooves, The aforementioned semiconductor layer is made of β-Ga2O3 crystal. The crystal orientation of the first main surface of the semiconductor layer is (001), The longitudinal direction of the groove is parallel to the intersection line of the surface orientation of the first main surface and the {310} plane. The longitudinal side walls of the groove are {310} faceted surfaces. The bottom of the groove has a surface orientation of (001), A semiconductor device wherein the longitudinal side walls of the groove are inclined at 8.4° with respect to the vertical plane of the first main surface. (Composition 6) A semiconductor device according to any one of configurations 1 to 5, wherein at least a portion of at least one side surface of the groove is a channel. (Composition 7) A semiconductor device according to any one of configurations 1 to 6, comprising a Fin-type MOSFET structure having a linear protruding semiconductor layer formed by a plurality of grooves. (Composition 8) The anode electrode is formed in at least a part of the three-dimensional structure having the side surface and the bottom surface, via an insulating film disposed on at least a part of the side surface and the bottom surface of the groove. A semiconductor device according to any one of configurations 1 to 5, wherein the anode electrode is part of the three-dimensional structure and comprises a Tench-type MOSSBD structure in which it is connected to the semiconductor layer by a Schottky link. (Composition 9) A power device having a semiconductor device according to any one of configurations 1 to 8. (Composition 10) A semiconductor layer is prepared, consisting of a β-Ga2O3 crystal whose first main surface orientation is (001) or (-102). An etching mask having groove-shaped openings having a longitudinal direction parallel to the intersection lines of one or more crystal planes selected from the group consisting of (100) and {310} is formed on the first main surface, A method for manufacturing a semiconductor device, comprising using a reducing gas and selectively etching the β-Ga2O3 crystal exposed at the opening of the mask at atmospheric pressure and a temperature of 300°C to 1200°C. (Composition 11) The method for manufacturing a semiconductor device according to configuration 10, wherein the reducing gas is one or more gases selected from the group consisting of hydrogen halide gas and hydrogen gas. (Composition 12) The method for manufacturing a semiconductor device according to configuration 10, wherein the reducing gas is hydrogen chloride gas. [Effects of the Invention]

[0009] According to the present invention, a semiconductor device having a trench or fin structure using a β-Ga2O3 semiconductor that is suitable for microfabrication is provided, which has less processing damage, suppresses the generation of interface states at the crystal surface and bonding interface, and yields good device characteristics, and in particular a power device that takes advantage of the properties of the β-Ga2O3 semiconductor and a method for manufacturing the same. [Brief explanation of the drawing]

[0010] [Figure 1] This is a cross-sectional view illustrating the structure of the β-Ga2O3 structure according to the present invention. [Figure 2] This is a flowchart illustrating the manufacturing process of the β-Ga2O3 fin structure of the present invention. [Figure 3] This is a cross-sectional diagram showing the manufacturing process of the β-Ga2O3 structure of the present invention. [Figure 4] This is a cross-sectional process diagram showing the manufacturing process of Trench MOSSBD according to the present invention. [Figure 5] This is a cross-sectional process diagram showing the manufacturing process of Trench MOSSBD according to the present invention. [Figure 6] This is a cross-sectional process diagram showing the manufacturing process of Trench MOSSBD according to the present invention. [Figure 7] This is a cross-sectional process diagram showing the manufacturing process of Trench MOSSBD according to the present invention. [Figure 8] This is a cross-sectional view illustrating the device structure of a vertical FinFET. [Figure 9] This is a surface SEM image showing the etching process when selective etching is performed on a circular window. [Figure 10] These surface SEM images show the etching process when selective etching is performed on radial linear windows, with (a) showing the orientation of the linear windows at 10° intervals and (b) showing the orientation of the main in-plane orientation. [Figure 11] This is a selective etching characteristic diagram showing the in-plane anisotropy of the under-etching amount in polar coordinates. [Figure 12]

[0010] This is an SEM image after selective etching of a linear window mask pattern with different azimuth window widths and mask widths. [Figure 13]

[0010] (a) and (b) SEM images showing the cross-sectional processed shape after selective etching of the linear window for orientation, and (c) a schematic cross-sectional diagram created based on those images. (a) shows the case where the window width is 1.2 μm and the mask width is 2.8 μm, and (b) shows the case where the window width is 5.5 μm and the mask width is 1.0 μm. Carbon has been deposited to prevent surface deformation due to focused ion beam processing. [Figure 14] (a) SEM image showing the cross-sectional shape after selective etching of a linear window in the [-130] orientation, and (b) a schematic cross-sectional diagram created based on that image. [Figure 15] This is an SEM image observing the selective etching process when using a (-10°) surface substrate. The pattern consists of radial linear windows, with their orientations spaced at 10° intervals. [Figure 16] This is an SEM image observing the selective etching process for linear windows with different window widths and mask widths in the

[0010] orientation when using a (-102) surface substrate. [Figure 17] (a) SEM image and (b) schematic cross-sectional diagram created based on the (-102) surface substrate, showing the cross-sectional processed shape after selective etching of a linear window with a window width of 1.4 μm and a mask width of 2.6 μm in the

[0010] direction. [Figure 18] This is an SEM image showing the cross-sectional processed shape after selective etching of a linear window with a window width of 0.5 μm and a mask width of 5.7 μm in the

[0010] direction when using a (-102) surface substrate. [Figure 19] This is a diagram illustrating the configuration of the HVPE apparatus used as a heat reduction treatment apparatus in the example. [Modes for carrying out the invention]

[0011] (Embodiment 1) In Embodiment 1, a trench structure 101 (see FIG. 1) having a trench used for manufacturing a β-type Ga₂O₃ (β-Ga₂O₃) power semiconductor device is described. Here, the trench structure 101 is composed of a β-Ga₂O₃ semiconductor layer 11 having a trench formed below an opening 13 of a mask 12, and as will be described later, side surfaces 11α, 11β of the trench, bottom 11γ, which is a structure characterized by an angle θ of the side surface with respect to a vertical plane.

[0012] The trench structure 101 of the present invention described in Embodiment 1 includes a semiconductor layer 11 having a trench, the semiconductor layer 11 is formed of a β-Ga₂O₃ crystal, the crystal plane orientation of the first main surface of the semiconductor layer 11 is (001), the longitudinal direction of the trench is a direction parallel to the intersection line between the plane orientation of the first main surface and the (100) plane, and the bottom 11 of the trench γ is a structure having a (-101) plane orientation in a region where the width of the trench is more than 0 μm and 2.0 μm or less.

[0013] With this structure, the side surfaces 11 of the semiconductor layer 11 α and 11 β become stable (100) facet planes with the lowest surface energy. The side surfaces 11 of the semiconductor layer 11 formed of β-Ga₂O₃ crystal formed of the most stable (100) facet α and 11 β have fewer dangling bonds and a lower surface state density. Therefore, the semiconductor device according to Embodiment 1 using the side walls of the present invention has excellent electrical characteristics, for example, excellent leakage current, mobility, reliability, and breakdown voltage. In particular, the side surface 11 formed of the (100) facet plane α and 11 β the semiconductor device using said as a channel layer or a drift layer has excellent electrical characteristics, reliability and quality stability.

[0014] In addition, in the trench structure 101, in a region where the width of the trench is 2.0 μm or more, the bottom 11 of the trench γ is constituted not only by (-101) but also by (001) which is the first main surface. Thus, the bottom 11 γThe facet configuration can be controlled by the width of the groove.

[0015] The second trench structure 101 of the present invention, as described in Embodiment 1, comprises a semiconductor layer 11 having a groove, the semiconductor layer 11 is made of β-Ga2O3 crystal, the crystal orientation of the first main surface of the semiconductor layer 11 is (-102), the longitudinal direction of the groove is parallel to the intersection line of the crystal orientation of the first main surface and the (100) plane, and the side walls 11 in the longitudinal direction of the groove α and 11 β This is a structure perpendicular to the first main surface, i.e., where θ is 0.

[0016] This structure allows the longitudinal side walls 11 of the groove α and 11 β The (100) facet surface is stable and the semiconductor layer sidewall 11 is made of β-Ga2O3 crystal. α and 11 β This significantly suppresses the generation of unbonded density. As a result, the crystal plane becomes free from problems with crystal surface energy levels and bonding interface energy level densities, and semiconductor devices fabricated using this structure, particularly the side surface 11 consisting of this (100) facet plane, α and 11 β Semiconductor devices that use this material as a channel layer or drift layer exhibit superior electrical characteristics, reliability, and quality stability. Furthermore, the second trench structure 101 has longitudinal side walls 11 α and 11 β Since the θ is perpendicular to the first main surface of the semiconductor layer 11, i.e., θ is 0, it has the characteristic of being easy to handle, including processing.

[0017] The third trench structure 101 of the present invention, as described in Embodiment 1, comprises a semiconductor layer 11 having a groove, the semiconductor layer 11 is made of β-Ga2O3 crystal, the crystal orientation of the first main surface of the semiconductor layer is (001), the longitudinal direction of the groove is parallel to the intersection line of the crystal orientation of the first main surface and the {310} plane, the longitudinal sidewall of the groove is a {310} facet plane, the bottom of the groove has a (001) crystal orientation, and the longitudinal sidewall of the groove is inclined at 8.4° with respect to the vertical plane of the main surface.

[0018] This structure allows the longitudinal side walls 11 of the groove α and 11 β The {310} facet surface is stable, and the semiconductor layer sidewall 11 is made of β-Ga2O3 crystal. α and 11 β This significantly suppresses the generation of unbonded density. As a result, the crystal plane becomes free from problems with crystal surface energy levels and bonding interface energy level densities, and semiconductor devices fabricated using this structure, particularly the side surface 11 consisting of this {310} facet plane, α and 11 β Semiconductor devices that use this material as a channel layer or drift layer exhibit superior electrical characteristics, reliability, and quality stability.

[0019] Next, the manufacturing method of the trench 101 will be explained with reference to Figure 2, which is a flowchart, and Figure 3, which is a cross-sectional view of the process.

[0020] As the first step, a semiconductor layer 11a made of a β-Ga2O3 crystalline semiconductor having a crystal plane of (001) or (-102) is prepared (step S11 in Figure 2, Figure 3(a)). As the semiconductor layer 11a, a β-Ga2O3 crystalline substrate manufactured by methods such as FZ, CZ, VB, and EFG may be used, or a β-Ga2O3 epitaxial layer deposited on a β-Ga2O3 crystalline substrate by methods such as HVPE (Halide Vapor Phase Epitaxy) or MOCVD (Metal Organic Chemical Vapor Deposition), or both a β-Ga2O3 crystalline substrate and a β-Ga2O3 epitaxial layer may be used.

[0021] In the second step, an etching mask 12 is formed having groove-shaped openings whose longitudinal direction is aligned parallel to the intersection lines of one or more crystal planes selected from the group consisting of the substrate plane, the (100) plane, and the {310} plane (step S12). Specifically, a thin film 12a made of an etching hard mask such as SiO2 is formed on the semiconductor layer 11a (Figure 3(b)), and a resist pattern 15 having groove-shaped openings is formed thereon (Figure 3(c)). Here, the thin film 12a is made of SiO2, as well as SiO2. x , SiON, SiN X Si may also be used. In this example, the etching mask pattern is shown as groove-shaped openings, focusing on the grooves, but as shown in Figure 3(c), if we focus on the mask surrounded by the grooves, it can also be considered as a fin-shaped pattern, which is a linear projection pattern. Next, the resist pattern 15 is used as a mask to perform wet etching or dry etching to form openings 13 in the thin film 12a (Figure 3(d)). Subsequently, the resist pattern 15 is peeled off using oxygen plasma ashing, ozone ashing, or a resist stripping solution to form an etching mask 12 having groove-shaped openings 13 (Figure 3(e)). Here, the thickness of the mask 12 is preferably 1 nm or more and 1000 nm or less. If the thickness is less than 1 nm, defects are likely to occur. The mask 12 is a dummy object that is not essential for the semiconductor device being manufactured, and from the viewpoint of suppressing crack formation in the mask, its thickness is preferably 1000 nm or less.

[0022] In the third step, the semiconductor layer 11a made of β-Ga2O3 is dry-etched using a reducing gas. This etching is preferably performed under atmospheric pressure in a temperature environment of 300°C to 1200°C, preferably 500°C to 1100°C. Using atmospheric pressure makes handling easier and increases the etching rate, improving productivity. Furthermore, the above temperature range allows for a high etching rate, improving productivity. Because it is crystal plane selective etching, even high-temperature etching with a fast etching rate can be performed on the processed side surface 11α Ya 11 β This results in (100) or {310} planes, providing stable and defect-free surfaces. Furthermore, because plasma is not used, damage to the etched surface is kept to a negligible level.

[0023] As a reducing gas, one or more gases selected from the group consisting of hydrogen halides and hydrogen gas can be mentioned. Among these, hydrogen chloride gas (HCl gas) is preferred because it is relatively easy to handle and can achieve a sufficient etching rate. Since etching is performed under atmospheric pressure, it is preferable to add a carrier gas in addition to the reducing gas during etching. Suitable carrier gases include nitrogen gas and noble gases such as argon, krypton, and neon. Among these, nitrogen gas is particularly preferred because it is easy to handle and relatively inexpensive. As mentioned in the examples, etching at the 2μm level takes 5 minutes, demonstrating the high productivity of this selective etching method using reducing gas. By the above method, a trench structure 101 is manufactured in which the desired trenches are formed in a semiconductor layer 11 made of β-Ga2O3 (step S13, Figure 3(f)).

[0024] The openings in the mask 12 can be microfabricated by using a thin film 12a such as SiO2, which is easy to process. Therefore, this method makes it possible to easily manufacture a trench structure 101 using fine β-Ga2O3.

[0025] (Embodiment 2) Embodiment 2 describes Trench MOSSBD (Trench Metal Oxide Semiconductor Schottky Barrier Diode) 201, one of the semiconductor devices suitable for power applications, including its manufacturing method.

[0026] The manufacturing method of Trench MOSSBD(201) will be described with reference to Figures 4 to 7.

[0027] First, a sample is prepared in which a β-Ga2O3 epitaxial layer 53a is formed on a β-Ga2O3 substrate 51 (Figure 4(a)). Here, the β-Ga2O3 substrate 51 has a first main surface orientation of (001) or (-102). Regarding impurities, Si, Sn, etc. are 10 18 cm -3 The above 10 20 cm -3 The following doped materials can be preferred. The β-Ga2O3 substrate 51 can be formed using any of the FZ, CZ, VB, or EFG methods, but from the standpoint of mass production cost and quality, those manufactured by the EFG method can be preferred. The β-Ga2O3 epitaxial layer 53a can be formed using HVPE, MOCVD, and low-pressure CVD methods. The surface orientation of the first main surface of the β-Ga2O3 epitaxial layer 53a is (001) or (-102). Here, since the irregularities formed by epitaxial growth degrade the device performance, it is preferable to polish the β-Ga2O3 epitaxial layer 53a by CMP or the like after formation. Regarding the impurities in the β-Ga2O3 epitaxial layer 53a, Si, Sn, Ge, etc. are present in 10 15 cm -3 The above 10 17 cm -3 The following doped products can be used as preferred. There are no particular restrictions on the thickness of the β-Ga2O3 epitaxial layer 53a, but for example, it can be between 1 μm and 50 μm.

[0028] In the following explanation of Trench MOSSBD(201), the case where the surface orientation of the first main surface is (001) is described. However, if a β-Ga2O3 substrate 51 with a (-102) surface orientation is used, the surface orientation (001) should be replaced with (-102). In the drawing, when the surface orientation (001) is used, an inclined groove (opening) pattern is formed, but when the surface orientation (-102) is used, a vertical groove pattern is formed.

[0029] Next, a mask 52, which will serve as an etching hard mask, is formed on the β-Ga2O3 epitaxial layer 53a (Figure 4(b)). SiO2 can be preferred as the material for the mask 52, but SiO2 is also used. x , SiON, SiN x Alternatively, materials that have a slow etching rate against β-Ga2O3 reducing etching gases such as Si and can be easily removed by dry etching using fluorine-based gases or wet etching using hydrofluoric acid-based aqueous solutions may be used.

[0030] Subsequently, the β-Ga2O3 epitaxial layer 53a is etched using a reducing gas with the mask 52 as an etching mask to form a β-Ga2O3 semiconductor layer 53 having a groove-like pattern (Figure 4(c)). Here, as the reducing gas, one or more gases selected from the group consisting of hydrogen halide gas and hydrogen gas can be preferred, as mentioned above, and hydrogen chloride gas (HCl gas) can be used in particular. The pressure can be atmospheric pressure, which is easy to handle, and the etching temperature can be 300°C to 1200°C. In particular, a temperature of 500°C to 1100°C is preferred because it allows for the acquisition of a flat facet surface at a high etching rate, thereby improving the manufacturing throughput of Trench MOSSBD (201). Subsequently, the mask 52 is removed using dry etching, wet etching, or both (Figure 5(a)).

[0031] Next, as shown in Figure 5(b), a conformally formed insulating film 54a is created. The insulating film 54a is preferably made of a material with few energy levels or defects and excellent breakdown voltage, such as HfO2, Al2O3, SiO2, Ta2O5, or HfSiO2. x One or more films can be selected from the group consisting of Si3N4 and SiON. These films can be single-layer or multilayer films. The film deposition method is not particularly limited, but examples include CVD, sputtering, and ALD (Atomic Layer Deposition). The ALD method is particularly preferred due to its low defect rate and excellent conformability. The thickness of the insulating film 54a is not particularly limited, but it can be said to be between 10 nm and 100 nm.

[0032] Next, as shown in Figure 5(c), the first insulating film 54 is processed by removing the upper surface portion of the insulating film 54a so that at least the upper surface portion 55 of the β-Ga2O3 semiconductor layer 53 (the surface that will later become a Schottky connection) is exposed. Examples of processing methods for this include CMP (Chemical Mechanical Polishing), etch-back, and combinations thereof.

[0033] Subsequently, an insulating film 56a is deposited (Figure 6(a)), and then a resist pattern 57 having openings that expose the desired region where a trench is to be formed is formed (Figure 6(b)). Here, the insulating film 56a is, for example, SiO x Examples of materials include SiON, SOG (Spin on Glass), and polyimide. Methods for forming these materials include, for example, CVD, sputtering, and coating. Subsequently, the insulating film 56a is etched (Figure 6(c)), and the resist pattern 57 is removed by oxygen gas ashing, ozone treatment, and stripping solution, thereby forming a second insulating film 56 in at least a portion of the field area other than the trench region (Figure 7(a)).

[0034] Next, after thoroughly cleaning the upper surface portion 55 of the β-Ga2O3 semiconductor layer 53 where β-Ga2O3 is exposed and the exposed surface of the first insulating film 54, a conductive film 58a to serve as the anode is formed on the surface (upper surface) facing the β-Ga2O3 semiconductor layer 53, and a conductive film 59 to serve as the cathode is formed on the back side (Figure 7(b)). Here, the conductive film 58a can be made of Pt, Au, Ni, Ag, Ru, Rh, Pd, W, Mo, Ta, and Cu. Methods for forming the conductive film 58a include vapor deposition, sputtering, and MOCVD. Examples of the conductive film 59 include at least one selected from the group consisting of Ti, Al, Au, Pt, and ITO, and alloys containing at least one selected from these groups. Examples of methods for forming the conductive film 59 include vapor deposition, sputtering, and MOCVD. It is preferable that the conductive film 59 is in ohmic contact with the β-Ga2O3 substrate 51. Taking this into consideration, it is also preferable to control the doping of the β-Ga2O3 substrate 51 and to form the conductive film 59 as a multilayer film.

[0035] Finally, the conductive film 58a is processed by lithography and etching to produce a Trench MOSSBD (201) having the desired anode electrode 58 and cathode electrode (conductive film) 59 (Figure 7(c)). The anode electrode 58 may be formed by a lift-off method instead of the deposition, lithography, and etching method.

[0036] The manufactured Trench MOSSBD(201) has a β-Ga2O3 semiconductor 53 that makes Schottky contact with the anode electrode 58. The sides of the β-Ga2O3 semiconductor 53 in the grooves reflect the crystal facets, resulting in a low density of unbonded elements, which in turn results in a low density of crystal defects and interface states on the crystal surface. The combination of this high-quality β-Ga2O3 semiconductor 53 and the Trench MOSSBD structure, which can produce high breakdown voltage characteristics, results in a manufactured Trench MOSSBD(201) that is a high-voltage diode with excellent leakage current characteristics, making it particularly suitable for power devices.

[0037] (Embodiment 3) Embodiment 3 describes a vertical FinFET (203), which is one of the semiconductor devices suitable for power applications.

[0038] As shown in Figure 8, the vertical FinFET (203) consists of a substrate 71 made of β-Ga2O3, a β-Ga2O3 semiconductor layer (epitaxial β-Ga2O3 layer) 72, a fin (β-Ga2O3) 73 made of β-Ga2O3, an insulating film 75 that functions as a gate insulating film, a gate electrode 76, an insulating layer 77 that electrically separates the gate electrode and the source electrode, etc., and n that makes ohmic contact between the fin 73 and the source electrode 79 and has the function of reducing the contact resistance. + It consists of a layer 78 and a drain electrode 80.

[0039] Substrate 71 has 10 units of Si, Sn, etc. due to electrical resistance. 18 cm -3 The above 10 20 cm -3 The following doped materials are preferred. The β-Ga2O3 semiconductor layer 72 has a dopant amount of 10 formed by methods such as HVPE. 15 cm -3 The above 10 17 cm -3 The following β-Ga2O3 crystals are used, and their thickness is preferably between 1 μm and 50 μm. The fins 73 are formed in the same manner as in Embodiment 1 by etching a β-Ga2O3 semiconductor layer (epitaxially formed β-Ga2O3 layer) with a reducing gas using an etching hard mask (not shown). Here, the doping of the fins 73 is 10 15 cm -3 The above 10 17 cm -3 The following is preferable: The surface layer near the side of fin 73 functions as a channel layer. In addition to SiO2, HfO2 and HfSiO2 can be used as insulating film (gate insulating film) 75. x So-called High-k films such as Al2O3 and Si3N4 can be preferred. Their thickness is preferably between 10 nm and 100 nm.

[0040] As the gate electrode 76, Pt, Cr, Au, Ni, Ag, Ru, Rh, Pd, W, Mo, Ta, PolySi, and Cu can be preferred, and as the source electrode 79 and drain electrode 80, at least one selected from the group consisting of Ti, Al, Au, Pt, and ITO, and an alloy containing at least one selected from these groups can be preferred. Considering the adhesion which is important in microfabrication, for example, a multilayer film in which Ti, Al, and Pt are stacked in order from the bottom layer can be preferred as the source electrode 79, and a two-layer film in which Ti and Au are stacked in order from the bottom layer can be preferred as the drain electrode. For example, the insulating layer 77 is SiO x Examples include SiON, SOG (Spin on Glass), and polyimide. n + Layer 78 can be formed by ion implantation. Si or Sn can be used as the dopant, and the amount of dopant is 10 18 cm -3 The above 10 20 cm -3 The following can be listed. Its thickness can be between 50 nm and 500 nm. Note that this n + Since layer 78 is not easy to fabricate, it may be omitted depending on the amount of doping in fin 73.

[0041] The vertical FinFET (203) is manufactured by preparing a fin structure having fins 73 by dry etching an epitaxial β-Ga2O3 layer with a reducing gas under atmospheric pressure using the method described in Embodiment 1, forming an insulating film (gate insulating film) 75 by CVD or sputtering, forming a gate electrode 76 in a region including at least a part of the side surface of the fins 73 by vapor deposition, sputtering, CVD, or MOCVD, forming an insulating layer 77 by sputtering, CVD, or coating, and then forming a source electrode 79 and a drain electrode 80.

[0042] The vertical FinFET (203) is a semiconductor device having the trench structure 101 described in Embodiment 1, wherein a gate electrode is arranged to cover at least both sides (2 and 4 sides) of the fins, which are linear protrusions formed by the plurality of grooves. Furthermore, in the vertical FinFET (203), the side surfaces of the fin 73, which is made of β-Ga2O3 semiconductor that forms the channel layer, reflect the crystal facets and have a low density of unbonded elements, resulting in a low density of crystal defects and interface states on the crystal surface. The combination of such high-quality β-Ga2O3 semiconductor fin 73 and the vertical FinFET structure, which can extract excellent electrical properties, results in an FET with excellent current characteristics.

[0043] In a vertical FinFET (203), a larger channel layer area is desirable to maximize current output. The vertical FinFET structure allows for a larger surface area by forming numerous fins per unit area through microfabrication. According to the present invention, fins 73 with high packing density, fineness, and a high aspect ratio can be formed. Therefore, the vertical FinFET (203) according to Embodiment 4 exhibits excellent electrical characteristics, making it particularly suitable for power devices. [Examples]

[0044] (Example 1) <Sample preparation> First, a β-Ga2O3 substrate 11a was prepared by the EFG method (Figure 3(a)), and amorphous SiO2 (12a) was formed on the substrate 11a (Figure 3(b)). Here, the β-Ga2O3 substrate used was a (001) and (-102) plane substrate manufactured by Novel Crystal Technology. Amorphous SiO2(12a) was formed by plasma chemical vapor deposition using tetraethoxysilane (TEOS) as a precursor, with a film thickness of 100 nm.

[0045] Subsequently, a resist pattern 15 having a groove-like opening pattern was formed (Figure 3(c)). Then, wet etching was performed using hydrofluoric acid buffer (Figure 3(d)), and the resist pattern 15 was subsequently peeled off to form a mask 12 made of SiO2 having groove-like openings 13 (Figure 3(e)). Here, the resist was peeled off by acetone and oxygen plasma ashing to degrease the exposed areas of the β-Ga2O3 substrate.

[0046] Subsequently, the sample was heated to 1038°C using a halide vapor phase epitaxy (HVPE) apparatus as a reducing heat treatment device, and selective etching was performed for 5 minutes with the introduction of HCl gas to fabricate the trench structure 101, which was the evaluation sample (Figure 3(f)). The amount of HCl gas introduced was 5 sccm, and purified N2 gas (dew point <-110°C) was also introduced simultaneously as a carrier gas, and the etching process was carried out under atmospheric pressure. The partial pressure of the HCl gas at this time was 63 Pa.

[0047] HVPE device 2001 is an in-house manufactured device, and its overview is shown in Figure 19. The HVPE apparatus 2001 has a reactor 1001 that can be heated to a desired temperature by a heater 1012. The reactor 1001 is equipped with a gallium raw material supply source 1002 (unused), an oxygen raw material supply source supply pipe 1006 (unused), an etchable gas supply pipe 1008, and a substrate holder 1010. The gas supplied to the reactor 1001, which is made of quartz, is discharged through an exhaust pipe 1011. The etching gas supply tube 1008 supplies etching gas 1009 to the sample placed on the substrate holder 1010 in a controlled amount. A reducing gas is used as the etching gas 1009, but in this example, HCl gas was used because it has low reactivity with quartz and is easy to handle.

[0048] <Rating> The etched samples were evaluated by SEM (Scanning Electron Microscope) observation. The SEM used was a Hitachi SU8230.

[0049] First, the circular window pattern was examined from the surface using a scanning electron microscope (SEM). The results are shown in Figure 9, which reveals that the mask area was not etched, while the window area was. The etching status in the depth direction, several microns deep, can be observed from the density changes, not just on the surface. Furthermore, observation at an accelerating voltage of 10kV revealed that there is an etched region beneath the mask, indicating under-etching. The shape formed by this under-etching is a flattened hexagon, indicating in-plane anisotropy in the under-etching rate.

[0050] To evaluate the in-plane anisotropy in detail, Figure 10 shows the results of observations made from above on a radial window pattern. The window orientations are of two types, as shown in the figure: (a) in 10° increments and (b) the main in-plane orientations. Figure 11 shows the in-plane anisotropy of the amount of under-etching on the surface obtained by observation. Here, n [hkl] This represents the direction obtained by rotating the in-plane [hkl] orientation 90° counterclockwise around the axis perpendicular to the plane. As can be seen from Figure 11, the amount of underetching is small in certain orientations. The orientations with the smallest amount of underetching are [-100] and

[0100] , and the second smallest is n

[0130] , n [-130] , n [1-30] , n [-1-30] This result corresponds to the flattened hexagonal structure shown in Figure 10. Here, in both cases, a slight difference in etching amount is observed between the

[0100] side and the [-100] side (upper and lower sides of the pole figure).

[0051] Since orientations with small amounts of under-etching are useful in the process, we evaluated in more detail the groove-shaped openings (stripe windows) extending in the

[0010] direction. Figure 12 shows SEM images of trenches (window width 1.2 μm, mask width 2.8 μm) and fins (window width 5.5 μm, mask width 1.0 μm) fabricated by selective etching with controlled mask and window widths. It can be seen that submicron fins can also be formed.

[0052] Furthermore, as shown in Figure 13, cross-sections of these structures were machined using a Focused Ion Beam System (FIB) and observed with a Scanning Electron Microscope (SEM). Figure (a) shows the case where the window width is small, and it can be seen that a trench structure has been formed. Figure (b) shows the case where the mask width is small, and it can be seen that submicron fins have been formed. In both cases, the sidewall surface is composed of (100) facets, which have the lowest surface energy density (see Figure 13(c) which shows the processing status after tracing).

[0053] Furthermore, due to the crystal structure, the (100) facet is necessarily tilted at 13.7° rather than vertical. Also, if we focus on the bottom of the trench, when the window width is small and the trench width is small, the bottom is entirely composed of the (-102) plane, but when the window width is large and the trench width is wide, the bottom is composed not only of the (-102) plane but also of the substrate plane, the (001) plane.

[0054] Secondly, cross-sectional observation was also performed in orientations with small underetching. Figure 14 shows the etched cross-section of a groove-shaped opening with a window direction of [-130]. ​​The bottom is composed solely of (001) planes, and the side walls show (310) facet planes, tilted at 8.4°. In this case, regardless of the window width, the bottom is entirely composed of (001) planes, resulting in nearly vertical side walls, which is considered useful for fin formation. However, the amount of underetching is large. Therefore, from the viewpoint of forming fine trench patterns, groove-shaped openings with a window direction of

[0010] , which have less underetching, are considered to be more useful.

[0055] The (-102) substrate is considered a highly useful trench for device applications because the (-102) and the (100) sidewalls are perpendicular to each other. Furthermore, by using the (-102) substrate, it is possible to obtain a trench structure in which the (100) facet sidewalls are perpendicular to each other and the bottom is composed solely of (-102) for all mask widths. Therefore, a β-Ga2O3 substrate 11 with a (-102) plane was prepared and evaluated. The (-102) plane of the substrate was confirmed by X-ray diffraction measurement.

[0056] First, similar to the evaluation using the (001) substrate described above, the in-plane anisotropy of underetching was evaluated by observing the radial window pattern from above using SEM. The results are shown in Figure 15. As a result, it can be seen that the amount of underetching is minimized in the

[0010] direction of the window (groove-shaped opening). This is thought to be because the side surface of the groove is a (100) facet.

[0057] Next, the fabricated trenches (window width 1.4 μm, mask width 2.6 μm) and fins (window width 0.5 μm, mask width 5.7 μm) were observed using SEM. The results are shown in Figure 16, which reveals that the structure is formed by neatly arranged facet shapes.

[0058] Furthermore, cross-sections of these structures were machined using a Focused Ion Beam System (FIB), and these cross-sections were observed using a Scanning Electron Microscope (SEM). The tilt angle was 54°, and a protective film made of carbon was formed on the surface to prevent surface deformation. Figure 17(a) is an SEM image with a small window width, and Figure 17(b) is a traced representation based on that image. It can be seen that a trench structure with a (100) facet surface is formed on the side wall of the groove. The bottom of the groove is located between the (-102) and (-101) surfaces and cannot be determined. Figure 18 is an SEM image of a case where a wide window, a so-called fin, is formed. Similar to the case with a narrow window, the fin sidewalls are (100) faceted surfaces. The surface at the bottom of the groove is relatively rough and, as in Figure 17, is not composed of specific facets. [Industrial applicability]

[0059] The present invention provides a semiconductor device using a β-Ga2O3 semiconductor that is suitable for microfabrication, as it suppresses the generation of interface states and other factors, resulting in excellent device characteristics. This semiconductor device has a trench or fin structure, which brings out the characteristics of a β-Ga2O3 semiconductor with high breakdown voltage and a wide bandgap, and is particularly suitable as a high-performance power device. Power devices are used in a wide range of fields, including powertrains for EVs and hybrid vehicles, power supplies for servers, renewable energy equipment, industrial machinery, and railway vehicles, and are considered essential devices for realizing a smart society. Therefore, we believe that this invention will have a significant social impact and a major influence on industry. [Explanation of Symbols]

[0060] 11 β-Ga2O3 semiconductor layer (a semiconductor layer with grooves) 11a β-Ga2O3 semiconductor layer (semiconductor layer) 12 Mask (SiO2) 12a Thin film (SiO2) 13 Aperture 15 Resist Patterns 51 Substrate (β-Ga2O3 substrate) 52 Mask (SiO2) 53 β-Ga2O3 semiconductor layer 53a β-Ga2O3 epitaxial layer 54 First insulating film 54a Insulating film 55 β-Ga2O3 exposed area (Schottky connection area) 56 Second insulating film 56a insulating film 57 Resist Patterns 58 Electrodes (Anode Electrodes) 58a Conductive film 59 Conductive film (cathode electrode) 71 Substrate (β-Ga2O3) 72 β-Ga2O3 semiconductor layer (epitaxial β-Ga2O3 layer) 73 Fins (β-Ga2O3) 75 Insulating film (gate insulating film) 76 Airports 77 Insulating layer 78 n + layer 79 Source electrodes 80 Drain electrode 101 Trench structure (evaluation sample) 201 Trench SBDMOS 203 Vertical FinFET 301 Semiconductor devices, fin structures, trench structures 1001 Reactor 1002 Gallium raw material source 1003 Gallium metal 1004 Gallium compound gas (halogen gas) 1005 Gallium raw material gas supply pipe 1006 Oxygen raw material supply source supply pipe 1007 Oxygen source gas 1008 Etching gas supply pipe 1009 Etching gas (reducing gas) 1010 PCB holder 1011 Exhaust pipe 1012 Heater 2001 HVPE device

Claims

1. A semiconductor layer having grooves, The semiconductor layer is β-Ga ２ O ３ It consists of crystals, The crystal orientation of the first main surface of the semiconductor layer is (001), The longitudinal direction of the groove is parallel to the intersection line of the surface orientation of the first main surface and the (100) plane. The longitudinal side walls of the groove are (100) faceted surfaces, A semiconductor device wherein the bottom of the groove has a surface orientation of (-101) in locations where the width of the groove is greater than 0 μm and less than or equal to 2.0 μm.

2. The semiconductor device according to claim 1, wherein the bottom of the groove has a surface orientation of (-101) and (001) in places where the width of the groove is 2.0 μm or more.

3. The semiconductor device according to claim 1 or 2, wherein the longitudinal side wall of the groove is inclined at 13.7° with respect to the vertical plane of the first main surface.

4. A semiconductor layer comprising a groove with a bottom, The semiconductor layer is β-Ga ２ O ３ It consists of crystals, The crystal orientation of the first main surface of the semiconductor layer is (-102). The longitudinal direction of the groove is parallel to the intersection line of the surface orientation of the first main surface and the (100) plane. A semiconductor device wherein at least one of the longitudinal side walls of the groove is a (100) facet surface and is perpendicular to the first main surface.

5. A semiconductor layer having grooves, The semiconductor layer is β-Ga ２ O ３ It consists of crystals, The crystal orientation of the first main surface of the semiconductor layer is (001), The longitudinal direction of the groove is parallel to the intersection line of the surface orientation of the first main surface and the {310} plane. The longitudinal side walls of the groove are {310} faceted surfaces. The bottom of the groove has a surface orientation of (001), A semiconductor device wherein the longitudinal side walls of the groove are inclined at 8.4° with respect to the vertical plane of the first main surface.

6. The semiconductor device according to claim 1, 4, or 5, wherein at least a portion of at least one side surface of the groove is a channel.

7. The semiconductor device according to claim 1, 4, or 5, comprising a Fin-type MOSFET structure having a linear protruding semiconductor layer formed by a plurality of grooves.

8. The anode electrode is formed in at least a part of the three-dimensional structure having the side surface and the bottom, via an insulating film disposed at least a part of the side surface and the bottom of the groove. The semiconductor device according to claim 1, 4, or 5, further comprising a Tench-type MOSBD structure in which the anode electrode is Schottky connected to the semiconductor layer as part of the three-dimensional structure.

9. A power device having the semiconductor device described in claim 1, 4, or 5.

10. β-Ga whose first main surface orientation is (001) or (-102) ２ O ３ Preparing a semiconductor layer made of crystals, An etching mask having groove-shaped openings having a longitudinal direction parallel to the intersection lines of one or more crystal planes selected from the group consisting of (100) and {310} is formed on the first main surface, Using a reducing gas, under atmospheric pressure, at 300°C to 1200°C inclusive, the β-Ga exposed at the opening of the mask ２ O ３ A method of manufacturing a semiconductor device, comprising selectively etching crystals.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the reducing gas is one or more gases selected from the group consisting of hydrogen halide gases and hydrogen gases.

12. The method for manufacturing a semiconductor device according to claim 10, wherein the reducing gas is hydrogen chloride gas.

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