Wiring board, semiconductor device, and method for manufacturing a wiring board

Abstract

To suppress the occurrence of damage.SOLUTION: A wiring board includes a first wiring board, a plurality of second wiring boards, and an adhesive layer. The plurality of second wiring boards are arranged adjacent to each other on the first wiring board. The adhesive layer bonds the first wiring board and the plurality of second wiring boards. The adhesive layer has a filling portion that fills a groove formed by facing the side surfaces of the adjacent second wiring boards.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a wiring substrate, a semiconductor device, and a method for manufacturing a wiring substrate.

Background Art

[0002] Conventionally, for example, a laminated wiring substrate in which a relay substrate having fine wiring is laminated on a main substrate is known. When a relatively large semiconductor chip or the like is mounted on such a laminated wiring substrate, a plurality of relay substrates may be arranged and laminated on one main substrate to constitute a laminated wiring substrate. That is, by laminating a plurality of relay substrates adjacent to each other on a large main substrate, a large laminated wiring substrate can be configured, and a large semiconductor chip or the like can be mounted thereon.

Prior Art Literature

Patent Literature

[0003]

Patent Literature 1

Summary of the Invention

Problem to be Solved by the Invention

[0004] However, in a laminated wiring substrate obtained by laminating a plurality of relay substrates on a single main substrate, there is a problem that the relay substrate may be damaged when deformation such as warpage of the main substrate occurs.

[0005] That is, for example, when a heat cycle test for evaluating the reliability of a laminated wiring substrate is performed, thermal expansion and thermal contraction deform the main substrate and cause warpage. At this time, along with the warpage of the main substrate, the opposing side surfaces of adjacent relay substrates approach each other. As a result, the opposing side surfaces of adjacent relay substrates may collide with each other, damaging the relay substrates.

[0006] The disclosed technology was made in view of the above, and aims to provide a wiring board, a semiconductor device, and a method for manufacturing a wiring board that can suppress the occurrence of damage. [Means for solving the problem]

[0007] In one embodiment, the wiring board disclosed in this application comprises a first wiring board, a plurality of second wiring boards, and an adhesive layer. The plurality of second wiring boards are arranged adjacent to each other on the first wiring board. The adhesive layer adheres the first wiring board to the plurality of second wiring boards. The adhesive layer has a filling portion that fills the groove formed by the facing sides of adjacent second wiring boards. [Effects of the Invention]

[0008] According to one embodiment of the wiring board disclosed in this application, the effect is that the occurrence of damage can be suppressed. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows the structure of a substrate according to an embodiment. [Figure 2] Figure 2 is a flowchart showing the manufacturing method of the main substrate. [Figure 3] Figure 3 shows a specific example of the core layer formation process. [Figure 4] Figure 4 shows a specific example of the build-up process. [Figure 5] Figure 5 shows a specific example of the solder resist layer formation process. [Figure 6] Figure 6 shows a specific example of the pad formation process. [Figure 7] Figure 7 is a flowchart showing the method for manufacturing a relay substrate. [Figure 8] Figure 8 shows a specific example of a glass support. [Figure 9] Figure 9 shows a specific example of the pad formation process. [Figure 10]FIG. 10 is a diagram showing a specific example of a flash etching step. [Figure 11] FIG. 11 is a diagram showing a specific example of an insulating layer forming step. [Figure 12] FIG. 12 is a diagram showing a specific example of a via hole forming step. [Figure 13] FIG. 13 is a diagram showing a specific example of an electrolytic copper plating step. [Figure 14] FIG. 14 is a diagram showing a specific example of a chemical mechanical polishing step. [Figure 15] FIG. 15 is a diagram showing a specific example of a second wiring structure forming step. [Figure 16] FIG. 16 is a diagram showing a configuration of an assembly of depaneled interposer substrates. [Figure 17] FIG. 17 is a diagram showing a specific example of a solder adding step. [Figure 18] FIG. 18 is a diagram showing a specific example of an adhesive layer forming step. [Figure 19] FIG. 19 is a diagram showing a specific example of a cutting step. [Figure 20] FIG. 20 is a flowchart showing a method of manufacturing a substrate. [Figure 21] FIG. 21 is a diagram showing a specific example of an interposer substrate mounting step. [Figure 22] FIG. 22 is a diagram showing a specific example of an adhering step. [Figure 23] FIG. 23 is a diagram showing a specific example of a curing step. [Figure 24] FIG. 24 is a diagram showing a configuration example of a semiconductor device. MODE FOR CARRYING OUT THE INVENTION

[0010] Hereinafter, embodiments of the wiring substrate, the semiconductor device, and the method of manufacturing the wiring substrate disclosed in the present application will be described in detail with reference to the drawings. Note that the disclosed technology is not limited by this embodiment.

[0011] Figure 1 shows the structure of a substrate 1 according to an embodiment. Figure 1 schematically shows a cross-section of the substrate 1 according to the embodiment. The substrate 1 shown in Figure 1 is a laminated wiring board obtained by laminating a plurality of relay substrates, including relay substrates (examples of second wiring boards) 200a and 200b, on a main substrate (an example of a first wiring board) 100, and bonding the main substrate 100 and the plurality of relay substrates with an adhesive layer 300. In the following description, the direction from the main substrate 100 toward the relay substrates 200a and 200b in Figure 1 is considered up, and the direction from the relay substrates 200a and 200b toward the main substrate 100 is considered down. However, the main substrate 100 and the relay substrates 200a and 200b may be manufactured and used upside down, for example, or in any orientation.

[0012] The main substrate 100 has a core layer 110 and build-up layers 120 and 130.

[0013] The core layer 110 has wiring layers formed on both sides of an insulating substrate by plating. The wiring layers on both sides are connected by vias 111 as needed.

[0014] The build-up layer 120 is formed on the upper surface of the core layer 110 and consists of layers laminated together, each comprising an insulating layer made of, for example, build-up resin and a wiring layer 121 made of a conductor. Each wiring layer 121 is connected by vias 122. The surface of the build-up layer 120 is covered with a solder resist layer 123. In the region of the build-up layer 120 that includes the position where the vias 122 are exposed, an opening is formed in the solder resist layer 123, and an electrode pad 124 that connects to the vias 122 is formed. The electrode pad 124 is made of, for example, a conductor such as copper and serves as a connection terminal when the main substrate 100 is joined to the intermediate substrates 200a and 200b.

[0015] The build-up layer 130 is formed on the underside of the core layer 110 and consists of layers laminated together, each comprising an insulating layer made of, for example, build-up resin and a wiring layer 131 made of a conductor. Each wiring layer 131 is connected by vias 132. Electrode pads 134 are formed on the surface of the build-up layer 130, made of, for example, a conductor such as copper, and serve as connection terminals when the main substrate 100 is joined to external components such as a motherboard. The surface of the build-up layer 130 is then covered with a solder resist layer 133 that exposes the electrode pads 134.

[0016] Each of the relay substrates 200a and 200b has a base layer first wiring structure 210 and a second wiring structure 220 in which multiple thin film layers are laminated. An electrode pad 211 is formed on the lower surface of the first wiring structure 210. The electrode pad 211 is made of a conductor such as copper and serves as a connection terminal when the relay substrates 200a and 200b are joined to the main substrate 100. The electrode pad 211 is also connected to the wiring of the second wiring structure 220 via vias 212. When the relay substrates 200a and 200b are mounted on the main substrate 100, the electrode pad 211 is joined to an electrode pad 124, which is a connection terminal of the main substrate 100, by solder 101.

[0017] The intermediate substrates 200a and 200b are mounted on the main substrate 100 adjacent to each other and bonded together. That is, the intermediate substrates 200a and 200b and the main substrate 100 are bonded together by the adhesive layer 300. The sides of the adjacent intermediate substrates 200a and 200b face each other, forming a groove at the boundary between the intermediate substrates 200a and 200b. A filler portion 301, which is part of the adhesive layer 300, is formed in this groove.

[0018] The adhesive layer 300 is a layer made of a thermosetting resin such as NCF (Non-Conductive Film), and it adheres the intermediate substrates 200a and 200b to the main substrate 100. That is, the adhesive layer 300 is formed between the lower surfaces of the multiple intermediate substrates, including the intermediate substrates 200a and 200b, and the upper surface of the main substrate 100, and it adheres the multiple intermediate substrates to the main substrate 100. A portion of the adhesive layer 300 fills the grooves formed by the opposing sides of adjacent intermediate substrates 200a and 200b, forming a filled portion 301.

[0019] In this way, the filling portion 301 fills the groove formed by the opposing sides of the adjacent relay substrates 200a and 200b, thereby protecting the opposing sides of the adjacent relay substrates 200a and 200b. Therefore, even if deformation such as warping occurs in the main substrate 100, the opposing sides of the adjacent relay substrates 200a and 200b will not collide with each other, and as a result, damage to the relay substrates 200a and 200b can be suppressed.

[0020] Furthermore, the end face 301a of the filling portion 301 is located on the same plane as the upper surfaces of the adjacent relay substrates 200a and 200b. As a result, when semiconductor chips are mounted on the relay substrates 200a and 200b via the underfill resin, the underfill resin does not enter the groove formed by the opposing sides of the adjacent relay substrates 200a and 200b. Therefore, it is possible to suppress the concentration of stress based on the difference in thermal expansion coefficients between the underfill resin and the resin forming the adhesive layer 300 on the opposing sides of the adjacent relay substrates 200a and 200b, thereby suppressing the occurrence of cracks on those sides.

[0021] Furthermore, the adhesive layer 300 adheres the relay substrates 200a and 200b to the main substrate 100 while covering a portion of the non-facing sides of the adjacent relay substrates 200a and 200b. As a result, all sides of each of the adjacent relay substrates 200a and 200b are covered by the adhesive layer 300 and the filler portion 301. Therefore, the stress acting on the relay substrates 200a and 200b when semiconductor chips are mounted on them is evenly distributed from each side of the relay substrates 200a and 200b to the adhesive layer 300. Consequently, damage to the relay substrates 200a and 200b caused by stress concentration can be suppressed.

[0022] Next, a method for manufacturing the substrate 1 configured as described above will be explained. Below, the method for manufacturing the main substrate 100 and the intermediate substrates 200a and 200b will be explained, followed by a method for manufacturing the substrate 1 having the main substrate 100 and the intermediate substrates 200a and 200b.

[0023] Figure 2 is a flowchart showing the manufacturing method of the main substrate 100.

[0024] First, a core layer 110, which will serve as a support member for the main substrate 100, is formed (step S101). Specifically, as shown in Figure 3, for example, vias 111 penetrating the substrate are formed on an insulating substrate, and metal layers, such as copper, are formed on both sides of the substrate. Figure 3 is a diagram showing a specific example of the core layer formation process. The wiring layers on both sides of the substrate are connected by vias 111 as needed.

[0025] Then, build-up layers 120 and 130 are formed on the upper and lower surfaces of the core layer 110 by a build-up method (step S102). Specifically, as shown in Figure 4, for example, a layer having an insulating layer and a wiring layer 121 is laminated on the upper surface of the core layer 110 to form the build-up layer 120. Figure 4 is a diagram showing a specific example of the build-up process. The wiring layer 121 is connected by vias 122 that penetrate the insulating layer. Also, a layer having an insulating layer and a wiring layer 131 is laminated on the lower surface of the core layer 110 to form the build-up layer 130. The wiring layer 131 is connected by vias 132 that penetrate the insulating layer. In addition, electrode pads 134 are formed on the surface of the build-up layer 130. The insulating layer is formed using an insulating resin such as epoxy resin or polyimide resin. The wiring layers 121, 131, vias 122, 132 and electrode pads 134 are formed by plating with a metal such as copper.

[0026] Then, solder resist layers 123 and 133 are formed on the surfaces of the build-up layers 120 and 130 (step S103). That is, as shown in Figure 5, the surface of the build-up layer 120 is covered by the solder resist layer 123, and the surface of the build-up layer 130 is covered by the solder resist layer 133. Figure 5 is a diagram showing a specific example of the solder resist layer formation process. In the region of the build-up layer 120 that includes the position corresponding to the uppermost via 122, an opening is formed in the solder resist layer 123. In other words, the upper surface of the via 122 is exposed through the opening in the solder resist layer 123. On the other hand, in the position of the build-up layer 130 that corresponds to the electrode pad 134, an opening is formed in the solder resist layer 133. In other words, the electrode pad 134 is exposed through the opening in the solder resist layer 133.

[0027] Next, connection terminals for connecting the main substrate 100 and the intermediate substrates 200a and 200b are formed at the position where the upper surface of the via 122 of the uppermost layer of the build-up layer 120 is exposed at the opening of the solder resist layer 123 (step S104). That is, as shown in Figure 6 for example, electrode pads 124, which are connection terminals, are formed at the position where the upper surface of the via 122 of the uppermost layer of the build-up layer 120 is exposed, for example by copper plating. Figure 6 is a diagram showing a specific example of the pad formation process. With the formation of the electrode pads 124, the main substrate 100 that forms the lower layer of the substrate 1 is obtained.

[0028] Next, Figure 7 is a flowchart showing the manufacturing methods for relay substrates 200a and 200b.

[0029] First, a glass support 400, which will serve as the support for manufacturing the intermediate substrates 200a and 200b, is prepared (step S201). Specifically, as shown in Figure 8, for example, a release layer 401, a first metal layer 402, and a second metal layer 403 are formed sequentially on the flat upper surface of the glass support 400. Figure 8 shows a specific example of the glass support 400. The first metal layer 402 is formed, for example, by titanium sputtering, and the second metal layer 403 is formed, for example, by copper sputtering. Although an example using a glass support 400 as the support for manufacturing the intermediate substrates 200a and 200b is shown here, a support made from a core material or a metal plate or other material that can be used for process transport may be used instead of the glass support 400.

[0030] Then, an electrode pad 211 is formed above the second metal layer 403 (step S202). Specifically, as shown in Figure 9, for example, a resist layer 251 having an opening 251a is formed on the second metal layer 403, and the electrode pad 211 is formed on the second metal layer 403 exposed at the opening 251a by electroplating. Figure 9 shows a specific example of the pad formation process. The resist layer 251 is formed using, for example, a dry film resist, and the opening 251a can be formed by, for example, photolithography or laser processing.

[0031] Next, the resist layer 251 is removed, and unnecessary portions of the second metal layer 403 are removed by flash etching (step S203). Specifically, the etching solution that dissolves the second metal layer 403 dissolves the portion of the second metal layer 403 that is exposed without contacting the electrode pad 211, and as shown in Figure 10, for example, the first metal layer 402 is exposed in the portion that is not in contact with the electrode pad 211. Figure 10 shows a specific example of the flash etching process.

[0032] Once the electrode pad 211 is formed, an insulating layer of the first wiring structure 210 that covers the electrode pad 211 is formed on the first metal layer 402 (step S204). That is, as shown in Figure 11, for example, a semi-cured first insulating layer 213, a second insulating layer 214, and a third insulating layer 215 are sequentially laminated on the first metal layer 402, and the electrode pad 211 is covered by the first insulating layer 213 and the second insulating layer 214. Figure 11 is a diagram showing a specific example of the insulating layer formation process. The first insulating layer 213 is formed using an insulating resin that hardens by heat, such as epoxy resin or polyimide resin. The second insulating layer 214 is laminated adjacent to and above the first insulating layer 213 and is formed by impregnating a reinforcing member such as glass fiber with an insulating resin. The inclusion of a reinforcing member in the second insulating layer 214 improves the strength of the relay substrates 200a and 200b. The insulating resin impregnated into the reinforcing member of the second insulating layer 214 is a resin that hardens by heat, such as epoxy resin or polyimide resin. The third insulating layer 215 is laminated adjacent to and above the second insulating layer 214 and is formed using an insulating resin that hardens by heat, such as epoxy resin or polyimide resin. The insulating layer formed on the first metal layer 402 is heat-cured.

[0033] Then, via holes are formed in the first wiring structure 210 (step S205). Specifically, as shown in Figure 12, for example, via holes 252 are formed that penetrate the second insulating layer 214 and the third insulating layer 215 and expose the upper surface of the electrode pad 211. Figure 12 is a diagram showing a specific example of the via hole formation process. The via holes 252 can be formed, for example, by laser processing. Residue of insulating resin (smear) generated by laser processing is removed by desmearing, and electroless copper plating 253 is applied to the surface of the first wiring structure 210.

[0034] Once the via holes 252 are formed, electrolytic copper plating is applied to form the vias 212 of the first wiring structure 210 (step S206). Specifically, a resist layer having openings at the positions of the via holes 252 is formed on the upper surface of the first wiring structure 210 (i.e., the upper surface of the third insulating layer 215), and the entire intermediate structure laminated on the glass support 400 is immersed in the plating solution to perform electrolytic copper plating. As a result, electrolytic copper is filled into the via holes 252, forming the vias 212, as shown in Figure 13, for example. Figure 13 shows a specific example of the electrolytic copper plating process. After electrolytic copper plating, the resist layer having openings at the positions of the vias 212 is removed, and the electroless copper plating 253 that was in contact with the resist layer is removed by flash etching. Note that the electroless copper plating 253 in contact with the vias 212 remains even after flash etching, but is omitted from the illustration in Figure 13.

[0035] Then, the first wiring structure 210 is completed by chemical mechanical polishing (CMP) on the upper surface of the intermediate structure (step S207). Specifically, as shown in Figure 14, for example, the CMP process creates a first wiring structure 210 with a flat upper surface 210a on the glass support 400. Figure 14 shows a specific example of the chemical mechanical polishing process.

[0036] Once the first wiring structure 210 is completed, the second wiring structure 220 is formed on the upper surface 210a of the first wiring structure 210 (step S208). That is, as shown in Figure 15, for example, four thin film layers are sequentially stacked on the first wiring structure 210 by a build-up method to form the second wiring structure 220 having a wiring layer 225 containing fine wiring. Figure 15 is a diagram showing a specific example of the second wiring structure formation process. Here, it is assumed that the second wiring structure 220 is formed by stacking four thin film layers on the upper surface 210a of the first wiring structure 210, but the number of thin film layers stacked on the upper surface 210a of the first wiring structure 210 does not have to be four. The four thin film layers are thin film layers in which a wiring layer 225 containing fine wiring is formed on an insulating layer. The wiring layers 225 of the four thin film layers are connected by vias 226 that penetrate the insulating layer.

[0037] By the steps taken so far, an intermediate structure is obtained in which a first wiring structure 210 and a second wiring structure 220 are formed on the glass support 400. The first wiring structure 210 and the second wiring structure 220 constitute an assembly including relay substrates 200a and 200b. Therefore, by depaneling the first wiring structure 210 and the second wiring structure 220 from the intermediate structure (step S209), an assembly including relay substrates 200a and 200b is obtained. Specifically, for example as shown in Figure 16, the layer above the first metal layer 402 of the intermediate structure is peeled off from the release layer 401, thereby obtaining an assembly 200 including relay substrates 200a and 200b. Figure 16 is a diagram showing the structure of the assembly 200 of depaneled relay substrates 200a and 200b.

[0038] Next, as shown in Figure 17, for example, the first metal layer 402 is removed and solder 101 is added to the electrode pad 211 (step S210). Figure 17 is a diagram showing a specific example of the soldering process.

[0039] When solder 101 is applied to the electrode pad 211, an adhesive layer 300 covering the solder 101 is formed on the lower surface of the assembly 200 including the relay substrates 200a and 200b (i.e., the lower surface of the first wiring structure 210) (step S211). That is, as shown in Figure 18, for example, an uncured adhesive layer 300 is laminated on the lower surface of the assembly 200 including the relay substrates 200a and 200b, and the solder 101 is covered by the uncured adhesive layer 300. Figure 18 is a diagram showing a specific example of the adhesive layer formation process.

[0040] Once the adhesive layer 300 is formed, the assembly 200, including the intermediate substrates 200a and 200b, is cut, for example, by a dicer or slicer (step S212) to separate it into intermediate substrates 200a and 200b of appropriate size. That is, as shown in Figure 19, for example, the assembly 200 is cut along the cutting line A that defines the intermediate substrates 200a and 200b, thereby obtaining multiple intermediate substrates including the intermediate substrates 200a and 200b that form the upper layer of the substrate 1. Figure 19 shows a specific example of the cutting process.

[0041] Next, Figure 20 is a flowchart showing the manufacturing method of substrate 1. Substrate 1 is manufactured using the main substrate 100 and intermediate substrates 200a and 200b described above.

[0042] First, multiple relay substrates are mounted on the main substrate 100 via an uncured adhesive layer 300 (step S301). Specifically, as shown in Figure 21, for example, multiple relay substrates, including relay substrates 200a and 200b, each having an adhesive layer 300 formed on its lower surface, are mounted side by side on the main substrate 100 via the uncured adhesive layer 300. At this time, the relay substrates 200a and 200b are aligned so that the solder 101 applied to their respective electrode pads 211 faces the electrode pads 124 of the main substrate 100. Figure 21 shows a specific example of the relay substrate mounting process. Adjacent relay substrates 200a and 200b are mounted on the main substrate 100 with a gap between them, and a groove 235 is formed by the opposing sides of the relay substrates 200a and 200b. In other words, when multiple relay boards, including relay boards 200a and 200b, are mounted on the main board 100, grooves 235 are formed at the boundary between adjacent relay boards 200a and 200b.

[0043] Next, multiple intermediate substrates, including intermediate substrates 200a and 200b, are bonded to the main substrate 100 by the adhesive layer 300 (step S302). Specifically, first, a release film 501 is laminated onto the upper surfaces of the intermediate substrates 200a and 200b so as to close the opening of the groove 235. Then, for example as shown in Figure 22, the release film 501 is pressed from above by a pressure plate 500, thereby bonding the intermediate substrates 200a and 200b to the upper surfaces of the main substrate 100 by the adhesive layer 300. At this time, the adhesive layer 300 sandwiched between the main substrate 100 and the intermediate substrates 200a and 200b is discharged around the intermediate substrates 200a and 200b, covering a portion of the non-facing sides of adjacent intermediate substrates 200a and 200b and forming a fillet. In addition, a portion of the adhesive layer 300 fills the groove 235, forming a filled portion 301. The filling portion 301 seals the boundary between adjacent relay substrates 200a and 200b, protecting the opposing sides of the adjacent relay substrates 200a and 200b. Therefore, even if deformation such as warping occurs in the main substrate 100, the opposing sides of the adjacent relay substrates 200a and 200b will not collide with each other, and as a result, damage to the relay substrates 200a and 200b can be suppressed. Figure 22 shows a specific example of the bonding process.

[0044] Furthermore, the filling portion 301, which is part of the adhesive layer 300, reaches the release film 501, which is located on the same plane as the upper surfaces of the adjacent relay substrates 200a and 200b, as shown in Figure 22. In other words, the end face 301a of the filling portion 301 is located on the same plane as the upper surfaces of the adjacent relay substrates 200a and 200b. This prevents the underfill resin from entering the groove formed by the opposing sides of the adjacent relay substrates 200a and 200b when semiconductor chips are mounted on the relay substrates 200a and 200b via the underfill resin.

[0045] Furthermore, the adhesive layer 300 has a lower coefficient of thermal expansion than the insulating resin that forms the insulating layer of the second wiring structure 220 in the relay substrates 200a and 200b. For example, the coefficient of thermal expansion of the insulating resin that forms the insulating layer of the second wiring structure 220 is 40-70 (ppm / °C), while the coefficient of thermal expansion of the adhesive layer 300 is 20-40 (ppm / °C). Because the coefficient of thermal expansion of the adhesive layer 300 is lower than that of the insulating resin that forms the insulating layer of the second wiring structure 220, thermal expansion and contraction of the adhesive layer 300 are suppressed, thereby reducing stress concentration from the adhesive layer 300 to the relay substrates 200a and 200b. In addition, the adhesive layer 300 has a higher elastic modulus than the insulating resin that forms the insulating layer of the second wiring structure 220 in the relay substrates 200a and 200b. For example, the elastic modulus of the insulating resin forming the insulating layer of the second wiring structure 220 is 2 to 4 (GPa), and the elastic modulus of the adhesive layer 300 is 6 to 9 (GPa). Because the elastic modulus of the adhesive layer 300 is higher than that of the insulating resin forming the insulating layer of the second wiring structure 220, the stress on the opposing sides of the relay substrates 200a and 200b can be relieved.

[0046] When multiple intermediate substrates, including intermediate substrates 200a and 200b, are bonded together, the adhesive layer 300 is heat-cured (step S303). Specifically, with the opening of the groove 235 sealed by the release film 501, the release film 501 is pressurized and heated from above by an elastic pressure plate 600, for example, as shown in Figure 23, thereby heat-curing the adhesive layer 300. Figure 23 shows a specific example of the curing process. When the adhesive layer 300 is heat-cured, the pressure plate 600 is heated to a temperature above the melting point of the solder 101 applied to each electrode pad 211 of the intermediate substrates 200a and 200b. As a result, the solder 101 melts, and the electrode pads 211 of the intermediate substrates 200a and 200b are joined to the electrode pads 124 of the main substrate 100 by the solder 101. Once the adhesive layer 300 has set and the soldering by 101 is complete, the release film 501 is removed. This completes the substrate 1.

[0047] Substrate 1 can be used in semiconductor devices that mount components such as semiconductor chips. Specifically, as shown in Figure 24, semiconductor chips 710 and 720 are mounted on the upper surface of substrate 1 (i.e., the upper surfaces of the relay substrates 200a and 200b). Semiconductor chip 710 is mounted on the upper surface of relay substrate 200a. Figure 24 shows an example of the configuration of a semiconductor device. That is, the electrodes 715 of semiconductor chip 710 and the wiring layer 225 located on the uppermost layer of relay substrate 200a are joined by solder 201. Semiconductor chip 720 is mounted across the upper surfaces of adjacent relay substrates 200a and 200b and the end face 301a of the filling portion 301. That is, the electrodes 725 of semiconductor chip 720 and the wiring layer 225 located on the uppermost layer of relay substrate 200a are joined by solder 201, and the electrodes 725 of semiconductor chip 720 and the wiring layer 225 located on the uppermost layer of relay substrate 200b are joined by solder 202. The joints between electrode 715 and wiring layer 225, and between electrode 725 and wiring layer 225, are sealed with underfill resin 730. This results in a semiconductor device in which semiconductor chips 710 and 720 are mounted on relay substrates 200a and 200b via underfill resin 730.

[0048] When semiconductor chips 710 and 720 are mounted via the underfill resin 730, the end face 301a of the filling portion 301 is on the same plane as the upper surface of the intermediate substrates 200a and 200b, so the underfill resin 730 does not penetrate into the boundary portion of the intermediate substrates 200a and 200b. Therefore, it is possible to suppress the concentration of stress based on the difference in thermal expansion coefficients between the underfill resin 730 and the resin forming the adhesive layer 300 on the opposing sides of the adjacent intermediate substrates 200a and 200b. As a result, it is possible to suppress the occurrence of cracks on the opposing sides of the adjacent intermediate substrates 200a and 200b.

[0049] As described above, the wiring board according to the embodiment (for example, substrate 1) comprises a first wiring board (for example, main substrate 100), a plurality of second wiring boards (for example, relay substrates 200a, 200b), and an adhesive layer (for example, adhesive layer). The plurality of second wiring boards are arranged adjacent to each other on the first wiring board. The adhesive layer adheres the first wiring board to the plurality of second wiring boards. The adhesive layer has a filling portion (for example, filling portion 301) that fills a groove (for example, groove 235) formed by the facing sides of adjacent second wiring boards. As a result, the wiring board according to the embodiment can suppress the occurrence of damage.

[0050] Furthermore, the filling portion may have an end face (for example, end face 301a) that is located on the same plane as the upper surface of the adjacent second wiring board. As a result, according to the wiring board of the embodiment, when semiconductor chips (for example, semiconductor chips 710, 720) are mounted via the underfill resin (for example, underfill resin 730), the underfill resin does not penetrate into the boundary portion of the adjacent second wiring board.

[0051] Furthermore, the second wiring board may have a wiring structure (for example, a second wiring structure 220) comprising a laminated wiring layer and an insulating layer. The adhesive layer may have a lower coefficient of thermal expansion than the insulating resin forming the insulating layer of the wiring structure. As a result, according to the wiring board of the embodiment, thermal expansion and contraction of the adhesive layer are suppressed, thereby reducing stress concentration from the adhesive layer to the second wiring board.

[0052] Furthermore, the adhesive layer may bond the first wiring board to a plurality of second wiring boards while covering a portion of the non-facing side surfaces of adjacent second wiring boards. As a result, according to the wiring board of this embodiment, it is possible to suppress the occurrence of damage to the second wiring boards caused by stress concentration. [Explanation of Symbols]

[0053] 1 circuit board 100 Main board 120,130 build-up layer 200a, 200b relay board 210 1st wiring structure 220 2nd wiring structure 235 Groove 300 adhesive layer 301 Filling section 301a End face 710,720 semiconductor chips

Claims

1. First wiring board and A plurality of second wiring boards arranged adjacent to each other on the first wiring board, An adhesive layer for bonding the first wiring board and the plurality of second wiring boards. It has, Each of the plurality of second wiring boards has a wiring structure comprising a plurality of insulating layers including a plurality of alternately stacked wiring layers and a resin layer made of an insulating resin that hardens by heat curing, The adhesive layer has a filling portion that fills the groove formed by the opposing sides of the adjacent second wiring boards. The aforementioned filling section is A wiring board characterized by having an end face located on the same plane as the upper surface of the uppermost insulating layer in the plurality of insulating layers included in the wiring structure of at least two adjacent second wiring boards among the plurality of second wiring boards.

2. The aforementioned adhesive layer is The wiring substrate according to claim 1, characterized in that its coefficient of thermal expansion is lower than that of the insulating resin forming the insulating layer of the wiring structure.

3. The aforementioned adhesive layer is The wiring board according to claim 1, characterized in that the first wiring board and the plurality of second wiring boards are bonded together while covering a portion of the non-facing side surface of an adjacent second wiring board.

4. The adhesive layer has a covering portion that covers a part of the non-facing side surface of the adjacent second wiring board, The end face is higher in height from the first wiring board than the top of the covering portion. The wiring board according to feature 3.

5. Wiring board and The semiconductor chip mounted on the aforementioned wiring board and It has, The aforementioned wiring board is First wiring board and A plurality of second wiring boards arranged adjacent to each other on the first wiring board, An adhesive layer for bonding the first wiring board and the plurality of second wiring boards. It has, The adhesive layer has a filling portion that fills the groove formed by the opposing sides of the adjacent second wiring boards. The aforementioned filling section is It has an end face that is located on the same plane as the upper surface of at least two adjacent second wiring boards among the plurality of second wiring boards, The aforementioned semiconductor chip is A semiconductor device characterized by being mounted across the upper surface of the adjacent second wiring board and the end surface of the filling portion.

6. Multiple second wiring boards are mounted adjacent to each other on the first wiring board via an uncured adhesive layer. The plurality of second wiring boards are bonded onto the first wiring board by the adhesive layer, The process includes curing the adhesive layer, The bonding step involves filling a portion of the adhesive layer into a groove formed by the opposing sides of the adjacent second wiring boards. The aforementioned bonding step is, By laminating a release film onto the upper surfaces of the plurality of second wiring boards so as to close the openings in the grooves and applying pressure, a portion of the adhesive layer is filled into the grooves and reaches the release film located on the same plane as the upper surfaces of adjacent second wiring boards. A method for manufacturing a wiring board, characterized by the following:

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