Semiconductor and electronic equipment

Abstract

To provide a semiconductor device that can reduce a leakage current and improve a breakdown voltage.SOLUTION: A semiconductor device includes a semiconductor substrate including a first layer and having a first region in plan view, an anode electrode located on the first region of the semiconductor substrate, a first semiconductor layer of a first conductivity type located in the first layer, and a second semiconductor region of a second conductivity type located on the top of the first layer. The second semiconductor region is located in a part of the first region in plan view. The anode electrode is joined to the second semiconductor region and the first semiconductor layer. The second semiconductor region has a linear shape in plan view, and includes a curved section curved at a corner of the first region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and an electronic apparatus. [Background Art]

[0002] Patent Document 1 describes a junction barrier Schottky diode (JBS) as a semiconductor device. The semiconductor device comprises a guard ring surrounding an active region, and a striped low-resistance layer located inside the active region. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Unexamined Patent Publication No. 2016-66813 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] Further improvement in characteristics is desired for semiconductor devices. An object of the present disclosure is to provide a semiconductor device capable of achieving reduction in leakage current and improvement in breakdown voltage. [Means for Solving the Problem]

[0005] A semiconductor device according to the present disclosure includes: a semiconductor substrate including a first layer and having a first region in plan perspective view; an anode electrode located on the first region of the semiconductor substrate; a first semiconductor layer of a first conductivity type located in the first layer; a second semiconductor region of a second conductivity type located above the first layer; wherein the second semiconductor region is located in a part of the first region in plan perspective view, the anode electrode is joined to the second semiconductor region and the first semiconductor layer, the second semiconductor region is Having a linear shape in planar perspective, and including a curved section at the corner of the first region, The system comprises multiple preceding second semiconductor regions, The edge of the first region includes a first corner and a first and second side adjacent to the first corner, The plurality of second semiconductor regions include a first linear portion extending along the first edge to the second edge in a planar perspective view, and a plurality of second linear portions located between the first linear portion and the first edge. The plurality of second linear portions have a straight section extending along the first side and a curved section curving along the first corner, and the curved section It has an end, and the end is It is joined to the first linear portion.

[0006] The electronic equipment relating to this disclosure includes the semiconductor devices described above. [Effects of the Invention]

[0007] According to this disclosure, it is possible to reduce leakage current and improve breakdown voltage in semiconductor devices. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view (A) showing a semiconductor device of Embodiment 1 of the present disclosure and a diagram (B) illustrating the first region. [Figure 2] This is a cross-sectional view along line AA in Figure 1(A). [Figure 3] This is an enlarged view showing the area around the first corner of the first region. [Figure 4] This graph shows the characteristics of the semiconductor device of Embodiment 1 and the comparative example. [Figure 5] This is a plan view showing a semiconductor device according to Embodiment 2 of the present disclosure. [Modes for carrying out the invention]

[0009] Each embodiment of this disclosure will be described in detail below with reference to the drawings.

[0010] (Embodiment 1) Figure 1 is a plan view (A) and a diagram (B) illustrating the first region of a semiconductor device according to Embodiment 1 of the present disclosure. In Figure 1(A), the guard ring 41 is shown by shading. Figure 1(A) shows the configuration excluding elements above the semiconductor substrate 101 (anode electrode 31, field insulating film 42, and surface protective film 43). Figure 2 is a cross-sectional view along line AA in Figure 1(A).

[0011] The semiconductor device 1 of this embodiment 1 is a junction barrier Schottky diode (JBS) having a Schottky junction region and a pn junction region between the anode electrode 31 and the cathode electrode 37. The presence of the Schottky junction region reduces the forward voltage and improves the switching speed. The presence of the pn junction region causes a depletion layer to spread near the pn junction region during reverse bias. Therefore, compared to a Schottky barrier diode without a pn junction region, the semiconductor device 1 can reduce leakage current. Furthermore, the presence of the pn junction region reduces the forward resistance and improves surge resistance.

[0012] As shown in Figure 1(B), the semiconductor device 1 includes a semiconductor substrate 101 having a first region 21 in planar view. Planar view means viewing from a direction perpendicular to the upper surface of the semiconductor substrate 101. The first region 21 may have a Schottky junction region and a pn junction region, and may be an active region through which current flows. The first region 21 may also be the region inside the guard ring 41, which will be described later.

[0013] The semiconductor substrate 101 may comprise a first semiconductor layer 32 of a first conductivity type (e.g., n-type) located on the first layer 11, and a second semiconductor region 33 of a second conductivity type (e.g., p-type) located in a part of the first layer 11. The second semiconductor region 33 may be located above the first layer 11, and the first semiconductor layer 32 may be located below the second semiconductor region 33. The semiconductor substrate 101 may comprise a plurality of second semiconductor regions 33. The first semiconductor layer 32 may be an epitaxial layer. The second semiconductor region 33 may be an epitaxial layer in which impurities are implanted in a predetermined pattern and then annealed.

[0014] The semiconductor substrate 101 may further include a base drift layer 34 located below the first layer 11, a buffer layer 35 located below the base drift layer 34, and a high resistance drift layer 36. The base drift layer 34 and the buffer layer 35 may each be an epitaxial layer. The high resistance drift layer 36 may be an n-type SiC substrate.

[0015] The semiconductor substrate 101 may include one or more semiconductor materials selected from the group consisting of silicon, silicon carbide, silicon germanium, silicon nitride, silicon dioxide, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide and germanium, and may also be constituted of said semiconductor material(s).

[0016] The semiconductor device 1 may further include an anode electrode 31 located on the first region 21 of the semiconductor substrate 101, and a cathode electrode 37 located below the semiconductor substrate 101. The anode electrode 31 may have a two-layer structure of a lower first metal layer 31a and an upper second metal layer 31b. The anode electrode 31 may be joined to the first semiconductor layer 32 and the second semiconductor region 33 over the entire area within the first region 21. The cathode electrode 37 may be joined to the entire area of the semiconductor substrate 101 in plan perspective view. A junction region between the anode electrode 31 and the first semiconductor layer 32 corresponds to a Schottky junction region, and a junction region between the first semiconductor layer 32 and the second semiconductor region 33 corresponds to a pn junction region.

[0017] A guard ring 41 surrounding the first region 21 may be located in the first layer 11 of the semiconductor substrate 101. The guard ring 41 is a region having a lower resistance than the first semiconductor layer 32 and may be a region of the second conductivity type (e.g., p-type), similar to the second semiconductor region 33. The depth D2 of the guard ring 41 may be the same as the depth D1 of the second semiconductor region 33, or it may be deeper or shallower than the depth D1 of the second semiconductor region 33. The guard ring 41 may be annular in planar perspective. The width W2 of the guard ring 41 from the inner edge to the outer edge may be greater than the width W1 of the second semiconductor region 33 (width in the direction perpendicular to the longitudinal direction).

[0018] The semiconductor device 1 may further include a field insulating film 42 located on the semiconductor substrate 101 and a surface protective film 43 located on the field insulating film 42.

[0019] The field insulating film 42 is insulating and may be made of SiO2 (silicon oxide). The field insulating film 42 may be annular and extend along the outer edge of the guard ring 41. In a planar view, the inner edge of the field insulating film 42 may be located outward from the inner edge of the guard ring 41, and the outer edge of the field insulating film 42 may be located outward from the outer edge of the guard ring 41. In a planar view, the outer edge of the guard ring 41 may overlap the field insulating film 42 over its entire circumferential region.

[0020] The anode electrode 31 may overlap with a portion of the guard ring 41 and a portion of the field insulating film 42 over its entire circumferential region.

[0021] The surface protective film 43 is insulating and may be made of SiN (silicon nitride). The surface protective film 43 is annular and may be located above the outer periphery of the field insulating film 42 and the outer periphery of the anode electrode 31 throughout its entire circumferential region.

[0022] <Planar shape of the second semiconductor region 33 and guard ring 41> Figure 3 is an enlarged view showing the area around the first corner 21c of the first region 21. In Figure 3, the width of the second semiconductor region 33 and the width of the guard ring 41 are distorted. In the following description of the shape, unless otherwise specified, the shape is shown in planar perspective.

[0023] The edge of the first region 21 includes a rounded first corner 21c and two adjacent sides, the first side 21a and the second side 21b, on either side of the first corner 21c (see Figure 1(B)).

[0024] The guard ring 41 may have a strip-shaped first guard ring edge portion 41a, a strip-shaped second guard ring edge portion 41b, and a strip-shaped first guard ring corner portion 41c, corresponding to the first edge 21a, second edge 21b, and first corner portion 21c of the first region 21 (see Figure 1(A)). The first guard ring corner portion 41c may be curved in accordance with the curvature of the first corner portion 21c.

[0025] The multiple second semiconductor regions 33 may have multiple linear portions 33a (33a-1, 33a-2, 33a-3) having a linear shape. The multiple linear portions 33a may be separated from each other, or they may be connected (joined) at their ends or in the middle. In Figure 3, each linear portion 33a that is connected in a single line may have breaks in places and be divided into multiple parts.

[0026] As shown in Figure 3, at least one linear portion 33a (33a-2) comprises a first straight section 331 extending along the first side 21a and a curved section 332 that curves at the first corner 21c. In Figure 3, each section is shown enclosed by a dashed line for only one representative linear portion 33a (33a-2). With this configuration, the degree of symmetry around the tip 336 of the linear portion 33a can be increased compared to a configuration without the curved section 332, and the pressure resistance can be improved. That is, if there is no curved section 332 and the first straight section 331 is extended to the first guard ring corner 41c, the angle between the first straight section 331 and the first guard ring corner 41c will be asymmetrical. In other words, the angle will be acute on one side and obtuse on the other, spanning the first straight section 331. In this configuration, when a reverse bias is applied to the semiconductor device 1, the expansion of the depletion layer that occurs in the sharp-angled portion is reduced. Therefore, the breakdown voltage decreases. On the other hand, in Embodiment 1, the presence of the curved section 332 reduces the asymmetric structure described above. Therefore, the reduction in breakdown voltage described above can be reduced.

[0027] Specifically, as shown in Figure 3, the multiple linear portions 33a may include a first linear portion 33a-1 extending along the first side 21a to the second side 21b, and a second linear portion 33a-2 located between the first linear portion 33a-1 and the first side 21a. The second linear portion 33a-2 may have a first straight section 331 extending along the first side 21a and a curved section 332 curved along the first corner 21c. The tip portion 336 of the second linear portion 33a-2 on the curved section 332 side may be joined to the first linear portion 33a-1. This configuration further reduces the asymmetrical structure around the tip portion 336 and further reduces the decrease in pressure resistance.

[0028] The angle θ (Figure 3) at which the first linear portion 33a-1 and the second linear portion 33a-2 connect may be 85° ≤ θ ≤ 95°. Furthermore, the angle θ may be 90°. Here, the angle at which the two linear portions 33a connect may mean the angle between the centerlines in the longitudinal direction of each linear portion 33a at the connection point. With this configuration, the area around the tip portion 336 of the second linear portion 33a-2 becomes symmetrical, and the reduction in pressure resistance caused by the asymmetric structure can be further reduced. Note that the angle θ being X° (where X is an arbitrary value) includes not only the exact X° but also X° + error (the error is within the tolerance).

[0029] The tip portion 337 of the first linear portion 33a-1 may be joined to the side portion 41b of the second guard ring. With this configuration, the periphery of the tip portions 336 and 337 of both the first linear portion 33a-1 and the second linear portion 33a-2 can be made symmetrical, and the reduction in pressure resistance caused by the asymmetric structure can be further reduced.

[0030] More specifically, the first region 21 may include a first range 211 that overlaps with the first guard ring corner 41c when viewed from a direction along the first guard ring edge 41a, as shown in Figure 1(B), and a second range 212 that overlaps with the second guard ring edge 41b. In addition, the plurality of linear portions 33a may include a plurality of second linear portions 33a-2 located in the first range 211, a plurality of third linear portions 33a-3 located in the second range 212, and a first linear portion 33a-1 located between the plurality of second linear portions 33a-2 and the plurality of third linear portions 33a-3, as shown in Figure 1(A). The plurality of third linear portions 33a-3, the first linear portion 33a-1, and the plurality of second linear portions 33a-2 may be spaced apart from each other. Furthermore, the curvature of the multiple curved sections 332 (Figure 3) included in each of the multiple second linear sections 33a-2 may be smaller the closer they are to the first guard ring corner 41c. The centers of curvature of the multiple curved sections 332 may be the same point. With this configuration, the areas around the tip portions 336, 337, and 338 of many of the linear sections 33a included in the first region 21 can be made symmetrical, and the pressure resistance reduction caused by the asymmetric structure can be further reduced. In other words, the pressure resistance can be improved.

[0031] As shown in Figures 1 and 2, the first region 21 has two or more (e.g., four) corners and three or more (e.g., four) sides, and all corners may be rounded. The guard ring 41 may have a plurality of guard ring corners and a plurality of guard ring sides corresponding to all corners and all sides of the first region 21, respectively. Furthermore, all guard ring corners may be curved. The shape of the second semiconductor region 33 around the first corner 21c and the first guard ring corner 41c described above may also be present in the second semiconductor region 33 around all corners of the first region 21 and around all guard ring corners of the guard ring 41. With this configuration, the symmetry of the tips of the plurality of linear portions 33a (second semiconductor region 33) is improved throughout the first region 21, and the breakdown voltage of the semiconductor device 1 can be improved.

[0032] <Characteristics> Figure 4 is a graph showing the characteristics of the semiconductor devices of Embodiment 1 and the Comparative Example. In this graph, the horizontal axis represents the reverse voltage and the vertical axis represents the reverse current. The semiconductor device of the Comparative Example is a Schottky barrier diode with a planar structure that does not have a second semiconductor region 33, and is configured the same as the semiconductor device 1 of Embodiment 1, except that it does not have a second semiconductor region 33.

[0033] As shown in the graph of the comparative example, the semiconductor device of the comparative example generates a reverse current (leakage current) when a reverse voltage is applied. A large reverse current is generated when the reverse voltage reaches the breakdown voltage Vmax. On the other hand, in the semiconductor device 1 of Embodiment 1, the leakage current below the breakdown voltage Vmax is less than that of the comparative example. This characteristic is due to the effect of the depletion layer that spreads in the junction region (pn junction region) between the first semiconductor layer 32 and the second semiconductor region 33 when reverse biased.

[0034] Although not shown in Figure 4, the semiconductor device 1 of Embodiment 1 further has a pn junction region between the first semiconductor layer 32 and the second semiconductor region 33, which reduces forward resistance and improves surge resistance.

[0035] Here, as another comparative example not shown in Figure 4, let us consider a JBS in which the second semiconductor region 33 is striped throughout. Generally, the breakdown voltage Vmax of a JBS structure with a pn junction region is lower than that of a Schottky barrier diode with a planar structure. Therefore, the breakdown voltage of the JBS in the other comparative example is lower than the breakdown voltage Vmax of the comparative example. On the other hand, the breakdown voltage Vmax of the semiconductor device 1 of Embodiment 1 is equivalent to that of the Schottky barrier diode with a planar structure of the comparative example, as shown in Figure 4. In other words, the semiconductor device 1 of Embodiment 1 has a JBS structure that includes both a Schottky junction region and a pn junction region, but its breakdown voltage Vmax is not reduced. Therefore, the characteristic graph in Figure 4 shows that the breakdown voltage of the semiconductor device 1 of Embodiment 1 is improved.

[0036] Based on the above, the semiconductor device 1 of Embodiment 1 achieves reduced leakage current, improved surge resistance, and improved voltage resistance.

[0037] (Embodiment 2) Figure 5 is a plan view showing a semiconductor device according to Embodiment 2 of the present disclosure. In Figure 5, the guard ring 41 is shown by shading. Figure 5 shows the configuration excluding elements above the semiconductor substrate 101 (anode electrode 31, field insulating film 42, and surface protective film 43).

[0038] In the semiconductor device 1A of Embodiment 2, the second linear portion 33a-2 may have a first straight section 331 extending along the first side 21a, a curved section 332 curved along the first corner 21c, and a second straight section 333 extending along the second side 21b. The curved section 332 may be located between the first straight section 331 and the second straight section 333.

[0039] The second linear portion 33a-2 is annular and may have multiple (e.g., four) curved sections 332 and multiple (e.g., four) straight sections (331, 331, 333, 333). In Figure 5, each section of a representative second linear portion 33a-2 is shown enclosed by a dashed line.

[0040] As shown in Figure 5, the second straight section 333 of a plurality of second linear sections 33a-2 may intersect with the first linear section 33a-1. The second straight section 333 of a plurality of second linear sections 33a-2 may intersect with a plurality of third linear sections 33a-3. At each intersection, the two linear sections 33a may intersect at a 90-degree angle. Alternatively, although not shown, the first linear section 33a-1 and the third linear section 33a-3 may not intersect with the second linear section 33a-2 and may be located within the region surrounded by the innermost second linear section 33a-2.

[0041] In the semiconductor device 1A of Embodiment 2, the degree of symmetry at the tip or intersection of each linear portion 33a (33a-1, 33a-2, 33a-3) is improved, thereby achieving improved withstand voltage.

[0042] (electronic equipment) The electronic devices according to the embodiments of this disclosure include the semiconductor devices 1 and 1A of Embodiment 1 or Embodiment 2 described above. Specifically, the electronic devices may be configured such that the semiconductor devices 1 and 1A are housed in a package. The anode electrode 31 and cathode electrode 37 of the semiconductor devices 1 and 1A may be electrically connected to a plurality of electrodes exposed on the outside of the package. Alternatively, the electronic devices according to the embodiments of this disclosure may have a substrate (such as a printed circuit board), on which the semiconductor devices 1 and 1A are mounted. Other electrical elements, electronic elements, etc., may be mounted on the substrate. According to the electronic devices of this embodiment, the reliability of the electronic devices can be further improved due to the characteristics of the semiconductor devices 1 and 1A described above.

[0043] The embodiments of this disclosure have been described above. However, the semiconductor devices of this disclosure are not limited to the embodiments described above. For example, embodiments 1 and 2 above show examples in which the curved section 332 of the second linear portion 33a-2 is curved along the curvature of the first corner portion 21c or the first guard ring corner portion 41c. However, the curved section 332 may be curved in the opposite direction to the curvature of the first corner portion 21c or the curvature direction of the first guard ring corner portion 41c, and the tip of the second linear portion 33a-2 may be joined to the first guard ring corner portion 41c. In such a configuration, the second linear portion 33a-2 and the first guard ring corner portion 41c can be connected at an angle with a high degree of symmetry (for example, 90 degrees). Therefore, the voltage withstand capability of the semiconductor device can be improved. Other details shown in the embodiments can be modified as appropriate without departing from the spirit of the invention.

[0044] The following describes one embodiment of this disclosure. In one embodiment, (1) Semiconductor devices are A semiconductor substrate including a first layer and having a first region in planar perspective, an anode electrode located on the first region of the semiconductor substrate, A first semiconductor layer of a first conductivity type located in the aforementioned first layer, A second semiconductor region of the second conductivity type located above the first layer, Equipped with, The second semiconductor region is located within a part of the first region in a planar perspective view. The anode electrode is bonded to the second semiconductor region and the first semiconductor layer. The preceding second semiconductor region is, In planar perspective, it has a linear shape and includes a curved section at the corner of the first region.

[0045] (2) The semiconductor device described in (1) above is The system comprises multiple preceding second semiconductor regions, The edge of the first region includes a first corner and a first and second side adjacent to the first corner, Each of the plurality of second semiconductor regions includes a first linear portion extending along the first edge to the second edge in a planar perspective view, and a second linear portion located between the first linear portion and the first edge. The second linear portion has a straight section extending along the first side and a curved section curving along the first corner, with the end on the curved section side joined to the first linear portion.

[0046] (3) The semiconductor device described in (2) above is The angle θ at which the first linear portion and the second linear portion connect in planar perspective is 85° ≤ θ ≤ 95°.

[0047] (4) The semiconductor device described in (2) or (3) above is The first layer is further provided with a guard ring located above it and surrounding the first region in planar perspective, The guard ring includes a first guard ring edge, a first guard ring corner, and a second guard ring edge, which are aligned along the first edge, first corner, and second edge of the first region, respectively. In planar perspective, the corner of the first guard ring is curved. The first linear portion extends along the first guard ring edge and is joined to the second guard ring edge. The second linear portion extends along the edge portion and the corner portion of the first guard ring and is joined to the first linear portion.

[0048] (5) The semiconductor device described in (4) above is The plurality of second semiconductor regions include the first linear portion, the plurality of second linear portions, and the plurality of third linear portions extending along the first linear portion. The first region includes a first area that overlaps with the first guard ring corner when viewed from a direction along the first guard ring edge, and a second area that overlaps with the second guard ring edge. In planar perspective, the plurality of third linear portions are located in the second range with intervals between them, the second linear portions are located in the first range with intervals between them, and the first linear portion is located between the plurality of third linear portions and the plurality of second linear portions. The curvature of the multiple curved sections, each included in the multiple second linear sections, decreases as they are located closer to the first guard ring corner.

[0049] (6) Any semiconductor device described in (1) to (5) above is The semiconductor substrate comprises one or more semiconductor materials selected from the group consisting of silicon, silicon carbide, silicon germanium, silicon nitride, silicon dioxide, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, and germanium.

[0050] In one embodiment, (7) Electronic devices The semiconductor device has the above-mentioned (1) to (6). [Explanation of symbols]

[0051] 1, 1A Semiconductor Equipment 11 1st layer 21 First area 31 Anode electrode 32 First Semiconductor Layer 33. Semiconductor Area 2 33a Linear part 33a-1 1st linear part 33a-2 Second linear part 33a-3 Third linear part 331 First Straight Section 332 Curved section 333 Second Straight Section 336~338 Tip 34 Base drift layer 35 Buffer Layer 36 High-resistance drift layer 37 Cathode electrode 41 Guard Ring 41a First guard ring edge 41b Second guard ring edge 41c First guard ring corner 42 Field Insulating Film 43 Surface protective film 101 Semiconductor substrate 211 First Range 212 Second Range

Claims

1. A semiconductor substrate including a first layer and having a first region in planar perspective, an anode electrode located on the first region of the semiconductor substrate, A first semiconductor layer of a first conductivity type located in the first layer, A second semiconductor region of a second conductivity type located above the first layer, Equipped with, The second semiconductor region is located in a part of the first region in a planar perspective view. The anode electrode is bonded to the second semiconductor region and the first semiconductor layer. The aforementioned second semiconductor region is Having a linear shape in planar perspective, and including a curved section at the corner of the first region, The system comprises multiple of the aforementioned second semiconductor regions, The edge of the first region includes a first corner and a first and second side adjacent to the first corner, The plurality of second semiconductor regions include a first linear portion extending along the first edge to the second edge in a planar perspective view, and a plurality of second linear portions located between the first linear portion and the first edge. Each of the plurality of second linear portions has a straight section extending along the first side and a curved section curving along the first corner, the curved section having an end, and the end being joined to the first linear portion. Semiconductor equipment.

2. The angle θ at which the first linear portion and the second linear portion connect in planar perspective is 85° ≤ θ ≤ 95°. The semiconductor device according to claim 1.

3. The first layer is further provided with a guard ring located on the upper part of the first layer and surrounding the first region in planar perspective, The guard ring includes a first guard ring edge, a first guard ring corner, and a second guard ring edge, which are aligned along the first edge, first corner, and second edge of the first region, respectively. In planar perspective, the corner of the first guard ring is curved. The first linear portion extends along the first guard ring edge and is joined to the second guard ring edge. The second linear portion extends along the edge portion and the corner portion of the first guard ring and is joined to the first linear portion. The semiconductor device according to claim 1.

4. The plurality of second semiconductor regions include the first linear portion, the plurality of second linear portions, and the plurality of third linear portions extending along the first linear portion. The first region includes a first area that overlaps with the first guard ring corner when viewed from a direction along the first guard ring edge, and a second area that overlaps with the second guard ring edge. In planar perspective, the plurality of third linear portions are located in the second range with intervals between them, the second linear portions are located in the first range with intervals between them, and the first linear portion is located between the plurality of third linear portions and the plurality of second linear portions. The curvature of the multiple curved sections included in each of the multiple second linear sections decreases as they are located closer to the first guard ring corner. The semiconductor device according to claim 3.

5. The semiconductor device according to claim 1, wherein the semiconductor substrate comprises one or more semiconductor materials selected from the group consisting of silicon, silicon carbide, silicon germanium, silicon nitride, silicon dioxide, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, and germanium.

6. An electronic device having a semiconductor device according to any one of claims 1 to 5.

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