Apparatus and method for controlling a microcontroller port

Abstract

To provide a multi-system integrating microcontroller having a function of shutting down ports in emergency by determination of unsafe conditions, and operation of microcontroller ports.SOLUTION: A microcontroller unit includes at least one core, a plurality of safety fault management units, system control units operating in parallel, and port circuitries coupled to ports and to the system control units. Each of the plurality of safety fault management units detects one or more safety faults and outputs an alarm signal. Each of the plurality of system control units can be coupled to at least one of the safety fault management units and can include hardware circuitry to generate and output a port emergency stop (PES) signal based on the alarm signals obtained from a safety fault management unit. The port circuitries can selectively cause a respectively connected port to enter a non-operational electronic state in response to receiving a PES signal.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] Various embodiments generally relate to the operation of microcontrollers and microcontroller ports. [Background Art]

[0002] Currently, aggregated multiple systems are used in a single arithmetic unit or microcontroller unit such as an electronic control unit (ECU) to reduce costs and improve system efficiency. A microcontroller or ECU may have a function of shutting down its ports in an emergency. Emergency port shutdown is also known as port emergency stop (PES), and can be implemented in response to the determination of an unsafe situation. When PES is implemented, all ports are shut down.

[0003] In the drawings, like reference characters generally refer to the same parts throughout different views. The drawings are not necessarily to scale, instead, they generally focus on illustrating the basic principles of the present invention. In the following description, various embodiments of the present invention are described with reference to the following drawings. [Brief Description of the Drawings]

[0004] [Figure 1] It is a diagram illustrating an exemplary microcontroller unit according to at least one exemplary embodiment of the present disclosure. [Figure 2A] It is a diagram of exemplary components of a microcontroller according to at least one exemplary embodiment of the present disclosure. [Figure 2B] It is a diagram of exemplary components of a microcontroller according to at least one exemplary embodiment of the present disclosure. [Figure 2C] It is a diagram of exemplary components of a microcontroller according to at least one exemplary embodiment of the present disclosure. [Figure 3] It is a diagram of exemplary components of a microcontroller according to at least one exemplary embodiment of the present disclosure. [Figure 4] This is a diagram of an exemplary component of a microcontroller according to at least one exemplary embodiment of the present disclosure. [Figure 5] This is a diagram of an exemplary component of a microcontroller according to at least one exemplary embodiment of the present disclosure. [Figure 6] This figure shows a method according to at least one exemplary embodiment of the present disclosure. [Figure 7] This is a diagram of a system according to at least one exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0005] The following detailed description refers to the accompanying drawings, which illustrate specific details and embodiments that may be used to implement the present invention.

[0006] The term “exemplary” is used herein to mean “an example, case, or illustration.” Any embodiment or design described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other embodiments or designs.

[0007] In this description or claims, the terms “plurality” and “multiple” explicitly refer to a number greater than one. In this description or claims, terms such as “group,” “set,” “collection,” “sequence,” “series,” and “set” refer to a number equal to or greater than one, i.e., one or more. Similarly, plural terms that are not explicitly stated as “plural” or “multiple” also refer to a number equal to or greater than one. The terms “appropriate subset,” “reduced subset,” and “fewer subsets” refer to a subset of a set that is not equal to a set, i.e., a subset of a set that contains fewer elements than the set.

[0008] The terms "at least one" and "one or more" can be understood to include quantities greater than or equal to one (e.g., 1, 2, 3, 4, […] etc.).

[0009] Where used herein, unless otherwise specified, the use of adjectives such as “first,” “second,” “third,” etc., as ordinal numbers to describe common objects simply indicates that they refer to different instances of similar objects, and is not intended to imply that the objects described in this manner must be in a given order, temporally, spatially, sequentially, or otherwise.

[0010] As used herein, the term “data” can be understood to include any suitable analog or digital information provided, for example, as a file, a portion of a file, a set of files, a signal or stream, a portion of a signal or stream, or a set of signals or streams. Furthermore, the term “data” may also be used to mean a reference to information, for example, in the form of a pointer. However, the term “data” can take various forms and represent any information as understood in the art, and is not limited to the examples given herein.

[0011] For example, as used herein, the terms “processor” or “controller” can be understood as any type of entity capable of processing data, signals, etc. Data, signals, etc. can be processed according to one or more specific functions performed by the processor or controller.

[0012] Therefore, a processor or controller may be an analog circuit, a digital circuit, a mixed-signal circuit, a logic circuit, a processor, a microprocessor, a central processing unit (CPU), a neuromorphic computer unit (NCU), a graphics processing unit (GPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), an integrated circuit, an application-specific integrated circuit (ASIC), or any combination thereof, and may include these. Any other type of implementation of each of the functions described in more detail below may also be understood as a processor, controller, or logic circuit. Any two (or more) of the processors, controllers, or logic circuits detailed herein may be implemented as a single entity having equivalent functions, etc., and conversely, any single processor, controller, or logic circuit detailed herein may be implemented as two (or more) separate entities having equivalent functions, etc.

[0013] As used herein, “circuit” is understood to mean any kind of logic implementation entity, which may include special-purpose hardware or a processor that runs software. Thus, a circuit may be an analog circuit, a digital circuit, a mixed-signal circuit, a logic circuit, a processor, a microprocessor, a signal processor, a central processing unit ("CPU"), a graphics processing unit ("GPU"), a neuromorphic computer unit (NCU), a digital signal processor ("DSP"), a field-programmable gate array ("FPGA"), an integrated circuit, an application-specific integrated circuit ("ASIC"), or any combination thereof. Any other kind of implementation of each function, as described in more detail below, may also be understood as a “circuit.” It is understood that any two (or more) of the circuits detailed herein may be implemented as a single circuit having substantially equivalent functionality. Conversely, any single circuit detailed herein may be implemented as two (or more) separate circuits having substantially equivalent functionality. In addition, references to “circuit” may refer to two or more circuits that collectively form a single circuit.

[0014] As used herein, terms such as “module,” “component,” “system,” “circuit,” “element,” “interface,” “slice,” and “circuit device” are intended to refer to one or more electronic components, computer-related entities, hardware, software (e.g., running) and / or firmware sets. For example, a circuit or similar term may be a computer having a processor, processes running on a processor, controllers, objects, executable programs, storage devices and / or processing units. For illustrative purposes, applications running on a server and servers may also be circuits. One or more circuits may reside within the same circuit, and circuits may be localized on one computer and / or distributed across two or more computers. A set of elements or other sets of circuits may be described herein, in which case the term “set” can be interpreted as “one or more.”

[0015] As used herein, “signal” can be transmitted or conducted by a signal chain that processes the signal to alter its characteristics, such as phase, amplitude, and frequency. A signal may still be referred to as the same signal even if such characteristics are adapted. Generally, signals can be considered the same signal as long as they continue to encode the same information.

[0016] As used herein, a signal “indicating” a value or other information may be a digital or analog signal that encodes or otherwise transmits a value or other information in a manner that can be decoded by a receiving component and / or trigger a response action. The signal may be stored or buffered in a computer-readable storage medium before being received by the receiving component. The receiving component may retrieve the signal from the storage medium. Furthermore, a “value” “indicating” any number, state or parameter may be physically embodied as a digital signal, an analog signal, or as a storage bit that encodes or otherwise transmits a value.

[0017] When it is mentioned that one element is “connected” or “coupled” to another, it will be understood that one element can be physically connected or coupled to another, thereby allowing current and / or electromagnetic radiation (e.g., signals) to flow along the conductive paths formed by these elements. When it is described that elements are coupled or connected to one another, there may be intervening conductive, inductive, or capacitive elements between the elements. Furthermore, when elements are coupled or connected to one another, one element may induce a flow of voltage or current or propagation of electromagnetic waves in the other element without physical contact or intervening components. Furthermore, when it is mentioned that a voltage, current, or signal is “applied” to an element, the voltage, current, or signal may be conducted to the element by physical connection or by capacitive, electromagnetic, or inductive coupling without physical connection.

[0018] As used herein, “memory” is understood as a non-temporary, computer-readable medium that can store data or information for retrieval. Therefore, references to “memory” as used herein can be understood as referring to volatile or non-volatile memory, including random-access memory (RAM), read-only memory (ROM), flash memory, solid-state memory, magnetic tape, hard disk drives, optical drives, or any combination thereof. Furthermore, registers, shift registers, processor registers, and data buffers are also included in the term “memory” as used herein. A single component referred to as “memory” or “a memory” may consist of two or more different types of memory, and thus may refer to a collective component comprising one or more types of memory. Any single memory component may be separated into a number of collectively equivalent memory components, and vice versa. Furthermore, memory may be shown separately from one or more other components (as in the drawings), but memory may also be integrated with other components, such as on a common integrated chip or on a controller with built-in memory.

[0019] The term "software" refers to any type of executable instructions including firmware.

[0020] Unless otherwise specified, discussions in the present specification using terms such as "processing", "operation", "computation", "determination", "presentation", and "display" may refer to an action or process of a machine (e.g., a computer / processor / other device) that manipulates or transforms data represented as physical (electronic, magnetic, or optical) quantities within one or more memories (e.g., volatile memory, non-volatile memory, or a combination thereof), registers, or other machine components that receive, store, transmit, or display information.

[0021] Exemplary embodiments of the present disclosure can be implemented by one or more computers (or computing devices) that read and execute computer-executable instructions recorded on a storage medium (e.g., a non-transitory computer-readable storage medium) to implement one or more functions among the embodiments described herein of the present disclosure. The computer may include one or more of a central processing unit (CPU), a micro processing unit (MPU), or other circuits, and may include a network of separate computers or separate computer processors. The computer-executable instructions can be provided to the computer from, for example, a network or a non-volatile computer-readable storage medium. The storage medium may include, for example, one or more of a hard disk, a random access memory (RAM), a read only memory (ROM), a storage in a distributed computing system, an optical drive (such as a compact disc (CD), a digital versatile disc (DVD), a Blu-ray disc (BD), etc.), a flash memory device, a memory card, and the like. Specific details and embodiments for practicing the present invention are described for illustrative purposes.

[0022] As used in this specification, unless otherwise specified, the use of adjectives "first", "second", "third" and the like as ordinal numbers to describe common objects merely indicates that different instances of similar objects are referred to, and is not intended to mean that the objects so described must be in a given order temporally, spatially, in rank or in any other manner.

[0023] The terms "semiconductor substrate" or "semiconductor die" are defined to mean any structure including semiconductor material, such as, for example, a silicon substrate with or without an epitaxial layer, a silicon-on-insulator substrate with a buried insulator layer, or a substrate with a silicon germanium layer. The term "integrated circuit" as used herein refers to an electronic circuit having a plurality of individual circuit elements such as transistors, diodes, resistors, capacitors, inductors, and other active and passive semiconductor elements. The conductive regions formed in and / or on the semiconductor substrate or semiconductor die are part of a conductive path and have an exposed surface that can be processed by a planarization process such as chemical mechanical polishing. Suitable materials for the conductive regions may include, but are not limited to, for example, copper, aluminum, copper alloys or other mobile conductive materials. The copper interconnect level may be the first or any subsequent metal interconnect level of a semiconductor device.

[0024] FIG. 1 includes a diagram illustrating a microcontroller or microcontroller unit (MCU) 10 in accordance with one or more exemplary embodiments of the present disclosure. The microcontroller 10 includes one or more cores 100, a plurality of safety defect management units 200, a plurality of system control units 300, and a plurality of port circuits 400. Although not shown in FIG. 1, connections between the components of the microcontroller 10 are contemplated.

[0025] One or more cores 100 can be cores of a processor or central processing unit (CPU) that can perform one or more operations by executing program instructions or software. Such instructions can be stored or placed in a (non-temporary) computer-readable storage medium located in the microcontroller 10.

[0026] Each safety defect management unit 200 may include a circuit capable of determining or detecting (safety) defects, events, or conditions in the microcontroller 10 and outputting an alarm signal based on that detection. For example, determination or detection by the safety defect management unit 200 can be performed by collecting or receiving defect or alarm signals from other connected electronic components of the microcontroller 10.

[0027] Each safety defect management unit 200 can be configured to output an alarm signal (AS) in response to detecting or determining the occurrence of one or more defects (or events, situations, etc.). In the microcontroller 10, each safety defect management unit 200 can output an alarm signal to one or more of the multiple system control units 300.

[0028] Figure 3 shows an example of the safety defect management unit 200, which will be described in more detail later.

[0029] The system control unit 300 may include hardware circuitry that generates and outputs a port emergency stop (PES) signal. As used herein, “hardware circuitry” may refer to electronic hardware components or non-software implementations.

[0030] The system control unit 300 can output a PES signal based on one or more alarm signals received or acquired by the system control unit 300 from at least one safety defect management unit 200. The system control unit 300 can operate in parallel with at least one core 100. The output PES signal can trigger the closure or deactivation of ports (e.g., input and / or output ports) coupled to the system control unit 300. Figure 4 shows an example of the system control unit 300, which will be described in more detail later.

[0031] Each system control unit 300 can be connected to its respective port via a port circuit 400. That is, the port circuit 400 can be a circuit configured to selectively put the connected ports into an electronically inactive state in response to the reception of a PES signal. Figure 5 shows an example of a port circuit 400, which will be described in more detail later.

[0032] Figure 2A shows an exemplary configuration of the microcontroller 10. In Figure 2A, the microcontroller 10 includes a one-to-one configuration relating to a safety defect management unit 200, a system control unit 300, a port circuit 400, and a port / pin 500.

[0033] The microcontroller 10 in Figure 2A includes multiple safety defect management units 200, individually labeled 200a to 200N, where N represents any number. Similarly, it includes multiple system control units labeled 300a to 300N.

[0034] As shown in the diagram, each of the multiple safety defect management units 200 is connected to one of the multiple system control units 300. For example, safety defect management unit 200a is connected to system control unit 300a, safety defect management unit 200b is connected to system control unit 300b, safety defect management unit 200c is connected to system control unit 300c, and so on. Each of the multiple system control units 300 is also connected to one of the multiple port circuits 400. For example, system control unit 300a is connected to port circuit 400a, system control unit 300b is connected to port circuit 400b, system control unit 300c is connected to port circuit 400c, and so on. Furthermore, one of the multiple port circuits 400 is connected to one of the pins 500. For example, port circuit 400a is connected to port 500a, port circuit 400b is connected to port 500b, port circuit 400c is connected to port 500c, and so on.

[0035] In the example shown in Figure 2A, each safety defect management unit 200 can transmit an activation signal or an alarm signal (AL signal) to a corresponding one of the system control units 300. As described above, the safety defect management unit 200 can be configured to transmit an alarm signal AL when it detects or discovers that one or more specific defects or events have occurred or are occurring in the microcontroller 10. Furthermore, as shown in the figure, the system control unit 300 can generate a port emergency stop (PES signal) based on the reception of an AL signal and output it to a corresponding one of the port circuits 400.

[0036] The PES signal output by the system control unit 300 can trigger the corresponding port circuit 400, which can then close or disable the corresponding port 500 connected to the port circuit 400. In other words, the PES signal triggers an "emergency stop function" performed by the port circuit 400, putting the corresponding connected port 500 into a non-operational state. This ensures that shutdown or port emergency stop takes precedence and can disable any other operations or actions currently running on port 500.

[0037] In other embodiments, a one-to-one configuration, particularly with respect to the safety defect management unit 200 and the system control unit 300, is not necessarily required. Furthermore, the number of safety defect management units 200 and system control units 300 does not need to be equal.

[0038] Figure 2B shows another exemplary embodiment or aspect of the microcontroller 10. Figure 2B shows different configurations of the safety defect management unit 200 and the system control unit 300. However, as in Figure 2A, each system control unit 300 (system control units 300a to 300M) may be connected to a corresponding port circuit 400, and each port circuit 400 may also be connected to a corresponding port 500.

[0039] As shown in Figure 2B, the number of safety defect management units 200 (N safety defect management units) and the number of system control units 300 (M safety control units) may be different. Thus, the system control unit 300 in Figure 2B is not necessarily coupled to only one corresponding safety defect management unit 200. That is, in some embodiments, the system control unit 300 may be connected to one or more safety defect management units 200 and may be configured to receive or acquire AL signals from one or more safety defect management units 200.

[0040] In the example shown in Figure 2B, the system control unit 300a can be configured to receive AL signals from safety defect management units 200a and 200b. Safety defect management unit 200b can output and provide alarm signal AL2 to system control units 300a, 300b, and 300c. Safety defect management units 200a and 200c can output and provide their respective alarm signals AL1 and AL3 to system control units 300a and 300c, respectively. Of course, other combinations are also possible. That is, one or more system control units 300 can receive other combinations of alarm signals from one or more safety defect management units 200 (e.g., one, two, or more alarm signals AL).

[0041] In other examples, one or more circuits may exist between the safety defect management unit 200 and the system control unit 300. For example, Figure 2C shows another exemplary embodiment of the microcontroller 10. Specifically, the configuration of the safety defect management unit 200 and the system control unit 300 is shown. Each of the system control units 300 (system control units 300a to 300M) can be connected to a corresponding port circuit 400, and each of the port circuits 400 is also connected to a corresponding port 500.

[0042] Furthermore, in Figure 2C, the system control unit 300 can acquire an alarm signal AL from one or more safety control units via an intermediate circuit. The intermediate circuit can be, for example, a control logic circuit.

[0043] For example, the intermediate circuit IM1 can function as a logical "OR" or similarly, and when it receives an alarm signal from either the safety defect management unit 200a or the safety defect management unit 200b, it can provide or transfer the received AL signal to the system control unit 300a. That is, if the intermediate circuit IM1 receives one or both of the alarm signals AL1 and AL2 from the safety defect management unit 200a, it provides or transfers the alarm signal to the system control unit 300a.

[0044] In Figure 2C, the intermediate circuit IM2 can also operate as a logic "AND" and thus can transfer the alarm signal to the system control unit 300c only when it receives alarm signals AL2 and AL3 from the safety defect management unit 200b and the safety defect management unit 200c, respectively, for example, simultaneously.

[0045] The configurations shown in Figures 2A to 2C are merely illustrative, and other combinations or substitutions can be realized. That is, there may be several configurations using any suitable combination of one-to-one configurations, several numerous inputs to one or more of the implementation forms of the system control unit 300 (e.g., one or more numerous alarm signals), and several intermediate circuit implementation forms.

[0046] Figure 3 shows an exemplary safety defect management unit 200 according to at least one embodiment of the present disclosure. The safety defect management unit 200 can receive one or more inputs. In Figure 3, the safety defect management unit 200 can receive inputs (e.g., data or signals) on inputs or input lines 210a to 210N, where N represents any number.

[0047] The input 210 of the safety defect management unit 200 can be a signal from one or more electronic components of the microcontroller 10, for example, a safety or event signal. Multiple safety defect management units 200 can each have a different set of inputs or be able to receive a different set of input signals. That is, each safety defect management unit 200 can be configured to accept a different set of inputs (e.g., safety or event signals) in a different way.

[0048] In one example, one of several safety units 200 may receive one or more signals as input from one or more processor cores 100. Signals that may be provided to the safety unit 200 include a CPU reset signal, a signal indicating a voltage supply fault (e.g., an undervoltage or overvoltage), a signal indicating a clock fault (e.g., a watchdog signal), a signal indicating a data integrity error (e.g., an error correction code (ECC) signal, an error detection and correction (EDC) signal), and a signal indicating an input and / or output error (e.g., an unexpected frequency, pin mismatch, etc.).

[0049] Each safety defect management unit 200 can be configured to react to a signal received as input or to take one or more actions. The input terminals or input lines 210a to 210N may include switches so that when a signal is present at the input terminals 210a to 210N, the signal is forwarded to the control circuit 220.

[0050] The control circuit 220 can be configured to output an alarm signal AL based on its inputs. In one example, the control circuit can be a logical "OR" or can operate as a logical "OR". In this case, the presence or reception of a signal to any of the inputs to the safety defect management unit 200 can trigger the output of the alarm signal AL. The control circuit 220 can be implemented with other types of logic and may be implemented to include a logical "AND" type circuit, in which case the presence of two or more signals is required for the control logic circuit to output the alarm signal AL. In another example, the logic of the control logic circuit 220 can be more complex, including any suitable combination of logic circuit units such as AND, OR, etc. In general, the control circuit 220 may be implemented in other suitable forms.

[0051] Furthermore, the control circuit 220 may be configurable, for example, at least initially, and in some cases reconfigurable. For example, the microcontroller 10 includes interface circuitry that allows a user or another (e.g., external or internal) component to configure and / or reconfigure the control circuit 220. For example, the control circuit 220 may include configurable logic to cause the control circuit 220 to output an alarm signal based on one or more specified or set inputs.

[0052] Figure 4 shows a system control unit 300 according to at least one exemplary embodiment of the present disclosure. The system control unit 300 may be configured to output a PES signal based on the reception of a safety alarm signal AL. Input 310a may represent one of a plurality of input lines capable of receiving the alarm signal. Furthermore, in some embodiments, the system control unit 300 may also include additional inputs or input lines to receive inputs or input signals other than the alarm signal.

[0053] In the example shown in Figure 4, the system control unit 300 also includes input terminals 310 or input lines 310b to 310N. These input terminals 310 can be connected to one or more safety defect management units 200.

[0054] Furthermore, at least one input terminal or input line may be coupled to or connected to other components or electronic elements of the microcontroller 10, other than, for example, the safety defect management unit 200. In one example, one input terminal 310 may be connected to something connected to an input port of the microcontroller 10, or it may be connected to an input terminal or input port of the microcontroller 10. In another example, one or more of the input terminals 310b to 310N may be connected to one or more of the cores 100.

[0055] The system control unit 300 may include circuits, such as hardware circuits 320. The hardware circuits 320 can be configured to generate and output a Port Emergency Stop (PES) signal, for example, based on or in response to a specific input or input signal received by the system control unit 300. In particular, the hardware circuits 320 can be configured to output a PES signal based on a specific situation present in the microcontroller 10 and reflected in the inputs provided to the system control unit 300.

[0056] In some cases, one or more AL signals received by the system control unit 300 may not be sufficient to cause the hardware circuit 320 to generate and output a PES signal. The hardware circuit may require other conditions reflected in the input or signal fed to the system control unit 300 to generate and output a PES signal.

[0057] The system control unit 300 can be configurable. For example, configuration bits (e.g., set in a register or other suitable medium) can be configured or set (e.g., by an interface circuit) to control and identify a specific AL signal that can trigger the PES signal output by the system control unit 300.

[0058] The system control unit 300 may include a scanning circuit that can be always or continuously active. The scanning circuit of the system control unit 300 may be configured to scan all AL signals configured to trigger the PES signal output by the system control unit 300. When an AL signal indicating an error is generated, the scanning circuit is configured to identify the AL signal and further store the state of the event as a status bit, for example, in a register of the system control unit 300 or in another medium.

[0059] Furthermore, upon detecting or discovering the presence of an AL signal that triggers the output of a PES signal, the scanning circuit activates the PES generation circuit of the system control unit 300 to generate a PES signal output by the system control unit 300. In one example, simple logic can be implemented or realized within the PES generation circuit. For example, the state of the PES generation circuit can be settable or changed based on inputs (from "0" indicating a defect-free state (e.g., no PES signal to generate) to "1" indicating a defect state). The state may change based on or in response to inputs from the scanning circuit or another appropriate entity.

[0060] Furthermore, in some other exemplary embodiments of the present disclosure, the safety defect units described herein may have other types of reaction generating circuits. For example, a trigger interrupt (or non-maskable interrupt) for generating a PES signal may be implemented to notify software running or executing on the CPU that there is a defect in the microcontroller and the safety defect unit has triggered a PES.

[0061] Figure 5 shows a port circuit 400 according to at least one exemplary embodiment of the present disclosure. The port circuit 400 includes a data selector 415, which may be coupled to a data line 410, for example, a multiplexer, and the data selector may be further coupled to an input circuit or buffer 460, which may be connected to a port 500.

[0062] The port circuit 400 may include a plurality of registers 420. The registers 420 can be configured to control specific aspects of the port circuit 400. At least one of the registers 420 may be an input register (input) that can be configured to receive and store data input via port 500 by at least the input control circuit 470.

[0063] As illustrated, the port circuit 400 can receive PES signals from, for example, each system control unit 300. The PES signals received by the port circuit 400 can trigger the "shutting down" of port 500. The PES signal line may be directly coupled to the control unit circuit 440, or it may be coupled to the control unit circuit 440 via an enable circuit 430, as in the example of Figure 5. In Figure 5, the control unit circuit 440 can be triggered so that the PES signal disables port 500 only when the PES function of the port circuit 400 is enabled. The PES function can be enabled using an "enable" register having a value of high or "1". This data value can be provided by the register so that it is "ANDED" (a logical conjunction is formed) with the PES data line using the enable circuit 430. That is, when the enable is correctly set to, for example, 1 or another appropriate value, and the PES signal is present on the PES signal line, the enable circuit 430 can send a signal to activate the control unit circuit 440 according to the embodiments herein.

[0064] The control circuit 440 can be configured to control specific modes of operation of the port circuit 400. In the example in Figure 5, the control circuit 440, when activated by the PES signal, can disable further functions of the port 500, such as functioning as an input or output port. More specifically, the control circuit 440 can put the port 500 into a predefined electronic non-operational state in response to the trigger. In doing so, the control circuit 440 can immediately disable the current or future operation or function of the port 500.

[0065] In one example, the port circuit 400 includes a pull device circuit 450. The pull device circuit 450 can be a switchable pull-down or pull-up resistor, or a tristate logic device. Depending on whether it is activated or triggered by the control device circuit 440, the pull device circuit 450 can cause the port 500 to enter an electronically non-functional state, such as a low state (e.g., ground state), or pull it up to a voltage or high state. That is, when activated, the pull device circuit 450 can ensure that the port 500 is no longer functional or operational.

[0066] Furthermore, in some examples, the PES signal can cause the control unit circuit 440 to shut off or disable other electronic components of the port circuit, such as the data selector 415, input buffer 470, output buffer 460, etc., or can thus trigger the control unit circuit 440.

[0067] In one embodiment, after being activated by a PES signal to perform an emergency shutdown of port 500, the control circuit 440 may keep port 500 in a non-functional or non-operational state as long as the PES signal is present (and the PES function is enabled). In another example, the control circuit 440 may maintain port 500 in an emergency shutdown or non-functional state for a predetermined or pre-set period of time.

[0068] Figure 6 shows Method 600 according to at least one exemplary embodiment of the present disclosure. Method 600 can be implemented or carried out by an exemplary microcontroller described herein. For example, the method can be carried out by the microcontroller 10 of Figure 1, which may include at least one core, a plurality of safety defect units, a plurality of system control units, and a plurality of ports.

[0069] Method 600 includes detecting one or more safety defects by one or more of a plurality of safety defect units in 605. Next, in 610, Method 600 may include each of the plurality of safety defect units that have detected one or more safety defects outputting at least one alarm signal to one or more of the system control units. In 615, Method 600 includes each of the plurality of system control units that have received at least one alarm signal generating at least one port emergency stop (PES) signal and outputting it to one of the plurality of port circuits. Furthermore, in 620, Method 600 includes each of the plurality of port circuits that have received at least one PES signal putting one of the plurality of ports into an electronically inoperable state.

[0070] Figure 7 shows a system 700 which may include the microcontroller 10 of Figure 1. System 700 can be a high-voltage system, for example, a system implemented for a vehicle. System 700 can be an on-board charging (OBC) system. As shown, system 700 may include a system base chip (SBC) 710. In the example of Figure 7, the SBC 710 may include at least a controller area network 715 and a power supply 720.

[0071] Furthermore, the system 700 may include a microcontroller, which in this example may be the microcontroller 10 or another similar microcontroller as described according to embodiments of the present disclosure. The microcontroller 10 is coupled to and can communicate with the SBC 10 and the gate driver and isolation circuit 730. That is, the microcontroller 10 can interface with the components of the system 700 via the gate driver and isolation circuit. In this example, the system 700 includes a power factor correction (PFC) converter 740 and a DC-DC converter 750. The PFC 740 may take an AC signal as its input. Similarly, the DC-DC converter may take a DC input to generate another DC signal (high voltage) to be supplied to a high-voltage battery.

[0072] In some cases, the operation of the PFC740 and DC-DC converter 750 may be influenced by or directed by the microcontroller 10. In certain cases, there may be situations that require the blocking of one or more ports that interface with these components. For example, one or more ports to only one of the components, e.g., the PFC740 or the DC-DC converter 750, the microcontroller 10 may implement the PES function described herein so that only the necessary ports are blocked by the microcontroller's hardware. This allows other components to function freely or to freely interface with the microcontroller 10 without interruption.

[0073] The following examples relate to further aspects of this disclosure.

[0074] Example 1 is a microcontroller unit comprising: a plurality of safety defect management units, each having at least one core and a circuit configured to detect one or more safety defects and to output an alarm signal in response to the detection of one or more safety defects; a plurality of system control units operating in parallel with at least one core, each coupled to at least one of the plurality of safety defect management units, and each having hardware circuit configured to generate and output a port emergency stop (PES) signal based on one or more alarm signals obtained from at least one safety defect management unit; a plurality of ports; and a plurality of port circuits, each coupled to the plurality of ports and the plurality of system control units, each configured to selectively put the port connected to it into an electronically inoperable state in response to the reception of a PES signal.

[0075] Example 2 is the subject of Example 1, and the hardware circuitry of each of the multiple system control units can be further configured to acquire one or more additional input signals.

[0076] Example 3 is the subject of Example 2, wherein each hardware circuit of the system control unit may further include control logic circuits that selectively generate and output port emergency stop (PES) signals based on one or more additional input signals and their respective safety defect signals.

[0077] Example 4 is the subject of any of Examples 1 to 3, and each of the safety defect management units can be configured to independently detect one or more safety defects.

[0078] Example 5 is the subject of any of Examples 1 to 4, and each of the multiple safety defect management units can be configured to detect a unique combination of one or more safety defects.

[0079] Example 6 is the subject of any of Examples 1-5, and each of the system control units can operate independently of the others.

[0080] Example 7 is the subject of any of Examples 1-6, and each of the multiple ports connected to the system control unit can be an input and / or output port.

[0081] Example 8 is the subject of any of Examples 1-7, wherein each of the multiple port circuits can be configured to bring each port into an electronically non-operating state, and the ports are configured to connect to pull-down resistors, pull-up resistors, or tri-state logic devices.

[0082] Example 9 is a subject of any of Examples 1 to 8, each of which is a plurality of port circuits that can be configured to selectively put the ports connected to it into an electronically non-functional state, and each of these is further configured to keep the ports connected to it that have entered an electronically non-functional state in that electronically non-functional state as long as a PES signal is being received.

[0083] Example 10 is the subject of any of Examples 1 to 9, wherein each of a plurality of port circuits configured to selectively bring the ports connected to each of them into an electronically non-functional state is further configured to keep the ports connected to each of them that have entered an electronically non-functional state in that electronically non-functional state for at least a predetermined period of time.

[0084] Example 11 is the subject of any of Examples 1 to 10, wherein each of a plurality of port circuits configured to selectively put the respective connected ports into an electronically disabled state is further configured to release the respective connected ports that have entered the electronically disabled state from the electronically disabled state in response to the receipt of a release signal.

[0085] Example 1A is a method implemented by a microcontroller comprising at least one core, a plurality of safety defect management units, a plurality of system control units, and a plurality of ports, the method comprising: detecting one or more safety defects by one or more of the plurality of safety defect management units; each of the plurality of safety defect management units that has detected one or more safety defects outputting at least one alarm signal to one or more of the system control units; each of the plurality of system control units that has received at least one alarm signal generating at least one port emergency stop (PES) signal and outputting it to one of the plurality of port circuits; and each of the plurality of port circuits that has received at least one PES signal putting one of the plurality of ports into an electronically inoperable state.

[0086] Example 2A is the subject of Example 1A, in which each of the multiple system control units can operate in parallel with at least one core.

[0087] Example 3A is the subject of Example 1A or 2A, wherein each of the multiple system control units can be coupled to one or more of the multiple safety defect management units.

[0088] Example 4A is the subject of any of Examples 1A to 3A, and each of the multiple system control units may include hardware circuitry configured to generate and output a Port Emergency Stop (PES) signal.

[0089] Example 5A is the subject of Example 4A, in which the hardware circuitry of each of the multiple system control units can be further configured to acquire one or more additional input signals.

[0090] Example 6A is the subject of Example 5A, wherein the hardware circuit may further comprise a control logic circuit, and each of a plurality of system control units that have acquired at least one alarm signal may generate and output at least one PES signal, or the control logic circuit may generate and output a PES signal based on one or more additional input signals and at least one safety defect signal.

[0091] Example 7A is the subject of any of Examples 1A to 6A, and each of the safety defect management units can be configured to independently detect one or more safety defects.

[0092] Example 8A is the subject of any of Examples 1A to 7A, wherein each of the multiple safety defect management units can be configured to detect a unique combination of one or more safety defects.

[0093] Example 9A is the subject of any of Examples 1A to 8A, and the system control units can operate independently of each other.

[0094] Example 10A is the subject of any of Examples 1A to 9A, where multiple ports connected to the system control unit can each be input and / or output ports.

[0095] Example 11A is the subject of any of Examples 1A to 10A, where each port circuit can be coupled to one of a plurality of ports and one of a plurality of system control units.

[0096] Example 12A is the subject of Example 11A, in which each of the multiple port circuits can be configured to bring each port into an electronically non-operating state, and the ports can be configured to connect to pull-down resistors or pull-up resistors.

[0097] Example 13A is the subject of any of Examples 1A to 12A, and putting one of each of the multiple ports into an electronically non-operating state may further include keeping one of the multiple ports in an electronically non-operating state as long as at least one PES signal is being acquired by the respective port circuit.

[0098] Example 14A is the subject of any of Examples 1A to 13A, wherein putting one of each of a plurality of ports into an electronically non-operating state may further include keeping one of the plurality of ports in an electronically non-operating state for at least a predetermined period of time.

[0099] Example 15A is the subject of any of Examples 1A to 14A, wherein bringing one of the multiple ports into an electronically non-operating state may further include releasing one of the multiple ports from the electronically non-operating state in response to the reception of a release signal.

[0100] It should be noted that one or more features of any of the above examples can be suitably or appropriately combined with any of the other examples or embodiments disclosed herein.

[0101] Those skilled in the art will recognize that the foregoing description is provided for illustrative purposes only and can be modified without departing from the broader spirit or scope of the invention as defined in the claims. Accordingly, this specification and the drawings should be considered illustrative rather than restrictive.

[0102] Therefore, the scope of this disclosure is indicated by the attached claims and is thus intended to encompass the meaning of the claims and all modifications that fall within the equivalent scope.

[0103] It is understood that the implementations of the methods detailed herein are inherently empirical and therefore implementable in the corresponding apparatus. Similarly, it is understood that the implementations of the apparatus detailed herein are implementable as the corresponding method. Therefore, it is understood that the apparatus corresponding to the methods detailed herein may include one or more components configured to carry out each aspect of the relevant method.

[0104] All abbreviations defined in the above description apply additionally to all claims contained herein.

Claims

1. At least one core, Multiple safety defect management units, each configured to detect one or more safety defects and further configured to output an alarm signal in response to the detection of one or more safety defects, A plurality of system control units operating in parallel with the at least one core, each of which is coupled to at least one of the plurality of safety defect management units and has hardware circuitry configured to generate and output a port emergency stop (PES) signal based on one or more alarm signals obtained from the at least one safety defect management unit, Multiple ports, A plurality of port circuits coupled to the plurality of ports and the plurality of system control units, each configured to selectively put the port connected to it into an electronically inoperable state in response to the reception of a PES signal, A microcontroller unit equipped with the following features.

2. Each of the hardware circuits of the plurality of system control units is further configured to acquire one or more additional input signals. The microcontroller unit according to claim 1.

3. Each of the hardware circuits of the system control unit further comprises a control logic circuit that selectively generates and outputs a port emergency stop (PES) signal based on one or more additional input signals and one or more alarm signals. The microcontroller unit according to claim 2.

4. Each of the safety defect management units is configured to independently detect one or more safety defects. The microcontroller unit according to claim 1.

5. Each of the plurality of safety defect management units is configured to detect a unique combination of one or more safety defects. The microcontroller unit according to claim 1.

6. Each of the aforementioned system control units operates independently of the others. The microcontroller unit according to claim 1.

7. Each of the plurality of ports connected to the system control unit is an input and / or output port. The microcontroller unit according to claim 1.

8. Each of the aforementioned port circuits is configured to bring each of the aforementioned ports into an electronically non-operating state and is configured to connect the ports to a pull-down resistor, a pull-up resistor, or a tri-state logic device. The microcontroller unit according to claim 1.

9. Each of the plurality of port circuits, each configured to selectively put the connected ports into an electronically non-functional state, is further configured to keep the connected ports that have entered the electronically non-functional state in that state as long as a PES signal is received. The microcontroller unit according to claim 1.

10. Each of the plurality of port circuits, configured to selectively bring the respective connected ports into an electronically non-functional state, is further configured to keep the respective connected ports that have entered the electronically non-functional state in that electronically non-functional state for at least a predetermined period of time. The microcontroller unit according to claim 1.

11. Each of the plurality of port circuits, configured to selectively put the respective connected ports into an electronically disabled state, is further configured to release the respective connected ports that have entered the electronically disabled state from the electronically disabled state in response to the receipt of a release signal. The microcontroller unit according to claim 1.

12. A method implemented by a microcontroller comprising at least one core, a plurality of safety defect management units, a plurality of system control units, and a plurality of ports, wherein the method is The steps include detecting one or more safety defects using one or more of the aforementioned multiple safety defect management units, The steps include: each of the plurality of safety defect management units that has detected one or more safety defects outputs at least one alarm signal to one or more of the system control units; The steps include: each of the multiple system control units that has acquired the at least one alarm signal generates at least one port emergency stop (PES) signal and outputs it to one of the multiple port circuits; The steps include: each of the multiple port circuits that has acquired at least one PES signal causes each of the multiple ports to enter an electronically inoperable state; A method that includes this.

13. Each of the aforementioned plurality of system control units operates in parallel with the at least one core. The method according to claim 12.

14. Each of the aforementioned plurality of system control units is coupled to one or more of the aforementioned plurality of safety defect management units. The method according to claim 12.

15. Each of the aforementioned system control units includes hardware circuitry configured to generate and output a port emergency stop (PES) signal. The method according to claim 14.

16. Each of the hardware circuits of the plurality of system control units is further configured to acquire one or more additional input signals. The method according to claim 15.

17. The aforementioned hardware circuit further comprises a control logic circuit, The step of generating and outputting the at least one PES signal by each of the plurality of system control units that have acquired the at least one alarm signal includes the step of generating and outputting the PES signal by the control logic circuit based on the one or more additional input signals and the at least one alarm signal. The method according to claim 16.

18. Each of the safety defect management units is configured to independently detect one or more safety defects. The method according to claim 12.

19. Each of the plurality of safety defect management units is configured to detect a unique combination of one or more safety defects. The method according to claim 12.

20. The aforementioned system control units operate independently of each other. The method according to claim 12.

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