Diode, field-effect transistor incorporating a diode, and method for manufacturing a diode

Abstract

To provide a technique of suppressing energization degradation by reducing the amount of holes accumulated in an n-type semiconductor region in a diode including a semiconductor substrate formed of SiC.SOLUTION: In a diode including a semiconductor substrate formed of SiC, a semiconductor substrate includes a p-type first semiconductor region, a drift region in contact with the first semiconductor region from below, and an n-type second semiconductor region in contact with the drift region from below. The drift region has a structure in which a plurality of p-type column regions and a plurality of n-type column regions are alternately arranged in a lateral direction. In a part of the drift region in a depth direction, a particular region is provided distributing in the range from the p-type columns regions to the n-type column regions. In the particular region, the effective p-type impurity concentration of the p-type column region is lower than that in the periphery thereof and the effective n-type impurity concentration of the n-type column region is higher than that in the periphery thereof.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technology disclosed in the present specification relates to a diode, a field-effect transistor incorporating the diode, and a method for manufacturing a diode. Background Art

[0002] Patent Document 1 discloses a metal-oxide-semiconductor field-effect transistor (MOSFET). This MOSFET includes a semiconductor substrate made of SiC. The semiconductor substrate includes a p-type base region, an n-type drift layer and a p-type deep layer located below the base region, and an n-type substrate located below the drift layer and the deep layer. The drift layer and the deep layer are alternately arranged in a lateral direction. In this MOSFET, a high breakdown voltage can be maintained by the drift layer and the deep layer. Prior Art Literature Patent Literature

[0003] Patent Document 1 Japanese Patent Application Laid-Open No. 2013-17469 Summary of Invention Problem to be Solved by Invention

[0004] In the MOSFET of Patent Document 1, pn diodes are formed at the interface between the p-type base region and the n-type drift layer, and at the interface between the p-type deep layer and the n-type substrate. When this diode conducts electricity, holes flow from the base region to the n-type substrate through the drift layer. Holes also flow from the deep layer toward the n-type substrate. As a result, a large number of holes accumulate in the n-type substrate made of SiC.

[0005] It is known that multiple basal plane dislocations exist within SiC. Basal plane dislocations are dislocations that exist on the (0001) plane (i.e., the C plane), which is the basal plane of a SiC single crystal. When the hole concentration around basal plane dislocations in an n-type substrate increases, single Shockley-type stacking faults extend from the basal plane dislocations. Current becomes extremely difficult to flow in the areas where stacking faults are formed. In the MOSFET described in Patent Document 1, there is a problem that the current-carrying region of the pn diode decreases because a large number of holes accumulate in the n-type substrate, causing stacking faults to extend over a wide area inside the n-type substrate. This specification provides a technology to reduce the amount of holes accumulated in the n-type semiconductor region and suppress current-carrying degradation in a diode equipped with a semiconductor substrate made of SiC. [Means for solving the problem]

[0006] The diode disclosed herein comprises a semiconductor substrate (12) made of SiC. The semiconductor substrate comprises a first p-type semiconductor region (32b), a drift region (34) in contact with the first semiconductor region from below, and a second n-type semiconductor region (36) in contact with the drift region from below. The drift region has a structure in which a plurality of p-type column regions (34a) and a plurality of n-type column regions (34b) are arranged alternately in the lateral direction. A specific region (35) is provided in a part of the depth direction of the drift region, distributed across the plurality of p-type column regions and the plurality of n-type column regions. Within the specific region, the effective p-type impurity concentration of the p-type column region is lower than that of its surroundings, and the effective n-type impurity concentration of the n-type column region is higher than that of its surroundings.

[0007] In the diode described above, the semiconductor substrate has a drift region having a structure in which multiple p-type column regions and multiple n-type column regions are alternately arranged laterally, and a specific region is provided in a part of the depth direction of the drift region that is distributed across each p-type column region and each n-type column region. Within this specific region, the effective p-type impurity concentration of the p-type column region is lower than that of its surroundings, and the effective n-type impurity concentration of the n-type column region is higher than that of its surroundings. In this specification, the effective p-type impurity concentration refers to the concentration obtained by subtracting the n-type impurity concentration from the p-type impurity concentration. Similarly, in this specification, the effective n-type impurity concentration refers to the concentration obtained by subtracting the p-type impurity concentration from the n-type impurity concentration. That is, the hole concentration of the p-type column region within the specific region is lower than that of the surrounding p-type column region, and the electron concentration of the n-type column region within the specific region is higher than that of the surrounding n-type column region.

[0008] In the n-type column region within a specific area, the effective n-type impurity concentration is relatively high. Therefore, some of the holes flowing from the first semiconductor region to the second semiconductor region via the n-type column region are trapped in the n-type column region within that specific area. Furthermore, since the electron concentration in the n-type column region within the specific area is higher than that of its surroundings, the holes trapped in the n-type column region within that specific area are annihilated by recombining with electrons within that n-type column region. Similarly, in the p-type column region within a specific area, the effective p-type impurity concentration is relatively low. Therefore, some of the holes flowing from the first semiconductor region to the second semiconductor region via the p-type column region are trapped in the p-type column region within that specific area. Furthermore, since the hole concentration in the p-type column region within the specific area is lower than that of its surroundings (i.e., the relative electron concentration is higher), the holes trapped in the p-type column region within that specific area are annihilated by recombining with electrons within that p-type column region.

[0009] As described above, the diode can reduce the amount of holes that reach the second semiconductor region from the first semiconductor region through the drift region (i.e., the p-type column region and the n-type column region). Therefore, the amount of holes accumulated in the second semiconductor region made of SiC is reduced, and current degradation can be suppressed.

[0010] A method for manufacturing a diode disclosed herein comprises a first p-type semiconductor region (32b) made of SiC, a drift region (34) made of SiC and in contact with the first semiconductor region from below, and a second n-type semiconductor region (36) made of SiC and in contact with the drift region from below. The manufacturing method comprises a step of forming the drift region. The step of forming the drift region comprises a step of forming a lower n-type semiconductor layer (40) on the second semiconductor region by epitaxial growth, a step of forming an upper n-type semiconductor layer (42) on the lower n-type semiconductor layer by epitaxial growth, and a step of forming a plurality of p-type column regions (34a) extending across the lower n-type semiconductor layer and the upper n-type semiconductor layer by ion implantation, wherein the n-type regions remaining between the p-type column regions are n-type column regions (34b), and the plurality of p-type column regions and the plurality of n-type column regions are arranged alternately in the lateral direction. The process of forming the upper n-type semiconductor layer is carried out under conditions in which the concentration of n-type impurities is locally high in the portion formed in the early stages of epitaxial growth of the upper n-type semiconductor layer.

[0011] In this manufacturing method, the process of forming the upper n-type semiconductor layer is carried out under conditions where the n-type impurity concentration is locally high in the portion formed in the early stages of epitaxial growth of the upper n-type semiconductor layer. That is, the upper n-type semiconductor layer is formed such that the n-type impurity concentration of the upper n-type semiconductor layer formed near the top surface of the lower n-type semiconductor layer is higher than the n-type impurity concentration of the upper n-type semiconductor layer formed thereafter. Subsequently, multiple p-type column regions extending across the lower n-type semiconductor layer and the upper n-type semiconductor layer are formed by ion implantation. In the region at the bottom of the upper n-type semiconductor layer (near the top surface of the lower n-type semiconductor layer) (hereinafter referred to as the "specific region"), the n-type impurity concentration is higher than in other regions. Therefore, the effective p-type impurity concentration of the p-type column region inverted to p-type by ion implantation is lower in the specific region than in other regions. Similarly, the effective n-type impurity concentration of the remaining n-type column region after ion implantation is higher in the specific region than in other regions. As a result, in the manufactured diode, when current is applied, some of the holes flowing from the first semiconductor region through the drift region (i.e., the p-type column region and the n-type column region) into the second semiconductor region are captured in a specific region. Therefore, with the above manufacturing method, it is possible to manufacture a diode that does not easily accumulate holes in the second semiconductor region when current is applied and is less susceptible to degradation during current application. [Brief explanation of the drawing]

[0012] [Figure 1] Cross-sectional view of the semiconductor device of Example 1. [Figure 2] A diagram illustrating the manufacturing process of the semiconductor device of Example 1. [Figure 3] Schematic diagram of an apparatus for epitaxial growth. [Figure 4] A diagram illustrating the manufacturing process of the semiconductor device of Example 1. [Figure 5] A diagram illustrating the manufacturing process of the semiconductor device of Example 1. [Figure 6] A diagram illustrating the manufacturing process of the semiconductor device of Example 1. [Figure 7] A diagram illustrating the manufacturing process of the semiconductor device of Example 1. [Figure 8]A graph showing an example of the introduction timing and amount of each gas in the manufacturing method of Example 1. [Figure 9] A graph showing the nitrogen concentration distribution in the upper n-type semiconductor layer formed by the manufacturing method of Example 1. [Figure 10] A graph showing another example of the introduction timing and amount of each gas in the manufacturing method of Example 1. [Figure 11] A graph showing another example of the introduction timing and amount of each gas in the manufacturing method of Example 1. [Figure 12] Cross-sectional view of the semiconductor device of Example 2. [Modes for carrying out the invention]

[0013] In one example embodiment disclosed herein, a plurality of the specified regions may be provided at intervals in the depth direction.

[0014] This specification also discloses a field-effect transistor incorporating any of the diodes described above. The field-effect transistor may comprise a plurality of trenches extending from the upper surface of the semiconductor substrate through the first semiconductor region to the n-type column region, a gate insulating film covering the inner surface of each trench, and a gate electrode disposed within each trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate may further comprise an n-type source region separated from the drift region by the first semiconductor region and in contact with the gate insulating film.

[0015] (Example 1) With reference to the drawings, the semiconductor device 10 of Embodiment 1 will be described. The semiconductor device 10 is a MOSFET. As shown in FIG. 1, the semiconductor device 10 includes a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. A source electrode 70 is disposed on an upper surface 12a of the semiconductor substrate 12. A drain electrode 80 is disposed on a lower surface 12b of the semiconductor substrate 12. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as an x direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 and perpendicular to the x direction is referred to as a y direction, and a thickness direction of the semiconductor substrate 12 is referred to as a z direction.

[0016] A plurality of trenches 22 are formed on the upper surface 12a of the semiconductor substrate 12. As shown in FIG. 1, the plurality of trenches 22 are arranged at intervals in the x direction. Each trench 22 extends long in the y direction. A gate insulating film 24 and a gate electrode 26 are formed in each trench 22. The gate insulating film 24 is made of, for example, silicon oxide, and covers an inner surface of the trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. An upper surface of the gate electrode 26 is covered with an interlayer insulating layer 28. The gate electrode 26 is insulated from the source electrode 70 by the interlayer insulating layer 28.

[0017] Inside the semiconductor substrate 12, a plurality of source regions 30, a contact region 32a, a body region 32b, a drift region 34, and a drain region 36 are provided. Each of the regions 30, 32a, 32b, 34, and 36 is made of SiC.

[0018] Each source region 30 is an n-type region. Each source region 30 is exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 30 is in ohmic contact with the source electrode 70. Each source region 30 is in contact with the gate insulating film 24 at an upper end of the trench 22.

[0019] The contact region 32a is a p-type region. The contact region 32a is located in the area between the two source regions 30. The contact region 32a is exposed on the upper surface 12a of the semiconductor substrate 12. The contact region 32a is in ohmic contact with the source electrode 70.

[0020] The body region 32b is a p-type region. The body region 32b has a lower p-type impurity concentration than the contact region 32a. The body region 32b is in contact with the source region 30 and the contact region 32a from below. The body region 32b is in contact with the gate insulating film 24 below the source region 30.

[0021] The drift region 34 is in contact with the body region 32b from below. The drift region 34 has a plurality of p-type column regions 34a and a plurality of n-type column regions 34b. The plurality of p-type column regions 34a and the plurality of n-type column regions 34b are arranged alternately along the x-direction. Each p-type column region 34a extends downward from the lower end of the body region 32b. Each n-type column region 34b is in contact with the gate insulating film 24 below the body region 32b. Each n-type column region 34b is separated from the source region 30 by the body region 32b. The lower end of each trench 22 is surrounded by the n-type column regions 34b.

[0022] A specific region 35 is provided within the drift region 34. The specific region 35 is located in a part of the drift region 34 in the depth direction (z direction). The specific region 35 is distributed across multiple p-type column regions 34a and multiple n-type column regions 34b. In the specific region 35, the effective p-type impurity concentration of the p-type column region 34a is lower than that of its surroundings (i.e., the p-type column regions 34a located above and below the specific region 35). Also, in the specific region 35, the effective n-type impurity concentration of the n-type column region 34b is higher than that of its surroundings (i.e., the n-type column regions 34b located above and below the specific region 35).

[0023] The drain region 36 is an n-type region. The n-type impurity concentration in the drain region 36 is higher than the n-type impurity concentration in the n-type column region 34b. The drain region 36 is in contact with the drift region 34 from below. The drain region 36 is exposed on the lower surface 12b of the semiconductor substrate 12. The drain region 36 is in ohmic contact with the drain electrode 80.

[0024] Next, the operation of the semiconductor device 10 will be described. When the semiconductor device 10 is in use, a higher potential is applied to the drain electrode 80 than to the source electrode 70. When a potential above the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32b near the gate insulating film 24. Then, electrons flow from the source electrode 70 to the drain electrode 80, passing through the source region 30, the channel in the body region 32b, the n-type column region 34b in the drift region 34, and the drain region 36. In other words, the semiconductor device 10 is turned on. Also, when the potential of the gate electrode 26 is lowered to a potential below the gate threshold, the channel disappears, the flow of electrons stops, and the semiconductor device 10 is turned off.

[0025] In this semiconductor device 10, pn diodes are formed at the interface between the p-type body region 32b and the n-type column region 34b, and at the interface between the p-type column region 34a and the n-type drain region 36. When this diode is energized, holes flow from the body region 32b through the n-type column region 34b towards the drain region 36. Holes also flow from the body region 32b through the p-type column region 34a towards the drain region 36. Therefore, when the diode is turned on, many holes accumulate in the drain region 36, which is made of SiC.

[0026] As described above, since multiple basal plane dislocations exist inside SiC, if the hole concentration around the basal plane dislocations in the drain region 36 increases, single Shockley type stacking faults extend from the basal plane dislocations. In the areas where stacking faults are formed, current becomes extremely difficult to flow, which can lead to current-conductivity degradation. However, in the semiconductor device 10 of this embodiment, a specific region 35 is provided in the drift region 34 to suppress current-conductivity degradation. In the n-type column region 34b within the specific region 35, the effective n-type impurity concentration is relatively high, so some of the holes flowing from the body region 32b through the n-type column region 34b to the drain region 36 are captured in the n-type column region 34b within the specific region 35. Furthermore, since the electron concentration in the n-type column region 34b within the specific region 35 is higher than that of the surrounding n-type column region 34b, the holes captured in the n-type column region 34b within the specific region 35 disappear by recombining with electrons in the n-type column region 34b. Furthermore, in the p-type column region 34a within the specific region 35, the effective p-type impurity concentration is relatively low. Therefore, some of the holes flowing from the body region 32b through the p-type column region 34a to the drain region 36 are captured in the p-type column region 34a within the specific region 35. Also, since the hole concentration in the p-type column region 34a within the specific region 35 is lower (i.e., the relative electron concentration is higher) compared to the surrounding p-type column regions 34a, the holes captured in the p-type column region 34a within the specific region 35 are annihilated by recombining with electrons within that p-type column region 34a.

[0027] As described above, in the semiconductor device 10 of this embodiment, when the diode is turned on, the amount of holes that reach the drain region 36 from the body region 32b via the drift region 34 (i.e., the p-type column region 34a and the n-type column region 34b) can be reduced. Therefore, the amount of holes that accumulate in the drain region 36 made of SiC is reduced, and current degradation can be suppressed.

[0028] Next, the manufacturing method of the semiconductor device 10 will be explained with reference to Figures 2 to 7. Figures 2 and 4 to 7 show cross-sections corresponding to Figure 1. First, a semiconductor substrate 12 before processing, which is composed of drain regions 36, is prepared. Then, as shown in Figure 2, a lower n-type semiconductor layer 40 is formed on the drain regions 36 by epitaxial growth.

[0029] Specifically, as shown in Figure 3, a semiconductor substrate 12, which is composed of a drain region 36, is placed inside the chamber 90. The semiconductor substrate 12 is heated inside the chamber 90. Monosilane gas (SiH4), propane gas (C3H8), and doping gas (N2) are supplied into the chamber 90. As shown in Figure 3, the monosilane gas is supplied into the chamber 90 along with the carrier gas (H2) through the flow path 92a. The propane gas is supplied into the chamber 90 along with the carrier gas through the flow path 92b. The doping gas is supplied into the chamber 90 along with the carrier gas through the flow path 92c. The flow rate of the monosilane gas inside the chamber 90 is controlled by a flow control valve 94a located between the monosilane gas supply source and the flow path 92a. The flow rate of the propane gas inside the chamber 90 is controlled by a flow control valve 94b located between the propane gas supply source and the flow path 92b. The flow rate of the doping gas within the chamber 90 is controlled by a flow control valve 94c located between the doping gas supply source and the flow path 92c.

[0030] Here, monosilane gas, propane gas, and doping gas are supplied into the chamber 90 to epitaxially grow the lower n-type semiconductor layer 40 on the drain region 36, as shown in Figure 2.

[0031] Next, as shown in Figure 4, an upper n-type semiconductor layer 42 is formed on the lower n-type semiconductor layer 40 by epitaxial growth. This process is carried out under conditions in which the n-type impurity concentration is locally high in the portion formed in the early stages of epitaxial growth of the upper n-type semiconductor layer 42. That is, the upper n-type semiconductor layer 42 is formed such that the n-type impurity concentration of the upper n-type semiconductor layer 42 formed near the upper surface of the lower n-type semiconductor layer 40 is higher than the n-type impurity concentration of the upper n-type semiconductor layer 42 formed thereafter. The lower n-type semiconductor layer 40 and the upper n-type semiconductor layer 42 become the drift region 34. In addition, the portion of the upper n-type semiconductor layer 42 formed in the early stages of this process (the upper n-type semiconductor layer 42 formed near the upper surface of the lower n-type semiconductor layer 40) becomes the specific region 35. The n-type impurity concentration in the specific region 35 is higher than the n-type impurity concentration of the upper n-type semiconductor layer 42 above the specific region 35, and also higher than the n-type impurity concentration of the lower n-type semiconductor layer 40. The above conditions (i.e., the timing and amount of supply of each gas) in the process of forming the upper n-type semiconductor layer 42 on the lower n-type semiconductor layer 40 will be described later.

[0032] Next, as shown in Figure 5, multiple p-type column regions 34a are formed by ion implanting p-type impurities into the lower n-type semiconductor layer 40 and the upper n-type semiconductor layer 42. Here, p-type impurities are ion implanted so that they are distributed at a substantially uniform concentration from the upper surface of the upper n-type semiconductor layer 42 to the lower surface of the lower n-type semiconductor layer 40. The p-type impurities are implanted selectively at intervals. As a result, the regions into which p-type impurities are implanted are inverted to the p-type, forming multiple p-type column regions 34a that extend across the lower n-type semiconductor layer 40 and the upper n-type semiconductor layer 42. In addition, the n-type regions remaining between the p-type column regions 34a (i.e., regions where p-type impurities were not implanted) become n-type column regions 34b. Furthermore, as explained in the process shown in Figure 4, a specific region 35 is formed at the bottom of the upper n-type semiconductor layer 42 where the concentration of n-type impurities is higher than in other regions. Therefore, the effective p-type impurity concentration in the p-type column region 34a, which has been inverted to p-type by the injection of p-type impurities, becomes lower in a specific region 35 than in other regions. Similarly, the effective n-type impurity concentration in the remaining n-type column region 34b, which has been left behind by the injection of p-type impurities, becomes higher in a specific region 35 than in other regions.

[0033] Next, as shown in Figure 6, a p-type body region 32b, a source region 30, and a contact region 32a are formed on the upper n-type semiconductor layer 42 using epitaxial growth or ion implantation.

[0034] Next, as shown in Figure 7, a plurality of trenches 22 are formed by selectively etching the upper surface 12a of the semiconductor substrate 12. Here, trenches 22 are formed that penetrate the source region 30 and the body region 32b and reach the upper n-type semiconductor layer 42. Subsequently, the semiconductor device 10 shown in Figure 1 is completed by forming the interlayer insulating layer 28, gate insulating film 24, gate electrode 26, source electrode 70, and drain electrode 80 using techniques such as CVD (Chemical Vapor Deposition) and sputtering.

[0035] Next, referring to Figures 8 to 11, the supply timing and supply amount of each gas in the process of forming the upper n-type semiconductor layer 42 on the lower n-type semiconductor layer 40 by epitaxial growth will be explained.

[0036] The propane gas and monosilane gas supplied into chamber 90 are decomposed within the chamber 90. The decomposition of propane gas generates reactive carbon material (i.e., decomposed C atoms) within chamber 90. The decomposition of monosilane gas generates reactive silicon material (i.e., decomposed Si atoms) within chamber 90. Hereafter, the ratio of reactive carbon material to reactive silicon material present in the chamber will be referred to as the C / Si ratio. That is, the C / Si ratio is the value obtained by dividing the number of moles of reactive carbon material by the number of moles of reactive silicon material. The binding energy of monosilane gas is lower than that of propane gas. In other words, monosilane gas decomposes more easily than propane gas. For this reason, when propane gas and monosilane gas are supplied into chamber 90 at a constant supply ratio, the C / Si ratio is low in the initial stages of epitaxial growth, and then increases over time.

[0037] Furthermore, the dopant concentration in the SiC layer formed by epitaxial growth (e.g., the upper n-type semiconductor layer 42) depends on the C / Si ratio in the chamber. Specifically, the nitrogen (N) of the n-type dopant is incorporated into the SiC by coordinating with C. Therefore, the lower the C / Si ratio in the chamber (i.e., the less reactive carbon material in the gas), the easier it is for the n-type dopant to be incorporated into the SiC. In other words, the lower the C / Si ratio, the higher the n-type dopant concentration in the SiC formed by epitaxial growth.

[0038] In the manufacturing method of this embodiment, the process of forming the upper n-type semiconductor layer 42 is carried out under conditions in which the concentration of n-type impurities is locally high in the portion formed in the early stages of epitaxial growth of the upper n-type semiconductor layer 42, utilizing the characteristics described above.

[0039] Specifically, for example, as shown in Figure 8, monosilane gas and propane gas are introduced into the chamber 90 simultaneously at time t1. As mentioned above, monosilane gas decomposes more easily than propane gas, so when monosilane gas and propane gas are introduced into the chamber 90 simultaneously, monosilane gas decomposes before propane gas. Therefore, in the initial stages of epitaxial growth of the upper n-type semiconductor layer 42, there is a large amount of reactive silicon material, resulting in a low C / Si ratio. Consequently, a region with a high n-type impurity concentration is formed in the initial stages of growth of the upper n-type semiconductor layer 42. Subsequently, as the ratio of the decomposition amount of propane gas to the decomposition amount of monosilane gas stabilizes and the C / Si ratio converges to a constant value, the n-type impurity concentration of the upper n-type semiconductor layer 42 stabilizes at a lower value than in the initial stages of growth.

[0040] Thus, by forming the upper n-type semiconductor layer 42 under the above conditions, as shown in the graph in Figure 9, the portion of the upper n-type semiconductor layer 42 formed in the early stages of epitaxial growth (i.e., the period when the C / Si ratio is low) has a locally high n-type dopant concentration (n-type impurity concentration). In the portion of the upper n-type semiconductor layer 42 formed in the later stages of epitaxial growth (i.e., the period when the C / Si ratio is stable at a high value), the n-type impurity concentration stabilizes at a low value.

[0041] Thus, in this embodiment, a region with a high concentration of n-type impurities is formed in the upper n-type semiconductor layer 42 during the initial stages of epitaxial growth. Specifically, a region with a high concentration of n-type impurities is formed in the upper n-type semiconductor layer 42 near the upper surface of the lower n-type semiconductor layer 40. By adjusting the supply timing and amount of each gas in this way, a specific region 35 can be formed. As a result, when the diode is energized, stacking faults are less likely to spread within the drain region 36, and a semiconductor device 10 that is less susceptible to current degradation can be manufactured.

[0042] In the process of forming the upper n-type semiconductor layer 42, for example, as shown in Figure 10, monosilane gas may be introduced into the chamber 90 at time t2, and then propane gas may be introduced into the chamber 90 at time t3. Alternatively, for example, as shown in Figure 11, in a configuration in which monosilane gas and propane gas are introduced into the chamber 90 simultaneously at time t1, the flow rate of monosilane gas in the initial stages of growth of the upper n-type semiconductor layer 42 may be increased compared to the subsequent flow rate. Even with these configurations, for the same reasons as in the example shown in Figure 8, a region with a high concentration of n-type impurities (i.e., a specific region 35) can be formed in the initial stages of growth of the upper n-type semiconductor layer 42.

[0043] A pn diode composed of a body region 32b, an n-type column region 34b, a p-type column region 34a, and a drain region 36 is an example of a "diode." The body region 32b and the drain region 36 are examples of a "first semiconductor region" and a "second semiconductor region," respectively.

[0044] (Example 2) Next, with reference to Figure 12, the semiconductor device 100 of Example 2 will be described. In the semiconductor device 100 of Example 2, a plurality of specific regions 35 are provided within the drift region 34. As shown in Figure 12, each specific region 35 is spaced apart in the depth direction (z direction) of the semiconductor substrate 12. In this configuration, the amount of holes trapped in the specific regions 35 is greater than in Example 1. Therefore, the extension of stacking faults in the drain region 36 is further suppressed, and electrical degradation can be made less likely to occur.

[0045] To manufacture the semiconductor device 100 of Example 2, for example, after the step of forming the upper n-type semiconductor layer described in the Figure of Example 1, an additional n-type semiconductor layer may be formed on the upper n-type semiconductor layer under the same conditions as the step of forming the upper n-type semiconductor layer. Subsequently, a p-type body region may be formed on the additional n-type semiconductor layer by epitaxial growth.

[0046] In the embodiment described above, the p-type column region 34a does not need to be connected to the body region 32b in the cross-section shown in Figure 1. The p-type column region 34a only needs to have a potential approximately equal to that of the source electrode 70, and may be connected to the source electrode 70 via the body region 32b at a position not shown. Furthermore, the p-type column region 34a does not need to be connected to the drain region 36.

[0047] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0048] 10: Semiconductor device, 12: Semiconductor substrate, 22: Trench, 24: Gate insulating film, 26: Gate electrode, 28: Interlayer insulating layer, 30: Source region, 32a: Contact region, 32b: Body region, 34: Drift region, 34a: p-type column region, 34b: n-type column region, 35: Specific region, 36: Drain region, 40: Lower n-type semiconductor layer, 42: Upper n-type semiconductor layer, 70: Source electrode, 80: Drain electrode

Claims

1. A diode comprising a semiconductor substrate (12) made of SiC, The aforementioned semiconductor substrate p-type first semiconductor region (32b) and A drift region (34) that is in contact with the first semiconductor region from below, A second n-type semiconductor region (36) is in contact with the drift region from below, It is equipped with, The drift region has a structure in which a plurality of p-type column regions (34a) and a plurality of n-type column regions (34b) are arranged alternately in the lateral direction. A specific region (35) is provided in a part of the depth direction of the drift region, which is distributed across a plurality of p-type column regions and a plurality of n-type column regions. Multiple of the aforementioned specific regions are provided at intervals in the depth direction, Within the aforementioned specific region, the effective p-type impurity concentration in the p-type column region is lower than that of the surrounding area, and the effective n-type impurity concentration in the n-type column region is higher than that of the surrounding area. diode.

2. A field-effect transistor (10) incorporating the diode described in claim 1, A plurality of trenches (22) extending from the upper surface (12a) of the semiconductor substrate through the first semiconductor region to the n-type column region, A gate insulating film (24) covers the inner surface of each trench, A gate electrode (26) is disposed within each of the trenches and is insulated from the semiconductor substrate by the gate insulating film, It is equipped with, The aforementioned semiconductor substrate A field-effect transistor further comprising an n-type source region (30) separated from the drift region by the first semiconductor region and in contact with the gate insulating film.

3. A method for manufacturing a diode according to claim 1, The process involves forming a lower n-type semiconductor layer (40) on the second semiconductor region by epitaxial growth, The process of forming an upper n-type semiconductor layer (42) on the lower n-type semiconductor layer by epitaxial growth, The process of forming an additional n-type semiconductor layer on the upper n-type semiconductor layer by epitaxial growth, A step of forming a plurality of p-type column regions (34a) extending across the lower n-type semiconductor layer, the upper n-type semiconductor layer, and the additional n-type semiconductor layer by ion implanting p-type impurities such that the p-type impurities are distributed at a uniform concentration along the depth direction of the drift region, wherein the n-type regions remaining between the p-type column regions are n-type column regions (34b), and the plurality of p-type column regions and the plurality of n-type column regions are arranged alternately in the lateral direction. A step of forming the first semiconductor region on the additional semiconductor layer by epitaxial growth, It has, The process of forming the upper n-type semiconductor layer is carried out under conditions in which the concentration of n-type impurities locally increases in a first portion formed in the early stages of epitaxial growth of the upper n-type semiconductor layer, and the concentration of n-type impurities in the first portion is higher than the concentration of n-type impurities in the lower n-type semiconductor layer. The process of forming the additional n-type semiconductor layer is carried out under conditions in which the n-type impurity concentration is locally high in the second portion formed in the early stages of epitaxial growth of the additional n-type semiconductor layer, and the n-type impurity concentration in the second portion is higher than the n-type impurity concentration in the region of the upper n-type semiconductor layer other than the first portion. After the step of forming the plurality of p-type column regions, the first portion and the second portion each become the specific region. A method for manufacturing diodes.

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