Semiconductor equipment

Abstract

To provide a semiconductor device having stable characteristics.SOLUTION: One embodiment provides a semiconductor device containing silicon carbide. The semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer. The first to third semiconductor layers are of a first conductivity type, and the fourth semiconductor layer is of a second conductivity type. A carrier concentration of the second semiconductor layer is the same as or lower than a carrier concentration of the first semiconductor layer. The carrier concentration of the second semiconductor layer is the same as or higher than a carrier concentration of the third semiconductor layer. A point defect density in the second semiconductor layer is the same as or higher than a point defect density of the first semiconductor layer, and is higher than a point defect density of the third semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a semiconductor device. [Background Art]

[0002] For example, there is a semiconductor device using a substrate containing silicon carbide (SiC). Stable characteristics are desired for semiconductor devices. [Prior Art Literature] [Patent Literature]

[0003] [Patent Literature 1] Japanese Unexamined Patent Publication No. 2022-38594 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] An object of embodiments of the present invention is to provide a semiconductor device having stable characteristics. [Means for Solving the Problem]

[0005] A semiconductor device according to an embodiment comprises: a first conductivity type semiconductor substrate containing silicon carbide, the semiconductor substrate having a first surface and a second surface located on an opposite side of the first surface; a first conductivity type first semiconductor layer provided on the first surface and containing silicon carbide; a first conductivity type second semiconductor layer provided on the first semiconductor layer and containing silicon carbide; a first conductivity type third semiconductor layer provided on the second semiconductor layer and containing silicon carbide; and a second conductivity type fourth semiconductor layer provided on the third semiconductor layer and containing silicon carbide. A carrier concentration of the first conductivity type in the second semiconductor layer is equal to or lower than a carrier concentration of the first conductivity type in the first semiconductor layer. The carrier concentration of the first conductivity type in the second semiconductor layer is equal to or higher than a carrier concentration of the first conductivity type in the third semiconductor layer. A point defect density of the second semiconductor layer is equal to or higher than a point defect density of the first semiconductor layer, and higher than the point defect density of the third semiconductor layer. [Brief Description of the Drawings]

[0006] [Figure 1] This is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 2] This is a schematic cross-sectional view illustrating a part of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] This is a schematic cross-sectional view illustrating a part of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] This is a schematic cross-sectional view illustrating a part of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] This is a schematic cross-sectional view illustrating some examples of modified methods for manufacturing a semiconductor device according to the first embodiment. [Figure 6] This is a schematic cross-sectional view illustrating some examples of modified methods for manufacturing a semiconductor device according to the first embodiment. [Figure 7] This is a schematic cross-sectional view illustrating some other variations of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] This is a schematic cross-sectional view illustrating some other variations of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] This is a schematic cross-sectional view illustrating the operation of a semiconductor device according to the first embodiment. [Figure 10] This is a schematic cross-sectional view illustrating the operation of a comparative example semiconductor device. [Figure 11] This is a schematic cross-sectional view illustrating a semiconductor device according to a modified example of the first embodiment. [Figure 12] This is a schematic cross-sectional view illustrating a part of a method for manufacturing a semiconductor device according to a modified example of the first embodiment. [Figure 13] This is a schematic cross-sectional view illustrating a part of a method for manufacturing a semiconductor device according to a modified example of the first embodiment. [Figure 14] This is a schematic cross-sectional view illustrating a part of a modified example of the method for manufacturing a semiconductor device according to a modification of the first embodiment. [Figure 15]It is a schematic cross-sectional view illustrating part of a modification of a method for manufacturing a semiconductor device according to a modification of the first embodiment. [Figure 16] It is a schematic cross-sectional view illustrating a semiconductor device according to another modification of the first embodiment. [Figure 17] It is a schematic cross-sectional view illustrating part of a method for manufacturing a semiconductor device according to another modification of the first embodiment. [Figure 18] It is a schematic cross-sectional view illustrating part of a method for manufacturing a semiconductor device according to another modification of the first embodiment. [Figure 19] It is a schematic cross-sectional view illustrating part of a method for manufacturing a semiconductor device according to another modification of the first embodiment. [Figure 20] It is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. [Figure 21] It is a schematic cross-sectional view taken along line B-B of FIG. 20. [Figure 22] It is a schematic enlarged view of part C of FIG. 20. [Figure 23] It is a schematic cross-sectional view illustrating part of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 24] It is a schematic cross-sectional view illustrating part of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 25] It is a schematic cross-sectional view for explaining the operation of the semiconductor device according to the second embodiment. [Figure 26] It is a schematic cross-sectional view taken along line D-D of FIG. 25. [Figure 27] It is a schematic cross-sectional view for explaining the operation of a semiconductor device according to a comparative example. [Figure 28] It is a schematic cross-sectional view taken along line E-E of FIG. 27. [Figure 29] It is a schematic cross-sectional view illustrating a semiconductor device according to a modification of the second embodiment. [Figure 30] It is a schematic enlarged view of part F of FIG. 29. [Figure 31] It is a schematic cross-sectional view illustrating part of a method for manufacturing a semiconductor device according to a modification of the second embodiment. [Figure 32] This is a schematic cross-sectional view illustrating a part of the method for manufacturing a semiconductor device according to a modified example of the second embodiment. [Figure 33] This is a schematic cross-sectional view illustrating a semiconductor device according to another modification of the second embodiment. [Figure 34] This is a schematic enlarged view of section G in Figure 33. [Figure 35] This is a schematic cross-sectional view illustrating a part of a method for manufacturing a semiconductor device according to another variation of the second embodiment. [Figure 36] This is a schematic cross-sectional view illustrating a part of a method for manufacturing a semiconductor device according to another variation of the second embodiment. [Figure 37] This is a schematic cross-sectional view illustrating a semiconductor device according to a third embodiment. [Figure 38] Figure 37 is a schematic cross-sectional view along the HH line. [Figure 39] This is a schematic cross-sectional view illustrating the operation of a semiconductor device according to the third embodiment. [Figure 40] This is a schematic cross-sectional view along line II in Figure 39. [Figure 41] This is a schematic cross-sectional view illustrating the operation of a semiconductor device related to a comparative example. [Figure 42] Figure 41 is a schematic cross-sectional view of the JJ line. [Modes for carrying out the invention]

[0007] Each embodiment of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n- , p + When denoted as "p" or "+", these indicate the relative levels of each impurity concentration. That is, a "+" sign indicates a relatively higher impurity concentration than a "-" sign, and a "-" sign indicates a relatively lower impurity concentration than a "-" sign. These notations represent the relative levels of the net impurity concentration after compensation between p-type and n-type impurities in each region. Carrier concentration is considered the effective impurity concentration. Each embodiment described below may be implemented by reversing the p-type and n-type of each semiconductor region.

[0008] (First Embodiment) Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. As shown in Figure 1, the semiconductor device 1 according to this embodiment comprises a semiconductor substrate 10, a first semiconductor layer 20, a second semiconductor layer 30, and a third semiconductor layer 40. The semiconductor device 1 further comprises a fourth semiconductor layer 50, a first electrode 62, and a second electrode 64.

[0009] The first semiconductor layer 20 is provided on the semiconductor substrate 10. The second semiconductor layer 30 is provided on the first semiconductor layer 20. The third semiconductor layer 40 is provided on the second semiconductor layer 30. The fourth semiconductor layer 50 is provided on the third semiconductor layer 40. The first electrode 62 is provided on the side of the semiconductor substrate 10 opposite to the side on which the first semiconductor layer 20 is provided. The second electrode 64 is provided on the side of the fourth semiconductor layer 50 opposite to the side on which the third semiconductor layer 40 is provided.

[0010] The semiconductor substrate 10, the first semiconductor layer 20, the second semiconductor layer 30, the third semiconductor layer 40, and the fourth semiconductor layer 50 contain silicon carbide (SiC).

[0011] The semiconductor substrate 10, the first semiconductor layer 20, the second semiconductor layer 30, and the third semiconductor layer 40 are of the first conductivity type. The fourth semiconductor layer 50 is of the second conductivity type. For example, the first conductivity type is n-type, and the second conductivity type is p-type.

[0012] The impurity concentration of the first semiconductor layer 20 is higher than that of the third semiconductor layer 40. The impurity concentration of the second semiconductor layer 30 is the same as or higher than that of the third semiconductor layer 40. The impurity concentration of the second semiconductor layer 30 is the same as or lower than that of the first semiconductor layer 20. The semiconductor device 1 is, for example, a PiN diode.

[0013] The semiconductor substrate 10 has a first surface 11a and a second surface 11b. The second surface 11b is the surface opposite to the first surface 11a. A first semiconductor layer 20 is provided on the first surface 11a, and a first electrode 62 is provided on the second surface 11b. The semiconductor substrate 10 is, for example, a SiC bulk single crystal substrate.

[0014] In the following explanation, we will sometimes use a three-dimensional Cartesian coordinate system of XYZ. The XY plane is a plane parallel to the first plane 11a or the second plane 11b. The Z axis is perpendicular to the XY plane. As explained in relation to Figure 9, the X axis is tilted with respect to the [11-20] axis, which is perpendicular to the {11-20} plane of the semiconductor substrate 10. The [11-20] axis is tilted with respect to the X axis by an off-angle θoff. The definition of an angle is that counterclockwise is positive with respect to the reference axis. The Y axis is parallel to the [1-100] axis, which is perpendicular to the {1-100} plane of the semiconductor substrate 10. The Z axis is tilted with respect to the

[0001] axis, which is perpendicular to the {0001} plane of the semiconductor substrate 10. The

[0001] axis is tilted with respect to the Z axis by an off-angle θoff. In other words, the {0001} plane is tilted with respect to the XY plane by an off-angle θoff around the Y axis or the [1-100] axis. As shown in Figure 9, the coordinate axes for the crystal axes may be shown together with the XYZ coordinate axes. In this case, the [1-100] axis, which coincides with the Y axis, should be displayed below the Y axis. The same applies to Figures 10, 20, 25, 27, 39, and 41. As mentioned above, the [1-100] axis is parallel to the Y axis, and its positive and negative directions are opposite.

[0015] The first semiconductor layer 20 includes, for example, SiC and nitrogen (N) as an impurity. For example, phosphorus (P) may be included instead of N, or both N and P may be included. For example, the impurity concentration of N in the first semiconductor layer 20 is 10 -19 [cm -3 It is lower than ]. The first semiconductor layer 20 forms point defects that serve as recombination centers by appropriately setting the impurity concentration, thereby shortening the recombination time of minority carriers injected from the fourth semiconductor layer 50 and suppressing the intrusion of minority carriers, thereby suppressing the generation of recombination energy. In addition, the first semiconductor layer 20 converts basal plane dislocations (BPDs) generated in the semiconductor substrate 10 into threading edge dislocations (TEDs). By converting BPDs to TEDs, the first semiconductor layer 20 suppresses the expansion of BPDs into single Shockley stacking faults (1SSFs).

[0016] The second semiconductor layer 30 contains a first element as an impurity. The first element includes at least one selected from the group consisting of N, P, aluminum (Al), and boron (B). The second semiconductor layer 30 may also contain a second element instead of the first element. The second element includes at least one selected from the group consisting of iron (Fe), nickel (Ni), chromium (Cr), magnesium (Mg), zinc (Zn), copper (Cu), calcium (Ca), vanadium (V), gold (Au), and platinum (Pt). The second semiconductor layer 30 may contain the second element together with the first element.

[0017] The first semiconductor layer 20 and the second semiconductor layer 30 have a higher point defect density than the semiconductor substrate 10 and the third semiconductor layer 40. The second semiconductor layer 30 has a point defect density equal to or higher than that of the first semiconductor layer 20.

[0018] The second semiconductor layer 30 has a higher point defect density than the semiconductor substrate 10, the first semiconductor layer 20, and the third semiconductor layer 40, thereby promoting the recombination of minority carriers injected from the fourth semiconductor layer 50, shortening the lifetime of the minority carriers, and suppressing the generation of recombination energy due to the recombination of minority carriers. By suppressing the generation of recombination energy, the second semiconductor layer 30 prevents the BPD from expanding to 1SSF.

[0019] When the semiconductor device 1 operates in the forward direction as a diode, the third semiconductor layer 40 allows majority carriers of the first conductivity type to travel through it and conduct a forward current. When the semiconductor device 1 operates in the reverse blocking direction as a diode, the third semiconductor layer 40 forms a depletion layer to achieve a desired withstand voltage between the second electrode 64, which is the anode electrode, and the first electrode 62, which is the cathode electrode.

[0020] The fourth semiconductor layer 50 is joined to the third semiconductor layer 40 to realize a pn junction. When the semiconductor device 1 operates in the forward direction as a diode, the fourth semiconductor layer 50 allows majority carriers of the second conductivity type to travel and conduct a forward current. When the semiconductor device 1 operates in the reverse blocking direction as a diode, the fourth semiconductor layer 50, together with the third semiconductor layer 40, achieves a desired withstand voltage between the second electrode 64, which is the anode electrode, and the first electrode 62, which is the cathode electrode.

[0021] The first electrode 62 is ohmic-connected to the semiconductor substrate 10 and functions as one of the main electrodes of the semiconductor device 1. The second electrode 64 is ohmic-connected to the fourth semiconductor layer 50 and functions as the other main electrode of the semiconductor device 1. When the semiconductor device 1 is a diode, the first electrode 62 is the cathode electrode and the second electrode 64 is the anode electrode.

[0022] A method for manufacturing the semiconductor device 1 according to this embodiment will be described. Figures 2 to 4 are schematic cross-sectional views illustrating a part of the manufacturing method of a semiconductor device according to the first embodiment. Figures 2 to 4 show cross-sections of the portion corresponding to section A in Figure 1. In this embodiment, when showing cross-sections of the semiconductor device, other drawings are assumed to represent the portion corresponding to section A in Figure 1 unless otherwise specified. As shown in Figure 2, a first semiconductor layer 20 is formed on the prepared semiconductor substrate 10. The first semiconductor layer 20 is formed by epitaxial growth.

[0023] As shown in Figure 3, a second semiconductor layer 30 is formed on a first semiconductor layer 20. The second semiconductor layer 30 is formed by epitaxial growth. When the second semiconductor layer 30 is epitaxially grown, doping with a first element (N, P, Al, B) forms recombination centers for Auger recombination. After the second semiconductor layer 30 is formed by epitaxial growth, a second element (Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, Pt) may be introduced into the second semiconductor layer 30 by thermal diffusion. When a second element is introduced instead of a first element, it is preferable because the second element forms point defects that become recombination centers without increasing the impurity concentration of the second semiconductor layer 30.

[0024] As shown in Figure 4, a third semiconductor layer 40 is formed on the second semiconductor layer 30. The third semiconductor layer 40 is formed by epitaxial growth.

[0025] Subsequently, a fourth semiconductor layer 50 is formed on the third semiconductor layer 40, and a first electrode 62 and a second electrode 64 are formed to form the semiconductor device 1.

[0026] Figures 5 and 6 are schematic cross-sectional views illustrating some modified examples of the semiconductor device manufacturing method according to the first embodiment. As shown in Figure 5, and as explained in relation to Figure 2, a first semiconductor layer 20 is formed on the prepared semiconductor substrate 10, and an intermediate semiconductor layer 140 is formed on the first semiconductor layer 20 by epitaxial growth. For example, the impurity concentration of the intermediate semiconductor layer 140 is the same as that of the third semiconductor layer 40 shown in Figure 1. In other words, the impurity concentration of the intermediate semiconductor layer 140 is lower than that of the first semiconductor layer 20. For example, the intermediate semiconductor layer 140 is formed under the same conditions as the formation conditions of the third semiconductor layer 40.

[0027] As shown in Figure 6, a second semiconductor layer 30 is formed on the first semiconductor layer 20. The second semiconductor layer 30 is formed by ion implanting a third element into the intermediate semiconductor layer 140 shown in Figure 5. The third element includes at least one selected from the group consisting of hydrogen (H), helium (He), argon (Ar), neon (Ne), and xenon (Xe). The H introduced into the intermediate semiconductor layer 140 by ion implantation is introduced as a proton. The ion implantation energy is set according to the thickness of the intermediate semiconductor layer 140. The third element is desorbed by subsequent normal thermal processes. Therefore, by ion implanting the third element into the intermediate semiconductor layer 140, a second semiconductor layer 30 with a high density of point defects can be formed without increasing the impurity density.

[0028] Ion implantation into the intermediate semiconductor layer 140 may be performed using a second element (Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, Pt) instead of a third element. These elements form deep energy levels in the band gap of the intermediate semiconductor layer 140 and function as recombination centers, enabling the formation of a second semiconductor layer 30 with high-density point defects without increasing the impurity density.

[0029] Figures 7 and 8 are schematic cross-sectional views illustrating some other variations of the method for manufacturing a semiconductor device according to the first embodiment. As shown in Figure 7, an intermediate semiconductor layer 120 is formed on the prepared semiconductor substrate 10 by epitaxial growth. In this case, the intermediate semiconductor layer 120 is formed to be thicker than the first semiconductor layer 20 described in relation to Figure 2. The intermediate semiconductor layer 120 has a thickness equal to the thickness of the first semiconductor layer 20 plus the thickness of the second semiconductor layer 30.

[0030] As shown in Figure 8, a third element is ion-implanted into the intermediate semiconductor layer 120 to form a second semiconductor layer 30. By adjusting the ion implantation energy, the second semiconductor layer 30 can be formed on the first semiconductor layer 20. The ion implantation into the second semiconductor layer 30 may be the second element instead of the third element. In either case, the impurity density of the second semiconductor layer 30 can be made higher than that of the first semiconductor layer 20, and the second semiconductor layer 30 can have a higher point defect density than the point defect density of the first semiconductor layer 20 without increasing the impurity density of the second semiconductor layer 20.

[0031] The operation and effects of the semiconductor device 1 according to this embodiment will be described. Figure 9 is a schematic cross-sectional view illustrating the operation of a semiconductor device according to the first embodiment. Figure 9 shows the crystal axes of SiC along with the XYZ coordinate system. The [11-20] axis is tilted in the positive direction with respect to the X axis by an off-angle θoff, around the Y axis and the [1-100] axis. The

[0001] axis is tilted with respect to the Z axis by an off-angle θoff, around the Y axis and the [1-100] axis. In other words, the {0001} plane of the SiC forming the semiconductor substrate 10, the first semiconductor layer 20, the second semiconductor layer 30, and the third semiconductor layer 40 is tilted with respect to the XY plane by an off-angle θoff, around the Y axis and the [1-100] axis. The off-angle θoff is, for example, about 4°.

[0032] As shown in Figure 9, minority carriers, specifically holes h+, injected from the fourth semiconductor layer 50 shown in Figure 1 are injected into the second semiconductor layer 30 via the third semiconductor layer 40. In the second semiconductor layer 30, densely formed point defects function as recombination centers for minority carriers, recombining and annihilating holes h+ and electrons e- with short lifetimes. Therefore, in the second semiconductor layer 30, the BPD, which has obtained the minority carrier recombination energy, is prevented from expanding to 1SSF.

[0033] For example, a dislocation B1, which is a BPD in the semiconductor substrate 10, may be formed along the {0001} plane of SiC. That is, dislocation B1 is formed with an off-angle θoff with respect to the XY plane. When dislocation B1 reaches the first semiconductor layer 20, it is converted into a dislocation T1, which is a TED, in the first semiconductor layer 20.

[0034] Dislocation T1 is formed along the

[0001] axis. Holes h+ traveling through the third semiconductor layer 40 travel almost along the Z axis. Since the Z axis and the

[0001] axis have an off-angle θoff of about 4°, dislocation T1 does not obstruct the movement of holes h+. Therefore, the conversion of dislocation B1 to dislocation T1 in the first semiconductor layer 20 does not increase the resistance of the semiconductor device 1 when it is conducting.

[0035] Since minority carriers that pass through the third semiconductor layer 40 are rapidly recombined at the recombination center of the second semiconductor layer 30, they hardly supply any recombination energy to the dislocation B1 formed on the semiconductor substrate 10. Even if a very small number of minority carriers pass through the second semiconductor layer 30, they are rapidly recombined at the recombination center of the first semiconductor layer 20, so the expansion of dislocation B1 to 1SSF is prevented.

[0036] Figure 10 is a schematic cross-sectional view illustrating a semiconductor device related to a comparative example. In the comparative example semiconductor device shown in Figure 10, the second semiconductor layer 30 shown in Figure 9 is not provided on the first semiconductor layer 20, and the third semiconductor layer 40 is directly provided on the first semiconductor layer 20.

[0037] As shown in Figure 10, in the comparative semiconductor device, dislocation B1 that was not converted to dislocation T1 in the second semiconductor layer 30 gains recombination energy between holes h+ and electrons e- and expands into a defect S1 of 1SSF. Defect S1 expands in the third semiconductor layer 40 in the positive Z-axis direction along the [11-20] axis as long as recombination energy is supplied. Since defect S1 obstructs carrier movement, the forward voltage relative to the forward current of semiconductor device 1 increases, which can lead to increased losses.

[0038] Conventionally, it is known that BPDs expand to 1SSF by obtaining recombination energy through the recombination of holes and electrons. To promote the recombination of holes and electrons and suppress the expansion from BPD to 1SSF, a recombination-promoting buffer layer with a high concentration of nitrogen has been introduced (for example, Patent Document 1, etc.). In such techniques, increasing the nitrogen concentration introduced into the recombination-promoting buffer layer improves the point defect density and promotes the recombination of holes and electrons. On the other hand, if the nitrogen concentration is 10 -19 [cm -3 It is known that introducing it beyond [a certain level] can adversely affect the quality of the epitaxial crystals in the low-concentration drift layer adjacent to the recombination-promoting buffer layer.

[0039] The semiconductor device 1 according to this embodiment includes a second semiconductor layer 30 having an impurity concentration lower than that of the first semiconductor layer 20 corresponding to the recombination-promoting buffer layer, and a point defect density higher than that of the first semiconductor layer 20. A third semiconductor layer 40 corresponding to a low-concentration drift layer is connected to the first semiconductor layer 20 and the semiconductor substrate 10 via the second semiconductor layer 30.

[0040] The second semiconductor layer 30 has an impurity concentration that is the same as or lower than that of the first semiconductor layer 20, and a point defect density that is the same as or higher than that of the first semiconductor layer 20. Therefore, the low impurity concentration suppresses the impact on the crystal quality of the third semiconductor layer 40, while the high point defect density promotes the recombination of holes and electrons, preventing the recombination energy from reaching the BPD. Thus, by providing the second semiconductor layer 30, it is possible to suppress the expansion of the BPD to 1SSF. Even if the BPD expands to 1SSF, the second semiconductor layer 30 is located between the third semiconductor layer 40 and the first semiconductor layer 20, so it does not supply recombination energy to the 1SSF expanded from the BPD in the first semiconductor layer 20. Therefore, it is possible to prevent the 1SSF from expanding further above the second semiconductor layer 20.

[0041] Point defects in the second semiconductor layer 30 can be formed by introducing the first element (N, P, Al, B) into the second semiconductor layer 30, as well as by introducing the second element (Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, Pt). Since the second element functions as a recombination center but does not function as an impurity, the second semiconductor layer 30 can achieve a higher point defect density than the first semiconductor layer 20 at a lower impurity concentration than the first semiconductor layer 20.

[0042] In addition to the above, point defects in the second semiconductor layer 30 can also be formed by introducing a third element (H, He, Ar, Ne, Xe). After being introduced into the second semiconductor layer 30, the third element itself disappears through the normal heating process of the semiconductor device 1. Therefore, while the third element forms point defects, it does not function as an impurity, so the second semiconductor layer 30 can achieve a high point defect density at a low impurity concentration.

[0043] (Variation 1) Figure 11 is a schematic cross-sectional view illustrating a semiconductor device 1a according to a modified example of the first embodiment. As shown in Figure 11, semiconductor device 1a differs from semiconductor device 1 shown in Figure 1 in that it further comprises a fifth semiconductor layer 42. In other respects, it is the same as semiconductor device 1, and the same components are denoted by the same reference numerals, and detailed explanations are omitted.

[0044] The fifth semiconductor layer 42 is provided between the first semiconductor layer 20 and the second semiconductor layer 30. The impurity concentration of the first conductivity type in the fifth semiconductor layer 42 is approximately the same as that of the third semiconductor layer 40. The point defect density of the fifth semiconductor layer 42 is approximately the same as that of the third semiconductor layer 40. In other words, the impurity concentration of the second semiconductor layer 30 is approximately the same as or higher than that of the fifth semiconductor layer 42. The point defect density of the second semiconductor layer 30 is higher than that of the fifth semiconductor layer 42. Preferably, the point defect density of the second semiconductor layer 30 is the same as or higher than that of the first semiconductor layer 20.

[0045] Figures 12 and 13 are schematic cross-sectional views illustrating a part of a method for manufacturing a semiconductor device according to a modified example of the first embodiment. As shown in Figure 2 above, the first semiconductor layer 20 is formed on the prepared semiconductor substrate 10 by epitaxial growth. As shown in Figure 12, the fifth semiconductor layer 42 is formed on the first semiconductor layer 20 by epitaxial growth. For example, the fifth semiconductor layer 42 is formed so that its impurity concentration is approximately equal to that of the third semiconductor layer 40. For example, the fifth semiconductor layer 42 is formed under the same conditions as the third semiconductor layer 40.

[0046] As shown in Figure 13, a second semiconductor layer 30 is formed on the fifth semiconductor layer 42. The second semiconductor layer 30 is formed by epitaxial growth. As explained in relation to Figure 3, the second semiconductor layer 30 is doped with the first element (N, P, Al, B). Furthermore, point defects may be formed as recombination centers by thermal diffusion of the second element (Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, Pt).

[0047] Subsequently, a third semiconductor layer 40, a fourth semiconductor layer 50, and a first electrode 62 are formed on the second semiconductor layer 30, and a second electrode 64 is formed on the semiconductor substrate 10, thereby forming the semiconductor device 1a.

[0048] Figures 14 and 15 are schematic cross-sectional views illustrating some modified examples of the method for manufacturing a semiconductor device according to a modification of the first embodiment. As shown in Figure 14, the intermediate semiconductor layer 42a is formed on the first semiconductor layer 20 by epitaxial growth. For example, the formation conditions for the intermediate semiconductor layer 42a are the same as those for the third semiconductor layer 40. The intermediate semiconductor layer 42a to be formed has a thickness equal to the sum of the thickness of the fifth semiconductor layer 42 and the thickness of the second semiconductor layer 30.

[0049] As shown in Figure 15, a second semiconductor layer 30 is formed in the intermediate semiconductor layer 42a shown in Figure 14 by ion implantation. As explained in relation to Figure 6, the second semiconductor layer 30 is formed by implanting a third element (H, He, Ar, Ne, Xe) into the intermediate semiconductor layer 42a. The introduction of the third element creates point defects in the second semiconductor layer 30 as recombination centers. Instead of the third element, a second element (Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, Pt) may be ion-implanted.

[0050] Subsequently, a third semiconductor layer 40, a fourth semiconductor layer 50, and a first electrode 62 are formed on the second semiconductor layer 30, and a second electrode 64 is formed on the semiconductor substrate 10, thereby forming the semiconductor device 1a.

[0051] (Modification 2) Figure 16 is a schematic cross-sectional view illustrating a semiconductor device according to another modification of the first embodiment. As shown in Figure 16, the semiconductor device 1b according to this modified example includes a second semiconductor layer 130 instead of the second semiconductor layer 30 shown in Figure 1. The other components of semiconductor device 1b are the same as those of semiconductor device 1, and the same components are denoted by the same reference numerals, and detailed explanations are omitted.

[0052] The second semiconductor layer 130 is provided on the first semiconductor layer 20. The third semiconductor layer 40 is provided on the second semiconductor layer 130. The second semiconductor layer 130 includes the first layer 32 and the second layer 34. The first layer 32 is provided on the first semiconductor layer 20. The second layer 34 is provided on the first layer 32. The third semiconductor layer 40 is provided on the second layer 34.

[0053] Both the first layer 32 and the second layer 34 are of the first conductivity type. The impurity concentration of the first layer 32 is the same as or higher than that of the second layer 34. The impurity concentration of the first layer 32 is the same as or higher than that of the first semiconductor layer 20. The impurity concentration of the second layer 34 is the same as or higher than that of the third semiconductor layer 40. The impurity concentration of the second layer 34 is the same as or lower than that of the first semiconductor layer 20.

[0054] The point defect density of the first layer 32 and the point defect density of the second layer 34 are approximately the same, and are the same as or higher than the point defect density of the first semiconductor layer 20.

[0055] A method for manufacturing the semiconductor device 1b according to this modified example will be described. Figures 17 to 19 are schematic cross-sectional views illustrating a part of a method for manufacturing a semiconductor device according to another modification of the first embodiment. As shown in Figure 17, a first intermediate semiconductor layer 20a is formed on the prepared semiconductor substrate 10. The first intermediate semiconductor layer 20a is formed to have a thickness equal to the thickness of the first semiconductor layer 20 plus the thickness of the first layer 32 of the second semiconductor layer 30.

[0056] As shown in Figure 18, the second intermediate semiconductor layer 44 is formed on the first intermediate semiconductor layer 20a by epitaxial growth.

[0057] As shown in Figure 19, a third element (proton, He, Ar, Ne, Xe) is introduced into the first intermediate semiconductor layer 20a and the second intermediate semiconductor layer 44 by ion implantation. The energy during ion implantation is set to correspond to the thickness of the second semiconductor layer 30, which is the thickness of the first intermediate semiconductor layer 20a and the second intermediate semiconductor layer 44.

[0058] Subsequently, a third semiconductor layer 40, a fourth semiconductor layer 50, and a first electrode 62 are formed on the second semiconductor layer 30, and a second electrode 64 is formed on the semiconductor substrate 10, thereby forming the semiconductor device 1a.

[0059] In this way, the modified semiconductor devices 1a and 1b are formed. The modified semiconductor devices 1a and 1b have the same effects as the semiconductor device 1 shown in Figure 1.

[0060] (Second embodiment) Figure 20 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. Figure 21 is a schematic cross-sectional view along line BB in Figure 20. As shown in Figures 20 and 21, the semiconductor device 201 according to this embodiment comprises a semiconductor substrate 10, a first semiconductor layer 20, a plurality of first semiconductor regions 230, and a sixth semiconductor layer 240. The semiconductor device 201 differs from the semiconductor device 1 shown in Figure 1 in the plurality of first semiconductor regions 230 and the sixth semiconductor layer 240, but is otherwise the same as the semiconductor device 1. The same reference numerals are used for identical components, and detailed descriptions are omitted as appropriate.

[0061] Multiple first semiconductor regions 230 are provided on the first semiconductor layer 20. Each of the multiple first semiconductor regions 230 extends in the direction of the Y axis on the first semiconductor layer 20. The multiple first semiconductor regions 230 are spaced apart in the direction of the X axis. In this example, each of the multiple first semiconductor regions 230 is spaced approximately equally in the direction of the X axis.

[0062] As explained in relation to Figure 1, the XY plane is parallel to the first surface 11a or the second surface 11b of the semiconductor substrate 10, and the [11-20] axis of the semiconductor substrate 10 is tilted with respect to the X axis by an off angle θoff around the Y axis. The

[0001] axis of the semiconductor substrate 10 is tilted with respect to the Z axis by an off angle θoff around the Y axis. The Y axis is parallel to the [1-100] axis which is perpendicular to the {1-100} plane of the semiconductor substrate 10. In other words, each of the multiple first semiconductor regions 230 extends along the [1-100] axis of the semiconductor substrate 10. Each of the multiple first semiconductor regions 230 is spaced approximately equally apart with respect to the [11-20] axis of the semiconductor substrate 10.

[0063] The sixth semiconductor layer 240 is provided on the first semiconductor layer 20. The sixth semiconductor layer 240 is also provided between two adjacent first semiconductor regions 230 among the multiple first semiconductor regions 230. The sixth semiconductor layer 240 is also provided on each of the multiple first semiconductor regions 230.

[0064] The semiconductor substrate 10, the first semiconductor layer 20, the plurality of first semiconductor regions 230, and the sixth semiconductor layer 240 contain impurities of a first conductivity type. The first conductivity type is, for example, n-type.

[0065] The first semiconductor region 230, like the second semiconductor layer 30 of the semiconductor device 1 shown in Figure 1, contains SiC and a first element as an impurity. The first element includes at least one selected from the group consisting of N, P, Al, and B. The first semiconductor region 230, like the semiconductor device 1, may also contain a second element in place of the first element, or together with the first element. The second element includes at least one selected from the group consisting of Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, and Pt.

[0066] The impurity concentrations in multiple first semiconductor regions 230 are the same as or lower than the impurity concentration in the first semiconductor layer 20. The impurity concentrations in multiple first semiconductor regions 230 are the same as or higher than the impurity concentration in the sixth semiconductor layer 240.

[0067] The point defect density of the multiple first semiconductor regions 230 is the same as or higher than the point defect density of the first semiconductor layer 20. The point defect density of the multiple first semiconductor regions 230 and the point defect density of the first semiconductor layer 20 are higher than the point defect density of the semiconductor substrate 10 and the point defect density of the sixth semiconductor layer 240.

[0068] Figure 22 is a schematic enlarged view of section C in Figure 20. Figure 22 shows the relationship between distances W1, W2, and thickness h1. Distance W1 represents the distance in the X-axis direction between two adjacent first semiconductor regions 230 among the multiple first semiconductor regions 230. Distance W1 represents the width of each of the multiple first semiconductor regions 230. Thickness h1 represents the thickness of each of the multiple first semiconductor regions 230.

[0069] In Figure 22, distance W1 is the distance between the lower edges 230B or upper edges 230T of two adjacent first semiconductor regions 230.

[0070] From the viewpoint of preventing the BPD from being extended to 1SSF, it is preferable for W1 to be small and W2 to be large. The semiconductor device 1 described in relation to Figure 1 is an example when W1=0. The first semiconductor region 230 has a recombination center due to a point defect, which promotes the recombination of holes and electrons. On the other hand, the first semiconductor region 230 is located in the current path, and depending on the impurity concentration of the first semiconductor region 230, the resistance value may increase, so it is preferable to make W2 small.

[0071] 1SSF expands along the {0001} plane of SiC tilted from the XY plane at an off-angle θoff. Therefore, from the viewpoint of suppressing the expansion of 1SSF in the first semiconductor region 230, it is preferable that the relationship between W1, W2, and h1 be set based on the off-angle θoff.

[0072] The relationship between W1 and h1 can be shown using the angle θ1. W1 can be expressed by the following equation (1).

[0073] W1 = h / tan(θ1) (1)

[0074] The relationship between θ1 in equation (1) and the off-angle θoff is set, for example, by the following equation (2).

[0075] 2θoff≧θ1≧0.5θoff (2)

[0076] In equation (2), the coefficient of θoff is appropriately set based on manufacturing variations during the formation of the first semiconductor region 230.

[0077] A method for manufacturing the semiconductor device 201 according to this embodiment will be described. Figures 23 and 24 are schematic cross-sectional views illustrating a part of the manufacturing method of a semiconductor device according to the second embodiment. As shown in Figure 2, a first semiconductor layer 20 is formed on the prepared semiconductor substrate 10 by epitaxial growth. As shown in Figure 23, an intermediate semiconductor layer 240a is formed on the first semiconductor layer 20. The intermediate semiconductor layer 240a is formed under the same conditions as, for example, the sixth semiconductor layer 240 shown in Figure 20. After the intermediate semiconductor layer 240a is formed, a mask M1 is formed on the intermediate semiconductor layer 240a. In the mask M1, an opening AP is provided at the position where the first semiconductor region 230 is formed. A second element (Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, Pt) or a third element (H, He, Ar, Ne, Xe) is introduced into the intermediate semiconductor layer 240a by ion implantation through the mask M1.

[0078] As shown in Figure 24, the mask M1 is removed. An intermediate semiconductor layer 240b is formed where the mask M1 was located, and a first semiconductor region 230 is formed where the opening AP of the mask M1 was located.

[0079] Subsequently, a semiconductor layer is formed on the first semiconductor region 230 and the intermediate semiconductor layer 240a by epitaxial growth to form the sixth semiconductor layer 240 shown in Figure 20.

[0080] The operation and effects of the semiconductor device 201 according to this embodiment will be described. Figure 25 is a schematic cross-sectional view illustrating the operation of a semiconductor device according to the second embodiment. Figure 26 is a schematic cross-sectional view of the DD line in Figure 25. Figure 25 shows the crystal axes of SiC along with the XYZ coordinate system. The relationships between the [11-20] axis, the [1-100] axis, and the

[0001] axis are the same as those explained in relation to Figure 9. The same applies to Figures 27, 28, and 39-42, which will be discussed later. Figure 26 is shown as a cross-sectional view taken along the

[0001] axis.

[0081] As shown in Figures 25 and 26, in the semiconductor device 201 according to this embodiment, the sixth semiconductor layer 240 has a portion that is provided on the first semiconductor layer 20. In this portion, BPDs generated in the first semiconductor layer and the semiconductor substrate 10 can obtain minority carrier recombination energy and expand into a defect S1 with a value of 1SSF. The defect S1 expands upward with an off angle θoff with respect to the XY plane, centered on the Y axis.

[0082] As shown in Figure 26, 1SSF extends in a triangular shape on a plane parallel to the {0001} plane of SiC, starting from the BPD. In the semiconductor device 201 according to this embodiment, the starting point of the defect S1 that has expanded into 1SSF is in the sixth semiconductor layer 240, and the sixth semiconductor layer 240 has few point defects that can serve as recombination centers. Furthermore, minority carriers are continuously injected into the sixth semiconductor layer 240, and minority carrier recombination also continues. Therefore, the defect S1 obtains recombination energy and extends within the sixth semiconductor layer 240 between two adjacent first semiconductor regions 230.

[0083] In the first semiconductor region 230, point defects that function as recombination centers formed by the first, second, or third element are densely formed. As a result, in the first semiconductor region 230, the lifetime of minority carriers is shortened, and the intrusion of minority carriers is suppressed, thereby reducing the generated recombination energy. When a defect S1 reaches the first semiconductor region 230, the defect S1 cannot receive the supply of recombination energy, and therefore its expansion stops.

[0084] In this way, a semiconductor device 201 with low conduction loss is realized.

[0085] Figure 27 is a schematic cross-sectional view illustrating the operation of a semiconductor device according to a comparative example. Figure 28 is a schematic cross-sectional view of the EE line shown in Figure 27. As shown in Figures 27 and 28, in the comparative example semiconductor device, the first semiconductor region 230 is not provided, and the sixth semiconductor layer 240c is provided on the first semiconductor layer 20.

[0086] In the comparative semiconductor device, minority carriers supplied to the sixth semiconductor layer 240c recombine in the sixth semiconductor layer 240c, continuously supplying recombination energy to a defect S2 with a value of 1SSF. As long as the defect S2 receives recombination energy, it continues to spread in a planar shape with a triangular outer perimeter. Since the planar defect S2 spreads along the {0001} plane of the SiC in the sixth semiconductor layer 240, the defect S2 is formed almost perpendicular to the current path. As a result, the conduction of current in the semiconductor device is inhibited, and the operating voltage increases.

[0087] Thus, in the semiconductor device 201 according to this embodiment, the expansion of 1SSF can be stopped by the first semiconductor region 230, thereby preventing an increase in losses when the semiconductor device 201 is conducting.

[0088] In semiconductor devices, forward conduction of a pn junction is achieved by the movement of minority carriers. The first semiconductor region 230 provides a high-density recombination center and can therefore hinder the movement of minority carriers. For this reason, by arranging multiple first semiconductor regions 230 at intervals, the expansion to a single supersemiconductor fiber (SSF) starting from the bipolar distribution (BPD) is restricted. In this way, while ensuring the movement of minority carriers, the formation of a single SSF is inhibited, and a semiconductor device with low conduction loss can be stably realized.

[0089] As shown in Figure 22, by appropriately setting the spacing and thickness of the multiple first semiconductor regions 230, a semiconductor device 201 that can reliably prevent the expansion of 1SSF can be realized.

[0090] (Variation 1) Figure 29 is a schematic cross-sectional view illustrating a semiconductor device according to a modified example of the second embodiment. As shown in Figure 29, the configuration of the multiple first semiconductor regions 230a and the sixth semiconductor layer 240d in the semiconductor device 201 shown in Figure 20 differs from that of the semiconductor device 201 shown in Figure 20. In other respects, the semiconductor device 201a in this modified example is the same as that of the semiconductor device 201, and the same reference numerals are used for the same components, and detailed explanations are omitted as appropriate.

[0091] Multiple first semiconductor regions 230a are provided on the first semiconductor layer 20. Similar to the multiple first semiconductor regions 230 of the semiconductor device 201 shown in Figures 20 and 21, the multiple first semiconductor regions 230a each extend along the Y axis. Also, similar to the multiple first semiconductor regions 230 of the semiconductor device 201, the multiple first semiconductor regions 230a are arranged apart from each other in the X axis direction.

[0092] The sixth semiconductor layer 240d is provided on the first semiconductor layer 20. The sixth semiconductor layer 240d is provided between the first semiconductor layer 20 and each of the multiple first semiconductor regions 230a. Similar to the case of the sixth semiconductor layer 240 of the semiconductor device 201, the sixth semiconductor layer 240d is provided between adjacent first semiconductor regions 230a. Similar to the case of the sixth semiconductor layer 240 of the semiconductor device 201, the sixth semiconductor layer 240d is provided on a plurality of first semiconductor regions 230a.

[0093] Each of the multiple first semiconductor regions 230a contains either a first element (N, P, Al, B) or a second element as an impurity. The impurity concentration of the multiple first semiconductor regions 230a is the same as or lower than the impurity concentration of the first semiconductor layer 20. The impurity concentration of the multiple first semiconductor regions 230a is the same as or higher than the impurity concentration of the sixth semiconductor layer 240d.

[0094] The point defect density of the multiple first semiconductor regions 230a is the same as or higher than the point defect density of the first semiconductor layer 20. The point defect density of the multiple first semiconductor regions 230a and the point defect density of the first semiconductor layer 20 are higher than the point defect density of the semiconductor substrate 10 and the point defect density of the sixth semiconductor layer 240d.

[0095] Figure 30 is a schematic enlarged view of section F in Figure 29. Figure 30 shows the relationship between distances W1, W2, and thickness h1 for two adjacent first semiconductor regions 230a, similar to the case shown in Figure 22. In Figure 30, thickness h2 represents the thickness of the sixth semiconductor layer 240d between the first semiconductor layer 20 and the lower edge 230aB of the first semiconductor region 230a. Distance W1 is the distance between the lower edges 230aB or the upper edges 230aT of two adjacent first semiconductor regions 230, similar to the example shown in Figure 22.

[0096] 1SSF expands along the {0001} plane of SiC tilted from the XY plane at an off-angle θoff. Therefore, from the viewpoint of suppressing the expansion of 1SSF in the first semiconductor region 230a, it is preferable that the relationship between W1, W2, and h1 be set based on the off-angle θoff. As is clear from Figure 30, in this example as well, the relationship between W1 and h1 in the example shown in Figure 22 can be expressed using the angle θ2. W1 is expressed by the following equation (3), and the range of the angle θ2 can be set by equation (4), taking into account manufacturing variations, etc.

[0097] W1 = h / tan(θ2) (3) 2θoff≧θ2≧0.5θoff (4)

[0098] A method for manufacturing the semiconductor device 201a according to this modified example will be described. Figures 31 and 32 are schematic cross-sectional views illustrating a part of a method for manufacturing a semiconductor device according to a modified example of the second embodiment. As shown in Figure 2, a first semiconductor layer 20 is formed on a prepared semiconductor substrate 10 by epitaxial growth. As shown in Figure 31, an intermediate semiconductor layer 240e is formed on the first semiconductor layer 20. The intermediate semiconductor layer 240e is formed under the same conditions as, for example, the sixth semiconductor layer 240 shown in Figure 20. After the intermediate semiconductor layer 240e is formed, a mask M2 is formed on the intermediate semiconductor layer 240e. In the mask M2, an opening AP is provided at the position where the first semiconductor region 230a is formed. A second element (Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, Pt) or a third element (H, He, Ar, Ne, Xe) is introduced into the intermediate semiconductor layer 240a by ion implantation through the mask M2. The ion implantation energy is set to be the thickness h2 between the bottom 230aB of the first semiconductor region 230a and the first semiconductor layer 20.

[0099] As shown in Figure 32, mask M1 is removed. An intermediate semiconductor layer 240f is formed where mask M1 was provided, and a first semiconductor region 230a is formed where the opening AP of mask M2 was provided.

[0100] Subsequently, a semiconductor layer is formed on the first semiconductor region 230a and the intermediate semiconductor layer 240f by epitaxial growth to form the sixth semiconductor layer 240d shown in Figure 29.

[0101] (Modification 2) Figure 33 is a schematic cross-sectional view illustrating a semiconductor device according to another modification of the second embodiment. As shown in Figure 33, the semiconductor device 201b according to this modification differs from the semiconductor device 201 shown in Figure 20 in the configuration of the first semiconductor layer 220, the multiple first semiconductor regions 230b, and the sixth semiconductor layer 240g. In other respects, the semiconductor device 201b according to this modification is the same as the semiconductor device 201, and the same reference numerals are used for the same components, and detailed explanations are omitted as appropriate.

[0102] The first semiconductor layer 220 is provided on the semiconductor substrate 10. Multiple first semiconductor regions 230b are provided on the first semiconductor layer 220. The first semiconductor layer 220 is also provided between adjacent first semiconductor regions 230b.

[0103] Similar to the multiple first semiconductor regions 230 of the semiconductor device 201 shown in Figures 20 and 21, the multiple first semiconductor regions 230b each extend along the Y-axis. Also, similar to the multiple first semiconductor regions 230 of the semiconductor device 201, the multiple first semiconductor regions 230b are spaced apart from each other in the X-axis direction.

[0104] The sixth semiconductor layer 240g is provided on the first semiconductor layer 220. Similar to the case of the sixth semiconductor layer 240 of semiconductor device 201, the sixth semiconductor layer 240g is provided between adjacent first semiconductor regions 230b. Similar to the case of the sixth semiconductor layer 240 of semiconductor device 201, the sixth semiconductor layer 240g is provided on multiple first semiconductor regions 230b.

[0105] The impurity concentration of the first semiconductor layer 220 is the same as that of the first semiconductor layer 20 of the semiconductor device 201 shown in Figure 20. In other words, the impurity concentration of the first semiconductor layer 220 is higher than that of the sixth semiconductor layer 240g.

[0106] Each of the multiple first semiconductor regions 230b contains either a first element (N, P, Al, B) or a second element (Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, Pt) as an impurity. The impurity concentration in the multiple first semiconductor regions 230b is the same as or lower than the impurity concentration in the first semiconductor layer 220. The impurity concentration in the multiple first semiconductor regions 230b is the same as or higher than the impurity concentration in the sixth semiconductor layer 240g.

[0107] The point defect density of the multiple first semiconductor regions 230b is the same as or higher than the point defect density of the first semiconductor layer 220. The point defect density of the multiple first semiconductor regions 230b and the point defect density of the first semiconductor layer 220 are higher than the point defect density of the semiconductor substrate 10 and the point defect density of the sixth semiconductor layer 240g. Figure 34 is a schematic enlarged view of section G in Figure 23. Figure 34 shows the relationship between distances W1, W2, and thickness h1 for two adjacent first semiconductor regions 230b, similar to the case shown in Figure 22. In Figure 34, thickness h1 is the length from the top edge 230bT of the first semiconductor region 230b to the bottom edge 230bB1 of the first semiconductor region 230b to the boundary line 230bB with the first semiconductor layer 220 on the side surface of the first semiconductor region 230b. Thickness h3 is the length from the bottom edge 230bB1 of the first semiconductor region 230b to the boundary line 230bB with the first semiconductor layer 220 on the side surface of the first semiconductor region 230b.

[0108] Similar to the semiconductor device 201 shown in Figure 20, from the viewpoint of suppressing the expansion of 1SSF in the first semiconductor region 230b, it is preferable that the relationship between W1, W2, and h1 be set based on the off-angle θoff. As is clear from Figure 34, in this example as well, the relationship between W1 and h1 in the example shown in Figure 22 can be expressed using the angle θ3. W1 is expressed by the following equation (5), and the range of the angle θ2 can be set by equation (6), taking into account manufacturing variations, etc.

[0109] W1 = h / tan(θ3) (5) 2θoff≧θ3≧0.5θoff (6)

[0110] A method for manufacturing the semiconductor device 201b according to this modified example will be described. Figures 35 and 36 are schematic cross-sectional views illustrating a part of a method for manufacturing a semiconductor device according to another modification of the second embodiment. As shown in Figure 35, a first semiconductor layer 220a is formed on the prepared semiconductor substrate 10 by epitaxial growth. An intermediate semiconductor layer 240h is formed on the first semiconductor layer 220a. The intermediate semiconductor layer 240h is formed under the same conditions as, for example, the sixth semiconductor layer shown in Figure 20. After the intermediate semiconductor layer 240h is formed, a mask M3 is formed on the intermediate semiconductor layer 240h. In the mask M3, an opening AP is provided at the position where the first semiconductor region 230b is formed. A second element (Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, Pt) or a third element (H, He, Ar, Ne, Xe) is introduced into the intermediate semiconductor layer 240h by ion implantation through the mask M3. At this time, the ion implantation energy is set to be deeper than the thickness of the intermediate semiconductor layer 240h by a thickness h3.

[0111] As shown in Figure 36, the mask M3 is removed. An intermediate semiconductor layer 240k is formed where the mask M3 was located, and a first semiconductor region 230b is formed where the opening AP of the mask M3 was located. The first semiconductor region 230b is formed within the intermediate semiconductor layer 240k. The first semiconductor region 230b penetrates the intermediate semiconductor layer 240k, and a portion of the first semiconductor region 230b is also formed within the first semiconductor layer 220b.

[0112] Subsequently, a semiconductor layer is formed on the first semiconductor region 230b and the intermediate semiconductor layer 240k by epitaxial growth to form the sixth semiconductor layer 240g shown in Figure 33.

[0113] In this way, the modified semiconductor devices 201a and 201b are formed. The modified semiconductor devices 201a and 201b have the same effects as the semiconductor device 201 shown in Figure 20.

[0114] (Third embodiment) Figure 37 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment. Figure 38 is a schematic cross-sectional view along the HH line in Figure 37. As shown in Figures 37 and 38, the semiconductor device 301 according to this embodiment comprises a semiconductor substrate 10, a first semiconductor layer 20, a plurality of first semiconductor regions 330a, a plurality of second semiconductor regions 330b, and a sixth semiconductor layer 340. The semiconductor device 301 differs from the semiconductor device 201 shown in Figure 20 in the configuration of the plurality of first semiconductor regions 330a, the plurality of second semiconductor regions 330b, and the sixth semiconductor layer 340, but is otherwise the same as the semiconductor device 201. The same reference numerals are used for identical components, and detailed descriptions are omitted as appropriate.

[0115] Multiple first semiconductor regions 330a are provided on the first semiconductor layer 20. Each of the multiple first semiconductor regions 330a extends in the direction of the Y axis on the first semiconductor layer 20. The multiple first semiconductor regions 330a are spaced apart in the direction of the X axis. In this example, each of the multiple first semiconductor regions 330a is spaced approximately equally apart in the direction of the X axis.

[0116] Multiple second semiconductor regions 330b are provided on the first semiconductor layer 20. Each of the multiple second semiconductor regions 330b extends in the direction of the X axis on the first semiconductor layer 20. The multiple second semiconductor regions 330b are spaced apart in the direction of the Y axis. In this example, each of the multiple second semiconductor regions 330b is spaced approximately equally in the direction of the Y axis. That is, the first semiconductor region 330a and the second semiconductor region 330b are arranged to intersect on the XY plane, forming a lattice shape.

[0117] As explained in relation to Figure 1, the XY plane is parallel to the first surface 11a or the second surface 11b of the semiconductor substrate 10, and the [11-20] axis of the semiconductor substrate 10 is tilted with respect to the X axis by an off angle θoff around the Y axis. The

[0001] axis of the semiconductor substrate 10 is tilted with respect to the Z axis by an off angle θoff around the Y axis. The Y axis is parallel to the [1-100] axis which is perpendicular to the {1-100} plane of the semiconductor substrate 10. In other words, each of the multiple first semiconductor regions 330a extends along the [1-100] axis of the semiconductor substrate 10. Each of the multiple first semiconductor regions 330a is arranged at approximately equal intervals with respect to the [11-20] axis of the semiconductor substrate 10. Also, each of the multiple second semiconductor regions 330b extends along the [11-20] axis of the semiconductor substrate 10. Each of the multiple second semiconductor regions 330b is arranged at approximately equal intervals with respect to the [1-100] axis of the semiconductor substrate 10.

[0118] The sixth semiconductor layer 340 is provided on the first semiconductor layer 20. The sixth semiconductor layer 340 is also provided on the first semiconductor layer 20 in the area surrounded by two adjacent and opposing first semiconductor regions 330a and two adjacent and opposing second semiconductor regions 330b. The sixth semiconductor layer 340 is provided on each of the multiple first semiconductor regions 330a and each of the multiple second semiconductor regions 330b.

[0119] The semiconductor substrate 10, the first semiconductor layer 20, the plurality of first semiconductor regions 330a, the plurality of second semiconductor regions 330b, and the sixth semiconductor layer 340 contain impurities of a first conductivity type. The first conductivity type is, for example, n-type.

[0120] The first semiconductor region 330a and the second semiconductor region 330b, like the second semiconductor layer 30 of the semiconductor device 1 shown in Figure 1, contain SiC and a first element as an impurity. The first element includes at least one selected from the group consisting of N, P, Al, and B. The second semiconductor region 330b, like the semiconductor device 1, may also contain a second element in place of or together with the first element. The second element includes at least one selected from the group consisting of Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, and Pt.

[0121] The impurity concentrations in multiple first semiconductor regions 330a and multiple second semiconductor regions 330b are the same. The impurity concentrations in the first semiconductor regions 330a and second semiconductor regions 330b are the same as or lower than the impurity concentration in the first semiconductor layer 20. The impurity concentrations in the first semiconductor regions 330a and second semiconductor regions 330b are the same as or higher than the impurity concentration in the sixth semiconductor layer 340.

[0122] The point defect densities of the multiple first semiconductor regions 330a and the multiple second semiconductor regions 330b are the same. The point defect densities of the first semiconductor regions 330a and the second semiconductor regions 330b are the same as or higher than the point defect density of the first semiconductor layer 20. The point defect densities of the first semiconductor region 330a, the second semiconductor region 330b, and the first semiconductor layer 20 are higher than the point defect density of the semiconductor substrate 10 and the point defect density of the sixth semiconductor layer 340.

[0123] The relationship between the distance between adjacent first semiconductor regions 330a and the thickness of the first semiconductor region 330a can be the same as in the example shown in Figure 22, from the viewpoint of preventing the expansion of 1SSF.

[0124] The semiconductor device 301 according to this embodiment can be manufactured in the same manner as the semiconductor device 201 shown in Figure 20. That is, the first semiconductor region 330a and the second semiconductor region 330b can be formed by positioning the aperture AP of the mask M1 shown in Figure 23 to correspond to the first semiconductor region 330a and the second semiconductor region 330b that intersect in a grid pattern.

[0125] The operation of the semiconductor device 301 according to this embodiment will be described. Figure 39 is a schematic cross-sectional view illustrating the operation of a semiconductor device according to the third embodiment. Figure 40 is a schematic cross-sectional view along line II in Figure 39. As shown in Figures 39 and 40, in the semiconductor device 301 according to this embodiment, the sixth semiconductor layer 340 has a portion that is provided on the first semiconductor layer 20. In this portion, BPDs generated in the first semiconductor layer and the semiconductor substrate 10 can obtain minority carrier recombination energy and expand into a defect S3 with a value of 1SSF. The defect S3 expands upward with an off angle θoff with respect to the XY plane, centered on the Y axis.

[0126] In addition to the triangular expansion of 1SSF shown in Figures 26 and 28, a bar-shaped expansion of 1SSF is also known. Bar-shaped defects S3 expand along the {0001} plane of SiC in both the [1-100] axis direction and the

[1100] axis direction. Therefore, in the semiconductor region 230 of the semiconductor device 201 shown in Figure 20, even if expansion in the [11-20] axis direction can be prevented, expansion of 1SSF in the [1-100] axis direction and the

[1100] axis direction may not be prevented. In the semiconductor device 301 according to this embodiment, the first semiconductor region 330a and the second semiconductor region 330b are intersected to prevent the expansion of bar-shaped defects in the first semiconductor region 330a and the second semiconductor region 330b.

[0127] Figure 41 is a schematic cross-sectional view illustrating the operation of a semiconductor device related to a comparative example. Figure 42 is a schematic cross-sectional view of the JJ line in Figure 41. The configuration of the semiconductor device in the comparative example shown in Figures 41 and 42 is the same as the configuration of the semiconductor device shown in Figures 27 and 28. That is, as shown in Figures 41 and 42, the semiconductor device in the comparative example does not have a first semiconductor region 330a and a second semiconductor region 330b, and a sixth semiconductor layer 240c is provided on the first semiconductor layer 20.

[0128] In the comparative semiconductor device, minority carriers supplied to the sixth semiconductor layer 240c recombine in the sixth semiconductor layer 240c and continue to supply recombination energy to a defect S4 with a value of 1SSF. As long as the defect S4 receives recombination energy, it continues to spread within the third semiconductor layer 40 in a planar shape with a triangular outer periphery, and can reach the interface with the fourth semiconductor layer 50. Since the planar defect S4 spreads along the {0001} plane of the SiC of the sixth semiconductor layer 240c, the defect S4 is formed almost perpendicular to the current path. As a result, the conduction of the semiconductor device is inhibited and the operating voltage increases.

[0129] Thus, in the semiconductor device 301 according to this embodiment, the intersecting first semiconductor region 330a and second semiconductor region 330b in a grid pattern prevent the expansion of any form of 1SSF, thereby preventing an increase in losses when the semiconductor device 301 is conductive.

[0130] In the semiconductor device 301 according to this embodiment, modifications of the second embodiment described in relation to Figures 29 and 33 can be applied to the first semiconductor region and the second semiconductor region, and similar effects can be obtained.

[0131] In the embodiments and modifications described above, the semiconductor device was described as primarily a PiN diode. However, the semiconductor device is not limited to a PiN diode as long as it has a PiN structure in which a semiconductor layer of a second conductivity type is bonded to a semiconductor layer of a first conductivity type with a low impurity concentration. For example, a MOSFET with a DMOS structure may be used as the semiconductor device in each embodiment and modification.

[0132] In this way, a semiconductor device with stable characteristics can be realized.

[0133] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other.

[0134] The embodiments include the following aspects:

[0135] (Note 1) A semiconductor substrate of a first conductivity type containing silicon carbide, having a first surface and a second surface located opposite the first surface, A first semiconductor layer of a first conductivity type containing silicon carbide is provided on the first surface, A second semiconductor layer having a first conductivity type and containing silicon carbide is provided on the first semiconductor layer, A third semiconductor layer of first conductivity type containing silicon carbide is provided on the second semiconductor layer, A fourth semiconductor layer of second conductivity type containing silicon carbide is provided on the third semiconductor layer, Equipped with, The carrier concentration of the first conductivity type in the second semiconductor layer is the same as or lower than the carrier concentration of the first conductivity type in the first semiconductor layer. The carrier concentration of the first conductivity type in the second semiconductor layer is the same as or higher than the carrier concentration of the first conductivity type in the third semiconductor layer. A semiconductor device in which the point defect density of the second semiconductor layer is the same as or higher than the point defect density of the first semiconductor layer, and higher than the point defect density of the third semiconductor layer.

[0136] (Note 2) The present invention further comprises a fifth semiconductor layer of a first conductivity type containing silicon carbide, provided between the first semiconductor layer and the second semiconductor layer. The carrier concentration of the first conductivity type in the second semiconductor layer is the same as or higher than the carrier concentration of the first conductivity type in the fifth semiconductor layer. The semiconductor device according to Appendix 1, wherein the point defect density of the second semiconductor layer is higher than the point defect density of the fifth semiconductor layer.

[0137] (Note 3) The second semiconductor layer includes a first layer provided on the first semiconductor layer and a second layer provided on the first layer. The carrier concentration of the first conductivity type in the first layer is the same as or lower than the carrier concentration of the first conductivity type in the first semiconductor layer. The carrier concentration of the first conductivity type in the second layer is the same as or lower than the carrier concentration of the first conductivity type in the first layer, and the carrier concentration of the first conductivity type in the third semiconductor layer is the same as or higher. The point defect density of the first layer and the point defect density of the second layer are the same as or higher than the point defect density of the first semiconductor layer. The semiconductor device according to Appendix 1 or 2, wherein the point defect density is higher than that of the third semiconductor layer.

[0138] (Note 4) A semiconductor substrate of a first conductivity type containing silicon carbide, having a first surface and a second surface located opposite the first surface, A first semiconductor layer of a first conductivity type containing silicon carbide is provided on the first surface, A plurality of first semiconductor regions of a first conductivity type containing silicon carbide are provided on the first semiconductor layer, A sixth semiconductor layer of first conductivity type containing silicon carbide is provided on the first semiconductor layer, A fourth semiconductor layer of second conductivity type containing silicon carbide is provided on the sixth semiconductor layer, Equipped with, The first surface is parallel to a plane that includes a first direction and a second direction intersecting the first direction. The plurality of first semiconductor regions each extend along the first direction and are provided at intervals along the second direction. The {0001} plane of silicon carbide forms a first angle with the first plane, with respect to the [1-100] axis which is perpendicular to the {1-100} plane of silicon carbide. The second direction is parallel to the direction in which the [1-100] axis extends, The carrier concentration of the first conductivity type in the plurality of first semiconductor regions is the same as or lower than the carrier concentration of the first conductivity type in the first semiconductor layer. The carrier concentrations of the first conductivity type in the plurality of first semiconductor regions are the same as or higher than the carrier concentration of the first conductivity type in the sixth semiconductor layer. A semiconductor device in which the point defect density of the plurality of first semiconductor regions is the same as or higher than the point defect density of the first semiconductor layer, and higher than the point defect density of the sixth semiconductor layer.

[0139] (Note 5) The semiconductor device described in Appendix 4, wherein the sixth semiconductor layer is provided on the first semiconductor layer and between the first semiconductor layer and each of the plurality of first semiconductor regions.

[0140] (Note 6) The semiconductor device described in Appendix 4 or 5, wherein the first semiconductor layer is provided between two adjacent first semiconductor regions among the plurality of first semiconductor regions.

[0141] (Note 7) The first semiconductor layer is provided with a plurality of second semiconductor regions of a first conductivity type containing silicon carbide, The plurality of second semiconductor regions each extend along the second direction and are provided at intervals along the first direction. The sixth semiconductor layer is surrounded on the first semiconductor layer by two first semiconductor regions from the plurality of first semiconductor regions and two second semiconductor regions from the plurality of second semiconductor regions. The carrier concentrations of the first conductivity type in the plurality of second semiconductor regions are the same as or lower than the carrier concentration of the first conductivity type in the first semiconductor layer. The carrier concentrations of the first conductivity type in the plurality of second semiconductor regions are the same as or higher than the carrier concentration of the first conductivity type in the sixth semiconductor layer. The point defect density of the plurality of second semiconductor regions is the same as or higher than the point defect density of the first semiconductor layer, and The semiconductor device described in Appendix 4, wherein the point defect density is higher than that of the sixth semiconductor layer.

[0142] (Note 8) The distance between two adjacent first semiconductor regions among the plurality of first semiconductor regions is set based on the thickness of the plurality of first semiconductor regions and the first angle, according to any one of the appendices 4 to 7 of the semiconductor device.

[0143] (Note 9) The carriers of the first conductivity type in the second semiconductor layer include the first element, The semiconductor device according to any one of the appendices 1 to 3, wherein the first element comprises at least one selected from the group consisting of N, P, Al, and B.

[0144] (Note 10) The aforementioned second semiconductor layer contains the second element, The semiconductor device according to any one of the appendices 1 to 3, wherein the second element is at least one selected from the group consisting of Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, and Pt. [Explanation of Symbols]

[0145] 1, 1a, 1b, 201, 201a, 201b, 301... Semiconductor equipment, 10… Semiconductor substrates, 20, 220, 220a... First semiconductor layer, 30, 130... Second semiconductor layer, 32...first layer, 34...Second layer, 40...Third semiconductor layer, 42...Fifth semiconductor layer, 50...Fourth semiconductor layer, 62...first electrode, 64...second electrode, 230, 230a, 230b, 330a... First semiconductor region, 240, 240d, 240g, 340...6th semiconductor layer, 330b...Second Semiconductor Region

Claims

1. A semiconductor substrate of a first conductivity type containing silicon carbide, having a first surface and a second surface located opposite the first surface, A first semiconductor layer of a first conductivity type containing silicon carbide is provided on the first surface, A second semiconductor layer having a first conductivity type and containing silicon carbide is provided on the first semiconductor layer, A third semiconductor layer of first conductivity type containing silicon carbide is provided on the second semiconductor layer, A fourth semiconductor layer of second conductivity type containing silicon carbide is provided on the third semiconductor layer, A fifth semiconductor layer of first conductivity type containing silicon carbide is provided between the first semiconductor layer and the second semiconductor layer, Equipped with, The carrier concentration of the first conductivity type in the second semiconductor layer is lower than the carrier concentration of the first conductivity type in the first semiconductor layer. The carrier concentration of the first conductivity type in the second semiconductor layer is higher than the carrier concentration of the first conductivity type in the third semiconductor layer and the carrier concentration of the first conductivity type in the fifth semiconductor layer. A semiconductor device in which the point defect density of the second semiconductor layer is the same as or higher than the point defect density of the first semiconductor layer, and higher than the point defect density of the third semiconductor layer and the point defect density of the fifth semiconductor layer.

2. A semiconductor substrate of a first conductivity type having a first surface and a second surface located opposite to the first surface, and containing silicon carbide, A first semiconductor layer of a first conductivity type containing silicon carbide is provided on the first surface, A second semiconductor layer having a first conductivity type and containing silicon carbide is provided on the first semiconductor layer, A third semiconductor layer of first conductivity type containing silicon carbide is provided on the second semiconductor layer, A fourth semiconductor layer of second conductivity type containing silicon carbide is provided on the third semiconductor layer, Equipped with, The carrier concentration of the first conductivity type in the second semiconductor layer is lower than the carrier concentration of the first conductivity type in the first semiconductor layer. The carrier concentration of the first conductivity type in the second semiconductor layer is higher than the carrier concentration of the first conductivity type in the third semiconductor layer. The point defect density of the second semiconductor layer is the same as or higher than the point defect density of the first semiconductor layer, and higher than the point defect density of the third semiconductor layer. The second semiconductor layer includes a first layer provided on the first semiconductor layer and a second layer provided on the first layer. The carrier concentration of the first conductivity type in the first layer is lower than the carrier concentration of the first conductivity type in the first semiconductor layer. The carrier concentration of the first conductivity type in the second layer is lower than the carrier concentration of the first conductivity type in the first layer, and higher than the carrier concentration of the first conductivity type in the third semiconductor layer. The point defect density of the first layer and the point defect density of the second layer are the same as or higher than the point defect density of the first semiconductor layer. A semiconductor device having a point defect density higher than that of the third semiconductor layer.

3. A semiconductor substrate of a first conductivity type containing silicon carbide, having a first surface and a second surface located opposite the first surface, A first semiconductor layer of a first conductivity type containing silicon carbide is provided on the first surface, A plurality of first semiconductor regions of a first conductivity type containing silicon carbide are provided on the first semiconductor layer, A sixth semiconductor layer of first conductivity type containing silicon carbide is provided on the first semiconductor layer, A fourth semiconductor layer of second conductivity type containing silicon carbide is provided on the sixth semiconductor layer, Equipped with, The first surface is parallel to a plane that includes a first direction and a second direction intersecting the first direction, The plurality of first semiconductor regions each extend along the first direction and are provided at intervals along the second direction. The {0001} plane of silicon carbide forms a first angle with the first plane, with respect to the [1-100] axis which is perpendicular to the {1-100} plane of silicon carbide. The first direction is parallel to the direction in which the [1-100] axis extends, The carrier concentration of the first conductivity type in the plurality of first semiconductor regions is lower than the carrier concentration of the first conductivity type in the first semiconductor layer. The carrier concentration of the first conductivity type in the plurality of first semiconductor regions is higher than the carrier concentration of the first conductivity type in the sixth semiconductor layer. A semiconductor device in which the point defect density of the plurality of first semiconductor regions is the same as or higher than the point defect density of the first semiconductor layer, and higher than the point defect density of the sixth semiconductor layer.

4. The semiconductor device according to claim 3, wherein the sixth semiconductor layer is provided on the first semiconductor layer and between the first semiconductor layer and each of the plurality of first semiconductor regions.

5. The semiconductor device according to claim 3, wherein the first semiconductor layer is provided between two adjacent first semiconductor regions among the plurality of first semiconductor regions.

6. The first semiconductor layer is provided with a plurality of second semiconductor regions of a first conductivity type containing silicon carbide, The plurality of second semiconductor regions each extend along the second direction and are spaced apart along the first direction. The sixth semiconductor layer is surrounded on the first semiconductor layer by two first semiconductor regions from the plurality of first semiconductor regions and two second semiconductor regions from the plurality of second semiconductor regions. The carrier concentration of the first conductivity type in the plurality of second semiconductor regions is lower than the carrier concentration of the first conductivity type in the first semiconductor layer. The carrier concentration of the first conductivity type in the plurality of second semiconductor regions is higher than the carrier concentration of the first conductivity type in the sixth semiconductor layer. The point defect density of the plurality of second semiconductor regions is the same as or higher than the point defect density of the first semiconductor layer, and The semiconductor device according to claim 3, wherein the point defect density is higher than that of the sixth semiconductor layer.

7. The semiconductor device according to claim 3, wherein the distance between two adjacent first semiconductor regions among the plurality of first semiconductor regions is set based on the thickness of the plurality of first semiconductor regions and the first angle.

8. The carriers of the first conductivity type in the second semiconductor layer include the first element, The semiconductor device according to claim 1 or 2, wherein the first element comprises at least one selected from the group consisting of N, P, Al, and B.

9. The second semiconductor layer contains the second element, The semiconductor device according to claim 1 or 2, wherein the second element comprises at least one selected from the group consisting of Fe, Ni, Cr, Mg, Zn, Cu, Ca, V, Au, and Pt.

Images