Semiconductor equipment

Abstract

To provide a semiconductor device capable of improving heat dissipation in a portion close to a surface electrode.SOLUTION: A wiring member 50 has a bonded surface 55 in contact with a bonding member 60. In a plan view along a direction perpendicular to a surface electrode 10, the bonded surface 55 covers at least a part of each of a plurality of diode regions 2. The plurality of diode regions 2 have a first diode region 21, a second diode region 22, and a third diode region 23. In the plan view, the second diode region 22 is located in a first direction 101 with respect to the first diode region 21 and is spaced apart from the first diode region 21. In the plan view, the third diode region 23 is located in a second direction 102 perpendicular to the first direction 101 with respect to the first diode region 21 and is spaced apart from each of the first diode region 21 and the second diode region 22.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Semiconductor elements such as insulated gate bipolar transistors (IGBTs) and reverse conducting-insulated gate bipolar transistors (RC-IGBTs) generate heat when energized, at the start of energization, and at the end of energization. This heat generation may shorten the service life of the semiconductor device on which the semiconductor element is mounted, thereby reducing the reliability of the semiconductor device. Accordingly, there is a need for a technique for dissipating the heat generated by the heat generation of the semiconductor element.

[0003] As an example of a semiconductor device, Japanese Unexamined Patent Publication No. 2022-158037 (Patent Document 1) describes a semiconductor device having an RC-IGBT chip disposed on a copper circuit pattern. In this semiconductor device, a wire is bonded to a surface electrode (emitter electrode) of the RC-IGBT, and the wire is used as an external wiring.

Prior Art Literature

Patent Literature

[0004]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0005] When an RC-IGBT is short-circuited, the IGBT region of the RC-IGBT generates heat. In particular, heat is generated in the portion of the IGBT region close to the surface electrodes. According to the semiconductor device described in Patent Document 1, the surface of the RC-IGBT is electrically connected to the outside using wires. Therefore, the heat generated in the portion of the RC-IGBT chip close to the surface electrodes is not sufficiently dissipated. This disclosure has been made in view of the above, and its purpose is to provide a semiconductor device that can improve heat dissipation in the portion close to the surface electrodes. [Means for solving the problem]

[0006] The semiconductor device according to this disclosure comprises an insulated-gate bipolar transistor region, a plurality of diode regions, a surface electrode, a bonding member, and a wiring member. The plurality of diode regions are in contact with the insulated-gate bipolar transistor region. The surface electrode is in contact with the insulated-gate bipolar transistor region and the plurality of diode regions. The bonding member is provided on the surface electrode. The wiring member is bonded to the surface electrode by the bonding member. The insulated-gate bipolar transistor region and the plurality of diode regions constitute a reverse-conducting insulated-gate bipolar transistor. The wiring member has a bonded surface that is in contact with the bonding member. In a plan view along a direction perpendicular to the surface electrode, the bonded surface covers at least a portion of each of the plurality of diode regions. The plurality of diode regions include a first diode region, a second diode region, and a third diode region. In a plan view, the second diode region is located in a first direction relative to the first diode region and is spaced apart from the first diode region. In a plan view, the third diode region is located in a second direction perpendicular to the first direction relative to the first diode region, and is spaced apart from both the first and second diode regions. [Effects of the Invention]

[0007] In the semiconductor device described herein, the second diode region is located in a first direction relative to the first diode region, and the third diode region is located in a second direction relative to the first diode region. Therefore, heat can be transferred from the insulated gate bipolar region to multiple diode regions, and heat can be easily dissipated using wiring members. This makes it possible to provide a semiconductor device that can improve heat dissipation in the portion close to the surface electrodes. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic plan view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 2] This is a schematic cross-sectional view along line II-II in Figure 1. [Figure 3] This is a schematic planar diagram showing the configuration of a semiconductor device. [Figure 4] This is a schematic cross-sectional diagram showing the configuration of a semiconductor device. [Figure 5] This is a schematic plan view showing the configuration of a semiconductor device according to a first modified example of Embodiment 1. [Figure 6] This is a schematic plan view showing the configuration of a semiconductor element according to a second modified example of Embodiment 1. [Figure 7] This is a schematic plan view showing the configuration of a semiconductor device according to a third modified example of Embodiment 1. [Figure 8] This is a schematic plan view showing the configuration of the semiconductor device according to Embodiment 2. [Figure 9] Figure 8 is a schematic cross-sectional view along the line IX-IX. [Figure 10] This is a schematic plan view showing the configuration of a semiconductor device according to Embodiment 3. [Figure 11] This is a schematic plan view showing the configuration of a semiconductor device according to Embodiment 3. [Figure 12] This is a schematic cross-sectional view along the line XII-XII in Figure 11. [Figure 13] This is a schematic plan view showing the configuration of the semiconductor device according to Embodiment 4. [Figure 14]It is a schematic plan view showing the configuration of the semiconductor device according to Embodiment 5. [Figure 15] It is a schematic cross-sectional view showing the configuration of the semiconductor device according to Embodiment 6. [Figure 16] It is a schematic cross-sectional view showing the configuration of the semiconductor device according to a modification of Embodiment 6. [Figure 17] It is a schematic cross-sectional view showing the configuration of the semiconductor device according to Embodiment 7. [Figure 18] It is a schematic plan view showing the configuration of the semiconductor device according to Embodiment 8. [Figure 19] It is a schematic cross-sectional view taken along line XIX-XIX in FIG. 18. [Figure 20] It is a schematic cross-sectional view showing the configuration of the semiconductor device according to Embodiment 9. DETAILED DESCRIPTION OF EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding portions are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0010] Embodiment 1.

[0011] <Configuration of Semiconductor Device>

[0012] First, the configuration of the semiconductor device 100 according to Embodiment 1 will be described with reference to FIGS. 1 and 2. For convenience of description, a plurality of diode regions 2 described later are shown by broken lines in FIG. 1.

[0013] As shown in FIGS. 1 and 2, the semiconductor device 100 according to Embodiment 1 mainly includes a semiconductor element 30, a bonding member 60, and a wiring member 50. The bonding member 60 bonds the semiconductor element 30 and the wiring member 50. The wiring member 50 electrically connects the semiconductor element 30 and an external device (not shown).

[0014] As shown in Figures 2 and 3, the semiconductor device 30 has a surface electrode 10, a back electrode 11, an insulated gate bipolar transistor region 1, a plurality of diode regions 2, and a termination region 4. In the following, the insulated gate bipolar transistor region 1 will also be referred to as the IGBT region 1.

[0015] As shown in Figure 2, the semiconductor device 30 has a first surface 71 and a second surface 72. The second surface 72 is on the opposite side of the first surface 71. The direction from the first surface 71 to the second surface 72 is called the third direction 103. The third direction 103 is perpendicular to the surface electrode 10. The surface electrode 10 is provided on the first surface 71. The surface electrode 10 is the emitter electrode. The back surface electrode 11 is provided on the second surface 72. The back surface electrode 11 is the collector electrode.

[0016] The IGBT region 1 and the multiple diode regions 2 constitute the first surface 71 and the second surface 72. The IGBT region 1 is in contact with each of the surface electrode 10 and the back electrode 11. The IGBT region 1 is electrically connected to each of the surface electrode 10 and the back electrode 11.

[0017] As shown in Figure 2, each of the multiple diode regions 2 is in contact with the IGBT region 1. Each of the multiple diode regions 2 is in contact with each of the surface electrode 10 and the back electrode 11. Each of the multiple diode regions 2 is electrically connected to each of the surface electrode 10 and the back electrode 11.

[0018] Each of the multiple diode regions 2 is spaced apart from one another. When viewed along a direction perpendicular to the surface electrode 10 (hereinafter also referred to as a plan view), the shape of each of the multiple diode regions 2 is, for example, rectangular.

[0019] The termination region 4 is in contact with the IGBT region 1. The termination region 4 surrounds the IGBT region 1 and multiple diode regions 2. The termination region 4 constitutes part of the second surface 72. The detailed configuration of the termination region 4 will be described later.

[0020] As shown in Figure 2, the bonding member 60 is provided on the surface electrode 10. The bonding member 60 is, for example, solder. In plan view, the bonding member 60 is surrounded by the termination region 4. The bonding member 60 transfers heat from the surface electrode 10 to the wiring member 50.

[0021] The wiring member 50 is metallically bonded to the surface electrode 10 by the bonding member 60. Specifically, the wiring member 50 is electrically connected to the surface electrode 10 by the bonding member 60. The wiring member 50 is made of metal.

[0022] As shown in Figures 1 and 2, the wiring member 50 has a flat plate portion 49 and a conductive plate portion 51. The wiring member 50 is a DLB (Direct Lead Bonding) electrode. In plan view, the shape of the flat plate portion 49 is rectangular. The flat plate portion 49 is in contact with the bonding member 60. In the third direction 103, the bonding member 60 is provided between the flat plate portion 49 and the surface electrode 10. The flat plate portion 49 may be spaced apart from the surface electrode 10. In plan view, the flat plate portion 49 is surrounded by a terminal region 4.

[0023] As shown in Figures 1 and 2, the plate portion 49 has a first end 81 and a second end 82. The first end 81 extends, for example, along the direction in which the long sides of the plurality of diode regions 2 extend. In the plate portion 49, the second end 82 is provided on the opposite side of the first end 81. The direction in which the second end 82 extends may be substantially parallel to the direction in which the first end 81 extends, for example.

[0024] As shown in Figure 2, the flat plate portion 49 has a surface to be joined 55 and a surface 56. The surface to be joined 55 is the surface of the flat plate portion 49 that is in contact with the joining member 60. In other words, at the surface to be joined 55, the flat plate portion 49 is in contact with the joining member 60. The surface to be joined 55 is, for example, planar. The surface 56 is opposite to the surface to be joined 55. From another point of view, the surface 56 is provided in a direction opposite to the third direction 103 with respect to the surface to be joined 55.

[0025] As shown in Figure 1, in a plan view, the flat plate portion 49 covers at least a portion of each of the multiple diode regions 2. From another viewpoint, in a plan view, the bonded surface 55 (see Figure 2) covers at least a portion of each of the multiple diode regions 2.

[0026] As shown in Figures 1 and 2, the conductive plate portion 51 is connected to the flat plate portion 49. Specifically, for example at the first end portion 81, the conductive plate portion 51 is connected to the flat plate portion 49. The conductive plate portion 51 is provided, for example, in a direction opposite to the third direction 103 relative to the flat plate portion 49. The conductive plate portion 51 is spaced apart from the joining member 60. The interface between the conductive plate portion 51 and the flat plate portion 49 is a connecting portion 59. In other words, the conductive plate portion 51 and the flat plate portion 49 are connected at the connecting portion 59. The conductive plate portion 51 constitutes a path for the current flowing between the surface electrode 10 and an external device (not shown).

[0027] The direction in which the conductive plate portion 51 extends is substantially parallel to the direction in which the long sides of the multiple diode regions 2 extend. From another perspective, the connection portion 59 extends along the direction in which the long side of each of the multiple diode regions 2 extends.

[0028] <Configuration of semiconductor elements>

[0029] Next, the configuration of the semiconductor device 30 will be explained using Figures 3 and 4. For the sake of explanation, the surface electrode 10 is not shown in Figure 3. The cross-section shown in Figure 4 is a cross-section perpendicular to the surface electrode 10.

[0030] As shown in Figure 3, the semiconductor element 30 is an island-type RC-IGBT. Specifically, multiple diode regions 2 are arranged in an island-like configuration. From another perspective, in a plan view, two or more diode regions 2 are arranged side by side along the first direction 101 and the second direction 102 within a region that overlaps with one surface electrode 10.

[0031] The multiple diode regions 2 include a first diode region 21, a second diode region 22, and a third diode region 23. The first diode region 21 is, for example, a diode region 2 located at a corner among the multiple diode regions 2. The second diode region 22 is spaced apart from the first diode region 21. In a plan view, the direction from the first diode region 21 to the second diode region 22 is defined as the first direction 101. From another point of view, in a plan view, the second diode region 22 is located in the first direction 101 relative to the first diode region 21.

[0032] The third diode region 23 is spaced apart from both the first diode region 21 and the second diode region 22. In a plan view, the direction from the first diode region 21 towards the third diode region 23 is the second direction 102. From another point of view, the third diode region 23 is located in the second direction 102 relative to the first diode region 21. The second direction 102 is perpendicular to the first direction 101. The longer side of each of the multiple diode regions 2 may be, for example, parallel to the second direction 102.

[0033] As shown in Figure 3, the multiple diode regions 2 have multiple rows 20. Each of the multiple rows 20 consists of multiple diode regions 2 arranged along the second direction 102. The number of diode regions 2 in a single row 20 is not particularly limited, but for example, there are four. In a row 20, for example, four diode regions 2 may be arranged at substantially equal intervals along the second direction 102. Multiple rows 20 are arranged along the first direction 101. Multiple rows 20 may be arranged at equal intervals along the first direction 101, for example. The number of rows 20 is not particularly limited, but for example, there are eight.

[0034] Each of the multiple diode regions 2 is surrounded by an IGBT region 1. From another perspective, the IGBT region 1 has a portion sandwiched between two diode regions 2 in the first direction 101. The IGBT region 1 also has a portion sandwiched between two diode regions 2 in the second direction 102.

[0035] In a plan view, the shape of the semiconductor element 30 is, for example, rectangular. In a plan view, the direction in which the longer side of the semiconductor element 30 extends is the first direction 101. In a plan view, the direction in which the shorter side of the semiconductor element 30 extends is the second direction 102.

[0036] As shown in Figure 4, the semiconductor element 30 has a semiconductor substrate 70. The configuration of the diode region 2 will now be described. The semiconductor substrate 70 has, for example, an n-type drift layer 43, an n+-type carrier store layer 32, a p-type base layer 35, a p-type anode layer 28, an n-type buffer layer 37, and an n+-type cathode layer 29.

[0037] The n+ type carrier store layer 32 is provided on the n- type drift layer 43. The n+ type carrier store layer 32 has a higher concentration of n-type impurities than the n- type drift layer 43. The p-type base layer 35 is provided on the n+ type carrier store layer 32.

[0038] The p-type anode layer 28 is provided on the p-type base layer 35. The p-type anode layer 28 is provided in the diode region 2. The p-type impurity concentration of the p-type anode layer 28 is higher than that of the p-type impurity concentration of the p-type base layer 35. The p-type anode layer 28 constitutes a part of the first surface 71 (see Figure 2).

[0039] The n-type buffer layer 37 is provided in a third direction 103 relative to the n-type drift layer 43. The n-type buffer layer 37 is in contact with the n-type drift layer 43. The n-type buffer layer 37 has a higher concentration of n-type impurities than the n-type drift layer 43.

[0040] The n+ type cathode layer 29 is provided in a third direction 103 relative to the n type buffer layer 37. The n+ type cathode layer 29 is in contact with the n type buffer layer 37. The n+ type cathode layer 29 is provided in the diode region 2. The n+ type cathode layer 29 is electrically connected to the back electrode 11. The n+ type cathode layer 29 constitutes a part of the second surface 72 (see Figure 2).

[0041] A first trench gate 31a is provided in the semiconductor substrate 70 in the diode region 2. The first trench gate 31a extends from the first surface 71 along the third direction 103. The first trench gate 31a reaches the n-type drift layer 43. The first trench gate 31a is electrically connected to the surface electrode 10.

[0042] Next, the configuration of IGBT region 1 will be described. The semiconductor substrate 70 has an n+ type source layer 33, a p+ type contact layer 38, and a p-type collector layer 36. The n+ type source layer 33 is provided on a p-type base layer 35. The n+ type source layer 33 is provided in IGBT region 1. The n+ type source layer 33 constitutes a part of the first surface 71 (see Figure 2).

[0043] The p+ type contact layer 38 is provided on the p-type base layer 35. The p+ type contact layer 38 is provided in the IGBT region 1 and the termination region 4. The p+ type contact layer 38 is spaced apart from the n+ type source layer 33. The p-type impurity concentration of the p+ type contact layer 38 is higher than the p-type impurity concentration of the p-type base layer 35. The p-type impurity concentration of the p+ type contact layer 38 may be the same as the p-type impurity concentration of the p-type anode layer 28.

[0044] The p-type collector layer 36 is provided in a third direction 103 relative to the n-type buffer layer 37. The p-type collector layer 36 is in contact with the n-type buffer layer 37. The p-type collector layer 36 is provided in the IGBT region 1. The p-type collector layer 36 constitutes a part of the second surface 72 (see Figure 2). The p-type collector layer 36 is electrically connected to the back electrode 11. The p-type collector layer 36 is in contact with the n+-type cathode layer 29. The interface between the p-type collector layer 36 and the n+-type cathode layer 29 is the boundary between the diode region 2 and the IGBT region 1.

[0045] A second trench gate 31b and a third trench gate 31c are provided in the semiconductor substrate 70 in the IGBT region 1. The second trench gate 31b extends from the first surface 71 along the third direction 103. The second trench gate 31b reaches the n-type drift layer 43. The second trench gate 31b is in contact with the n+-type source layer 33. An interlayer insulating film 34 is provided on the second trench gate 31b. The interlayer insulating film 34 electrically insulates the second trench gate 31b from the surface electrode 10.

[0046] The third trench gate 31c extends from the first surface 71 along the third direction 103. The third trench gate 31c reaches the n-type drift layer 43. The third trench gate 31c is in contact with the p+-type contact layer 38. The third trench gate 31c is electrically connected to the surface electrode 10.

[0047] Next, the configuration of the termination region 4 will be described. The semiconductor substrate 70 has a p-type termination well layer 41, an n+-type channel stopper layer 42, and a p-type termination collector layer 36a.

[0048] The p-type termination well layer 41 is provided in the termination region 4. The p-type termination well layer 41 is in contact with the n-type drift layer 43. The p-type termination well layer 41 constitutes a part of the first surface 71 (see Figure 2). The semiconductor substrate 70 has, for example, three p-type termination well layers 41. Each of the three p-type termination well layers 41 is spaced apart from the others. In plan view, the shape of each of the three p-type termination well layers 41 is annular. Each of the three p-type termination well layers 41 surrounds the IGBT region 1 and a plurality of diode regions 2.

[0049] The n+ type channel stopper layer 42 is provided in the terminal region 4. The n+ type channel stopper layer 42 constitutes a part of the first surface 71 (see Figure 2). In plan view, the shape of the n+ type channel stopper layer 42 is annular. The n+ type channel stopper layer 42 surrounds the p type terminal well layer 41.

[0050] A termination electrode 10a is provided on a p-type termination well layer 41 and an n+-type channel stopper layer 42. The termination electrode 10a is electrically connected to the p-type termination well layer 41 and the n+-type channel stopper layer 42.

[0051] A termination protective film 5 is provided in the termination region 4. The termination protective film 5 covers the surface electrode 10, the termination electrode 10a, and the interlayer insulating film 34. The termination protective film 5 is made of, for example, polyimide. The end face of the termination protective film 5 closest to the IGBT region 1 is considered the boundary between the termination region 4 and the IGBT region 1.

[0052] The p-type termination collector layer 36a is provided in a third direction 103 relative to the n-type buffer layer 37. The p-type termination collector layer 36a is in contact with the n-type buffer layer 37. The p-type termination collector layer 36a is provided in the termination region 4. The p-type termination collector layer 36a constitutes a part of the second surface 72 (see Figure 2). The configuration of the p-type termination collector layer 36a is substantially the same as the configuration of the p-type collector layer 36.

[0053] Next, the effects and advantages of the semiconductor device 100 according to Embodiment 1 will be described.

[0054] RC-IGBTs generate heat while energized, at the start of energization, and at the end of energization. Specifically, when IGBT region 1 is energized, IGBT region 1 generates heat. A copper circuit pattern may be connected to the back electrode 11 of the RC-IGBT. In this case, the portion of the RC-IGBT closest to the back electrode 11 is cooled by the copper circuit pattern. However, if a short circuit occurs in the RC-IGBT, particularly large amounts of heat are generated in the portion of IGBT region 1 closest to the front electrode 10. In this case, the RC-IGBT may be damaged instantaneously due to the heat.

[0055] According to the semiconductor device 100 of Embodiment 1, in a plan view, the bonding surface 55 of the wiring member 50 covers at least a portion of each of the plurality of diode regions 2. In a plan view, the second diode region 22 is located in a first direction 101 with respect to the first diode region 21. The second diode region 22 is spaced apart from the first diode region 21. In a plan view, the third diode region 23 is located in a second direction 102 with respect to the first diode region 21. The third diode region 23 is spaced apart from each of the first diode region 21 and the second diode region 22. As a result, the contact area between the plurality of diode regions 2 and the IGBT region 1 can be increased. This allows heat to be efficiently transferred from the IGBT region 1 to the plurality of diode regions 2 when the IGBT region 1 generates heat. Furthermore, because the bonding surface 55 covers at least a portion of each of the plurality of diode regions 2, heat can be efficiently transferred from each of the plurality of diode regions 2 to the wiring member 50. As a result, heat dissipation can be improved in the portion of the semiconductor device 100 that is close to the surface electrode 10.

[0056] According to the semiconductor device 100 of Embodiment 1, heat dissipation can be improved in the portion of the semiconductor device 100 that is close to the surface electrode 10. Therefore, when a short circuit occurs in the RC-IGBT, it is possible to suppress the temperature of the semiconductor device 100 from becoming excessively high locally. As a result, the short-circuit withstand capability of the semiconductor device 100 can be extended.

[0057] According to the semiconductor device 100 of Embodiment 1, the shape of the first diode region 21 is rectangular in a plan view. The wiring member 50 has a flat plate portion 49 and a conductive plate portion 51. The connection portion 59 between the flat plate portion 49 and the conductive plate portion 51 extends along the direction in which the long side of the first diode region 21 extends. Therefore, compared to the case where the connection portion 59 extends along the direction in which the short side of the first diode region 21 extends, the uniformity of the current flowing between the first diode region 21 and the connection portion 59 can be improved. Therefore, the increase in heat generation due to localized current concentration can be suppressed. As a result, the heat dissipation of the semiconductor device 100 can be improved when multiple diode regions 2 are energized.

[0058] (First modified example of Embodiment 1)

[0059] Next, the configuration of the semiconductor device 100 according to the first modified example of Embodiment 1 will be described using Figure 5. For the sake of clarity, the surface electrodes 10 are not shown in Figure 5.

[0060] In the above description, a configuration in which each of the multiple diode regions 2 in a plan view is rectangular has been described, but the configuration of the semiconductor device 100 according to this disclosure is not limited to the above configuration. Specifically, as shown in Figure 5, each of the multiple diode regions 2 in a plan view may be square. From another point of view, the length of the diode region 2 in the first direction 101 and the length of the diode region 2 in the second direction 102 may be substantially the same. One side of each of the multiple diode regions 2 is substantially parallel to the first direction 101.

[0061] This reduces the difference in current uniformity between the multiple diode regions 2 and the connection portion 59 when the connection portion 59 of the wiring member 50 extends along the first direction 101, and between the current uniformity between the multiple diode regions 2 and the connection portion 59 when the connection portion 59 extends along the second direction 102. From another perspective, the heat dissipation of the semiconductor device 100 can be sufficiently improved in both cases: when the connection portion 59 extends along the first direction 101 and when the connection portion 59 extends along the second direction 102. Therefore, the arrangement of the conductive plate portion 51 can be determined while maintaining the heat dissipation of the multiple diode regions 2, taking into account the wiring between the conductive plate portion 51 and external equipment. As a result, the degree of freedom in wiring can be improved.

[0062] (Second modified example of Embodiment 1)

[0063] Next, the configuration of the semiconductor device 100 according to a second modified example of Embodiment 1 will be described using Figure 6. The surface electrode 10 is not shown in Figure 6.

[0064] As shown in Figure 6, the density of diode regions 2 may be lower in the center of the region where multiple diode regions 2 are arranged. Specifically, in a plan view, the smallest rectangular region that encloses all of the multiple diode regions 2 is defined as the virtual region 91. The virtual line located midway between the outer edge (first outer edge 92) and the center (first center 93) of the virtual region 91 is defined as the boundary line 95.

[0065] The virtual region 91 is composed of an outer region 96 and a central region 97. The outer region 96 is located between the first outer edge 92 and the boundary line 95. The central region 97 is located inside the boundary line 95. The central region 97 is connected to the outer region 96. The central region 97 is surrounded by the outer region 96.

[0066] In a plan view, the density of multiple diode regions 2 in the central region 97 is smaller than the density of multiple diode regions 2 in the outer region 96. The size of the diode regions 2 in the central region 97 may be smaller than the size of the diode regions 2 in the outer region 96. Specifically, for example, the length of the diode region 2 in the central region 97 in the second direction 102 is shorter than the length of the diode region 2 in the outer region 96 in the second direction 102.

[0067] The length of the diode region 2 in the central region 97 in the first direction 101 may be substantially the same as the length of the diode region 2 in the outer peripheral region 96 in the first direction 101. In a plan view, the plurality of diode regions 2 may include both square-shaped diode regions 2 and rectangular-shaped diode regions 2.

[0068] When multiple diode regions 2 are energized, the temperature of the central region 97 tends to rise more easily than that of the outer region 96. In the semiconductor device 100 according to the second modification of Embodiment 1, in a plan view, the density of multiple diode regions 2 in the central region 97 is smaller than the density of multiple diode regions 2 in the outer region 96. Therefore, when multiple diode regions 2 are energized, it is possible to suppress the temperature of the central region 97 from becoming excessively higher than that of the outer region 96. This improves the heat dissipation of the portion of the semiconductor device 100 close to the surface electrode 10 when multiple diode regions 2 are energized.

[0069] (Third modified example of Embodiment 1)

[0070] Next, the configuration of the semiconductor device 100 according to the third modified example of Embodiment 1 will be described using Figure 7. As shown in Figure 7, the wiring member 50 may cover all of each of the plurality of diode regions 2. Specifically, in a plan view, the bonding surface 55 (see Figure 2) may cover all of each of the plurality of diode regions 2. In a plan view, the bonding member 60 (see Figure 2) may cover all of each of the plurality of diode regions 2. From another point of view, in a plan view, the plurality of diode regions 2 are surrounded by the outer edge of the flat plate portion 49.

[0071] This further increases the thermal energy transmitted from the multiple diode regions 2 to the wiring member 50 via the surface electrodes 10 and the bonding member 60. As a result, the heat dissipation in the portion of the semiconductor device 100 closest to the surface electrodes 10 can be further improved.

[0072] In the above description, the configuration in which the first diode region 21 is located at the corner of multiple diode regions 2 was explained, but the position of the first diode region 21 does not have to be at the corner of multiple diode regions 2. Diode regions 2 may be provided in the direction opposite to the first direction 101 and the direction opposite to the second direction 102 with respect to the first diode region 21.

[0073] Embodiment 2.

[0074] Next, the configuration of the semiconductor device 100 according to Embodiment 2 will be described using Figures 8 and 9. The semiconductor device 100 according to Embodiment 2 differs from the semiconductor device 100 according to Embodiment 1 mainly in that it has a protective film 6, and is substantially the same as the semiconductor device 100 according to Embodiment 1 in other respects. The following description will focus on the differences from the semiconductor device 100 according to Embodiment 1.

[0075] As shown in Figures 8 and 9, the semiconductor device 100 may have a protective film 6. The protective film 6 is provided on the termination region 4. The protective film 6 covers the termination region 4. The protective film 6 is in contact with the surface electrode 10. The protective film 6 covers a portion of the surface electrode 10. In a plan view, the protective film 6 surrounds a plurality of diode regions 2. The protective film 6 is composed of a nitride film such as polyimide, silicon nitride (SiN), and semi-insulating silicon nitride (SInSiN), or an oxide film such as SIPOS (Semi-Insulating Polycrystalline Silicon). By providing the protective film 6 on the termination region 4, the concentration of the electric field in the termination region 4 can be mitigated.

[0076] Embodiment 3.

[0077] Next, the configuration of the semiconductor device 100 according to Embodiment 3 will be described using Figures 10 to 12. The main difference between the semiconductor device 100 according to Embodiment 1 and the semiconductor device 100 according to Embodiment 3 is that the distance in plan view between each of the outer edge and termination region 4 of the bonded surface 55 and the plurality of diode regions 2 is sufficiently long. In other respects, it is substantially the same as the semiconductor device 100 according to Embodiment 1. The following description will focus on the differences from the semiconductor device 100 according to Embodiment 1.

[0078] As shown in Figure 10, the shortest distance between the termination region 4 and the multiple diode regions 2 in a plan view is defined as the first distance L1. Specifically, the first distance L1 is the shortest distance in a plan view between the termination protective film 5 (see Figure 4) of the termination region 4 and the n+ type cathode layer 29 (see Figure 4). The first distance L1 is, for example, the shortest distance between the termination region 4 and the multiple diode regions 2 in the first direction 101.

[0079] As shown in Figures 11 and 12, the shortest distance between the outer edge (second outer edge 98) of the bonded surface 55 (see Figure 12) and the plurality of diode regions 2 in a plan view is the second distance L2. Specifically, the second distance L2 is the shortest distance in a plan view between the second outer edge 98 and the n+ type cathode layer 29 (see Figure 4). The second distance L2 is, for example, the shortest distance between the second outer edge 98 and the plurality of diode regions 2 in the first direction 101. In a plan view, the second outer edge 98 may substantially overlap with the outer edge of the flat plate portion 49.

[0080] As shown in Figure 12, the distance between the first surface 71 and the second surface 72 in the third direction 103 is the thickness H of the IGBT region 1 in the third direction 103. Thickness H is the thickness of the semiconductor substrate 70 (see Figure 4) in the third direction 103. Thickness H is substantially the same as the thickness of the diode region 2 in the third direction 103.

[0081] As shown in Figures 10 to 12, the first distance L1 is greater than or equal to the thickness H. The second distance L2 is greater than or equal to the thickness H. The second distance L2 is shorter than the first distance L1.

[0082] According to the semiconductor device 100 of Embodiment 3, the first distance L1 is greater than or equal to the thickness H. In this way, the distance between the termination region 4 and the plurality of diode regions 2 is sufficiently long. This suppresses the inflow of holes from the termination region 4 into the plurality of diode regions 2. This suppresses power loss when the plurality of diode regions 2 are energized.

[0083] When multiple diode regions 2 are energized, carriers diffuse from the diode regions 2 along a direction inclined at 45° or less with respect to the third direction 103. Heat is generated in the region where the carriers have diffused. According to the semiconductor device 100 of Embodiment 3, the second distance L2 is greater than or equal to the thickness H. Therefore, in a plan view, the bonded surface 55 can cover the region where carriers diffuse when multiple diode regions 2 are energized. This further improves the heat dissipation of the semiconductor device 100.

[0084] Embodiment 4.

[0085] Next, the configuration of the semiconductor device 100 according to Embodiment 4 will be described using Figure 13. The semiconductor device 100 according to Embodiment 4 differs from the semiconductor device 100 according to Embodiment 1 mainly in that it has diode regions 2 arranged to sandwich the gate pad 7, and is substantially the same as the semiconductor device 100 according to Embodiment 1 in other respects. The following description will focus on the differences from the semiconductor device 100 according to Embodiment 1.

[0086] As shown in Figure 13, the semiconductor device 100 has a gate pad 7. In a plan view, the gate pad 7 is located, for example, in a first direction 101 with respect to the center (second center 94) of the surface electrode 10. The gate pad 7 is adjacent to, for example, the termination region 4. In a plan view, a virtual line passing through the second center 94 and parallel to the first direction 101 is defined as the center line A. In a plan view, the center line A passes through, for example, the gate pad 7. The gate pad 7 is configured to receive a signal that controls the conductivity of the IGBT region 1 (see Figure 2).

[0087] In the semiconductor device 100, the gate pad 7 is located on the opposite side of the back electrode 11. From another perspective, the gate pad 7 is located in the direction opposite to the third direction 103 with respect to the IGBT region 1.

[0088] Each of the diode regions 2 has two sets of pad-sandwich diode regions. Specifically, each of the diode regions 2 has a fourth diode region 24, a fifth diode region 25, a sixth diode region 26, and a seventh diode region 27. The fourth diode region 24, the fifth diode region 25, the sixth diode region 26, and the seventh diode region 27 are spaced apart from each other.

[0089] The fifth diode region 25 is located in a second direction 102 relative to the fourth diode region 24. In the second direction 102, the fourth diode region 24 and the fifth diode region 25 are positioned so as to sandwich the gate pad 7. From another perspective, in a plan view, the gate pad 7 is located between the fourth diode region 24 and the fifth diode region 25.

[0090] The seventh diode region 27 is located in a second direction 102 relative to the sixth diode region 26. In the second direction 102, the sixth diode region 26 and the seventh diode region 27 are positioned so as to sandwich the gate pad 7. From another perspective, in a plan view, the gate pad 7 is located between the sixth diode region 26 and the seventh diode region 27.

[0091] The flat plate portion 49 does not cover the gate pad 7. From another point of view, in plan view, the bonded surface 55 (see Figure 2) is spaced apart from the gate pad 7. In plan view, the portion of the flat plate portion 49 closest to the gate pad 7 is bifurcated. Specifically, the flat plate portion 49 has a main body portion 80, a first portion 61, and a second portion 62. The first portion 61 is connected to the main body portion 80. The first portion 61 is provided in a first direction 101 relative to the main body portion 80. In plan view, the first portion 61 overlaps the fourth diode region 24 and the sixth diode region 26, respectively.

[0092] The second portion 62 is connected to the main body 80. The second portion 62 is positioned in a first direction 101 relative to the main body 80. The second portion 62 is spaced apart from the first portion 61. The second portion 62 is positioned in a second direction 102 relative to the first portion 61. In a plan view, the second portion 62 overlaps the fifth diode region 25 and the seventh diode region 27, respectively. In a plan view, the gate pad 7 is positioned between the first portion 61 and the second portion 62.

[0093] In a plan view, the conductive plate portion 51 is positioned, for example, in the direction opposite to the gate pad 7 with respect to the second center 94. From another point of view, in a plan view, the conductive plate portion 51 is positioned, for example, in the direction opposite to the first direction 101 with respect to the second center 94. In a plan view, the second center 94 is located, for example, between the conductive plate portion 51 and the gate pad 7.

[0094] According to the semiconductor device 100 of Embodiment 4, the plurality of diode regions 2 include a fourth diode region 24 and a fifth diode region 25. The gate pad 7 is provided between the fourth diode region 24 and the fifth diode region 25. Therefore, compared to the case where there is no fourth diode region 24 and a fifth diode region 25, the density of the plurality of diode regions 2 can be reduced when the total area of ​​the plurality of diode regions 2 in a plan view is the same. Therefore, the heat dissipation of the portion of the semiconductor device 100 close to the surface electrode 10 can be improved when the plurality of diode regions 2 are energized.

[0095] According to the semiconductor device 100 of Embodiment 4, the flat plate portion 49 has a first portion 61 and a second portion 62. In a plan view, the first portion 61 overlaps the fourth diode region 24. In a plan view, the second portion 62 overlaps the fifth diode region 25. Therefore, the amount of thermal energy transmitted from the fourth diode region 24 and the fifth diode region 25 to the wiring member 50 can be increased. This improves the heat dissipation of the fourth diode region 24 and the fifth diode region 25.

[0096] According to the semiconductor device 100 of Embodiment 4, in a plan view, the conductive plate portion 51 is provided in the direction opposite to the gate pad 7 with respect to the second center 94. Therefore, interference between the gate wiring connected to the gate pad 7 and the conductive plate portion 51 can be suppressed. This improves the degree of freedom of wiring.

[0097] Furthermore, the multiple diode regions 2 may have only one set of pad-inserted diode regions. In other words, the multiple diode regions 2 do not necessarily have a sixth diode region 26 and a seventh diode region 27.

[0098] Embodiment 5.

[0099] Next, the configuration of the semiconductor device 100 according to Embodiment 5 will be described using Figure 14. The semiconductor device 100 according to Embodiment 5 differs from the semiconductor device 100 according to Embodiment 4 mainly in that the bonding surface 55 covers the temperature sense diode 8, and is substantially the same as the semiconductor device 100 according to Embodiment 4 in other respects. The following description will focus on the differences from the semiconductor device 100 according to Embodiment 4.

[0100] As shown in Figure 14, the semiconductor device 100 includes a temperature sense diode 8, an anode pad 12, and a cathode pad 13. In a plan view, the temperature sense diode 8 is located between any two of the plurality of diode regions 2. The temperature sense diode 8 is located, for example, near the center of the semiconductor device 100. Specifically, in a plan view, the second center 94 may overlap with the temperature sense diode 8. In a plan view, the center line A may pass through the temperature sense diode 8. In a plan view, the flat plate portion 49 covers the temperature sense diode 8. From another point of view, in a plan view, the bonded surface 55 (see Figure 2) covers the temperature sense diode 8.

[0101] The anode pad 12 is electrically connected to the temperature sense diode 8. The cathode pad 13 is electrically connected to the temperature sense diode 8. In a plan view, the flat plate portion 49 does not cover either the anode pad 12 or the cathode pad 13. In other words, in a plan view, the bonded surface 55 (see Figure 2) is spaced apart from either the anode pad 12 or the cathode pad 13.

[0102] In a plan view, the conductive plate portion 51 may be provided in the first direction 101 with respect to the second center 94. In a plan view, the conductive plate portion 51 may be provided between the second center 94 and the gate pad 7. If the semiconductor device 100 has a plurality of surface electrodes 10, the second center 94 is defined as the center of the smallest rectangular region that surrounds all of the plurality of surface electrodes 10 in a plan view.

[0103] According to the semiconductor device 100 of Embodiment 5, the bonding surface 55 covers the temperature sense diode 8. Therefore, heat can be easily transferred from the temperature sense diode 8 to the wiring member 50. This improves the heat dissipation performance of the temperature sense diode 8.

[0104] The temperature sense diode 8 may be provided along the gate pad 7. The temperature sense diode 8 may also be provided in the first direction 101 with respect to the second center 94.

[0105] Embodiment 6.

[0106] Next, the configuration of the semiconductor device 100 according to Embodiment 6 will be described using Figure 15. The semiconductor device 100 according to Embodiment 6 differs from the semiconductor device 100 according to Embodiment 1 mainly in that the wiring member 50 has a rising portion 52, and is substantially the same as the semiconductor device 100 according to Embodiment 1 in other respects. The following description will focus on the differences from the semiconductor device 100 according to Embodiment 1. Note that the cross-section shown in Figure 15 corresponds to the cross-section shown in Figure 2.

[0107] As shown in Figure 15, the wiring member 50 has a rising portion 52. The rising portion 52 is connected to the flat plate portion 49. The rising portion 52 is distinct from the conductive plate portion 51. At the second end portion 82, the rising portion 52 is connected to the flat plate portion 49. The rising portion 52 is spaced apart from the conductive plate portion 51. The rising portion 52 is inclined with respect to the flat plate portion 49 in the direction from the surface electrode 10 toward the flat plate portion 49. The inclination angle of the rising portion 52 with respect to the flat plate portion 49 is not particularly limited.

[0108] According to the semiconductor device 100 of Embodiment 6, the wiring member 50 has a rising portion 52. Therefore, the surface area of ​​the wiring member 50 can be increased compared to the case where the wiring member 50 does not have a rising portion 52. This improves the heat dissipation from the wiring member 50 to the outside of the semiconductor device 100.

[0109] (Modified version of Embodiment 6)

[0110] As shown in Figure 16, a first uneven surface 53 may be provided on the surface 56 of the flat plate portion 49. Specifically, a plurality of first recesses 75 and a plurality of first protrusions 76 may be provided on the surface 56. Each of the plurality of first protrusions 76 is spaced apart from one another. In the first direction 101, the plurality of first protrusions 76 are provided between the conductive plate portion 51 and the rising portion 52. A first recess 75 is provided between two adjacent first protrusions 76. Each of the plurality of first protrusions 76 extends, for example, along the second direction 102. The size of each of the plurality of first recesses 75 and the plurality of first protrusions 76 is not particularly limited.

[0111] According to the semiconductor device 100 of the modified embodiment 6, a first uneven portion 53 is provided on the surface 56 of the flat plate portion 49. This further increases the surface area of ​​the wiring member 50. As a result, the heat dissipation performance of the semiconductor device 100 can be further improved.

[0112] Embodiment 7.

[0113] Next, the configuration of the semiconductor device 100 according to Embodiment 7 will be described. The semiconductor device 100 according to Embodiment 7 differs from the semiconductor device 100 according to Embodiment 6 mainly in that the flat plate portion 49 has a third protrusion 79, and is substantially the same as the semiconductor device 100 according to Embodiment 6 in other respects. The following description will focus on the differences from the semiconductor device 100 according to Embodiment 6.

[0114] As shown in Figure 17, the flat portion 49 has a plate-like portion 48 and a third protrusion 79. The plate-like portion 48 is the portion that constitutes the surface 56, the first end 81 and the second end 82. The third protrusion 79 is provided in a third direction 103 relative to the plate-like portion 48. The third protrusion 79 is convex along the third direction 103. The plate-like portion 48 and the third protrusion 79 constitute the joined surface 55. The third protrusion 79 is in contact with the joining member 60. The bottom surface of the third protrusion 79 may be, for example, planar or convex along the third direction 103. The third protrusion 79 may be spaced apart from the surface electrode 10. In a plan view, the third protrusion 79 is surrounded, for example, by the joining member 60. In a plan view, for example, the third protrusion 79 may cover all of each of the plurality of diode regions 2.

[0115] According to the semiconductor device 100 of Embodiment 7, the flat plate portion 49 has a third protrusion 79. Therefore, during the manufacturing process of the semiconductor device 100, the third protrusion 79 pushes the bonding member 60 outward before it solidifies, along an in-plane direction perpendicular to the third direction 103. This effectively brings the flat plate portion 49 and the bonding member 60 into close contact. As a result, the generation of voids at the boundary between the flat plate portion 49 and the bonding member 60 is suppressed.

[0116] Embodiment 8.

[0117] Next, the configuration of the semiconductor device 100 according to Embodiment 8 will be described using Figures 18 and 19. The semiconductor device 100 according to Embodiment 8 differs from the semiconductor device 100 according to Embodiment 6 mainly in that through holes 99 are provided in the flat plate portion 49, and is substantially the same as the semiconductor device 100 according to Embodiment 6 in other respects. The following description will focus on the differences from the semiconductor device 100 according to Embodiment 6.

[0118] As shown in Figures 18 and 19, the flat plate portion 49 is provided with at least one through hole 99. Specifically, the number of through holes 99 may be one or two or more. The through holes 99 extend along the third direction 103. The through holes 99 penetrate the surface 56 and the surface to be joined 55. A part of the joining member 60 is located in the through holes 99.

[0119] In the manufacturing process of the semiconductor device 100, when the surface electrode 10 and the wiring member 50 are joined using the joining member 60, the joining member 60 is heated. As a result, due to the thermal expansion of the joining member 60, pressure is applied from the joining member 60 to the semiconductor element 30. In the semiconductor device 100 according to Embodiment 8, at least one through hole 99 is provided in the flat plate portion 49. Therefore, when the surface electrode 10 and the wiring member 50 are joined using the joining member 60, the joining member 60 wets and spreads inside the through hole 99. This reduces the pressure applied from the joining member 60 to the semiconductor element 30 when joining the surface electrode 10 and the wiring member 50. As a result, cracking of the semiconductor element 30 can be suppressed.

[0120] Embodiment 9.

[0121] Next, the configuration of the semiconductor device 100 according to Embodiment 9 will be described using Figure 20. The semiconductor device 100 according to Embodiment 9 differs from the semiconductor device 100 according to Embodiment 6 mainly in that a second uneven portion 54 is provided on the bonding surface 55, and is substantially the same as the semiconductor device 100 according to Embodiment 6 in other respects. The following description will focus on the differences from the semiconductor device 100 according to Embodiment 6.

[0122] As shown in Figure 20, a second uneven portion 54 is provided on the surface to be joined 55. Specifically, a plurality of second recesses 77 and a plurality of second protrusions 78 are provided on the surface to be joined 55. Each of the plurality of second protrusions 78 is spaced apart from one another. In the first direction 101, the plurality of second protrusions 78 are provided between the conductive plate portion 51 and the rising portion 52. A second recess 77 is provided between two adjacent second protrusions 78. Each of the plurality of second protrusions 78 extends, for example, along the second direction 102. The second uneven portion 54 is in contact with the joining member 60. The size of each of the plurality of second recesses 77 and the plurality of second protrusions 78 is not particularly limited.

[0123] According to the semiconductor device 100 of Embodiment 9, a second uneven portion 54 is provided on the surface 55 to be joined. Therefore, the bonding strength between the surface electrode 10 and the wiring member 50 using the bonding member 60 can be improved by the anchoring effect. Specifically, when joining the surface electrode 10 and the wiring member 50 using the bonding member 60, the molten bonding member 60 enters the second uneven portion 54. This allows the wiring member 50 and the bonding member 60 to be brought into close contact. As a result, the bonding strength between the surface electrode 10 and the wiring member 50 can be improved.

[0124] Although a modified example of Embodiment 6 and Embodiments 7 to 9 described a configuration in which the wiring member 50 has a rising portion 52, the configuration of the wiring member 50 is not limited to the above configuration. Specifically, the wiring member 50 does not need to have a rising portion 52.

[0125] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims rather than the foregoing description and is intended to include all modifications within the meaning and scope of equivalence to the claims.

[0126] The various aspects of this disclosure are summarized below as an appendix. (Note 1) Insulated gate bipolar transistor region, Multiple diode regions in contact with the insulated gate bipolar transistor region, A surface electrode in contact with the insulated gate bipolar transistor region and the plurality of diode regions, A bonding member provided on the surface electrode, The system comprises a wiring member joined to the surface electrode by the aforementioned joining member, The insulated gate bipolar transistor region and the plurality of diode regions constitute a reverse-conducting insulated gate bipolar transistor. The wiring member has a surface to be joined that is in contact with the joining member. In a plan view along a direction perpendicular to the surface electrode, the bonded surface covers at least a portion of each of the plurality of diode regions. In the plan view, the plurality of diode regions are The first diode region and A second diode region is located in a first direction relative to the first diode region and is spaced apart from the first diode region, A semiconductor device having a third diode region located in a second direction perpendicular to the first direction with respect to the first diode region, and spaced apart from both the first diode region and the second diode region. (Note 2) The aforementioned wiring member is The flat plate portion that constitutes the surface to be joined, The semiconductor device according to Appendix 1, further comprising a conductive plate portion connected to the flat plate portion and spaced apart from the joining member. (Note 3) In the aforementioned plan view, the shape of the first diode region is rectangular. The semiconductor device according to Appendix 2, wherein the connection portion between the flat plate portion and the conductive plate portion extends along the direction in which the long side of the first diode region extends. (Note 4) The device further comprises a gate pad provided in the direction from the insulated gate bipolar transistor region toward the surface electrode, and to which a signal controlling the conductivity of the insulated gate bipolar transistor region is input. The plurality of diode regions include a fourth diode region and a fifth diode region spaced apart from the fourth diode region. In the plan view, the gate pad is provided between the fourth diode region and the fifth diode region. In the aforementioned plan view, the surface to be joined is spaced apart from the gate pad. The aforementioned flat plate portion is The first portion overlapping the fourth diode region in the plan view, It has a second portion that overlaps with the fifth diode region in the plan view, The second part is a semiconductor device as described in Appendix 2 or Appendix 3, separated from the first part. (Note 5) In the plan view, the gate pad is provided in the first direction with respect to the center of the surface electrode, The semiconductor device according to Appendix 4, wherein, in the plan view, the conductive plate portion is provided in a direction opposite to the gate pad with respect to the center of the surface electrode. (Note 6) The wiring member is connected to the flat plate portion and has a raised portion that is different from the conductive plate portion. The semiconductor device according to any one of Appendix 2 to Appendix 5, wherein the rising portion is inclined with respect to the flat plate portion in a direction toward the flat plate portion from the surface electrode. (Note 7) The flat plate portion has a surface opposite to the surface to be joined, The semiconductor device according to any one of the appendices 2 to 6, wherein the surface is provided with a first uneven portion. (Note 8) The flat plate portion has a convex portion that is convex in the direction toward the surface electrode from the flat plate portion, The semiconductor device according to any one of the appendices 2 to 7, wherein the convex portion constitutes a part of the surface to be bonded. (Note 9) The semiconductor device according to any one of the appendices 2 to 8, wherein at least one through hole is provided in the flat plate portion. (Note 10) The surface to be joined is provided with a second uneven portion, The semiconductor device according to any one of the appendices 2 to 9, wherein the second uneven portion is in contact with the joining member. (Note 11) The semiconductor device according to Appendix 1 or Appendix 2, wherein, in the plan view, the shape of each of the plurality of diode regions is square. (Note 12) In the plan view, if the smallest rectangular region surrounding all of the plurality of diode regions is defined as a virtual region, and the virtual line located midway between the outer edge of the virtual region and the center of the virtual region is defined as the boundary line, The aforementioned virtual area is The outer peripheral region between the outer edge of the virtual region and the boundary line, It is composed of a central region located inside the aforementioned boundary line and connected to the aforementioned outer peripheral region, The semiconductor device according to any one of the appendices 1 to 11, wherein, in the plan view, the density of the plurality of diode regions in the central region is smaller than the density of the plurality of diode regions in the outer peripheral region. (Note 13) The semiconductor device according to any one of the appendices 1 to 12, wherein, in the plan view, the bonding surface covers all of each of the plurality of diode regions. (Note 14) A termination region that is in contact with the insulated gate bipolar transistor region and surrounds the insulated gate bipolar transistor region and the plurality of diode regions, The semiconductor device according to any one of the appendices 1 to 13, further comprising a protective film provided on the terminal region. (Note 15) The terminal region is in contact with the insulated gate bipolar transistor region and further comprises a terminal region that surrounds the insulated gate bipolar transistor region and the plurality of diode regions, The semiconductor device according to any one of the appendices 1 to 13, wherein the shortest distance between the termination region and the plurality of diode regions in the plan view is greater than or equal to the thickness of the insulated gate bipolar transistor region in a direction perpendicular to the surface electrode. (Note 16) The semiconductor device according to any one of the appendices 1 to 15, wherein the shortest distance between the outer edge of the surface to be joined and the plurality of diode regions in the plan view is greater than or equal to the thickness of the insulated gate bipolar transistor region in a direction perpendicular to the surface electrode. (Note 17) In the plan view, the device further comprises a temperature-sensing diode provided between any two of the plurality of diode regions. In the plan view, the bonding surface covers the temperature sense diode, as described in any one of Appendix 1 to Appendix 16. [Explanation of symbols]

[0127] 1 Insulated gate bipolar transistor region (IGBT region), 2 Diode region, 4 Termination region, 5 Termination protective film, 6 Protective film, 7 Gate pad, 8 Temperature sense diode, 10 Surface electrode, 10a Termination electrode, 11 Backside electrode, 12 Anode pad, 13 Cathode pad, 20 Row, 21 First diode region, 22 Second diode region, 23 Third diode region, 24 Fourth diode region, 25 Fifth diode region, 26 Sixth diode region, 27 Seventh diode region, 28 p-type anode layer, 29 n+-type cathode layer, 30 Semiconductor element, 31a First trench gate, 31b Second trench gate, 31c Third trench gate, 32 n+-type carrier store layer, 33 n+-type source layer, 34 Interlayer insulating film, 35 p-type base layer, 36 p-type collector layer, 36a p-type termination collector layer, 37 n-type buffer layer, 38 p+ type contact layer, 39 leading edge, 41 p-type termination well layer, 42 n+ type channel stopper layer, 43 n- type drift layer, 48 plate-like portion, 49 flat plate portion, 50 wiring member, 51 conductive plate portion, 52 rising portion, 53 first uneven portion, 54 second uneven portion, 55 surface to be joined, 56 surface, 59 connection portion, 60 joining member, 61 first portion, 62 second portion, 70 semiconductor substrate, 71 first surface, 72 second surface, 75 first recess, 76 first protrusion, 77 second recess, 78 second protrusion, 79 third protrusion, 80 main body portion, 81 first end, 82 second end, 91 virtual region, 92 first outer edge, 93 first center, 94 second center, 95 boundary line, 96 outer region, 97 central region, 98 second outer edge, 99 Through hole, 100 semiconductor device, 101 first direction, 102 second direction, 103 third direction, A center line, H thickness, L1 first distance, L2 second distance.

Claims

1. Insulated gate bipolar transistor region, Multiple diode regions in contact with the insulated gate bipolar transistor region, A surface electrode in contact with the insulated gate bipolar transistor region and the plurality of diode regions, A bonding member provided on the surface electrode, The system comprises a wiring member joined to the surface electrode by the aforementioned joining member, The insulated gate bipolar transistor region and the plurality of diode regions constitute a reverse-conducting insulated gate bipolar transistor. The wiring member has a surface to be joined that is in contact with the joining member. In a plan view along a direction perpendicular to the surface electrode, the bonded surface covers at least a portion of each of the plurality of diode regions. In the plan view, the plurality of diode regions are The first diode region and A second diode region is located in a first direction relative to the first diode region and is spaced apart from the first diode region, The present invention has a third diode region located in a second direction perpendicular to the first direction with respect to the first diode region, and spaced apart from each of the first and second diode regions. The wiring member has a flat plate portion that constitutes the surface to be joined, The flat plate portion is provided with at least one through hole, A semiconductor device in which a part of the joining member is located in at least one of the through holes.

2. The semiconductor device according to claim 1, wherein the wiring member has a conductive plate portion that is connected to the flat plate portion and spaced apart from the joining member.

3. In the aforementioned plan view, the shape of the first diode region is rectangular. The semiconductor device according to claim 2, wherein the connection portion between the flat plate portion and the conductive plate portion extends along the direction in which the long side of the first diode region extends.

4. The device further comprises a gate pad provided in the direction from the insulated gate bipolar transistor region toward the surface electrode, and to which a signal controlling the conductivity of the insulated gate bipolar transistor region is input. The plurality of diode regions include a fourth diode region and a fifth diode region spaced apart from the fourth diode region. In the plan view, the gate pad is provided between the fourth diode region and the fifth diode region. In the aforementioned plan view, the surface to be joined is spaced apart from the gate pad. The aforementioned flat plate portion is The first portion overlapping the fourth diode region in the plan view, It has a second portion that overlaps with the fifth diode region in the plan view, The semiconductor device according to claim 2 or 3, wherein the second portion is spaced apart from the first portion.

5. In the plan view, the gate pad is provided in the first direction with respect to the center of the surface electrode, The semiconductor device according to claim 4, wherein, in the plan view, the conductive plate portion is provided in a direction opposite to the gate pad with respect to the center of the surface electrode.

6. The wiring member is connected to the flat plate portion and has a raised portion that is different from the conductive plate portion. The semiconductor device according to claim 2 or 3, wherein the rising portion is inclined with respect to the flat plate portion in a direction toward the flat plate portion from the surface electrode.

7. The flat plate portion has a surface opposite to the surface to be joined, The semiconductor device according to claim 2 or claim 3, wherein the surface is provided with a first uneven portion.

8. The flat plate portion has a convex portion that is convex in the direction toward the surface electrode from the flat plate portion, The semiconductor device according to claim 2 or claim 3, wherein the convex portion constitutes a part of the surface to be bonded.

9. The surface to be joined is provided with a second uneven portion, The semiconductor device according to claim 2 or 3, wherein the second uneven portion is in contact with the joining member.

10. The semiconductor device according to claim 1 or claim 2, wherein, in the plan view, the shape of each of the plurality of diode regions is square.

11. In the plan view, if the smallest rectangular region surrounding all of the plurality of diode regions is defined as a virtual region, and the virtual line located midway between the outer edge of the virtual region and the center of the virtual region is defined as the boundary line, The aforementioned virtual area is The outer peripheral region between the outer edge of the virtual region and the boundary line, It is composed of a central region located inside the aforementioned boundary line and connected to the aforementioned outer peripheral region, The semiconductor device according to any one of claims 1 to 3, wherein, in the plan view, the density of the plurality of diode regions in the central region is smaller than the density of the plurality of diode regions in the outer peripheral region.

12. The semiconductor device according to any one of claims 1 to 3, wherein, in the plan view, the bonding surface covers all of each of the plurality of diode regions.

13. A termination region that is in contact with the insulated gate bipolar transistor region and surrounds the insulated gate bipolar transistor region and the plurality of diode regions, The semiconductor device according to any one of claims 1 to 3, further comprising a protective film provided on the terminal region.

14. The terminal region is in contact with the insulated gate bipolar transistor region and further comprises a terminal region that surrounds the insulated gate bipolar transistor region and the plurality of diode regions, The semiconductor device according to any one of claims 1 to 3, wherein the shortest distance between the termination region and the plurality of diode regions in the plan view is greater than or equal to the thickness of the insulated gate bipolar transistor region in a direction perpendicular to the surface electrode.

15. The semiconductor device according to any one of claims 1 to 3, wherein the shortest distance between the outer edge of the surface to be bonded and the plurality of diode regions in the plan view is greater than or equal to the thickness of the insulated gate bipolar transistor region in a direction perpendicular to the surface electrode.

16. In the plan view, the device further comprises a temperature-sensing diode provided between any two of the plurality of diode regions. The semiconductor device according to any one of claims 1 to 3, wherein, in the plan view, the surface to be bonded covers the temperature sense diode.

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