Semiconductor device driving device

Abstract

To provide a technology that enables a secondary side circuit to determine whether the ASC mode is being executed.SOLUTION: A semiconductor device drive device includes a primary circuit, a signal transmission circuit including an insulating element, and a secondary circuit that drives a semiconductor device on the basis of a plurality of transmission signals corresponding to a plurality of signals transmitted from the primary circuit via the signal transmission circuit. The secondary circuit includes an ASC mode determination circuit that determines whether a normal mode or an ASC mode is being executed on the basis of a transmission transition signal corresponding to a transition signal or a control transition signal among the plurality of transmission signals.SELECTED DRAWING: Figure 1

Description

[[Technical Field]]

[0001] The present disclosure relates to a semiconductor element driving device. [[Background Art]]

[0002] Various techniques have been proposed for semiconductor element driving devices that drive semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) in inverter systems. For example, a technique has been proposed in which a primary-side circuit transmits a signal to a secondary-side circuit via an insulating element capable of signal transmission, so that the secondary-side circuit drives the semiconductor element.

[0003] As one example, Patent Document 1 proposes a technique in which the primary-side circuit prioritizes a second control signal for driving the semiconductor element in an ASC (Active Short Circuit) mode over a first control signal for driving the semiconductor element in a normal mode, and transmits the prioritized signal to the secondary-side circuit. That is, the technique proposes that when the first control signal is input to the primary-side circuit without the second control signal being input, the primary-side circuit transmits the first control signal to the secondary-side circuit; and when the second control signal is input to the primary-side circuit, the primary-side circuit transmits the second control signal to the secondary-side circuit regardless of whether the first control signal is input or not. [[Prior Art Documents]] [[Patent Documents]]

[0004] [[Patent Document 1]] International Publication No. 2023 / 105943 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0005] However, with the technique of Patent Document 1, the secondary-side circuit cannot determine whether the normal mode or the ASC mode is being executed. For this reason, there has been a problem that the secondary-side circuit cannot make the operation in the ASC mode different from the operation in the normal mode.

[0006] Therefore, this disclosure has been made in view of the above-mentioned problems, and aims to provide a technology that enables the secondary circuit to determine whether or not ASC mode is being executed. [Means for solving the problem]

[0007] The semiconductor device driving device according to this disclosure comprises a primary circuit to which a plurality of signals are input, including a first control signal for controlling the driving of a semiconductor device in normal mode, a second control signal for controlling the driving of the semiconductor device in ASC mode, and a transition signal for transitioning from the normal mode to the ASC mode, or a control transition signal corresponding to the first control signal, the second control signal, and the transition signal; a signal transmission circuit including an insulating element capable of transmitting signals; and a secondary circuit that drives the semiconductor device based on a plurality of transmission signals corresponding to the plurality of signals transmitted from the primary circuit through the signal transmission circuit, wherein the secondary circuit includes the plurality of transmission signals The system includes an ASC mode determination circuit that determines whether the normal mode is being executed or the ASC mode is being executed based on a transfer transition signal corresponding to the transition signal or the control transition signal among the plurality of transfer signals, and a logic circuit that, if the ASC mode determination circuit determines that the normal mode is being executed, drives the semiconductor element based on a first transfer control signal corresponding to the first control signal among the plurality of transfer signals, and if the ASC mode determination circuit determines that the ASC mode is being executed, drives the semiconductor element based on a second control signal or a second transfer control signal corresponding to the control transition signal among the plurality of transfer signals. [Effects of the Invention]

[0008] According to this disclosure, the secondary circuit includes an ASC mode determination circuit that determines whether the normal mode is being executed or the ASC mode is being executed based on a transfer transition signal corresponding to a transition signal or control transition signal among a plurality of transfer signals. With such a configuration, the secondary circuit can determine whether or not the ASC mode is being executed. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram showing the configuration of a semiconductor element driving device according to Embodiment 1. [Figure 2] This is a timing chart showing the operation of the semiconductor element driving device according to Embodiment 1. [Figure 3] This is a timing chart showing the operation of the ASC mode determination circuit according to Embodiment 1. [Figure 4] This is a circuit diagram showing the configuration of the semiconductor element driving device according to Embodiment 2. [Figure 5] This is a timing chart showing the operation of the semiconductor element driving device according to Embodiment 2. [Figure 6] This is a circuit diagram showing the configuration of the semiconductor element driving device according to Embodiment 3. [Figure 7] This is a timing chart showing the operation of the semiconductor element driving device according to Embodiment 3. [Figure 8] This is a circuit diagram showing the configuration of a semiconductor device driving device according to Embodiment 4. [Figure 9] This is a timing chart showing the operation of the semiconductor element driving device according to Embodiment 4. [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the attached drawings. The features described in each of the embodiments below are illustrative, and not all features are necessarily required. In addition, in the descriptions below, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components will be described primarily.

[0011] <Embodiment 1> Figure 1 is a circuit diagram showing the configuration of a semiconductor device driving device according to this first embodiment. The semiconductor device driving device in Figure 1 comprises a primary circuit 1 to which multiple signals are input, a secondary circuit 5 for driving semiconductor devices (not shown), and a signal transmission circuit 3 including an insulating element that enables signal transmission from the primary circuit 1 to the secondary circuit 5. In other words, the semiconductor device driving device in Figure 1 is a gate driver IC with an insulating element.

[0012] Multiple signals input to the primary circuit 1 are output from, for example, an ECU (Electronic Control Unit) and an MCU (Micro Controller Unit). The multiple signals according to this embodiment 1 include a first control signal for controlling the driving of semiconductor elements in normal mode, a second control signal for controlling the driving of semiconductor elements in ASC (Active Short Circuit) mode, and a transition signal for transitioning from normal mode to ASC mode.

[0013] The primary circuit 1 includes an IN terminal to which a first control signal is input, an ASC_IN terminal to which a second control signal is input, an ASC_EN terminal to which a transition signal is input, and modulation circuits 11, 12, 13, 14, and 15. The modulation circuits 11, 12, 13, 14, and 15 modulate the multiple signals input to the primary circuit 1 into modulated signals that can be transmitted by the signal transmission circuit 3.

[0014] The signal transmission circuit 3 includes an isolator that enables signal transmission through an insulating portion such as space. In the following description, the isolator is described using a configuration in which the isolator is a transformer magnetically coupled to each other, as shown in Figure 1, as an example, but it is not limited to this configuration. For example, the isolator may be a capacitor capacitively coupled to each other, or a photocoupler optically coupled to each other.

[0015] The secondary-side circuit 5 includes demodulation circuits 51, 52, 53, 54, 55, pulse restoration circuits 61 and 62, an ASC mode determination circuit 63, an abnormality detection and protection operation circuit 64 which is an abnormality detection circuit, a logic circuit 65, a drive circuit 66, an OUT terminal, and an ErrIN terminal. Note that the abnormality detection and protection operation circuit 64 and the ErrIN terminal are not necessarily required to be provided.

[0016] The demodulation circuits 51 to 55 and the pulse restoration circuits 61 and 62 generate a plurality of transmission signals corresponding to the plurality of signals of the primary-side circuit 1, based on a modulated signal transmitted from the primary-side circuit 1 via the signal transmission circuit 3.

[0017] In the first embodiment, a first transmission control signal corresponding to a first control signal among the plurality of transmission signals has substantially the same waveform as the first control signal. A second transmission control signal corresponding to a second control signal among the plurality of transmission signals has substantially the same waveform as the second control signal. A transmission transition signal corresponding to a transition signal among the plurality of transmission signals has a different waveform from the transition signal. As described below, the secondary-side circuit 5 drives the semiconductor element based on the plurality of transmission signals including the first transmission control signal, the second transmission control signal, and the transmission transition signal.

[0018] The ASC mode determination circuit 63 determines whether a normal mode or an ASC mode is being executed based on the transmission transition signal corresponding to the transition signal of the ASC_EN terminal, and outputs a determination signal indicating the determination result.

[0019] The abnormality detection and protection operation circuit 64 acquires a signal indicating the operation state of the semiconductor element via the ErrIN terminal. The abnormality detection and protection operation circuit 64 detects an abnormality of the semiconductor element based on the signal, and outputs an abnormality detection signal indicating the detection result of the abnormality of the semiconductor element. Note that the abnormality of the semiconductor element may include an abnormality of the semiconductor element driving device that is reflected in the operation state of the semiconductor element.

[0020] The logic circuit 65 receives a first transmission control signal corresponding to the first control signal of the IN terminal, a second transmission control signal corresponding to the second control signal of the ASC_IN terminal, a determination signal from the ASC mode determination circuit 63, and an abnormality detection signal from the abnormality detection protection operation circuit 64. Based on the first transmission control signal, the second transmission control signal, the determination result of the ASC mode determination circuit 63, and the detection result of the abnormality detection protection operation circuit 64, the logic circuit 65 outputs a drive signal from the drive circuit 66 via the OUT terminal to drive a semiconductor element (not shown).

[0021] In this embodiment 1, if the ASC mode determination circuit 63 determines that the normal mode is being executed (i.e., the ASC mode is not being executed), the logic circuit 65 drives the semiconductor element based on the first transmission control signal. However, if the ASC mode determination circuit 63 determines that the normal mode is being executed and the abnormality detection protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 performs an operation to protect the semiconductor element regardless of the first transmission control signal. The operation to protect the semiconductor element is, for example, an operation to shut down the semiconductor element.

[0022] On the other hand, if the ASC mode determination circuit 63 determines that ASC mode is being executed, the logic circuit 65 drives the semiconductor element based on the second transmission control signal instead of the first transmission control signal. Also, if the ASC mode determination circuit 63 determines that ASC mode is being executed and the abnormality detection protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 drives the semiconductor element based on the second transmission control signal without performing any protective operation for the semiconductor element.

[0023] Semiconductor elements not shown are driven by a drive signal output from the OUT terminal of the secondary circuit 5. The semiconductor elements are, for example, semiconductor switching elements in an inverter system that drives an inductive load such as a motor. The semiconductor elements include, for example, IGBTs (Insulated Gate Bipolar Transistors), RC-IGBTs (Reverse Conducting IGBTs), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The material of the semiconductor element may include ordinary silicon (Si), or it may include wide-bandgap semiconductors such as silicon carbide (Si), gallium nitride (GaN), and diamond. When the semiconductor element is made of a wide-bandgap semiconductor, stable operation at high temperatures and high voltages, and faster switching speeds become possible.

[0024] Figure 2 is a timing chart showing the operation of the semiconductor device driving device according to this embodiment 1. The following describes the normal mode, the normal mode when an abnormality is detected, the ASC mode, and the ASC mode when an abnormality is detected. Note that in the following descriptions of each mode, redundant information will be omitted as appropriate.

[0025] <Normal Mode> Modulation circuit 11 generates a modulated signal based on the rising edge of the first control signal input to the IN terminal, and modulation circuit 12 generates a modulated signal based on the falling edge of the first control signal input to the IN terminal. In other words, modulation circuits 11 and 12 generate modulated signals by performing edge-triggered modulation on the first control signal. The modulated signals generated by modulation circuits 11 and 12 are provided to demodulation circuits 51 and 52, respectively, via the signal transmission circuit 3.

[0026] The demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulated signals generated by the modulation circuits 11 and 12 to the S and R terminals of the pulse restoration circuit 61, respectively. Based on the edge trigger signals output from the demodulation circuits 51 and 52, the pulse restoration circuit 61 generates a first transmission control signal having substantially the same waveform as the first control signal input to the primary circuit 1, and outputs it to the logic circuit 65 via the Q terminal. With this configuration, the first transmission control signal corresponding to the first control signal can be transmitted from the primary circuit 1 to the secondary circuit 5 without losing the square wave information of the first control signal, while maintaining the isolation state between the primary circuit 1 and the secondary circuit 5.

[0027] The second control signal input to the ASC_IN terminal is processed in the same way as the first control signal. Specifically, modulation circuit 13 generates a modulated signal based on the rising edge of the second control signal, and modulation circuit 14 generates a modulated signal based on the falling edge of the second control signal. In other words, modulation circuits 13 and 14 generate modulated signals by performing edge-triggered modulation on the second control signal. The modulated signals generated by modulation circuits 13 and 14 are provided to demodulation circuits 53 and 54, respectively, via signal transmission circuit 3.

[0028] The demodulation circuits 53 and 54 output edge trigger signals equivalent to the modulated signals generated by the modulation circuits 13 and 14 to the S and R terminals of the pulse restoration circuit 62, respectively. Based on the edge trigger signals output from the demodulation circuits 53 and 54, the pulse restoration circuit 62 generates a second transmission control signal having substantially the same waveform as the second control signal input to the primary circuit 1, and outputs it to the logic circuit 65 via the Q terminal.

[0029] In normal mode, a transition signal for the invalid signal (Low) is input to the ASC_EN terminal. When the modulation circuit 15 receives the transition signal for the invalid signal, it outputs an invalid signal. The invalid signal is transmitted to the demodulation circuit 55 via the signal transmission circuit 3, and the demodulation circuit 55 outputs the transmitted transition signal of the invalid signal to the ASC mode determination circuit 63. The ASC mode determination circuit 63 determines that normal mode is being executed based on the transmitted transition signal of the invalid signal, and outputs an invalid signal determination signal indicating this determination result to the logic circuit 65.

[0030] If the ASC mode determination circuit 63 determines that the normal mode is being executed, the logic circuit 65 rejects the second transmission control signal corresponding to the second control signal and outputs a drive signal to the OUT terminal based on the first transmission control signal corresponding to the first control signal.

[0031] <Normal mode when an anomaly is detected> If an abnormality occurs in a semiconductor element or other component during normal mode, a valid signal (High) is input to the ErrIN terminal of the secondary circuit 5. When the valid signal is input to the ErrIN terminal, the abnormality detection protection circuit 64 detects the abnormality of the semiconductor element and outputs an abnormality detection signal to the logic circuit 65.

[0032] When the ASC mode determination circuit 63 determines that the normal mode is being executed and the abnormality detection protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 outputs a signal (Low) to the OUT terminal to shut down the semiconductor element, regardless of the first transmission control signal.

[0033] <ASCモード> In ASC mode, the transition signal of the active signal is input to the ASC_EN terminal. When the transition signal is the active signal, the modulation circuit 15 generates a modulated signal including burst-like pulses by OOK (On-Off-Keying) modulation. The modulated signal is transmitted to the demodulation circuit 55 via the signal transmission circuit 3, and the demodulation circuit 55 outputs a transmission transition signal corresponding to the modulated signal to the ASC mode determination circuit 63. The transmission transition signal has substantially the same waveform as the modulated signal of the modulation circuit 15.

[0034] Figure 3 is a timing chart showing the operation of the ASC mode determination circuit 63 according to this embodiment 1. The ASC mode determination circuit 63 generates a count reset trigger to reset the pulse count of the transfer transition signal to 0, and a determination trigger for the ASC mode determination circuit 63 to make a determination. The determination cycle is the period between the count reset trigger and the determination trigger.

[0035] The ASC mode determination circuit 63 determines that ASC mode is being executed when it counts the pulses of the transfer transition signal a predetermined N times (N≧2) within a predetermined determination cycle. In this case, the ASC mode determination circuit 63 outputs a valid signal determination signal to the logic circuit 65, indicating that ASC mode is being executed. On the other hand, even if the transition signal at the ASC_EN terminal is a valid signal momentarily, if the number of times the pulses of the transfer transition signal are counted within the determination cycle does not reach N times, the ASC mode determination circuit 63 does not determine that ASC mode is being executed. In this case, the ASC mode determination circuit 63 outputs an invalid signal determination signal to the logic circuit 65, indicating that normal mode is being executed. With this configuration, misjudgments by the ASC mode determination circuit 63 due to noise can be suppressed.

[0036] If the ASC mode determination circuit 63 determines that the normal mode is being executed, the logic circuit 65 rejects the first transmission control signal corresponding to the first control signal and outputs a drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal.

[0037] <ASC mode when an anomaly is detected> When an abnormality occurs in a semiconductor element or other component while in ASC mode, a valid signal is input to the ErrIN terminal of the secondary circuit 5. When the valid signal is input to the ErrIN terminal, the abnormality detection protection circuit 64 detects the abnormality of the semiconductor element and outputs an abnormality detection signal to the logic circuit 65.

[0038] The logic circuit 65 outputs a drive signal to the OUT terminal based on a second transmission control signal corresponding to the second control signal when the ASC mode determination circuit 63 determines that the ASC mode is being executed and the abnormality detection protection operation circuit 64 detects an abnormality in the semiconductor element. With this configuration, when in ASC mode, the operation of the ASC mode can continue regardless of the detection result of the abnormality detection protection operation circuit 64.

[0039] <Summary of Embodiment 1> In the semiconductor device driving device according to this embodiment 1, the ASC mode determination circuit 63 of the secondary circuit 5 determines whether the normal mode is being executed or the ASC mode is being executed based on the transfer transition signal corresponding to the transition signal. With this configuration, the secondary circuit 5 can make the operation of the ASC mode when an abnormality is detected different from the operation of the normal mode when an abnormality is detected, based on the determination result of the ASC mode determination circuit 63.

[0040] <Embodiment 2> Figure 4 is a circuit diagram showing the configuration of a semiconductor device driving device according to this second embodiment. The configuration of the primary circuit 1 in Figure 4 is the same as the configuration of the primary circuit 1 in Figure 1, with the addition of a demodulation circuit 16, an output circuit FO output circuit 17, an input priority determination circuit 18, and an FO terminal, while the modulation circuits 13 and 14 are removed. The configuration of the secondary circuit 5 in Figure 4 is the same as the configuration of the secondary circuit 5 in Figure 1, with the addition of a modulation circuit 56, while the removal of demodulation circuits 53 and 54 and a pulse restoration circuit 62.

[0041] The modulation circuit 56 of the secondary circuit 5 generates a modulated signal including burst-like pulses based on the determination signal from the ASC mode determination circuit 63 and the abnormality detection signal from the abnormality detection protection operation circuit 64.

[0042] The demodulation circuit 16 of the primary circuit 1 generates a burst signal including burst-like pulses based on the modulated signal transmitted from the secondary circuit 5 via the signal transmission circuit 3. The FO output circuit 17 smooths the burst signal generated by the demodulation circuit 16 to generate a transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormal detection signal of the abnormal detection protection operation circuit 64. In this embodiment 2, the transmission result signal corresponds to the logical OR signal of the determination signal of the ASC mode determination circuit 63 and the abnormal detection signal of the abnormal detection protection operation circuit 64, but it may correspond to either the determination signal or the abnormal detection signal.

[0043] The input priority determination circuit 18 selects the first control signal for the IN terminal and the second control signal for the ASC_IN terminal based on the transmission result signal of the FO output circuit 17 and the transition signal of the ASC_EN terminal, and outputs them to the signal transmission circuit 3 via the modulation circuits 11 and 12. The FO terminal is a terminal for outputting the transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormal detection signal of the abnormal detection protection operation circuit 64 to the outside.

[0044] Figure 5 is a timing chart showing the operation of the semiconductor device driving device according to this second embodiment. The normal mode, the normal mode when an abnormality is detected, the ASC mode, and the ASC mode when an abnormality is detected will be described below. In the following descriptions of each mode, overlapping content will be omitted as appropriate.

[0045] <Normal Mode> In normal mode, the invalid signal transition signal is input to the ASC_EN terminal. The input priority determination circuit 18 determines that normal mode is being executed if the transition signal is an invalid signal, regardless of the output signal of the FO output circuit 17. In this case, the input priority determination circuit 18 rejects the second control signal from the ASC_IN terminal and outputs the first control signal from the IN terminal to the modulation circuits 11 and 12.

[0046] Modulation circuits 11 and 12 generate a modulated signal by performing edge-triggered modulation on the first control signal. The modulated signals generated by modulation circuits 11 and 12 are then supplied to demodulation circuits 51 and 52, respectively, via the signal transmission circuit 3.

[0047] The demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulated signals generated by the modulation circuits 11 and 12 to the S and R terminals of the pulse restoration circuit 61, respectively. Based on the edge trigger signals output from the demodulation circuits 51 and 52, the pulse restoration circuit 61 generates a first transmission control signal having substantially the same waveform as the first control signal input to the primary circuit 1, and outputs it to the logic circuit 65 via the Q terminal.

[0048] When the modulation circuit 15 receives a transition signal for the invalid signal, it outputs an invalid signal. The invalid signal is transmitted to the demodulation circuit 55 via the signal transmission circuit 3, and the demodulation circuit 55 outputs the transmission transition signal of the invalid signal to the ASC mode determination circuit 63. The ASC mode determination circuit 63 determines that the normal mode is being executed based on the transmission transition signal of the invalid signal, and outputs an invalid signal determination signal indicating this determination result to the logic circuit 65.

[0049] If the ASC mode determination circuit 63 determines that the normal mode is being executed, the logic circuit 65 outputs a drive signal to the OUT terminal based on the first transmission control signal corresponding to the first control signal of the IN terminal.

[0050] <Normal mode when an anomaly is detected> If an abnormality occurs in a semiconductor element or other component during normal mode, a valid signal is input to the ErrIN terminal of the secondary circuit 5. When the valid signal is input to the ErrIN terminal, the abnormality detection protection circuit 64 detects the abnormality of the semiconductor element and outputs an abnormality detection signal to the logic circuit 65 and the modulation circuit 56.

[0051] If the ASC mode determination circuit 63 determines that the normal mode is being executed and the abnormality detection protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 outputs a signal to the OUT terminal to shut down the semiconductor element, regardless of the first transmission control signal.

[0052] The modulation circuit 56 generates a modulated signal including burst-like pulses by OOK when the abnormality detection signal from the abnormality detection protection operation circuit 64 is a valid signal. The modulated signal is transmitted to the demodulation circuit 16 via the signal transmission circuit 3, and the demodulation circuit 16 outputs a burst signal corresponding to the modulated signal to the FO output circuit 17. The burst signal has substantially the same waveform as the modulated signal from the modulation circuit 56.

[0053] The FO output circuit 17 smooths the burst signal from the demodulation circuit 16 to generate a transmission result signal corresponding to the determination signal from the ASC mode determination circuit 63 and the abnormal detection signal from the abnormal detection protection operation circuit 64.

[0054] The transmission result signal is output to the FO terminal, and an external device on the primary circuit 1 side can check for abnormalities in the semiconductor element from the transmission result signal at the FO terminal. Furthermore, the transmission of the transmission result signal can be achieved using a pair of insulating elements (in this case, a pair of transformers).

[0055] The transmission result signal is also output to the input priority determination circuit 18, but since the transition signal of the ASC_EN terminal is an invalid signal, the input priority determination circuit 18 determines that the normal mode is being executed and outputs the first control signal of the IN terminal to the modulation circuits 11 and 12.

[0056] <ASCモード> In ASC mode, the transition signal of the active signal is input to the ASC_EN terminal. The modulation circuit 15 generates a modulated signal containing burst-like pulses using OOK when the transition signal is the active signal. The modulated signal is transmitted to the demodulation circuit 55 via the signal transmission circuit 3, and the demodulation circuit 55 outputs a transmission transition signal corresponding to the modulated signal to the ASC mode determination circuit 63. The transmission transition signal has substantially the same waveform as the modulated signal of the modulation circuit 15.

[0057] The ASC mode determination circuit 63 determines that ASC mode is being executed when it counts the pulse of the transfer transition signal N times within the determination cycle. If the ASC mode determination circuit 63 determines that ASC mode is being executed, it outputs a determination signal indicating the determination result to both the logic circuit 65 and the modulation circuit 56. On the other hand, if the ASC mode determination circuit 63 determines that normal mode is being executed, it outputs a determination signal indicating the determination result to both the logic circuit 65 and the modulation circuit 56.

[0058] The modulation circuit 56, signal transmission circuit 3, demodulation circuit 16, and FO output circuit 17 operate in the same way as in normal mode when an abnormality is detected. As a result, the transmission result signals corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection operation circuit 64 are output to the FO terminal and the input priority determination circuit 18. Since the determination signal of the ASC mode determination circuit 63 is a valid signal, the transmission result signal is also a valid signal.

[0059] The input priority determination circuit 18 determines that the ASC mode has been accepted by the secondary circuit 5 if the transition signal of the ASC_EN terminal is a valid signal and the transmission result signal of the FO output circuit 17 is a valid signal. In this case, the input priority determination circuit 18 rejects the first control signal of the IN terminal and outputs the second control signal of the ASC_IN terminal to the modulation circuits 11 and 12.

[0060] The modulation circuits 11 and 12, the signal transmission circuit 3, the demodulation circuits 51 and 52, and the pulse restoration circuit 61 perform the same operations as in normal mode in response to the second control signal. As a result, a second transmission control signal corresponding to the second control signal at the ASC_IN terminal is output to the logic circuit 65. If the ASC mode determination circuit 63 determines that the ASC mode is being executed, the logic circuit 65 outputs a drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal at the ASC_IN terminal.

[0061] <ASC mode when an anomaly is detected> When an abnormality occurs in a semiconductor element or other component while in ASC mode, a valid signal is input to the ErrIN terminal of the secondary circuit 5. When the valid signal is input to the ErrIN terminal, the abnormality detection protection circuit 64 detects the abnormality in the semiconductor element and outputs an abnormality detection signal to the logic circuit 65 and the modulation circuit 56.

[0062] The logic circuit 65 outputs a drive signal to the OUT terminal based on a second transmission control signal corresponding to the second control signal when the ASC mode determination circuit 63 determines that the ASC mode is being executed and the abnormality detection protection operation circuit 64 detects an abnormality in the semiconductor element. With this configuration, when in ASC mode, the operation of the ASC mode can continue regardless of the detection result of the abnormality detection protection operation circuit 64.

[0063] The modulation circuit 56, signal transmission circuit 3, demodulation circuit 16, and FO output circuit 17 operate in the same way as in normal mode when an anomaly is detected. As a result, the transmission result signals corresponding to the determination signal of the ASC mode determination circuit 63 and the anomaly detection signal of the anomaly detection protection operation circuit 64 are output to the FO terminal and the input priority determination circuit 18. Since both the determination signal of the ASC mode determination circuit 63 and the anomaly detection signal of the anomaly detection protection operation circuit 64 are valid signals, the transmission result signals are also valid signals.

[0064] <Summary of Embodiment 2> According to this second embodiment, the input priority determination circuit 18 of the primary circuit 1 selectively outputs the first control signal of the IN terminal and the second control signal of the ASC_IN terminal to the signal transmission circuit 3 based on the transition signal of the ASC_EN terminal. With this configuration, the number of modulation circuits and demodulation circuits can be reduced compared to the configuration of the first embodiment, thereby reducing the area and number of components of the semiconductor element driving device.

[0065] Furthermore, the input priority determination circuit 18 of the primary circuit 1 selectively outputs the first control signal for the IN terminal and the second control signal for the ASC_IN terminal to the signal transmission circuit 3 based on the transmission result signal of the FO output circuit 17 and the transition signal of the ASC_EN terminal. With this configuration, the input priority determination circuit 18 can perform control to switch between the first control signal and the second control signal while also considering the transmission result signal that reflects the determination result of the ASC mode determination circuit 63.

[0066] <Embodiment 3> Figure 6 is a circuit diagram showing the configuration of a semiconductor device driving device according to this third embodiment. The configuration of the primary circuit 1 in Figure 6 is the same as the configuration of the primary circuit 1 in Figure 4, but with the transition signal of the ASC_EN terminal input to the modulation circuits 11 and 12 and the modulation circuit 15 removed. The configuration of the secondary circuit 5 in Figure 6 is the same as the configuration of the secondary circuit 5 in Figure 4, but with the addition of an OR circuit 70 and the removal of the demodulation circuit 55.

[0067] If the transition signal at the ASC_EN terminal of the primary circuit 1 is an invalid signal, the modulation circuits 11 and 12 perform edge-triggered modulation on the output signal of the input priority determination circuit 18, similar to the modulation circuits 11 and 12 of Embodiment 2. On the other hand, if the transition signal at the ASC_EN terminal is an active signal, the modulation circuits 11 and 12 generate a modulated signal including burst-like pulses by performing OOK on the output signal of the input priority determination circuit 18.

[0068] The OR circuit 70 of the secondary circuit 5 outputs the logical OR signal of the output signals of the demodulation circuits 51 and 52 to the ASC mode determination circuit 63.

[0069] Figure 7 is a timing chart showing the operation of the semiconductor device driving device according to this embodiment 3. The following describes the normal mode, the normal mode when an abnormality is detected, the ASC mode, and the ASC mode when an abnormality is detected. Note that in the following descriptions of each mode, redundant information will be omitted as appropriate.

[0070] <Normal Mode> In this embodiment 3, the OR signal from the OR circuit 70 is input to the ASC mode determination circuit 63. However, since the pulse interval of the OR signal in normal mode is relatively long, the ASC mode determination circuit 63 determines that normal mode is being executed without counting the pulses of the transfer transition signal N times within the determination cycle.

[0071] The normal mode according to this embodiment 3 from this point onward is the same as the normal mode according to embodiment 2. That is, the input priority determination circuit 18 outputs a first control signal to the IN terminal, and the logic circuit 65 outputs a drive signal to the OUT terminal based on a first transmission control signal corresponding to the first control signal.

[0072] <Normal mode when an anomaly is detected> The normal mode during abnormality detection according to this third embodiment is the same as the normal mode during abnormality detection according to the second embodiment. That is, the abnormality detection protection operation circuit 64 outputs an abnormality detection signal of the valid signal to the logic circuit 65, and the logic circuit 65 outputs a signal to shut down the semiconductor element to the OUT terminal, regardless of the first transmission control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0073] <ASCモード> In ASC mode, the transition signal of the active signal is input to the ASC_EN terminal. In this case, the modulation circuits 11 and 12 do not perform edge-triggered modulation, but instead perform OOK on the output signal of the input priority determination circuit 18, thereby generating a modulated signal that includes burst-like pulses corresponding to the duration of the output signal.

[0074] The modulated signal is transmitted to the demodulation circuits 51 and 52 via the signal transmission circuit 3, and the demodulation circuits 51 and 52 output signals corresponding to the modulated signal to the S terminal and R terminal of the pulse restoration circuit 61, respectively. The demodulation circuits 51 and 52 also output signals corresponding to the modulated signal to the OR circuit 70.

[0075] The OR circuit 70 outputs the logical OR signal of the output signals of the demodulation circuits 51 and 52 as a transfer transition signal to the ASC mode determination circuit 63. The ASC mode determination circuit 63 counts the pulses of the transfer transition signal, which includes burst-like pulses, a predetermined N times within the determination cycle, similar to the transfer transition signal in Embodiment 2, and determines that the ASC mode is being executed.

[0076] The ASC mode according to this embodiment 3 from this point onward is the same as the ASC mode according to embodiment 2. That is, the input priority determination circuit 18 outputs a second control signal to the ASC_IN terminal, and the logic circuit 65 outputs a drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormal detection signal of the abnormal detection protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0077] <ASC mode when an anomaly is detected> As explained in the ASC mode section, the ASC mode during abnormality detection according to this embodiment 3 is the same as the ASC mode during abnormality detection according to embodiment 2, except that the generation process of the transfer transition signal differs from that of embodiment 2. In other words, the abnormality detection protection operation circuit 64 outputs an abnormality detection signal of the valid signal to the logic circuit 65, and the logic circuit 65 outputs a drive signal to the OUT terminal based on the second transfer control signal corresponding to the second control signal. In addition, the transfer result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0078] <Summary of Embodiment 3> According to this third embodiment, the number of modulation and demodulation circuits can be reduced compared to the configuration of the second embodiment, thus reducing the area and number of components of the semiconductor element drive device. Furthermore, the modulation circuits 11 and 12 may generate and output a modulated signal using OOK even in normal mode, provided that it does not affect the determination of the ASC mode determination circuit 63. With this configuration, the secondary circuit 5 can confirm the startup of the primary power supply of the primary circuit 1.

[0079] <Embodiment 4> Figure 8 is a circuit diagram showing the configuration of the semiconductor element driving device according to this embodiment 4. The configuration of the primary circuit 1 in Figure 8 is the same as the configuration of the primary circuit 1 in Figure 6, but with the ASC_IN terminal, ASC_EN terminal, and input priority determination circuit 18 removed. The configuration of the secondary circuit 5 in Figure 8 is the same as the configuration of the secondary circuit 5 in Figure 6, but with the waveform shaping circuit 72 added.

[0080] In this embodiment 4, multiple signals are selectively input to the IN terminal of the primary circuit 1. The multiple signals include a first control signal and a control transition signal. The control transition signal corresponds to the second control signal and transition signal described above, and includes burst-like pulses with a shorter pulse width than the first control signal.

[0081] The ASC mode determination circuit 63 determines whether normal mode is being executed or ASC mode is being executed based on the transfer transition signal corresponding to the control transition signal.

[0082] The modulation circuits 11 and 12, the demodulation circuits 51 and 52, and the pulse restoration circuit 61 generate a signal containing burst-like pulses that corresponds to the control transition signal. In this embodiment 4, the signal output from the pulse restoration circuit 61 has substantially the same waveform as the control transition signal. The waveform shaping circuit 72 generates a second transmission control signal, which is a square wave signal, based on the signal output from the pulse restoration circuit 61. If the ASC mode determination circuit 63 determines that the ASC mode is being executed, the logic circuit 65 drives the semiconductor element based on the second transmission control signal, which is a square wave signal generated by the waveform shaping circuit 72.

[0083] Figure 9 is a timing chart showing the operation of the semiconductor device driving device according to this embodiment 4. The following describes the normal mode, the normal mode when an abnormality is detected, the ASC mode, and the ASC mode when an abnormality is detected. Note that in the following descriptions of each mode, redundant information will be omitted as appropriate.

[0084] <Normal Mode> In normal mode, the first control signal is input to the IN terminal. Modulation circuits 11 and 12 generate a modulated signal by performing edge-triggered modulation on the first control signal. The modulated signals generated by modulation circuits 11 and 12 are supplied to demodulation circuits 51 and 52, respectively, via the signal transmission circuit 3.

[0085] The demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulated signals generated by the modulation circuits 11 and 12 to the S and R terminals of the pulse restoration circuit 61, respectively. Based on the edge trigger signals output from the demodulation circuits 51 and 52, the pulse restoration circuit 61 generates a first transmission control signal having substantially the same waveform as the first control signal input to the primary circuit 1, and outputs it to the waveform shaping circuit 72 via the Q terminal. Since the first transmission control signal has a frequency below the threshold, the waveform shaping circuit 72 outputs the first transmission control signal to the logic circuit 65.

[0086] The ASC mode determination circuit 63 does not count the pulses of the transfer transition signal N times within the determination cycle, and therefore determines that the normal mode is being executed. In addition, the ASC mode determination circuit 63 according to this embodiment 4 differs from the ASC mode determination circuit 63 according to embodiments 1 to 3 in that, for each signal applied to the IN terminal, it sequentially determines whether the signal is the first control signal of the normal mode or the control transition signal of the ASC mode.

[0087] As a result of the above operations, the logic circuit 65 outputs a drive signal to the OUT terminal based on the first transmission control signal corresponding to the first control signal.

[0088] <Normal mode when an anomaly is detected> The normal mode during abnormality detection according to this fourth embodiment is the same as the normal mode during abnormality detection according to the third embodiment. That is, the abnormality detection protection operation circuit 64 outputs an abnormality detection signal of the valid signal to the logic circuit 65, and the logic circuit 65 outputs a signal to shut down the semiconductor element to the OUT terminal, regardless of the first transmission control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0089] <ASCモード> In normal mode, the control transition signal is input to the IN terminal. The modulation circuits 11 and 12 generate a modulated signal containing burst-like pulses by performing edge-triggered modulation on the control transition signal. The modulated signals generated by the modulation circuits 11 and 12 are supplied to the demodulation circuits 51 and 52, respectively, via the signal transmission circuit 3.

[0090] The demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulated signals generated by the modulation circuits 11 and 12 to the S and R terminals of the pulse restoration circuit 61, respectively. Additionally, the demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulated signals generated by the modulation circuits 11 and 12 to the OR circuit 70.

[0091] The pulse restoration circuit 62 generates a signal that is substantially the same waveform as the control transition signal input to the primary circuit 1, based on the edge trigger signals output from the demodulation circuits 51 and 52, and outputs it to the waveform shaping circuit 72 via the Q terminal. Since the signal output from the pulse restoration circuit 62 has a frequency above the threshold, the waveform shaping circuit 72 generates a second transmission control signal, which is a square wave signal, based on this signal, and outputs this second transmission control signal to the logic circuit 65.

[0092] The OR circuit 70 outputs the logical OR signal of the edge trigger signals output from the demodulation circuits 51 and 52 to the ASC mode determination circuit 63. The ASC mode determination circuit 63 counts the pulses of the logical OR signal, which includes burst-like pulses, a predetermined N times within the determination cycle, similar to the transfer transition signal in Embodiment 3, and determines that the ASC mode is being executed.

[0093] The ASC mode according to this embodiment 3 from this point onward is the same as the ASC mode according to embodiment 3. That is, the logic circuit 65 outputs a drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormal detection signal of the abnormal detection protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0094] <ASC mode when an anomaly is detected> If the logic circuit 65 determines that the ASC mode is being executed by the ASC mode determination circuit 63 and an abnormality in the semiconductor element is detected by the abnormality detection protection operation circuit 64, it outputs a drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0095] <Summary of Embodiment 4> According to the semiconductor device driving device of this embodiment 4, similar to embodiments 1 to 3, the ASC mode determination circuit 63 of the secondary circuit 5 determines whether the normal mode is being executed or the ASC mode is being executed based on the transfer transition signal corresponding to the transition signal. With this configuration, the secondary circuit 5 can make the operation of the ASC mode when an abnormality is detected different from the operation of the normal mode when an abnormality is detected, based on the determination result of the ASC mode determination circuit 63.

[0096] Furthermore, according to this embodiment 4, the ASC_IN terminal, the ASC_EN terminal, and the input priority determination circuit 18 can be reduced from the configuration of embodiment 3, so a reduction in the area and number of components of the semiconductor element driving device can be expected.

[0097] Furthermore, it is possible to freely combine each embodiment and each variation, and to modify or omit each embodiment and each variation as appropriate.

[0098] The various aspects of this disclosure are summarized below as an appendix.

[0099] (Note 1) A primary side circuit to which a plurality of signals are input, including a first control signal for controlling the driving of a semiconductor element in normal mode, a second control signal for controlling the driving of the semiconductor element in ASC mode, and a transition signal for transitioning from the normal mode to the ASC mode, or the first control signal, the second control signal, and a control transition signal corresponding to the transition signal, A signal transmission circuit including an insulating element capable of transmitting signals, Based on the plurality of transmission signals corresponding to the plurality of signals transmitted from the primary side circuit via the signal transmission circuit, the secondary side circuit drives the semiconductor element. Equipped with, The secondary circuit is, An ASC mode determination circuit that determines whether the normal mode is being executed or the ASC mode is being executed based on a transfer transition signal corresponding to the transition signal or the control transition signal among the plurality of transfer signals, A logic circuit that, when the ASC mode determination circuit determines that the normal mode is being executed, drives the semiconductor element based on a first transmission control signal corresponding to the first control signal among the plurality of transmission signals, and when the ASC mode determination circuit determines that the ASC mode is being executed, drives the semiconductor element based on a second control signal among the plurality of transmission signals or a second transmission control signal corresponding to the control transition signal. A semiconductor device drive system, including a semiconductor element drive device.

[0100] (Note 2) A semiconductor device driving device as described in Appendix 1, The aforementioned transfer transition signal includes burst-like pulses. The ASC mode determination circuit determines that the ASC mode is being executed when the pulses of the transfer transition signal are counted a predetermined number of times within a predetermined period of time, and is a semiconductor device driving device.

[0101] (Note 3) A semiconductor element driving device as described in Appendix 1 or Appendix 2, The secondary circuit is, The system further includes an abnormality detection circuit for detecting abnormalities in the semiconductor element, The aforementioned logic circuit is If the ASC mode determination circuit determines that the normal mode is being executed, and the abnormality detection circuit detects an abnormality in the semiconductor element, then an operation to protect the semiconductor element is performed regardless of the first transmission control signal. A semiconductor element driving device that drives the semiconductor element based on the second transmission control signal when the ASC mode determination circuit determines that the ASC mode is being executed and the abnormality detection circuit detects an abnormality in the semiconductor element.

[0102] (Note 4) A semiconductor element driving device described in any one of the items from Appendix 1 to Appendix 3, The primary side circuit is, The modulation circuit includes a modulation circuit that generates a modulated signal based on the rising and falling edges of the first control signal, The secondary circuit is, A semiconductor device driving device further includes a demodulation circuit that generates an edge trigger signal used to generate the first transmission control signal based on the modulated signal transmitted from the primary side circuit via the signal transmission circuit.

[0103] (Note 5) A semiconductor device driving device as described in Appendix 4, The secondary circuit is, A semiconductor device drive device further includes a pulse recovery circuit that generates the first transmission control signal based on the edge trigger signal.

[0104] (Note 6) A semiconductor element driving device as described in Appendix 1 or Appendix 2, The secondary circuit is, The system further includes an abnormality detection circuit that outputs an abnormality detection signal indicating the result of detecting an abnormality in the semiconductor element, The primary side circuit is, A semiconductor device driving device including a terminal for outputting to the outside a transmission result signal corresponding to the abnormality detection signal transmitted from the secondary circuit via the signal transmission circuit.

[0105] (Note 7) A semiconductor element driving device as described in Appendix 1 or Appendix 2, The secondary circuit is, An abnormality detection circuit that outputs an abnormality detection signal indicating the detection result of an abnormality in the semiconductor element, A modulation circuit that generates a modulated signal including burst-like pulses based on the anomaly detection signal, It further includes, The primary side circuit is, A demodulation circuit that generates a burst signal including burst-like pulses based on the modulated signal transmitted from the secondary circuit via the signal transmission circuit, An output circuit that smooths the burst signal and generates a transmission result signal corresponding to the abnormality detection signal. A semiconductor device drive system, including a semiconductor element drive device.

[0106] (Note 8) A semiconductor element driving device described in any one of the items from Appendix 1 to Appendix 7, The plurality of signals include the first control signal, the second control signal, and the transition signal. The primary side circuit is, A semiconductor device driving device including an input priority determination circuit that selectively outputs the first control signal and the second control signal to the signal transmission circuit based on the transition signal.

[0107] (Note 9) A semiconductor device driving device as described in Appendix 8, The secondary circuit is, The system further includes an abnormality detection circuit for detecting abnormalities in the semiconductor element, The aforementioned input priority determination circuit is: A semiconductor device driving device that selectively outputs the first control signal and the second control signal to the signal transmission circuit based on the transmission result signal corresponding to the determination result of the ASC mode determination circuit and the detection result of the abnormality detection circuit transmitted from the secondary circuit via the signal transmission circuit, and the transition signal.

[0108] (Note 10) A semiconductor element driving device described in any one of the items from Appendix 1 to Appendix 7, The plurality of signals include the first control signal and the control transition signal, The secondary circuit is, A semiconductor device driving device further includes a waveform shaping circuit that generates the second transmission control signal, which is a square wave signal, based on a signal including a burst-like pulse corresponding to the control transition signal transmitted from the primary side circuit via the signal transmission circuit.

[0109] (Note 11) A semiconductor element driving device described in any one of the items from Appendix 1 to Appendix 10, The insulating elements include transformers that are magnetically coupled to each other, and the semiconductor element driving device.

[0110] (Note 12) A semiconductor element driving device described in any one of the items from Appendix 1 to Appendix 10, The aforementioned insulating element is a semiconductor element driving device, which includes capacitors that are capacitively coupled to each other.

[0111] (Note 13) A semiconductor element driving device described in any one of the items from Appendix 1 to Appendix 10, The aforementioned insulating elements include photocouplers that are optically coupled to each other, and is a semiconductor element driving device. [Explanation of Symbols]

[0112] 1 Primary circuit, 3 Signal transmission circuit, 5 Secondary circuit, 11-15, 56 Modulation circuit, 16, 51-55 Demodulation circuit, 17 FO output circuit, 18 Input priority determination circuit, 61, 62 Pulse restoration circuit, 63 ASC mode determination circuit, 64 Anomaly detection protection operation circuit, 65 Logic circuit, 70 OR circuit, 72 Waveform shaping circuit.

Claims

1. A primary side circuit to which a plurality of signals are input, including a first control signal for controlling the driving of a semiconductor element in normal mode, a second control signal for controlling the driving of the semiconductor element in ASC mode, and a transition signal for transitioning from the normal mode to the ASC mode, or the first control signal, the second control signal, and a control transition signal corresponding to the transition signal, A signal transmission circuit including an insulating element capable of transmitting signals, Based on the plurality of transmission signals corresponding to the plurality of signals transmitted from the primary side circuit via the signal transmission circuit, the secondary side circuit drives the semiconductor element. Equipped with, The secondary circuit is, An ASC mode determination circuit that determines whether the normal mode is being executed or the ASC mode is being executed based on a transmission transition signal corresponding to the transition signal or the control transition signal among the plurality of transmission signals, A logic circuit that, when the ASC mode determination circuit determines that the normal mode is being executed, drives the semiconductor element based on a first transmission control signal corresponding to the first control signal among the plurality of transmission signals, and when the ASC mode determination circuit determines that the ASC mode is being executed, drives the semiconductor element based on a second control signal or a second transmission control signal corresponding to the control transition signal among the plurality of transmission signals. A semiconductor device drive system, including a semiconductor element drive device.

2. A semiconductor device driving device according to claim 1, The aforementioned transfer transition signal includes burst-like pulses. The ASC mode determination circuit determines that the ASC mode is being executed when the pulses of the transfer transition signal are counted a predetermined number of times within a predetermined period of time, and is a semiconductor element driving device.

3. A semiconductor element driving device according to claim 1 or claim 2, The secondary circuit is, The system further includes an abnormality detection circuit for detecting abnormalities in the semiconductor element, The aforementioned logic circuit is If the ASC mode determination circuit determines that the normal mode is being executed, and the abnormality detection circuit detects an abnormality in the semiconductor element, then an operation to protect the semiconductor element is performed regardless of the first transmission control signal. A semiconductor element driving device that drives the semiconductor element based on the second transmission control signal when the ASC mode determination circuit determines that the ASC mode is being executed and the abnormality detection circuit detects an abnormality in the semiconductor element.

4. A semiconductor element driving device according to claim 1 or claim 2, The primary side circuit is, The modulation circuit includes a modulation circuit that generates a modulation signal based on the rising and falling edges of the first control signal, The secondary circuit is, A semiconductor device driving device further includes a demodulation circuit that generates an edge trigger signal used for generating the first transmission control signal based on the modulated signal transmitted from the primary side circuit via the signal transmission circuit.

5. A semiconductor device driving device according to claim 4, The secondary circuit is, A semiconductor device driving device further includes a pulse recovery circuit that generates the first transmission control signal based on the edge trigger signal.

6. A semiconductor element driving device according to claim 1 or claim 2, The secondary circuit is, The system further includes an abnormality detection circuit that outputs an abnormality detection signal indicating the result of detecting an abnormality in the semiconductor element, The primary side circuit is, A semiconductor device driving device including a terminal for outputting to the outside a transmission result signal corresponding to the abnormality detection signal transmitted from the secondary circuit via the signal transmission circuit.

7. A semiconductor element driving device according to claim 1 or claim 2, The secondary circuit is, An abnormality detection circuit that outputs an abnormality detection signal indicating the detection result of an abnormality in the semiconductor element, A modulation circuit that generates a modulated signal including burst-like pulses based on the anomaly detection signal, It further includes, The primary side circuit is, A demodulation circuit that generates a burst signal including burst-like pulses based on the modulated signal transmitted from the secondary circuit via the signal transmission circuit, An output circuit that smooths the burst signal and generates a transmission result signal corresponding to the abnormality detection signal. A semiconductor device drive system, including a semiconductor element drive device.

8. A semiconductor element driving device according to claim 1 or claim 2, The plurality of signals include the first control signal, the second control signal, and the transition signal. The primary side circuit is, A semiconductor device driving device including an input priority determination circuit that selectively outputs the first control signal and the second control signal to the signal transmission circuit based on the transition signal.

9. A semiconductor device driving device according to claim 8, The secondary circuit is, The system further includes an abnormality detection circuit for detecting abnormalities in the semiconductor element, The aforementioned input priority determination circuit is: A semiconductor device that selectively outputs the first control signal and the second control signal to the signal transmission circuit based on the transmission result signal corresponding to the determination result of the ASC mode determination circuit and the detection result of the abnormality detection circuit transmitted from the secondary circuit via the signal transmission circuit, and the transition signal.

10. A semiconductor element driving device according to claim 1 or claim 2, The plurality of signals include the first control signal and the control transition signal, The secondary circuit is, A semiconductor device driving device further includes a waveform shaping circuit that generates the second transmission control signal, which is a square wave signal, based on a signal including a burst-like pulse corresponding to the control transition signal transmitted from the primary side circuit via the signal transmission circuit.

11. A semiconductor element driving device according to claim 1 or claim 2, The insulating elements include transformers that are magnetically coupled to each other, and the semiconductor element driving device.

12. A semiconductor element driving device according to claim 1 or claim 2, The aforementioned insulating element is a semiconductor element driving device, which includes capacitors that are capacitively coupled to each other.

13. A semiconductor element driving device according to claim 1 or claim 2, The aforementioned insulating elements include photocouplers that are optically coupled to each other, and is a semiconductor element driving device.

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