Separation of oxide-bonded wafer pairs by laser delamination

Abstract

A method of fabricating a semiconductor structure includes forming a detachable layer capable of absorbing infrared (IR) radiation beneath a first carrier wafer. A first hard dielectric layer is formed beneath the detachable layer. A second hard dielectric layer is formed on a top surface of the semiconductor wafer. The first dielectric layer is bonded to the second dielectric layer. A connector on a bottom portion of the semiconductor wafer is formed to provide electrical connection to the semiconductor wafer. A second carrier wafer is connected to the connector on the bottom portion of the semiconductor wafer. The first carrier wafer is separated from the semiconductor wafer by degrading the detachable layer by penetrating IR into the first carrier wafer with IR radiation. Back-end-of-line (BEOL) interconnects are provided from the top surface of the semiconductor wafer through the first and second dielectric layers.

Description

[[Technical Field]]

[0001] The present disclosure relates generally to semiconductor devices, and more particularly to temporarily attaching a semiconductor wafer to a carrier wafer during processing, and to a method of manufacturing the same. [[Background Art]]

[0002] Today, integrated circuits are typically fabricated on semiconductor wafers that undergo various processing steps. Wafers are often thinned for further processing. Beyond a certain thickness, the wafer becomes structurally fragile for further processing. Therefore, the thinned wafer is preferably temporarily bonded to a handling wafer before thinning to enable further processing. Using an adhesive applied to the semiconductor wafer, the handler wafer, or both, the semiconductor wafer can be adhered to the handler wafer. After the semiconductor wafer has been processed, the semiconductor wafer can be separated from the handler wafer by dissolving the bonded adhesive, for example using a solvent or a laser. [[Summary of Invention]]

[0003] According to one embodiment, a semiconductor structure comprises a carrier wafer. A semiconductor wafer is bonded onto the top surface of the carrier wafer. A first dielectric layer is on the top surface of the semiconductor wafer. A second dielectric layer is directly bonded onto the top surface of the first dielectric layer. One or more back end of line (BEOL) wirings extend through the first and second dielectric layers from the top surface of the semiconductor wafer.

[0004] In one embodiment, the first and second dielectric layers comprise an oxide.

[0005] In one embodiment, the first and second dielectric layers have a thermal conductivity equal to or greater than the thermal conductivity of silicon oxide.

[0006] In one embodiment, the first and second dielectric layers comprise diamond films.

[0007] In one embodiment, the width of the semiconductor wafer is thinned to 50 μm to 100 μm.

[0008] In one embodiment, the carrier wafer includes glass.

[0009] In one embodiment, the junction between the first dielectric layer and the second dielectric layer is an oxynitride bond.

[0010] In one embodiment, the junction between the first dielectric layer and the second dielectric layer is a nitride bond.

[0011] According to one embodiment, a method for manufacturing a semiconductor structure includes providing a first carrier wafer and forming a scissionable layer capable of absorbing infrared (IR) radiation beneath the first carrier wafer. A first hard-dielectric layer is formed beneath the scissionable layer. A second hard-dielectric layer is formed on the top surface of the semiconductor wafer. The first dielectric layer is directly bonded to the second dielectric layer. A connector is formed on the bottom surface of the semiconductor wafer to provide an electrical connection to the semiconductor wafer. The second carrier wafer is connected to the connector on the bottom surface of the semiconductor wafer. The first carrier wafer is separated from the semiconductor wafer by degrading the scissionable layer by transmitting infrared (IR) radiation into the first carrier wafer. Back-end-of-line (BEOL) wiring is provided from the top surface of the semiconductor wafer through the first and second dielectric layers.

[0012] In one embodiment, the separable layer includes aluminum (Al).

[0013] In one embodiment, the separable layer is a light-to-heat-conversion release coating (LTHC) layer.

[0014] In one embodiment, the first and second dielectric layers include an oxide.

[0015] In one embodiment, after direct bonding of the first dielectric layer and the second dielectric layer, thermal annealing is performed to form a stronger bond between the first dielectric layer and the second dielectric layer.

[0016] In one embodiment, the semiconductor wafer is thinned after direct bonding of the first dielectric layer and the second dielectric layer.

[0017] In one embodiment, the semiconductor wafer is thinned to a thickness of 50 μm to 100 μm.

[0018] In one embodiment, at least one of the top or bottom surface of the carrier wafer is thinned with an anti-reflective layer.

[0019] In one embodiment, the anti-reflective layer includes a nitride.

[0020] In one embodiment, a second carrier wafer is attached beneath the semiconductor wafer with an adhesive.

[0021] In one embodiment, when the first carrier wafer is separated from the semiconductor wafer, the residue of the separable layer is removed by chemical etching of the separable layer.

[0022] In one embodiment, the semiconductor wafer includes a separable layer beneath a second hard dielectric layer.

[0023] The techniques described herein can be implemented in several ways. Exemplary implementations are given below with reference to the following figures.

[0024] The drawings relate to exemplary embodiments. The drawings do not illustrate all embodiments. Other embodiments may be used in addition or as alternatives. Details that are considered obvious or unnecessary may be omitted for space reasons or for a more efficient description. Some embodiments may be practiced with additional components or steps, without all of the described components or steps, or both. Where the same numeral appears in different drawings, it refers to the same or similar components or steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] [Figure 1] 1 is a simplified cross-sectional view of a handler and a semiconductor wafer, consistent with an exemplary embodiment. [Figure 2] 2 is a cross-sectional view of a carrier consistent with an exemplary embodiment. [Figure 3] 3 is a diagram showing a semiconductor structure including a separable layer, consistent with an exemplary embodiment. [Figure 4] 4 is a diagram showing a carrier structure including a hard dielectric layer deposited on the bottom surface of the separable layer. [Figure 5] 5 is a diagram showing the arrangement of the carrier structure of FIG. 4 placed above a semiconductor wafer, consistent with an exemplary embodiment. [Figure 6] 6 is a diagram showing a semiconductor structure of a carrier bonded to a semiconductor wafer, consistent with an exemplary embodiment. [Figure 7] 7 is a diagram showing a semiconductor structure that has undergone a wafer thinning process, consistent with an exemplary embodiment. [Figure 8] 8 is a diagram showing a semiconductor structure including a second carrier coupled to the semiconductor structure of FIG. 7, consistent with an exemplary embodiment. [Figure 9] 9 is a diagram showing the semiconductor structure of FIG. 8 exposed to infrared radiation, consistent with an exemplary embodiment. [Figure 10] 10 is a diagram showing a semiconductor structure with the hard dielectric remaining for use in BEOL connections, consistent with an exemplary embodiment. [Modes for carrying out the invention]

[0026] overview The following detailed explanation includes numerous specific details as examples to provide a complete understanding of the relevant teachings. However, it will be clear that these teachings can be carried out without such details. In other examples, well-known methods, procedures, components, or circuits, or combinations thereof, are described at a relatively high level without detailed explanation, in order to avoid unnecessarily obscuring aspects of these teachings.

[0027] In one embodiment, spatial terms such as “front,” “back,” “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper,” “side,” “left,” and “right” are used to describe the orientation of the diagram being described. Since the components of the embodiments of this disclosure may be arranged in several different orientations, the directional terms are used for illustrative purposes only and are not limiting. It will be understood that the spatial terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation depicted in the diagram. For example, if the device in the diagram is turned over, an element described as “below” or “beneath” other elements or features will then be oriented “above” other elements or features. Therefore, for example, the term "below" can encompass both the downward and upward directions. The device may be in other orientations (rotated 90 degrees, or viewed or referenced in other orientations), and the spatial descriptive terms used herein should be interpreted accordingly.

[0028] As used herein, the terms “lateral” and “horizontal” refer to an orientation parallel to the first surface of a semiconductor substrate or semiconductor base. For example, the substrate may be the surface of a wafer or die.

[0029] As used herein, the term “vertical” refers to an orientation perpendicular to the first surface of a semiconductor substrate or semiconductor base.

[0030] As used herein, the terms “coupled” or “electrically coupled” or both are not intended to mean that elements must be directly coupled to one another, and intervening elements may be present between “coupled” or “electrically coupled” elements. On the other hand, when an element is referred to as “directly connected” or “directly coupled” to another element, no intervening elements are present. The term “electrically connected” refers to a low-ohmic electrical connection between elements that are electrically connected to each other.

[0031] In this specification, terms such as "first," "second," etc., may be used to describe various elements, but these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes all combinations of one or more of the related enumerated items.

[0032] Exemplary embodiments are described herein with reference to schematic cross-sectional views of idealized or simplified embodiments (and intermediate structures). Thus, differences from the figures may be expected, for example, as a result of manufacturing techniques, tolerances, or both. Therefore, the areas shown in the figures are essentially schematic, and their shapes do not necessarily represent, nor limit, the actual shapes of the areas of the device.

[0033] It should be understood that other embodiments may be used and structural or logical modifications may be made without departing from the scope defined by the claims. The description of embodiments is not limiting. In particular, elements of the embodiments described below may be combined with elements of other embodiments.

[0034] To avoid obscuring the presentation of embodiments of this disclosure, some processing steps or operations may be combined for presentation and explanatory purposes, and in some examples, they may not be described in detail. In other examples, some processing steps or operations may not be described at all. Please understand that the following description focuses rather on notable features or elements of various embodiments of this disclosure.

[0035] The present invention generally relates to semiconductor structures and methods for manufacturing them, and more specifically to temporarily bonding a semiconductor wafer, also called a device wafer, to a carrier wafer ("carrier"), which may be referred to herein as a handler, during processing. Today, wafers with thin profiles offer several advantages, including the ability to utilize through-silicon vias (TSVs), thereby facilitating the miniaturization and integration of devices. However, their thinness compromises their structural integrity. Therefore, handling such wafers using existing process technologies and equipment is not easy. Thus, temporarily bonding a wafer to a thick carrier provides an effective means for backside processing of thin wafers. Conventional wafer processing using carriers may include optically transparent materials such as glass, quartz, or sapphire. An adhesive medium may be used to temporarily bond the device wafer to the handler. After processing (e.g., backside thinning, solder joint formation, or chip dicing, or a combination thereof) has been performed, the semiconductor wafer can be peeled off from the handler.

[0036] During a typical delamination process, visible or ultraviolet lasers can be directed at the adhesive medium through an optically transparent handler to ablate the adhesive medium and release the processed semiconductor wafer from the handler. However, the heat generated from the laser ablation process can also damage the semiconductor wafer. In addition, the use of adhesive to temporarily bond the wafers can leave residue on the handler at the end of the delamination process, which can become contaminated and ultimately lead to process yield problems.

[0037] Therefore, the teachings herein provide a method and structure for temporarily mounting a semiconductor wafer to a carrier wafer during processing, which is not limited by the thermal and structural constraints of using adhesives between the semiconductor wafer and the carrier wafer. The techniques described herein can be implemented in several ways. Exemplary mounting configurations will be described with reference to the following figures.

[0038] Exemplary hard dielectric bonded wafer pair structure Herein, we refer to Figure 1, which is a simplified cross-sectional view 100 of a handler and semiconductor wafer, consistent with an exemplary embodiment. A carrier wafer 804 is connected to a semiconductor wafer 802, and the carrier wafer 804 is located beneath the semiconductor wafer 802. On the top surface of the semiconductor wafer is a first hard dielectric layer 504. A second hard dielectric layer 402 is directly bonded to the top surface of the first dielectric layer 504, together forming a permanently bonded structure 602. In some embodiments, the first and second dielectric layers contain oxides. The second dielectric layer 402 is part of a previous carrier wafer (not shown) used for a previous processing step. The first dielectric layer 504 and the second dielectric layer 402 are not removed; rather, their dielectric layers are used for back-end-of-line (BEOL) wiring 1002 that penetrates the first and second dielectric layers from the top surface of the semiconductor wafer 802 to provide electrical connections to the semiconductor wafer 802.

[0039] Semiconductor wafer 802 may be a typical wafer known in the art and may comprise multiple layers and materials. These layers may comprise semiconductor materials, dielectric materials, and conductive materials. The semiconductor materials may include any known semiconductor materials, such as undoped Si, n-type doped Si, p-type doped Si, single-crystal Si, polycrystalline Si, amorphous Si, Ge, SiGe, SiC, SiGeC, Ga, GaAs, InAs, InP, and all other III / V or II / VI compound semiconductors. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. Typically, this semiconductor wafer may have a thickness of, for example, several hundred microns and may be thinned from 780 μm to approximately 100 μm or less.

[0040] Exemplary process Using the above description of the semiconductor wafer structure coupled to the carrier wafer in Figure 1, it may be useful to describe an exemplary process for manufacturing it. To that end, Figures 2 to 10 illustrate various steps in the manufacturing of a semiconductor structure using carriers, consistent with exemplary embodiments.

[0041] Referring here to Figure 2, a cross-sectional view 200 of a carrier (sometimes referred to herein as a carrier wafer) is given. In one embodiment, the carrier wafer 204 may be composed of a material such as undoped silicon or low-doped silicon that is transparent to infrared (IR) radiation. The carrier 204 may have a height ranging from approximately 400 μm to approximately 1000 μm and an overall diameter that matches the diameter of the corresponding semiconductor wafer to which it will later be bonded. Note that the thickness of the handler may vary depending on its diameter and the requirements of structural stability. In various embodiments, the bottom or top surface of the carrier 204, or both, may include an anti-reflective coating layer (e.g., nitride) 202, 206. The thickness of this anti-reflective coating may be optimized for IR absorption by a separable layer later formed beneath it, as will be described in more detail later.

[0042] Figure 3 shows a semiconductor structure 300 including a separable layer 302, which may be referred to herein as a sacrificial layer. In various embodiments, the separable layer 302 may be aluminum (Al) or any other photothermal conversion release coating (LTHC) layer capable of efficiently absorbing IR radiation (for example, materials with high IR absorption performance are preferred, but materials with low IR absorption performance do not need to be excluded). The separable layer 302 may be deposited on the bottom surface of the carrier 204 (for example, beneath the IR coating 202) using conventional deposition techniques such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), thermal CVD (THCVD), sputtering, or spin-on deposition.

[0043] Figure 4 shows a carrier structure 400 including a hard dielectric layer 402 deposited on the bottom surface of a separable layer 302. For example, the hard dielectric 402 can be deposited by a plasma chemical vapor deposition (PECVD) process (e.g., at 300°C or above). In various embodiments, the hard dielectric layer 402 may include, but is not limited to, silicon nitride, silicon oxynitride, silicon oxycarbonite, silicon carbonitride, boron nitride, boron oxynitride, boron oxycarbonite, boron carbonitride, aluminum nitride, aluminum oxynitride, aluminum oxycarbonite, or aluminum carbonitride, or a combination thereof. Generally, oxide, oxynitride, oxycarbonite, and carbonitride layers having a thermal conductivity equal to or greater than that of silicon-based oxides can be used for wafer bonding (e.g., silicon dioxide). For applications that can withstand temperatures higher than the approximately 400°C process limit for BEOL wiring, such as front-end-of-line (FEOL) applications, diamond films are also supported in this teaching as hard dielectric layers.

[0044] Figure 5 shows the arrangement 500 of the carrier structure 400 of Figure 4 placed on top of the semiconductor wafer 502, consistent with an exemplary embodiment. In various embodiments, the semiconductor wafer 502 may include various circuits and structures consistent with an integrated circuit. The semiconductor wafer 502 includes a hard dielectric layer 504 on the uppermost side facing the dielectric layer 402 of the carrier 404. The hard dielectric layer 504 may include a material substantially similar to the hard dielectric layer 402 of the carrier 404. For example, the hard dielectric layer 504 may be a junction film stack (single or multilayer) of oxide or other insulators directly on the semiconductor wafer 502 by a plasma chemical vapor deposition (PECVD) process at 300°C or higher. In one embodiment, the semiconductor wafer 502 has a separable layer directly beneath the dielectric layer 504, in addition to or as an alternative to the separable layer 302 of the carrier 404.

[0045] Figure 6 shows a semiconductor structure 600 of carriers 404 bonded to a semiconductor wafer 502, consistent with an exemplary embodiment. When carriers 404 are aligned to the semiconductor wafer 502, the hard dielectric 402 of the carriers is permanently bonded to the hard dielectric layer 504 of the semiconductor wafer (e.g., an oxide-to-oxide permanent bond). For example, an oxide (such as TEOS (tetra ethoxy silane)) may have a dangling bond, which is used to effectively bond the two interfaces. In one embodiment, after bonding, there is a thermal annealing cycle of approximately 300°C to 400°C to create a stronger bond between the two different hard dielectric layers, 402 and 504.

[0046] By bonding carrier 404 to the semiconductor wafer, various desired semiconductor processing steps can be performed that would not be possible without the additional structural support provided by carrier 404, due to the vulnerability of semiconductor wafer 504 alone. For example, the width of semiconductor wafer 502 can be significantly reduced by back-side thinning (e.g., from 780 μm to 100 μm). In this regard, Figure 7 shows a semiconductor structure 700 that has undergone a wafer thinning process, consistent with an exemplary embodiment. Various suitable techniques, such as grinding, can be used to thin the semiconductor wafer. In this way, through-silicon vias (TSVs) can be captured and bonded to pads, installed redistribution layers (RDLs), installed flip-chip (C4) compatible structures (e.g., Cu bases / pillars and solder caps 704), etc. A coating layer 702 is present, which may be silicon nitride, and is used to protect and seal the mechanical integrity of the semiconductor wafer 502 and the TSV during the TSV heading and capture process. In other embodiments, the coating layer 702 may also be any other dielectric material having a predetermined level of electrical barrier properties and mechanical strength (e.g., silicon oxynitride, silicon carbonitride, and other similar non-silicon-based materials).

[0047] In some scenarios, the semiconductor structure 700 can be further enhanced by further processing that adds functionality to the circuitry of the semiconductor wafer 802, or adds additional functionality, or both. In this regard, Figure 8 shows a semiconductor structure including a second carrier 804 coupled to the semiconductor structure of Figure 7, consistent with an exemplary embodiment. In various embodiments, the second carrier may be aligned and held together by tape or any suitable adhesive (for example, to maximize flexibility of processing depending on the application, especially if high topography may require the use of an adhesive layer), which may be removable by a subsequent laser process or chemical process or both. In this way, the first carrier 404 can be removed later for further processing while maintaining the structural integrity of the semiconductor wafer 802. Further processing may include, for example, an additional wafer coupled to the semiconductor wafer 802 for electrical communication.

[0048] Figure 9 shows a scenario 900 in which the semiconductor structure 800 of Figure 8 is exposed to infrared (IR) radiation 910, consistent with an exemplary embodiment. For example, IR (i.e., mid-infrared) laser radiation 910 is directed at the separable layer 302 through a first carrier 904, releasing the first carrier 904 from the rest of the structure, i.e., the semiconductor wafer 802, a suitable connector 704, and a second carrier 804. The IR radiation 910 acts to break the junction of the separable layer 302, causing the top surface of the semiconductor wafer 802 to detach from the first carrier 904.

[0049] Figure 10 shows the semiconductor structure 900 of Figure 9 with its top surface carrier 404 removed, consistent with an exemplary embodiment. The remaining separable layer 302 can be removed, for example, by a chemical etching process. It should be noted that the junction structure 602, comprising the top surface dielectric 402 and the bottom surface dielectric 504, which were bonded together in a prior processing step, is not removed. Rather, the junction structure 602 is used to provide support for the usual back-end-of-line (BEOL) processing to provide electrical connections to the circuits of the semiconductor wafer 802. For example, in various embodiments, individual semiconductor devices such as transistors, resistors, inductors, and capacitors can be interconnected with the wiring of the semiconductor wafer 802 by BEOL wiring that penetrates the first hard dielectric 402 and the second hard dielectric 504. Thus, electrical connectivity to the semiconductor wafer 802 can be ensured. In the semiconductor structure 1000 of Figure 10, the hard dielectric 602 is used for the BEOL connection 1002, as previously described in Figure 1. In this way, the top surface of the chip can communicate with the outside of the semiconductor wafer 802 and can accept additional circuitry on top of it (for example, another semiconductor wafer having an electrical connection path to the top surface of the dielectric 402). By repeating this process, a stacked architecture with multiple interconnected levels can be created.

[0050] By using the processes described herein, various processing constraints inherent when adhesives are used are eliminated. For example, processing of the back surface of the 3D wafer after bonding to the first carrier wafer becomes easier. Depending on the application, the second bonding of the carrier wafer may be done using adhesive. For example, processing can be performed using a typical BEOL semiconductor infrastructure that is processed at high temperatures (e.g., 400°C). In fact, when aluminum is used as the separable layer, processing of structures up to 500°C is possible.

[0051] It should be noted that known processes using adhesive layers (instead of dielectric bonding as described herein) typically cannot exceed 300°C. In other words, the processes discussed herein are no longer constrained by the thermal stability limitations of adhesives, which are typically below 300°C. Therefore, if a conventional adhesive were used in the context of the processing performed on the structures in Figures 7-9, the process would be limited by the stability of the adhesive, including its thermal integrity and any contaminants introduced during its removal. For example, concerns regarding adhesive contamination may arise due to the possibility of overflow from the wafer periphery during bonding, which can cause the wafer edge to become sticky and lead to processing failures during wafer handling in semiconductor manufacturing equipment. Avoiding such contamination usually involves extensive use of special cleaning equipment, which increases costs and reduces overall throughput. Therefore, since no adhesive is used in the processes described herein, there are no concerns about contamination specific to the use of adhesives.

[0052] For the sake of brevity, the manufacturing of a single semiconductor wafer is shown, but it will be understood that, based on the teachings herein, any desired number of semiconductor wafers can be stacked. Furthermore, although the term wafer is used for illustrative purposes, it will be understood that diced chips can also be used.

[0053] The methods described above can be used to manufacture integrated circuit chips. The finished integrated circuit chips can be supplied by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips can be mounted in single-chip packages (such as plastic carriers mounted on higher carriers such as motherboards by leads) or multi-chip packages (such as ceramic carriers with either surface-mounted or embedded-mounted wiring, or both). In any case, this chip can then be integrated with other chips, discrete circuit elements, or other signal processing devices, or combinations thereof, as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be anything containing an integrated circuit chip, ranging from low-end applications such as toys to input devices such as displays and keyboards, and advanced computer products with central processing units.

[0054] conclusion The descriptions of the various embodiments of this teaching are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the embodiments disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the embodiments described. The terms used herein have been selected to best describe the principles of these embodiments, their practical application to the technology available on the market, or improvements to the technology, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0055] The above describes what is considered to be the best-case scenario, other examples, or both. However, various modifications can be made thereto, and the subject matter disclosed herein can be practiced in various forms and examples. While only a portion is described herein, it should be understood that the teachings can be applied to a wide range of uses. The following claims are intended to assert any application, modification, and variation that falls within the true scope of these teachings.

[0056] The components, steps, features, objectives, benefits, and advantages described herein are merely illustrative. None of them, nor any discussions relating to them, are intended to limit the scope of protection. While various advantages are described herein, it should be understood that not all embodiments necessarily include all of these advantages. Unless otherwise noted, all measurements, values, grades, locations, scales, sizes, and other specifications described herein, including subsequent claims, are approximate rather than precise. They are intended to have a reasonable range that conforms to the functions they relate to and to the conventions of the art to which they relate.

[0057] Numerous other embodiments are also conceived. These include embodiments having fewer, additional, different, or combinations of components, steps, features, purposes, benefits, and advantages. These also include embodiments that differ in components or steps, or both, in arrangement or sequence, or both.

[0058] While the above has been described in relation to exemplary embodiments, it should be understood that the term “exemplary” means merely an example, not the best or optimal. Except as stated immediately above, nothing described or illustrated, whether or not it is included in the claims, is intended to be, and should not be construed as, a rejection of the invention, of any component, step, feature, subject matter, benefit, advantage, or equivalent.

[0059] The terms and expressions used herein shall be understood to have the ordinary meanings given to them in relation to their respective areas of study and research, unless otherwise specifically defined herein. Relational terms such as "first" and "second" may be used solely to distinguish one entity or act from another, and do not necessarily require or suggest any actual relationship or order between such entities or acts. The terms "comprise," "comprising," or other variations are intended to be subject to non-exclusive inclusion, such that a process, method, article, or apparatus having a list of elements may include not only those elements, but other elements not expressly listed or elements specific to such process, method, article, or apparatus. An element beginning with "a" or "an" does not, without further constraint, exclude the existence of additional identical elements in the processes, methods, articles, or apparatus constituting that element.

[0060] This abstract of the disclosure is provided to enable readers to quickly grasp the essence of the technical disclosure. It is presented with the understanding that the abstract is not intended to be used to interpret or limit the scope or meaning of the claims. Furthermore, it is found that, for the purpose of streamlining the disclosure, various features are grouped together in various embodiments in the forms for carrying out the invention described herein. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments have more features than those explicitly described in each claim. Rather, as reflected in the following claims, the subject matter of the invention lies in fewer features than all the features of a single disclosed embodiment. Therefore, the following claims stand independently as subject matter claimed individually and are incorporated into the forms for carrying out the invention herein.

Claims

1. Carrier wafers and, A semiconductor wafer bonded to the uppermost surface of the carrier wafer, A first dielectric layer on the uppermost surface of the semiconductor wafer, A second dielectric layer is directly bonded to the uppermost surface of the first dielectric layer, One or more back-end-of-line (BEOL) wirings extending from the top surface of the semiconductor wafer through the first and second dielectric layers and Equipped with, A semiconductor structure comprising the first and second dielectric layers being diamond films.

2. The semiconductor structure according to claim 1, wherein the first and second dielectric layers include an oxide.

3. The semiconductor structure according to claim 1, wherein the first and second dielectric layers have a thermal conductivity equal to or greater than that of silicon oxide.

4. The semiconductor structure according to claim 1, wherein the width of the semiconductor wafer is thinned to 50 μm to 100 μm.

5. The semiconductor structure according to claim 1, wherein the carrier wafer includes glass.

6. The semiconductor structure according to claim 1, wherein the junction between the first dielectric layer and the second dielectric layer is an oxynitride junction.

7. The semiconductor structure according to claim 1, wherein the junction between the first dielectric layer and the second dielectric layer is a nitride junction.

8. A method for manufacturing a semiconductor structure, To provide the first carrier wafer, Forming a separable layer capable of absorbing infrared (IR) radiation beneath the first carrier wafer, A first dielectric layer comprising a diamond film is formed below the separable layer, Forming a second dielectric layer comprising a diamond film on the uppermost surface of a semiconductor wafer, The first dielectric layer is directly bonded to the second dielectric layer, In order to provide an electrical connection to the semiconductor wafer, a connector is formed on the bottom surface of the semiconductor wafer, Connecting a second carrier wafer to the connector on the bottom surface of the semiconductor wafer, The first carrier wafer is separated from the semiconductor wafer by degrading the separable layer by transmitting infrared (IR) radiation into the first carrier wafer, The semiconductor wafer is provided with back-end-of-line (BEOL) wiring that penetrates the first and second dielectric layers from the uppermost surface. A method that includes this.

9. The method according to claim 8, wherein the separable layer comprises aluminum (Al).

10. The method according to claim 8, wherein the separable layer is a photothermal release coating (LTHC) layer.

11. The method according to claim 8, wherein the first and second dielectric layers include an oxide.

12. The method according to claim 8, further comprising performing thermal annealing after direct bonding of the first dielectric layer and the second dielectric layer to form a stronger bond between the first dielectric layer and the second dielectric layer.

13. The method according to claim 8, further comprising thinning the semiconductor wafer after the direct bonding of the first dielectric layer with the second dielectric layer.

14. The method according to claim 13, wherein the thinning of the semiconductor wafer results in a thickness of 50 μm to 100 μm.

15. The method according to claim 8, further comprising coating at least one of the top surface or bottom surface of the carrier wafer with an anti-reflective layer.

16. The method according to claim 15, wherein the anti-reflective layer includes a nitride.

17. The method according to claim 8, wherein the second carrier wafer is connected to the semiconductor wafer with an adhesive.

18. The method according to claim 8, further comprising separating the first carrier wafer from the semiconductor wafer, and then removing the residue of the separable layer by chemical etching of the separable layer.

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