memory devices

Abstract

To simplify a manufacturing process, reduce a size of a three-dimensional memory device, and improve a space availability of a chip in which the three-dimensional memory device is formed.SOLUTION: A memory device comprises: a substrate; a stack structure; at least one gate wire slit dividing the stack structure into at least two parts. The stack structure includes: a plurality of gate material layers and a plurality of insulation layers that are alternately arranged; and a plurality of two or more connection parts conductively connecting each gate material layer on a common one of a plurality of tiers. The plurality of tiers contains: a first tier; and a second tier that is a tier above the first tier. The two or more connection parts conductively connecting the gate material layers of the first tier contains the connection part having a length in a first direction being shorter than a length in the first direction of the two or more connection parts conductively connecting the gate material layer of the second tier.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] The present invention relates to a memory device and a method of forming the same.

[0002] Cross-Reference to Related Applications The present application claims priority from Chinese Patent Application No. 201710132422.8 filed on March 7, 2017, the entire content of which is incorporated herein by reference.

Background Art

[0003] Flash memory devices have been developing rapidly. Flash memory devices can retain data for a considerably long time without power supply, and have advantages such as high integration level, fast access, easy erasure and rewriting. To further improve bit density and reduce the cost of flash memory devices, three-dimensional NAND flash memory devices have been developed.

[0004] A three-dimensional NAND flash memory device comprises a stack of gate electrodes disposed on a substrate, wherein a plurality of semiconductor channels pass through word lines, and the word lines intersect the substrate. The lower gate electrode functions as a lower select gate. The upper gate electrode functions as an upper select gate. The word line / gate electrode between the upper select gate electrode and the lower gate electrode functions as a word line. The intersection of a word line and a semiconductor channel forms a memory cell. The upper select gate is connected to the word line for row selection, and the lower select gate is connected to a bit line for column selection.

Summary of the Invention

[0005] Accordingly, embodiments of three-dimensional memory device architectures and manufacturing methods are disclosed herein. The disclosed structures and methods offer many advantages, including, but not limited to, simplification of the manufacturing process, reduction in the size of the three-dimensional memory device, and improved space usefulness of the chip on which the three-dimensional memory device is formed.

[0006] In some embodiments, a three-dimensional memory device includes a substrate comprising adjacent device regions and connection regions, a plurality of separate stack structures within the device regions and connection regions, each stack structure comprising a plurality of stack word lines (e.g., gate electrodes), and isolation layers (e.g., gate line slits) on the substrate portions between adjacent stack structures. The three-dimensional memory device also includes connection structures located on the connection regions, which conductively connect adjacent stack structures. The connection structures comprise a plurality of repeating conductive connection portions, each of which two ends of the conductive layer connects a word line of the same height in an adjacent stack structure. The three-dimensional memory device further comprises a plurality of contact vias on the upper surface of each word line of the height. Each contact via is conductively connected to the word line it is contacting, another word line of the same height as the word line it is contacting, and a conductive connection portion of the same height as the word line it is contacting.

[0007] In some embodiments, the conductive connection portion is made from the same material as the word wire.

[0008] In some embodiments, the conductive connection parts and word wires are made from one or more of tungsten, aluminum, and copper.

[0009] In some embodiments, the stack structure further includes a first insulating portion between adjacent gate structures, and the connection structure further includes a second insulating portion between adjacent conductive connection portions.

[0010] In some embodiments, the first insulating portion and the second insulating portion are made from silicon oxide.

[0011] In some embodiments, the substrate further includes channel regions adjacent to one or more of the connection regions and device regions. The stack structure extends to a portion of the substrate in the channel region. In some embodiments, the three-dimensional memory device further includes a plurality of semiconductor channels on the portion of the substrate in the channel region, the semiconductor channels penetrating the stack structure.

[0012] In some embodiments, the three-dimensional memory device further includes a gate dielectric layer between the word lines and the semiconductor channel.

[0013] In some embodiments, a method for forming a three-dimensional memory device comprises providing a substrate, the substrate comprising adjacent device regions and connection regions, and forming a plurality of separate stack structures within the device regions and connection regions, the stack structures comprising a plurality of stack word lines, and forming isolation layers (e.g., gate line slits) on the substrate portions between adjacent stack structures. The method also comprises forming connection structures located on the connection regions and conductively connecting adjacent stack structures. The connection structures comprise a plurality of repeating conductive connection portions, the two ends of each conductive layer each connecting word lines of the same height in adjacent stack structures. The method further comprises forming a plurality of contact vias on the upper surface of each word line of each height. Each contact via is conductively connected to the word line it is contacting, another word line of the same height as the word line it is contacting, and a conductive connection portion of the same height as the word line it is contacting.

[0014] In some embodiments, the stack structure further includes insulating portions between adjacent gate structures, and the connection structure further includes insulating portions between adjacent conductive connection portions. In some embodiments, the operation of forming the stack structure and insulating portions includes forming a composite structure on portions of the substrate in the device region and the connection region. The composite structure includes a plurality of alternately arranged insulating portions and a plurality of sacrificial layers. The composite structure can be patterned to remove portions of the composite structure in the device region and form vertical trenches, which extend through the composite structure in a direction perpendicular to the substrate. The direction in which the vertical trenches extend can be perpendicular to the boundary between the device region and the connection region. Furthermore, isolation layers (e.g., gate line slits) can be formed within the vertical trenches. After the isolation layers are formed, sacrificial layers in the device region and the connection region can be removed, and horizontal trenches can be formed between adjacent insulating portions. Word line layers can be formed within the horizontal trenches in the device region and the connection region. Portions of the word line layers in the device region and portions of the word line layers in the connection region adjacent to the isolation layers can form word lines. The word line layers in the connection region can be connected to form conductive connection portions.

[0015] In some embodiments, patterning of the composite structure includes forming a mask layer on the composite structure, the mask layer covering a portion of the composite structure in the connection region and a portion of the composite structure in the device region. The mask layer can be used as an etching mask for etching the composite structure.

[0016] In some embodiments, etching of the composite structure includes dry etching and / or wet etching.

[0017] In some embodiments, this method further includes forming a gate dielectric layer on the bottom and side walls of a portion of the horizontal trenches in the device region and connection region before forming the word lines.

[0018] In some embodiments, the substrate further includes channel regions adjacent to one or more of the connection regions and device regions. The stack structure extends to a portion of the substrate in the channel region. In some embodiments, before removing the sacrificial layers in the device regions and connection regions, the method further includes forming a plurality of semiconductor channels on the portion of the substrate in the channel structure, the semiconductor channels penetrating the stack structure.

[0019] In some embodiments, the insulating portion comprises silicon oxide, the sacrificial layer comprises polysilicon, polygermanium, and / or silicon nitride, and the ward wire layer comprises tungsten, aluminum, and / or copper.

[0020] In some embodiments, removing the sacrificial layer within the device region and connection region includes isotropic dry etching and / or wet etching.

[0021] In some embodiments, forming word lines involves chemical vapor deposition (CVD).

[0022] In some embodiments, the conductive connection portion includes tungsten, aluminum, and / or copper.

[0023] Compared to prior art, this disclosure offers the following advantages.

[0024] The three-dimensional memory device provided by this disclosure allows conductive connection portions to connect word lines of the same height within adjacent stack structures, thereby obtaining electrical connections between word lines of the same height within adjacent stack structures. Thus, word lines of the same height within adjacent stack structures can share the same contact vias, and as a result, these word lines can be connected to external circuits. Therefore, the disclosed method can reduce the number of contact vias, simplify the manufacturing of the three-dimensional memory device, reduce the size of the memory device, and improve chip space utilization.

[0025] By using the method for forming a three-dimensional memory device provided by the present disclosure, a connection structure can be formed on a portion of a substrate in a connection region. The connection structure can connect adjacent stack structures. Electrical connection of word lines at the same level in adjacent stack structures can be achieved through the stack structure, and the word lines at the same level in adjacent stack structures can share the same contact via, as a result of which these word lines can be connected to an external circuit. Therefore, the disclosed method can reduce the number of contact vias, simplify the manufacturing of three-dimensional memory devices, reduce the size of memory devices, and improve chip space utilization.

[0026] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with the common practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily expanded or reduced for clarity of illustration and description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] [Figure 1] It is a diagram of a three-dimensional memory device. [Figure 2A] It is a top view of a three-dimensional memory structure at different stages of an exemplary manufacturing process according to some embodiments. [Figure 2B] It is a cross-sectional view of the three-dimensional memory structure of FIG. 2A according to some embodiments. [Figure 3A] It is a top view of a three-dimensional memory structure at different stages of an exemplary manufacturing process according to some embodiments. [Figure 3B] It is a cross-sectional view of the three-dimensional memory structure of FIG. 3A according to some embodiments. [Figure 4A] It is a top view of a three-dimensional memory structure at different stages of an exemplary manufacturing process according to some embodiments. [Figure 4B] It is a cross-sectional view of the three-dimensional memory structure of FIG. 4A according to some embodiments. [Figure 5A] This is a top view of a three-dimensional memory structure at different stages of an exemplary manufacturing process according to several embodiments. [Figure 5B] This is a cross-sectional view of the three-dimensional memory structure shown in Figure 5A, according to several embodiments. [Figure 6A] This is a top view of a three-dimensional memory structure at different stages of an exemplary manufacturing process according to several embodiments. [Figure 6B] This is a cross-sectional view of the three-dimensional memory structure shown in Figure 6A, according to several embodiments. [Figure 7A] This is a top view of a three-dimensional memory structure at different stages of an exemplary manufacturing process according to several embodiments. [Figure 7B] This is a cross-sectional view of the three-dimensional memory structure shown in Figure 7A, according to several embodiments. [Figure 7C] This is another cross-sectional view of the three-dimensional memory structure of Figure 7A, according to several embodiments. [Figure 8A] This is a top view of a three-dimensional memory structure at different stages of an exemplary manufacturing process according to several embodiments. [Figure 8B] This is a cross-sectional view of the three-dimensional memory structure shown in Figure 8A, according to several embodiments. [Figure 9A] This is a top view of a three-dimensional memory structure at different stages of an exemplary manufacturing process according to several embodiments. [Figure 9B] This is a cross-sectional view of the three-dimensional memory structure shown in Figure 9A, according to several embodiments. [Figure 10] This is a top view of another three-dimensional memory structure according to several embodiments. [Figure 11] This is a diagram of a manufacturing process for forming a three-dimensional memory structure according to several embodiments. [Modes for carrying out the invention]

[0028] While specific configurations and arrangements are described, it should be understood that these are for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used in a variety of other applications.

[0029] References in this specification such as “one embodiment,” “one example,” “exemplary embodiment,” and “several embodiments” indicate that the embodiments described may include certain features, structures, or characteristics, but it should be noted that not all embodiments necessarily include certain features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, if certain features, structures, or characteristics are described in relation to one embodiment, it will be within the knowledge of those skilled in the art that such features, structures, or characteristics may also be derived in relation to other embodiments, whether explicitly stated or not.

[0030] In general, terms can be understood, at least partially, from their use in context. For example, as used herein, the term “one or more” may, at least partially depending on the context, be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” and “the” can likewise be understood, at least partially depending on the context, to convey either a singular or plural usage.

[0031] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest sense, so that “on” means not only being “directly above” something, but also being “above” something with an intermediate feature or layer in between, and so that “above” or “over” means not only being “above” something or “on” something, but also being “above” something or “on” something without an intermediate feature or layer in between (i.e., directly above something).

[0032] Furthermore, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to facilitate explanation in describing the relationship between one element or feature and another element or feature, as shown in the figures. Spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or in other directions), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0033] As used herein, the term “substrate” refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate can be made from non-conductive materials such as glass, plastic, or sapphire wafers.

[0034] As used herein, the term “layer” refers to a portion of a material that includes a region of thickness. A layer may extend over the entirety of a structure that is underlying or above it, or it may have a smaller extent than the extent of the underlying or above it. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer and may contain one or more layers, and / or have one or more layers above, above, and / or below the substrate. A layer may contain multiple layers. For example, an interconnection layer may include one or more conductive layers and contact layers (with contacts, interconnection lines, and / or vias formed within the interconnection layer), and one or more dielectric layers.

[0035] As used herein, the term “nominal” refers to a desired or target value of a characteristic or parameter of a component or process operation, set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term “approximately” indicates a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of the subject. Based on a particular technology node, the term “approximately” may indicate a value of a particular quantity that varies, for example, within 10 to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0036] As used herein, the term “3D memory device” refers to a semiconductor device having vertically oriented strings of memory cell transistors (such as NAND strings, referred herein as “memory strings”) on a transversely oriented substrate, such that the memory strings extend perpendicularly to the substrate. As used herein, the term “perpendicular / vertically oriented” means nominally perpendicular to the outer surface of the substrate.

[0037] Trends in the 3D NAND memory industry include reducing device dimensions and simplifying manufacturing processes. In 3D NAND memory devices, memory cells for storing data are embedded in a stack of word lines (control gate electrodes) and semiconductor channels formed through the stack. Each word line is individually connected to a metal contact via, which is further connected to metal interconnects, bit lines, and / or external circuits (e.g., control circuits), so that writing and erasing data to memory cells can be controlled from the external circuit. Therefore, the number of metal contact vias is often equal to the number of word lines. As the demand for storage capacity increases, a larger number of memory cells, formed by an increased number of word lines and semiconductor channels, are formed within NAND memory devices. Therefore, more metal contact vias need to be formed to connect to the word lines. On the other hand, the size of NAND memory devices continues to decrease. Therefore, it is more difficult to form an increased number of metal contact vias (i.e., metal interconnects as well) in the reduced device space. For example, to accommodate an increased number of metal contact vias in a smaller NAND memory device, the manufacturing of word lines and metal contact vias must be adapted to the reduced dimensions of these components so that the desired number of word lines and metal contact vias can be formed within the smaller NAND memory device. As a result, manufacturing smaller NAND memory devices becomes more difficult, and the space within the smaller NAND memory device is not utilized efficiently.

[0038] In this disclosure, for the sake of clarity, the term “layer” is used to refer to elements that are substantially the same height along the vertical direction. For example, a word line and the gate dielectric layer beneath the word line can be referred to as a “layer,” a sacrificial layer and the insulating layer beneath the sacrificial layer can both be referred to as a “layer,” a word line and the insulating layer beneath the word line can both be referred to as a “layer,” and word lines that are substantially the same height can be referred to as a “word line layer,” and so on.

[0039] Figure 1 shows block 100 of a three-dimensional NAND flash memory device. The flash memory device includes a substrate 101, an insulating layer 103 on the substrate 101, a layer of lower selective gate electrodes 104 on the insulating layer 103, and multiple layers of control gate electrodes 107 stacked on top of the bottom selective gate electrodes 104. The flash memory device also includes a layer of upper selective gate electrodes 109 on top of the stack of control gate electrodes 107, doped source line regions 120 of the portion of the substrate 101 between adjacent lower selective gate electrodes 104, as well as a semiconductor channel 114 passing through the upper selective gate electrodes 109, control gate electrodes 107, lower selective gate electrodes 104, and the insulating layer 103. The semiconductor channel 114 includes a memory film 113 on the inner surface of the semiconductor channel 114 and a core-filling film 115 surrounded by the memory film 113 within the semiconductor channel 114. The flash memory device further includes a plurality of bit lines 111 connected to a semiconductor channel 114 on an upper selective gate electrode 109, and a plurality of metal interconnects 119 connected to the gate electrode through a plurality of metal contacts 117. Insulating layers between adjacent layers of the gate electrode are not shown in Figure 1. The gate electrode includes an upper selective gate electrode 109, a control gate electrode 107 (also called a word line, for example), and a lower selective gate electrode 104.

[0040] In Figure 1, for illustrative purposes, three layers of control gate electrodes 107-1, 107-2, and 107-3 are shown together with a single-layer upper selection gate electrode 109 and a single-layer lower selection gate electrode 104. Each layer of gate electrodes has substantially the same height on the substrate 101. The gate electrodes of each layer are separated by gate line slits 108-1 and 108-2 that pass through the stack of gate electrodes. Each gate electrode of the same layer is conductively connected to a metal interconnect 119 through a metal contact via 117. That is, the number of metal contacts formed on the gate electrodes is equal to the number of gate electrodes (i.e., the sum of all upper selection gate electrodes 109, control gate electrodes 107, and lower selection gate electrodes 104). Furthermore, the same number of metal interconnects are formed to connect to each metal contact via. As the dimensions of the flash memory device decrease, it becomes more difficult to form metal contact vias and metal interconnects that can fit into the reduced space of the device.

[0041] This disclosure describes a three-dimensional NAND memory device in which one or more word lines of the same hierarchy within a block are conductively connected together, and the connected word lines are conductively connected to shared metal contact vias, thereby reducing the number of metal contact vias and metal interconnects. The disclosed method and structure simplify the manufacturing process for forming a three-dimensional NAND memory device. In particular, the advantage of conductively connecting word lines of the same hierarchy is that the number of metal interconnects connected to control signals is greatly reduced. In other words, within the same hierarchy, connected word lines can share the same metal interconnects. Thus, the formed three-dimensional NAND memory device can reduce the number of metal contact vias and metal interconnects, with the total number of metal contact vias being less than the total number of word lines. Therefore, the manufacturing of the three-dimensional NAND memory device can be simplified, the dimensions of the memory device can be further reduced, and the space within the memory device can be utilized more efficiently.

[0042] For illustrative purposes, similar or identical parts of a three-dimensional NAND device are labeled using the same reference numerals. However, the reference numerals are used solely to distinguish relevant parts of embodiments for carrying out the invention and do not indicate any similarity or difference in function, configuration, or location. Structures 200–1000 shown in Figures 2–10 are each parts of a three-dimensional NAND memory device. Other parts of the memory device are not shown for the sake of clarity. While a three-dimensional NAND device is used as an example, the disclosed structures can also be applied to similar or different semiconductor devices in various applications and designs, for example, to reduce the number of metal connections or wiring. The specific applications of the disclosed structures should not be limited by the embodiments of this disclosure. For illustrative purposes, word lines and gate electrodes are used interchangeably to illustrate this disclosure.

[0043] Figures 2A and 2B show exemplary structures 200 for forming a three-dimensional memory structure according to several embodiments. Figure 2A is a top view 201 of the structure 200, and Figure 2B is a cross-sectional view 202 of the structure 200 along the 2-2' direction. In some embodiments, the structure 200 includes a base substrate 210 and a material layer 240 on the base substrate 210. The base substrate 210 can provide a platform for forming subsequent structures. The material layer 240 may include alternating stacks (e.g., pairs / stacks of dielectric layers) having alternatingly arranged first material / elements 211' and second material / elements 212'. The material layer 240 can be used to form subsequent word lines on the base substrate 210. For illustrative purposes, three layers / pairs of first material 211' / second material 212' are shown to illustrate this disclosure. In various applications and designs, the material layer 240 can include any appropriate number of layers / pairs of the first / second material stacked together, depending on the design of the three-dimensional memory device. For example, the material layer 240 can subsequently include 64 layers / pairs of the first / second material stacked together, forming a 64-layer word line within the three-dimensional memory device.

[0044] In some embodiments, the base substrate 210 includes any suitable material for forming a three-dimensional memory device. For example, the base substrate 210 may include silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), glass, gallium nitride, gallium arsenide, and / or other suitable III-V compounds.

[0045] In some embodiments, the material layer 240 includes an alternating stack of sacrificial material layers 211' (i.e., a first element or first material) and insulating material layers 212' (i.e., a second element or second material) arranged vertically (along the z-axis) on the base substrate 210. For illustrative purposes, the sacrificial material layers 211' and the insulating material layers 212' below the corresponding sacrificial layers are referred to as material pairs or material pairs of the same hierarchy. Each of the sacrificial material layers 211' may have the same thickness or different thicknesses. Each of the insulating material layers 212' may have the same thickness or different thicknesses. In some embodiments, the material layer 240 includes more sacrificial material layers and / or more insulating material layers than the material pairs. Each of the additional one or more sacrificial material layers may have the same or different thicknesses as the sacrificial material layers 211' of the material pairs, and each of the additional one or more insulating material layers may have the same or different thicknesses as the insulating material layers 212' of the material pairs. In some embodiments, the sacrificial material layer 211' is subsequently removed to deposit gate material for forming word lines. In some embodiments, the sacrificial material layer 211' comprises any suitable material different from the insulating material layer 212'. For example, in various embodiments, the sacrificial material layer 211' may include polycrystalline silicon, silicon nitride, polycrystalline germanium, and / or polycrystalline germanium silicon. In some embodiments, the sacrificial material layer 211' comprises silicon nitride. The insulating material layer 212' may include any suitable insulating material, such as silicon oxide. The material layer 240 can be formed by alternately depositing the insulating material layer 212' and the sacrificial material layer 211' on the base substrate 210. For example, the insulating material layer 212' can be deposited on the base substrate 210, the sacrificial material layer 211' can be deposited on the insulating material layer 212', and so on. The deposition of the sacrificial material layer 211' and the insulating material layer 212' may include any suitable deposition method such as CVD, physical vapor deposition (PVD), plasma CVD (PECVD), sputtering, metal-organic compound chemical vapor deposition (MOCVD), and / or atomic layer deposition (ALD).In some embodiments, the sacrificial material layer 211' and the insulating material layer 212' are formed by CVD, respectively.

[0046] For illustrative purposes, the structure 200 (e.g., base substrate 210) is divided into three regions, namely regions A, B, and C. In the subsequent manufacturing of the three-dimensional memory structure, word lines (gate electrodes) are formed through regions A (e.g., device region), B (e.g., connection region), and C (e.g., array region) along a horizontal direction (e.g., y-axis) substantially parallel to the upper surface of the base substrate 210, semiconductor channels (e.g., also known as memory strings) are formed substantially within region C, and connection portions that electrically connect the word lines are formed substantially within region B. It should be noted that regions A, B, and C are presented only for the sake of clarity and are not intended to indicate the physical division of the structure 200 or its dimensions.

[0047] Figures 3A and 3B show exemplary structures 300 for forming a three-dimensional memory device according to several embodiments. Figure 3A is a top view 301 of the structure 300, and Figure 3B is a cross-sectional view 302 of the structure 300 along the 3-3' direction. The structures shown by Figures 3A and 3B may be referred to as “staircase structures” or “stepped cavity structures.” The terms “staircase structure,” “stepped cavity structure,” etc., refer to structures having step-like surfaces. In this disclosure, “stepped surface” refers to a set of surfaces including at least two horizontal planes (e.g., along the xy plane) and at least two (e.g., first and second) vertical planes (e.g., along the z axis), such that each horizontal plane is adjacent to a first vertical plane extending upward from a first edge of the horizontal plane and to a second vertical plane extending downward from a second edge of the horizontal plane. “Step” or “staircase” refers to a vertical shift in the height of the set of adjacent surfaces.

[0048] The stepped structure, referring to Figures 3A and 3B, can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped structure changes in a step-like manner as a function of the vertical distance from the top surface of the structure 300. In some embodiments, the structure 300 is formed from the structure 200 by repeatedly etching the sacrificial material layer 211' and insulating material layer 212' of the material layer 240, for example, along the vertical direction (i.e., the z-axis) using a mask. For illustrative purposes, a structure formed by etching the material layer 240 on a base substrate 210 is referred to as a stack 240'. Thus, as shown in Figures 3A and 3B, the structure 300 can have multiple sacrificial layers (e.g., 211-1 to 211-4) and multiple insulating layers (e.g., 212-1 to 212-4). Each sacrificial layer 211 can form a pair or layer with an adjacent underlying insulating layer having substantially the same length / shape along the y-axis. For example, sacrificial layer 211-1 and insulating layer 212-1 form a first layer, sacrificial layer 211-2 and insulating layer 212-2 form a second layer, and so on. Etching of each pair of sacrificial and insulating layers can be carried out in one etching process or in different etching processes. After the formation of the stepped surface, the mask can be removed, for example, by ashing. In some embodiments, multiple photoresist layers and / or multiple etching processes are used to form the stepped surface. As shown in Figure 3A, in structure 300, the sacrificial layers of each layer (i.e., 211-1 to 211-4) are exposed along the z-axis. In various embodiments, within each pair / layer, the insulating layer 212 may also be on top of the sacrificial layer 211. In this case, an additional insulating layer can be placed between the material layer 240 and the base substrate 210. The manufacturing process for forming the word lines may be similar to the manufacturing process provided in this disclosure. Subsequently, metal contact vias that electrically connect to the word lines can be formed by penetrating the insulating layers of each layer and forming contact with the word lines below. Details of the manufacturing process can be found in this disclosure and are omitted here.

[0049] Figures 4A and 4B show exemplary structures 400 for forming a three-dimensional memory device according to several embodiments. Figure 4A is a top view 401 of the structure 400, and Figure 4B is a cross-sectional view 402 of the structure 400 along the 4-4' direction. In some embodiments, the structure 400 includes a plurality of semiconductor channels 220 formed within region C. The semiconductor channels 220 can be distributed as arrays along the x-axis, with each array separated by a suitable distance, for example, Δx. Δx can be any suitable distance depending on the design / layout of the three-dimensional memory device. Each array of semiconductor channels 220 can have the same or different number of semiconductor channels 220. Referring to Figure 4A for illustrative purposes, in this disclosure, each array includes four semiconductor channels 220, forming a 2×2 array array. The semiconductor channels 220 can be formed onto the base substrate 210 through a stack 240 substantially along the z-axis for the subsequent formation of the source and / or drain of the three-dimensional memory device. The semiconductor channel 220 and the word lines subsequently formed can, for example, form memory cells in a three-dimensional memory device for storing data.

[0050] Each semiconductor channel 220 may have a substantially columnar shape along the z-axis and may include multiple layers surrounding each other (not shown in the figures of this disclosure). For example, a semiconductor channel 220 may include a dielectric core positioned substantially at the center of the semiconductor channel 220 along the z-axis. The dielectric core may be surrounded by a semiconductor channel film. The semiconductor channel film may be surrounded by a memory film. The dielectric core, semiconductor channel film, and memory film may each include one or more layers and together fill the channel holes to form the semiconductor channel 220. In some embodiments, channel holes can be formed by patterning the stack 240' using a mask, for example, by etching the portion of the stack 240' exposed by the patterned mask using a suitable etching process such as dry etching and / or wet etching. The channel holes can penetrate the stack 240 and substantially enter the base substrate 210. The mask can be removed after the channel holes have been formed.

[0051] For example, the memory film is formed on the sidewalls of the channel holes and can be in contact with the sidewalls. In some embodiments, the memory film may include one or more block dielectric layers on the sidewalls of the channel holes to insulate other layers within the channel holes from the stack 240' surrounding the channel holes. The memory film may also include a storage unit layer (memory layer) surrounded by block dielectrics on top of the block dielectric layers to trap charges and form multiple charge storage regions along the z-axis. The memory film may also include a tunnel layer (e.g., a tunnel dielectric) surrounded by the memory layers on top of the memory layers. Charge tunneling can be performed through the tunneling layer under appropriate electrical bias. In some embodiments, depending on the operation of the three-dimensional memory device, charge tunneling can be performed through hot carrier injection or by charge transfer induced by Fowler-Nordheim tunneling.

[0052] One or more block dielectric layers may include a first block layer comprising a dielectric metal oxide layer having a relatively high dielectric constant. The term "metal oxide" may include metallic elements as well as nonmetallic elements such as oxygen, nitrogen, and other suitable elements. For example, the dielectric metal oxide layer may include aluminum oxide, hafnium oxide, lanthanum oxide, yttrium oxide, tantalum oxide, silicates, nitrogen-doped compounds, alloys, and the like. The first block layer may be deposited by, for example, CVD, ALD, pulsed laser deposition (PLD), liquid mist chemical deposition, and / or other suitable deposition methods.

[0053] One or more block dielectric layers may also include a second block layer comprising another dielectric layer on top of a dielectric metal oxide. The other dielectric layer may be different from the dielectric metal oxide layer. The other dielectric layer may include silicon oxide, a dielectric metal oxide having a different composition from the first block layer, silicon oxynitride, silicon nitride, and / or other suitable dielectric materials. The second block layer may be deposited, for example, by low-pressure chemical vapor deposition (LPCVD), ALD, CVD, and / or other suitable deposition methods. In some embodiments, one or more block dielectric layers include silicon oxide formed by CVD.

[0054] The storage unit layer may be formed continuously on one or more block dielectric layers. The storage unit layer may include charge trapping material, such as dielectric charge trapping material (e.g., silicon nitride) and / or conductive material (e.g., doped polysilicon). In some embodiments, the dielectric charge trapping material includes silicon nitride and can be formed by CVD, ALD, PVD, and / or other suitable deposition methods.

[0055] The tunnel layer can be formed continuously on top of the memory layer. The tunnel layer may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxide, dielectric metal oxynitride, dielectric metal silicate, alloy, and / or other suitable materials. The tunnel layer can be formed by CVD, ALD, PVD, and / or other suitable deposition methods. In some embodiments, the tunnel layer includes silicon oxide formed by CVD.

[0056] A semiconductor channel film can be formed continuously on a tunnel layer. The semiconductor channel film may include one or more layers of any suitable semiconductor material, such as silicon, silicon-germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and / or other suitable semiconductor materials. The semiconductor channel film can be formed by a suitable deposition method, such as metal-organic chemical vapor deposition (MOCVD), LPCVD, CVD, and / or other suitable deposition methods. In some embodiments, the semiconductor channel film is formed by depositing a layer of amorphous silicon using CVD, followed by an annealing process to convert the amorphous silicon to single-crystal silicon. In some embodiments, other amorphous materials can be annealed and crystallized to form a semiconductor channel film.

[0057] A dielectric core is formed on a semiconductor channel film and can fill the space at the center of the channel pore. The dielectric core may contain suitable dielectric materials such as silicon oxide and / or organosilicate glass. The dielectric core can be formed by a suitable conformal deposition method (e.g., LPCVD) and / or a self-planar deposition method (e.g., spin coating). In some embodiments, the dielectric core contains silicon oxide and is formed by LPCVD.

[0058] In various embodiments, the number of layers, the method of forming these layers, and the specific order in which these layers are formed may vary depending on the different design and should not be limited by embodiments of this disclosure.

[0059] Figures 5A and 5B show structures 500 for forming a three-dimensional memory device according to several embodiments. Figure 5A is a top view 501 of structure 500, and Figure 5B is a cross-sectional view 502 of structure 500 along the 5-5' direction. Structure 500 includes a plurality of insulating trenches or vertical trenches, each formed between two arrays of semiconductor channels 220 substantially along the y-axis to divide a stack 240' into a plurality of fingers, each finger extending substantially along the y-axis. In this disclosure, the term “vertical” means “along the z-axis” or “substantially perpendicular to the x-y plane.” Subsequently, word lines can be formed within each finger. A vertical trench may include one or more openings along the y-axis. The openings vertically form sub-openings aligned in different layers, allowing adjacent fingers of the same layer to be connected through the sub-openings in the layer by material connecting portions (i.e., the openings are filled with portions of material layer 240). Sub-openings formed from the same opening can be aligned with each other along the x, y, and z axes (i.e., having the same projected area on the upper surface of the base substrate 210). Subsequently, the vertical trench can be filled with appropriate insulating material to form a gate line slit, which is also referred to as an insulating spacer. That is, word lines subsequently formed within adjacent fingers are insulated at the locations filled with insulating material and connected at the locations of the openings. In other words, two adjacent word lines of the same hierarchical level can be electrically connected through a connection portion formed by one or more openings (a connection portion that is not filled with insulating material but is filled with gate metal material).

[0060] For illustrative purposes, two adjacent vertical trenches 221' and 222' are shown in Figures 5A and 5B. As shown in Figure 5A, vertical trench 221' includes an opening 223' formed through stack 240', and vertical trench 222' includes an opening 224' formed through stack 240'. The openings 223' and 224' can be formed within region B, and along the y-axis, vertical trench 221' can be divided into a first portion 221'-1 and a second portion 221'-2, and vertical trench 222' can be divided into a first portion 222'-1 and a second portion 222'-2. The two adjacent vertical trenches 221' and 222' divide the structure 500 into fingers 1, 2, and 3, each containing an array of semiconductor channels 220. The first portions 221'-1 and 222'-1 of the vertical trench are formed within region C to divide the array of semiconductor channels 220 into different fingers along the x-axis, and the second portions 221'-2 and 222'-2 are formed within region A to divide the subsequently formed word lines into different fingers. The array of semiconductor channels 220, together with the word lines subsequently formed within fingers 1, 2, and 3, can each form a memory cell. The sacrificial layer / insulating layer pairs of each layer of structure 500 are connected through openings. For example, Figure 5B shows a cross-sectional view of structure 500 between fingers 2 and 3. For fingers 2 and 3, the sacrificial layer 211-1 / insulating layer 212-1 pairs are connected through opening 224'. Similarly, the sacrificial / insulating layers of other layers within fingers 2 and 3 (211-2 / 212-2, 211-3 / 212-3, and 211-4 / 212-4) are connected through sub-openings of openings 223' and 224' in different layers. The sacrificial / insulating layers within fingers 1 and 2 are connected in a similar configuration. In other words, the fingers of stack 240' are connected through region B and separated within regions A and C by vertical trenches 221' and 222'. Thus, in subsequent manufacturing steps, word lines can be formed within each finger. Adjacent word lines of the same layer can be conductively connected through region B.Furthermore, adjacent insulating layers of the same hierarchical level can be connected through openings 223' and 224' (in region B). In some embodiments, fingers 1, 2, and 3 are referred to collectively as a block, and word lines of the same hierarchical level within the block are connected through region B.

[0061] Vertical trenches (e.g., 221' and 222') can be formed by forming a mask layer on top of the stack 240' and patterning the mask, for example using photolithography, to form openings corresponding to the vertical trenches within the patterned mask layer. A suitable etching process, e.g., dry etching and / or wet etching, can be performed to remove the portion of the stack 240' exposed by the openings until the vertical trenches expose the base substrate 210. The mask layer can be removed after the vertical trenches have been formed. In some embodiments, the vertical trenches pass through each layer in the stack 240', dividing the stack 240' into a plurality of fingers along the y-axis. The vertical trenches may include one or more of the above-mentioned openings along the y-axis so that the sacrificial / insulating layers of adjacent fingers within each layer can be connected through the opening(s) of the vertical trench between the fingers. In this disclosure, the term “vertical” means “substantially perpendicular to the x-y plane” or “substantially along the z-axis”. In some embodiments, the vertical trenches are substantially perpendicular to the top surface of the base substrate 210.

[0062] In some embodiments, the vertical trench may have two or more openings to allow adjacent sacrificial / insulating layers of hierarchies within the stack 240' to be connected at two or more locations. For example, region B may include multiple sub-regions separated by portions of the vertical trench along the y-axis. That is, the subsequently formed word lines of adjacent fingers of each hierarchy can be electrically connected at two or more locations. In some embodiments, the vertical trench may have two or more openings to allow sacrificial / insulating layers of several hierarchies within the stack 240' to be connected at two or more locations. For example, the vertical trench may have one or more openings distributed within region A along the y-axis. That is, the subsequently formed word lines of adjacent fingers of several hierarchies can be electrically connected at two or more locations. Further details are described below.

[0063] Figures 6A and 6B show structures 600 for forming a three-dimensional memory device according to several embodiments. Figure 6A is a top view 601 of structure 600, and Figure 6B is a cross-sectional view 602 of structure 600 along the 6-6' direction. Structure 600 includes multiple insulating layers within a stack 240'. In some embodiments, structure 600 is formed from structure 500 by removing a sacrificial layer. The insulating layers of each layer can be connected at locations(possibly) not separated by vertical trenches. Thus, horizontal trenches can be formed between insulating layers of adjacent layers, i.e., at locations / spaces where sacrificial layers have been removed. Horizontal trenches can be divided by vertical trenches along the z-axis. In this disclosure, the term “horizontal” means “substantially aligned with the x-y plane” or “substantially perpendicular to the z-axis.” Similarly, horizontal trenches of each layer can be connected at locations(possibly) not separated by vertical trenches. The upper surfaces of the insulating layers of each layer, and the outer sidewall portions of the semiconductor channel 220 that were previously surrounded by the sacrificial layer, can be exposed.

[0064] For example, as shown in Figures 6A and 6B, the structure 600 includes vertical trenches 221' and 222' that separate fingers 1, 2, and 3 from each other in locations filled with insulating material (e.g., within regions A and C). The insulating layers 212 of each layer are connected in locations not separated by the vertical trenches 221' and 222' (e.g., at the locations of openings 223' and 224'). After the sacrificial layers 211 of each layer are removed, horizontal trenches (e.g., 230-1, 230-2, 230-3, and 230-4) are formed. Thus, the top surfaces of the insulating layers of each layer (e.g., 212-1, 212-2, 212-3, and 212-4) and the outer sidewall portions of the semiconductor channel 220 that were previously surrounded by the sacrificial layers 211 are exposed. The horizontal trenches 230 and insulating layers 212 of each layer are connected in region B, respectively. In some embodiments, other support structures (e.g., dummy / auxiliary channels within the stack 240') can be formed to support the stack 240' during the removal of the sacrificial layer 211. Details of the support structures are not described herein.

[0065] The sacrificial layer 211 can be removed by a suitable etching process, such as isotropic dry etching or wet etching. The etching process can have sufficiently high etching selectivity of the material of the sacrificial layer 211 compared to the material of other parts of the substrate 200, so that the etching process can minimize the impact of the etching process on other parts of the substrate 200. Isotropic dry etching and / or wet etching can remove the sacrificial layer 211 in various directions to expose the top and bottom surfaces of each insulating layer 212, as well as the outer sidewall portions of the semiconductor channel 220 that were previously surrounded by the sacrificial layer 211. Horizontal trenches 230 can then be formed within each layer. In some embodiments, the sacrificial layer 211 contains silicon nitride, and the etching agent for isotropic dry etching contains one or more of CF4, CHF3, C4F8, C4F6, and CH2F2. The radio frequency (RF) power of isotropic dry etching can be less than about 100 W, and the bias can be less than about 10 V. In some embodiments, the sacrificial layer 211 contains silicon nitride, and the etching agent for wet etching contains phosphoric acid.

[0066] Figures 7A, 7B, and 7C show structures 700 for forming a three-dimensional memory device according to several embodiments. Figure 7A is a top view 701 of the structure 700, Figure 7B is a cross-sectional view 702 of the structure 700 along the 7-7' direction, and Figure 7C is a cross-sectional view 703 of the structure 700 along the 7''-7''' direction. In the structure 700, the stack 240' includes alternately arranged gate material layers 231' and insulating layers 212. For example, each layer of the structure 700 includes a gate material layer 231' on top of its respective insulating layer 212. In some embodiments, the structure 700 can be formed from the structure 600 shown in Figures 6A and 6B by filling horizontal trenches 230 with suitable gate material (e.g., conductors and / or metals). The gate material can fill each horizontal trench along the xy plane and cover each insulating layer 212. The gate material layer 231' can provide the base material for the word lines (i.e., gate electrodes) that are subsequently formed. After the horizontal trenches 230 are filled with the gate material, connection portions made of the gate material can be formed in the openings of the vertical trenches within each layer of the stack 240'. A connection portion refers to the portion of the gate material layer 231' deposited on each insulating layer 212 in the openings formed by the vertical trenches. Multiple subconnection portions can be formed vertically from aligned sub-openings in different layers. Subconnection portions formed from a single opening can be aligned with each other along the x, y, and z axes (i.e., have the same projected area on the upper surface of the base substrate 210). Connection portions can electrically connect different portions of the gate material layer 231' that are in the same layer and connected to the connection portion (i.e., gate material deposited in a finger adjacent to / connected to the connection portion, or gate material deposited in an adjacent finger). For the sake of clarity, the portion of the insulating layer 212 below the word line (i.e., inside the finger) is referred to as the first insulating portion 2121, and the portion of the insulating layer 212 below the connection portion (i.e., between the fingers) is referred to as the second insulating portion 2122.

[0067] For example, as shown in Figure 7A, gate material can be deposited in the horizontal trenches (230-1, 230-2, 230-3, and 230-4) of each layer of stack 240' to form conductor / dielectric layer pairs / stacks. The gate material (e.g., a conductor) can fill each horizontal trench 230 to form the gate material layers (231'-1, 231'-2, 231'-3, and 231'-4) of each layer of stack 240'. At least a portion of each gate material layer 231' is exposed along the x-y plane. Connecting portions 223 and 224 may be formed by portions of gate material deposited in the openings 223' and 224'. Thus, the subconnecting portions of connecting portions 223 and 224 of each layer may be formed by portions of gate material deposited in the openings 223' and 224' of each layer. As shown in Figure 7B, the gate material is formed on each of the first insulating portions (2121-1, 2121-2, 2121-3, and 2121-4) within finger 2, with each first insulating portion 2121 electrically insulating adjacent gate material on both sides of the first insulating portion 2121 along the z-axis. As shown in Figure 7C, a connection portion is formed at the position of the opening 224', including subconnecting portions 224-1, 224-2, 224-3, and 224-4 in different layers aligned along the z-axis (within region B). Each subconnecting portion 224 is formed on each of the second insulating portions 2122, with each second insulating portion 2122 electrically insulating adjacent subconnecting portions 224 from each other along the z-axis. The subconnecting portions 224 in each layer electrically connect the respective gate materials of fingers 1 and 2. For example, subconnection portion 224-1 electrically connects the gate material (e.g., the word lines subsequently formed) deposited within the first layer of fingers 1 and 2. Similarly, subconnection portions 224-2 to 224-4 electrically connect the gate material deposited in the second to fourth layers of fingers 1 and 2, respectively. The gate material layers 231' of each layer surround the respective outer sidewall portions of the semiconductor channel 220.

[0068] The gate material may include any suitable conductive material, such as tungsten, aluminum, and / or copper, to form the word line (i.e., gate electrode or conductor layer). The gate material can be deposited in the horizontal trench 230 using a suitable deposition method such as CVD, sputtering, MOCVD, and / or ALD. In some embodiments, the gate material includes tungsten, which is formed by CVD.

[0069] In some embodiments, a gate dielectric material layer (not shown in the figures of this disclosure) can be formed in a horizontal trench before the deposition of the gate metal material. The gate dielectric material layer can be formed on the horizontal trench, the outer sidewall portion of the semiconductor channel 220 between opposing surfaces, and on the opposing surfaces of adjacent insulating layers forming the respective vertical trenches. The gate dielectric material layer provides the base material for the subsequently formed gate dielectric layer. The gate dielectric layer can insulate each word line from the underlying insulating layer 212. The gate insulating material layer can include any suitable dielectric material with electrical insulating properties. For example, the gate insulating material layer can include one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the gate insulating material layer can include a high-k dielectric material (k is less than 3.9). In some embodiments, the gate insulating material layer can include a first silicon oxide layer, a silicon nitride layer on the first silicon oxide layer, and a second silicon oxide layer on the silicon nitride layer. The formation of the gate dielectric material layer may include one or more of CVD, PECVD, PVD, and / or ALD.

[0070] The connection portion (e.g., 223 or 224) can electrically connect the gate material deposited on the fingers adjacent to / connected to the connection portion. In some embodiments, the vertical trench includes two or more openings in the layer, resulting in the formation of two or more connection portions from the openings after the deposition of the gate metal material. In some embodiments, each layer includes two or more subconnection portions. Two or more subconnection portions in one layer can enhance / improve the conductive connection between the gate material deposited on the fingers adjacent to / connected to the two or more subconnection portions, thereby ensuring electrical connection between these fingers. Thus, word lines subsequently formed within connected fingers can share the same metal contact vias, which are further connected to their respective metal interconnects to transmit electrical signals from an external circuit. Thus, the number of metal contact vias can be reduced, simplifying the manufacturing of three-dimensional memory devices.

[0071] Figures 8A and 8B show structures 800 for forming a three-dimensional memory device according to several embodiments. Figure 8A is a top view 801 of the structure 800, and Figure 8B is a cross-sectional view 802 of the structure 800 along the 8-8' direction. The structure 800 includes a plurality of gate line slits substantially along the y-axis. The gate line slits can be formed by filling vertical trenches, as described in Figures 5A to 7C, with appropriate insulating material. The formed gate line slits electrically insulate and isolate the word lines that are subsequently formed between adjacent fingers and in different layers at the location where the insulating material is filled. The gate line slits may include one or more openings along the y-axis that connect the gate material layers / insulating layers of adjacent fingers.

[0072] For illustrative purposes, Figure 8A shows two gate line slits 221 and 222 formed from vertical trenches 221' and 222'. Gate line slit 221 includes a connecting portion 223 that divides gate line slit 221 into a first portion 221-1 and a second portion 221-2, and gate line slit 222 includes a connecting portion 224 that divides gate line slit 222 into a first portion 222-1 and a second portion 222-2. Gate line slits 221 and 222 divide stack 240' into fingers 1, 2, and 3. Each of the gate line slits 221 and 222 insulates adjacent gate material layers / insulating layers of each hierarchical level in locations filled with insulating material (e.g., within regions A and C). Adjacent gate material layers / insulating layers of each hierarchical level are connected in locations not filled with insulating material (e.g., region B). For example, as shown in Figure 8B, the first portion 222-1 and the second portion 222-2 of the gate line slit 222 insulate finger 2 from finger 3 in regions A and C through the stack 240', and the gate material layer / insulating layer pairs of finger 2 and finger 3 of the same hierarchical level (e.g., 231'-1 / 2121-1, 231'-2 / 2121-2, 231'-3 / 2121-3, and 231'-4 / 2121-4) are connected in region B.

[0073] In some embodiments, gate wire slits (e.g., 221 and 222) can be formed by filling vertical trenches (e.g., 221' and 222') with a suitable insulating material. For example, the insulating material can be deposited in the vertical trenches using a suitable deposition method such as CVD, PVD, PECVD, and / or ALD. The insulating material can include any suitable material that enables electrical insulation between the fingers. For example, the insulating material can include silicon oxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the insulating material includes silicon oxide. In some embodiments, after deposition, recess etching and / or chemical mechanical planarization (CMP) is used to remove excess insulating material on the post-deposited stack 240', resulting in the exposure of the gate material layer 231'-1, and the upper surface of the gate wire slit being at the same height as the upper surface of the gate material layer 231'-1.

[0074] In some embodiments, a doping process is performed before the formation of the gate wire slits so that the base substrate 210 is doped at the bottom of the vertical trenches (221' and 222') with a dopant type opposite to that of the base substrate 210. The doped region at the bottom of the vertical trenches can form a source region. Then, insulating material can be deposited on the bottom and side walls of the vertical trenches. Subsequently, source contact vias can be formed within the vertical trenches by filling the center of the vertical trenches with the source material. Thus, the insulating material can provide electrical insulation between the source contact vias and the rest of the stack 240'. In some embodiments, the annular bottom surface of the gate wire slits is in contact with the source region, and the source contact vias are electrically connected to the source region. In some embodiments, ion implantation is utilized so that the base substrate 210 is doped at the bottom of the vertical trenches to form a source region, and insulating material can be deposited to cover the side walls of the vertical trenches, resulting in the formation of a cavity within the vertical trenches surrounded by the insulating material. A suitable source metal can be deposited to fill the cavity and form a source contact via. The insulating material may include silicon oxide, silicon nitride, and / or silicon oxynitride. The source metal may include tungsten and / or other suitable conductive materials. In some embodiments, a barrier layer, such as TiN, is formed between the gate wire slit and the source contact via to prevent the source metal from penetrating the stack 240'.

[0075] Figures 9A and 9B show a structure 900 for forming a three-dimensional memory device according to several embodiments. Figure 9A is a top view 901 of the structure 900, and Figure 9B is a cross-sectional view 902 of the structure 900 along the 9-9' direction. The structure 900 includes multiple layers of word lines stacked along the z-axis, each layer containing multiple word lines, each word line aligned within a different finger. To electrically insulate the word lines of two adjacent layers, an insulating layer is formed between the word lines of adjacent layers. One or more word lines of the same layer can be electrically connected through one or more connection portions. Connected word lines can share the same metal contact vias. One or more metal contact vias can be formed on each layer to electrically connect the connected word lines.

[0076] In some embodiments, structure 900 may be formed from structure 800 shown in Figures 8A and 8B. In some embodiments, excess gate material and gate dielectric material on the sidewalls of stack 240' (e.g., the sidewalls of insulating layer 212) can be removed using a suitable etching process (e.g., dry etching and / or wet etching). The remaining portion of the gate material layer can form the word lines of each layer, and the remaining portion of the gate dielectric material layer can form the gate dielectric layers of each layer. In some embodiments, each word line is formed on top of its respective gate dielectric layer. Furthermore, metal contact vias can be formed on top of each layer to connect the word lines of each layer to an external circuit. In some embodiments, structure 900 includes a dielectric stack (not shown) on top of / surrounding stack 240' to electrically insulate the subsequently formed metal contact vias from each other. In some embodiments, the metal contact vias are formed by patterning the dielectric stack to form a plurality of contact openings that expose the contact areas of each layer, and filling the contact openings with a suitable conductive material to form the metal contact vias. The patterning process may include forming a mask on the dielectric stack, performing a photolithography process to define contact openings within the mask, and removing material within the contact openings until the contact areas of the stack 240' are exposed. The contact areas of each layer may lie on one or more word lines. Furthermore, the contact openings may be filled with suitable conductive materials such as tungsten, aluminum, and / or copper.

[0077] As shown in Figures 9A and 9B, after the excess gate material and gate dielectric material are removed from the stack 240', the remaining gate material in each layer of the stack 240' forms word lines (231-m-wln, m=1~4, n=1~4) in substantially different fingers along the y-axis. In some embodiments, each finger (e.g., fingers 1~3) contains a plurality of word lines 231-m-wln stacked along the z-axis, and each word line 231-m-wln is insulated from one another along the z-axis by an adjacent first insulating portion(s). Gate line slits 221 and 222 provide electrical insulation between adjacent fingers in regions A and C, separating the word lines 231-m-wln of different fingers and, respectively, separating the arrays of semiconductor channels 220 of different fingers. Adjacent word lines 231-m-wln (or word lines 231-m-wln of adjacent fingers) in the same hierarchy are conductively connected by subconnectors in the same hierarchy (e.g., 223-1 to 223-4 and / or 224-1 to 224-4, see Figures 7C and 9A). That is, two or more word lines 231-m-wln in the same hierarchy can be conductively connected by one or more subconnectors in the same hierarchy, and as a result, connected word lines 231-m-wln can share the same metal contact via. In some embodiments, each word line 231-m-wln is connected to other word lines 231-m-wln in the same hierarchy through a connector, and as a result, word lines 231-m-wln in the same hierarchy can share one metal contact via.

[0078] For example, structure 900 includes fingers 1, 2, and 3. Word lines 231-1-wl1, 231-2-wl1, 231-3-wl1, and 231-4-wl1 are stacked along the z-axis within finger 1, word lines 231-1-wl2, 231-2-wl2, 231-3-wl2, and 231-4-wl2 are stacked along the z-axis within finger 2, and word lines 231-1-wl3, 231-2-wl3, 231-3-wl3, and 231-4-wl3 are stacked along the z-axis within finger 3. Word lines 231-1-wl1, 231-1-wl2, and 231-1-wl3 are on the same hierarchical level 1 and are conductively connected by connection parts 223 and 224 (for example, or subconnection parts of connection parts 223 and 224). A metal contact via 232-1 is formed on word line 231-1-wl2 to connect word lines 231-1-wl1, 231-1-wl2, and 231-1-wl3. Similarly, word lines 231-2-wl1, 231-2-wl2, and 231-2-wl3 are in the same tier 2 and are conductively connected by connection portions 223 and 224; word lines 231-3-wl1, 231-3-wl2, and 231-3-wl3 are in the same tier 3 and are conductively connected by connection portions 223 and 224; and word lines 231-4-wl1, 231-4-wl2, and 231-4-wl3 are in the same tier 4 and are conductively connected by connection portions 223 and 224. Metal contact vias 232-2, 232-3, and 232-4 are formed on tiers 2-4, respectively, and are conductively connected to the word lines of each tier. In some embodiments, two adjacent word lines 231-m-wln are conductively connected by two or more connection portions. In some embodiments, several word lines 231-m-wln of the same hierarchy are electrically connected, and the connected word lines share one or more metal contact vias 232. In some embodiments, two or more metal contact vias 232 are formed to connect to the connected word line 231-m-wln to ensure / enhance the electrical connection between the connected word line 231-m-wln and the corresponding metal interconnect(s).Depending on the design, metal contact vias 232 can be formed at any suitable location(s) in the hierarchy (in the xy plane). In some embodiments, other structures, such as drain regions, can be formed within the structure 900. For the sake of clarity, details of the formation of other structures are omitted in this disclosure.

[0079] By using the methods and structures disclosed in Figures 2 to 9, the number of metal contact vias in a three-dimensional memory device can be significantly reduced. In some embodiments, each word line in the same hierarchy can be electrically connected to other word lines by two or more connection parts, resulting in improved electrical connectivity during operation and making the memory device less susceptible to connection failures in these connection parts. In some embodiments, one metal contact via is formed to connect each hierarchy of a block of word lines, and all word lines are electrically connected. Assuming each hierarchy contains N word lines, only one metal contact via needs to be formed in this hierarchy. Compared to conventional methods and structures, the number of metal contact vias is reduced by (N-1) for each hierarchy of word lines. In some embodiments, for manufacturing considerations, connection parts of different hierarchies are aligned along the z-axis, as shown in Figure 7C. In various embodiments, some connection parts in different hierarchies are misaligned along the z-axis. That is, the specific location of connection parts in each hierarchy can be determined individually according to different design requirements. In some embodiments, other components of the three-dimensional memory device can be adjusted to apply electrical signals to desired word lines during operation. For example, an external circuit can be programmed or tuned to select a desired word line and apply an electrical signal / bias to that word line. Other suitable means can also be applied.

[0080] Figure 10 shows a top view 1001 of another exemplary structure 1000 of a three-dimensional memory device. Unlike structure 900, structure 1000 includes two or more connection portions within each layer to electrically connect to shared metal contact vias(or more) of the word lines of each layer. For illustrative purposes, one metal contact via is shown for each layer (232-1, 232-2, 232-3, and 232-4). Each of the gate line slits 221 and 222 includes two or more openings substantially along the y-axis, resulting in the formation of two or more connection portions (e.g., within regions B1, B2, B3, B4, and B5) substantially along the y-axis. Since the stack of connection parts is formed vertically (along the z-axis) at the position of the gate line slit opening, in Figure 10, the first layer word lines (i.e., 231-1-wln (n=1~3)) are conductively connected by four connection parts 223, 224, 225, and 229, and the second layer word lines (i.e., 231-2-wln (n=1~3)) are connected by six connection parts 223, 224, 225, 229, 226, and 230. The third tier of word lines (i.e., 231-3-wln(n=1~3)) are electrically connected by eight connection parts 223, 224, 225, 229, 226, 230, 227, and 231, and the fourth tier of word lines (i.e., 231-4-wln(n=1~3)) are electrically connected by ten connection parts 223, 224, 225, 229, 226, 230, 227, 231, 228, and 232. By increasing the number of connection parts in the word line hierarchy, the desired word lines can be connected more effectively, and the possibility of connection failures between word lines can be reduced. In various embodiments, the total number of metal contact vias is less than the total number of word lines. Therefore, the number of metal contact vias can be reduced, simplifying the manufacturing of the three-dimensional memory device. Space within the three-dimensional memory device can be utilized more efficiently.

[0081] For the sake of clarity, the connecting portions formed between different fingers are substantially aligned along the x-axis. In various other embodiments, the connecting portions formed between different fingers may be offset or misaligned along the x-axis. For example, in Figure 10, connecting portions 223 and 224 may or may not be aligned with each other along the x-axis. In various designs and applications, the number and location of connecting portions may vary according to different design rules and should not be limited by embodiments of this disclosure.

[0082] Figure 11 illustrates exemplary method 1100 for forming a three-dimensional memory device according to several embodiments. For illustrative purposes, the operations shown in method 1100 are described in the context of Figures 2 to 9. In various embodiments of this disclosure, the operations of method 1100 may be performed in a different order and / or may be varied.

[0083] In operation 1101, a substrate can be provided. Figures 2A and 2B show an exemplary substrate in this operation. The substrate may include a base substrate and material layers on the substrate. The base substrate may include any suitable material for forming a three-dimensional structure. For example, the base substrate may include silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), glass, gallium nitride, gallium arsenide, and / or other suitable III-V compounds. In some embodiments, the material layers may include alternating stacks of sacrificial material layers and insulating material layers arranged perpendicularly on the base substrate. In some embodiments, the sacrificial material layers may include silicon nitride and the insulating material layers may include silicon oxide.

[0084] In operation 1102, multiple word lines extending horizontally on the base substrate and at least one connection portion electrically connecting two or more word lines can be formed. Figures 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A-7C, 8A, 8B, 9A, and 9B show exemplary structures in this operation. Referring to Figures 3A and 3B, an alternating stack having a stepped structure can be formed from the substrate provided in operation 1101. Multiple alternating stacked sacrificial / insulating layer pairs can be formed within the stack. A portion of the top surface of each sacrificial layer can be exposed, and each insulating layer can be placed beneath the sacrificial layer. Furthermore, as shown in Figures 4A and 4B, multiple semiconductor channels can be formed substantially into the base substrate through the stack. Each semiconductor channel may include at least a dielectric core, a semiconductor channel film, and a memory film. The semiconductor channels can be formed by continuously depositing the memory film, semiconductor channel film, and dielectric core using a suitable deposition method.

[0085] Furthermore, referring to Figures 5A, 5B, 6A, and 6B, vertical trenches can be formed horizontally through the stack to divide the stack into multiple fingers. The vertical trenches can subsequently form gate line slits. At least one of the vertical trenches includes one or more openings horizontally to connect pairs of sacrificial / insulating layers of adjacent fingers of the same hierarchical level. The vertical trenches can be formed by patterning a mask over the stack and etching the portion of the stack exposed by the mask. Furthermore, the sacrificial layers within the stack can be removed using a suitable isotropic etching process so that horizontal trenches can be formed. The horizontal trenches can expose the remaining insulating layers and sidewall portions of the semiconductor channels.

[0086] Furthermore, referring to Figures 7A to 7C, gate material can be deposited to fill horizontal trenches, and gate material layers can be formed on each insulating layer. Portions of the gate material layer deposited in different fingers can form word lines in subsequent steps. Portions of the gate material layer located at the openings of vertical trenches can form connection portions that electrically connect the subsequently formed word lines adjacent to the openings. In some embodiments, the gate material includes one or more of tungsten, aluminum, and copper and can be deposited by any suitable deposition method such as CVD, sputtering, and / or ALD. Furthermore, referring to Figures 8A and 8B, gate line slits can be formed by depositing a suitable dielectric material in vertical trenches. After the dielectric material is deposited, the top surface of the stack can be planarized using recess etching and / or CMP processes.

[0087] Furthermore, referring to Figures 9A and 9B, excess gate material on the sidewalls of the stack can be removed (e.g., by a suitable etching process), resulting in the formation of word lines along the horizontal direction within different fingers. In some embodiments, the stack may include a plurality of horizontally aligned fingers, each finger containing a plurality of vertically stacked word lines. One or more of the word lines may be electrically connected to other word lines of the same hierarchical level through one or more connecting portions. In some embodiments, the word lines of each hierarchical level are electrically connected through one or more conductive portions.

[0088] In operation 1103, metal contact vias can be formed on the word lines. Figures 9A and 9B show exemplary structures of this operation. One or more metal contact vias can be formed on the connected word lines to electrically connect the connected word lines to an external circuit. In some embodiments, word lines of the same hierarchy are electrically connected, and one metal contact via is formed on one of the word lines.

[0089] In various embodiments, the total number of metal contact vias formed is less than the total number of word lines. Therefore, the number of metal contact vias can be reduced, simplifying the manufacturing of the three-dimensional memory device. The volume of the three-dimensional memory device can be further reduced, allowing for more efficient use of space within the three-dimensional memory device.

[0090] This disclosure describes various embodiments of three-dimensional NAND memory devices and methods for manufacturing them. In some embodiments, the three-dimensional memory device includes a substrate and a first layer comprising a first length of conductive layers including a first plurality of conductive layers extending along a first direction on the substrate. The first direction is substantially parallel to the top surface of the substrate. The memory device also includes at least one connection portion that electrically connects two or more conductive layers of the first layer, and a first metal contact via that is electrically shared by the connected conductive layers of the first layer and connected to a first metal interconnect.

[0091] In some embodiments, a method for forming a three-dimensional memory device includes providing a substrate; forming an alternating stack on the substrate, the alternating stack comprising a plurality of layers of sacrificial layer / insulating layer pairs extending along a first direction substantially parallel to the upper surface of the substrate; forming a plurality of layers of conductor layers extending along the first direction based on the alternating stack; forming at least one connection portion that electrically connects two or more conductor layers of the plurality of layers of conductor layers; and forming at least one metal contact via that is electrically shared by the connected conductor layers, the at least one metal contact via being connected to at least one metal interconnect.

[0092] In some embodiments, the three-dimensional memory device includes a substrate, a plurality of semiconductor channels, each with one end of the plurality of semiconductor channels extending substantially perpendicular to the upper surface of the substrate, a drain region above each end of the plurality of semiconductor channels, a plurality of charge storage regions, each charge storage region being surrounded by each of the plurality of semiconductor channels, and a source region in the substrate. The three-dimensional memory device also includes a plurality of bit lines, each above each end of the plurality of semiconductor channels, a plurality of word lines extending along a direction substantially parallel to the upper surface of the substrate, including an upper selection gate, a lower selection gate, and a plurality of word lines between the upper word line and the lower selection gate, a plurality of metal contact vias connected to the plurality of word lines through a plurality of metal contact vias, and a driver circuit above the plurality of bit lines. Two or more of the plurality of word lines at substantially the same height on the substrate are conductively connected through at least one connection portion at substantially the same height. Multiple word lines share a metal contact via that electrically connects to their respective metal interconnects, and the metal contact via is formed on one of the two or more of the multiple word lines.

[0093] The foregoing descriptions of specific embodiments are intended to fully illustrate the general nature of the disclosure. A person skilled in the art can easily modify and / or adapt such specific embodiments to various uses without excessive experimentation and without departing from the general concepts of the disclosure, by applying knowledge within the scope of the skills of the art. Such adaptations and modifications are therefore intended to be within the meaning and scope of the equivalents of the disclosed embodiments based on the teachings and guidance presented herein. The language and terminology used herein are for illustrative purposes only and not limiting, and it should be understood that, as a result, the language and terminology used herein should be interpreted by a person skilled in the art in light of the teachings and guidance.

[0094] Embodiments of the present disclosure have been described above using functional components that show embodiments of specific functions and relationships between those embodiments. The boundaries of these functional components are defined in this specification in an arbitrary best manner for the convenience of explanation. Alternative boundaries may be defined as long as the relationships between the specified functions are adequately performed.

[0095] The summary and abstract sections may describe one or more exemplary embodiments of the present disclosure, but not all, as contemplated by the inventor(s) and are therefore not intended to limit the scope of the present disclosure and the accompanying claims.

[0096] The scope and width of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely in accordance with the appended claims and their equivalents.

Claims

1. circuit board and A stack structure on the substrate, including two parts, The connection portion between the two parts of the aforementioned stack structure, A gate line slit extending between the two portions of the stack structure along a first direction, The aforementioned connection portion is Connecting the two parts of the aforementioned stack structure, It includes at least two subsets of connecting portions arranged along the first direction, The stack structure includes a plurality of alternately arranged gate material layers and a plurality of insulating layers that extend along the first direction, The stack structure includes a plurality of layers, each of which is a pair of one of the plurality of gate material layers and one of the plurality of insulating layers. Each of the at least two subsets of the aforementioned connection portion is: A plurality of subconnection portions, each of which is electrically connected to at least one of the plurality of gate material layers of the same hierarchical level, The aforementioned plurality of levels include a first level and a second level above the first level. The first number of first subconnection portions that electrically connect the gate material layers of the first layer is different from the second number of second subconnection portions that electrically connect the gate material layers of the second layer. Memory device.

2. The first number is greater than the second number. The memory device according to claim 1.

3. Further equipped with multiple metal contact vias, Each of the plurality of metal contact vias is formed on each of the plurality of gate material layers. The memory device according to claim 1.

4. The aforementioned connecting portion is made from the same material as the plurality of gate material layers. The memory device according to claim 1.

5. The source region within the aforementioned substrate, The system further comprises a source contact via formed within the gate line slit and connected to the source region, The two aforementioned parts are electrically isolated from the source contact via. The memory device according to claim 1.

6. circuit board and A stack structure on the substrate, including two parts, A connecting portion between the two parts of the stack structure, which connects the two parts of the stack structure, A gate line slit extending between the two parts of the stack structure along the first direction, The source region within the aforementioned substrate, The gate line slit comprises a source contact via formed within the gate line slit and connected to the source region, The two aforementioned parts are electrically isolated from the source contact vias. The stack structure includes a plurality of alternately arranged gate material layers and a plurality of insulating layers that extend along the first direction, The stack structure includes a plurality of layers, each of which is a pair of one of the plurality of gate material layers and one of the plurality of insulating layers. The aforementioned connection portion includes at least two subsets of connection portions arranged along the first direction, Each of the at least two subsets of the aforementioned connection portion is: A plurality of subconnection portions, each of which is electrically connected to at least one of the plurality of gate material layers of the same hierarchical level, The aforementioned plurality of levels include a first level and a second level above the first level. The first number of first subconnection portions that electrically connect the gate material layers of the first layer is different from the second number of second subconnection portions that electrically connect the gate material layers of the second layer. Memory device.

7. The first number is greater than the second number. The memory device according to claim 6.

8. Further equipped with multiple metal contact vias, Each of the plurality of metal contact vias is formed on each of the plurality of gate material layers. The memory device according to claim 6.

9. The aforementioned connecting portion is made from the same material as the plurality of gate material layers. The memory device according to claim 6.

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