Manufacturing method of a substrate on which a packaging substrate is placed.

Abstract

To provide a method of manufacturing a substrate in which consistency of alignment marks in a packaging substrate and accuracy between layers are improved.SOLUTION: A method of manufacturing a substrate that is divided into a product area where a plurality of products is disposed and a dummy area other than the product area includes: a preparation step of preparing a glass core 21a having a plurality of core vias; a step of forming an electrically conductive layer 21d on the glass core; a step of laminating a first insulative material layer 23pa on the electrically conductive layer; and a step of curing the first insulative material layer 23pa to prepare a first insulating layer 23a, the step including a pre-curing process of pre-curing the first insulative material layer 23pa at a pre-curing temperature of 80°C or higher and lower than 175°C, and a post-curing process of post-curing the first insulative material layer 23pa at a post-curing temperature of 175°C or higher and 230°C or lower. The method also includes the steps of forming, above the first insulative material layer 23pa, an electrically conductive layer 23c electrically connected to the electrically conductive layer 21d, and laminating a second insulative material layer 23pe on the electrically conductive layer 23c.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present embodiment relates to a method for manufacturing a substrate provided with a semiconductor packaging substrate, and more particularly to a method for manufacturing a substrate provided with a packaging substrate including a glass core and an insulating layer, and a method for manufacturing a packaging substrate. Background Art

[0002] In manufacturing electronic components, the process of forming circuits on a semiconductor wafer is called Front-End (FE), and the process of assembling the wafer into a state usable for actual products is called Back-End (BE), and this back-end process includes a packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of recent electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as sub-micron nano-scale line widths, more than 10 million cells, high-speed operation, and large heat dissipation, but technology for perfect packaging of semiconductors has not been relatively well supported. Therefore, the electrical performance of a semiconductor may be determined by the packaging technology and the resulting electrical connection, rather than by the performance of the semiconductor technology itself.

[0004] Ceramic or resin is currently used as a material for packaging substrates. Recently, research on applying silicon or glass to high-end packaging substrates has been progressing, and in particular, a packaging substrate having a cavity structure using a glass core has been developed.

[0005] In addition, the most widely used packaging substrates, such as FC-BGA (Flip Chip-Ball Grid Array), use ABF (Ajinomoto Build-up Film) which functions as an insulator and an adhesive.

[0006] On the other hand, the redistribution layer (RDL) in the packaging process is a general term for techniques that change the position of already formed electrical terminals to any desired position. Such RDLs are used in semiconductor manufacturing plants as a way to overcome design limitations through packaging, that is, they are utilized in the stacking of semiconductor chips.

[0007] Relevant prior art includes Korean Published Patent Publication No. 10-2022-0135442, Korean Published Patent Publication No. 10-2013-0090115, and Chinese Patent Application Publication CN115334784. [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] The objective of this embodiment is to provide a method for manufacturing a packaging substrate in which the alignment and positional stability of alignment marks are improved when formed on the build-up layer.

[0009] Another objective of this embodiment is to provide a method for manufacturing a packaging substrate that can minimize or prevent the effects of shrinkage of insulating materials, etc. [Means for solving the problem]

[0010] To achieve the above objective, a method for manufacturing a substrate according to one embodiment relates to a method for manufacturing a substrate on which a packaging substrate is arranged, and includes: a preparation step of preparing a glass core which is a glass plate having a large number of core vias; a first-first step of forming a first metal layer on the glass core; a first-second step of laminating a first insulating material layer on the first metal layer; a first-third step of curing the first insulating material layer to provide a first insulating layer; a second-first step of forming a second metal layer on top of the first insulating material layer which is electrically connected to the first metal layer; and a second-second step of laminating a second insulating material layer on the second metal layer.

[0011] The first to third steps include: a pre-curing process in which the first insulating material layer is pre-cured at a pre-curing temperature of 80°C or more and less than 175°C; and a post-curing process in which the first insulating material layer is post-cured at a post-curing temperature of 175°C or more and 230°C or less.

[0012] Through this process, a substrate is manufactured that is divided into a product area where a large number of the packaging substrate products are arranged, and a dummy area other than the product area.

[0013] The aforementioned pre-curing process can proceed to the second step after the first step.

[0014] The first step is a heat treatment performed at a temperature of 110°C or higher but less than 150°C for 10 minutes or more.

[0015] The second step is a heat treatment performed at a temperature of 150°C or higher but less than 175°C for 10 minutes or more.

[0016] The method for manufacturing the substrate may further include a second-third step after the second-second step.

[0017] The second and third steps described above may be steps of curing the second insulating material layer to provide the second insulating layer.

[0018] The first redistribution layer includes the first metal layer and the first insulating layer, and the second redistribution layer includes the second metal layer and the second insulating layer.

[0019] A first alignment mark may be placed in the first redistribution layer of the dummy region, and a second alignment mark may be placed in the second redistribution layer of the dummy region.

[0020] The distance between the position of the first alignment mark and the position of the second alignment mark on the substrate may have a difference of 5 μm or less from a predetermined distance.

[0021] The first alignment mark may be a part of the first metal layer.

[0022] The second alignment mark may be a part of the second metal layer.

[0023] When the distance between the first alignment mark and the second alignment mark in step 2-1 is D1, and the distance between the first alignment mark and the second alignment mark in step 2-3 is D2, the difference between D1 and D2 may be 5 μm or less.

[0024] The step 2-3 may include: a pre-curing process of pre-curing the second insulating material layer at a temperature of 80°C or higher and lower than 175°C; and a post-curing process of post-curing the second insulating material layer at a temperature of 175°C or higher and 230°C or lower.

[0025] The substrate manufacturing method may further include a step 3-1, a step 3-2, and a step 3-3 after the step 2-2.

[0026] The step 3-1 is a step of forming a third metal layer electrically connected to the second metal layer on an upper portion of the second insulating material layer.

[0027] The step 3-2 is a step of laminating a third insulating material layer on the third metal layer.

[0028] The step 3-3 is a step of curing the third insulating material layer to provide a third insulating layer.

[0029] A degree of thermal shrinkage of the first insulating layer may be smaller than a degree of thermal shrinkage of the first insulating material layer.

[0030] A method of manufacturing a packaging substrate according to another embodiment includes a step of preparing a substrate manufactured by the above-described manufacturing method, and a singulation step of separating products arranged in the product area from the substrate. [Effects of the Invention]

[0031] In the example of the packaging substrate manufacturing method, the resistance to shrinkage and hardening of the insulating layer can be increased by repeatedly exposing insulating materials to heat during the build-up of the layers.

[0032] The manufacturing method for the packaging substrate in this example can minimize or prevent shrinkage of insulating materials during the heat treatment process. Through this, it is possible to reduce steps and surface bending of the insulating layer caused by shrinkage of the insulating material when the substrate is pre-cured.

[0033] The manufacturing method for the packaging substrate in this example can improve the consistency and positional stability of wiring, such as the alignment marks formed in the build-up layer.

[0034] In practice, minimizing deformation of pre-cured insulating material can improve the accuracy of pattern and via alignment between layers and enhance the positional stability of patterns and vias. [Brief explanation of the drawing]

[0035] [Figure 1] This is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate in a real-world example. [Figure 2] This is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate related to other concrete examples. [Figure 3] (a) and (b) are conceptual diagrams illustrating a portion of a packaging substrate related to an actual example in cross-section. [Figure 4] This flowchart shows a cross-sectional view of the process of generating the core layer in the manufacturing process of a packaging substrate related to a concrete example. PR stands for pre-cure, i.e., pre-curing, and PT stands for post-cure, i.e., post-curing. [Figure 5]This flowchart shows a cross-sectional view of the process of generating the first redistribution layer in the manufacturing process of a packaging substrate related to a concrete example. PR stands for pre-cure, i.e., pre-curing, and PT stands for post-cure, i.e., post-curing. [Figure 6] This flowchart shows a cross-sectional view of the process of generating the second redistribution layer in the manufacturing process of a packaging substrate related to a concrete example. PR stands for pre-cure, i.e., pre-curing, and PT stands for post-cure, i.e., post-curing. [Figure 7] This is a diagram illustrating the alignment marks on a packaging substrate in a concrete example. [Best Mode for Carrying Out the Invention]

[0036] The embodiments are described below in detail with reference to the accompanying drawings, so that they can be easily implemented by a person with ordinary skill in the art to which the embodiments belong. However, the embodiments can be realized in a variety of different forms and are not limited to the embodiments described herein. Similar parts are denoted by the same reference numerals throughout the specification.

[0037] Throughout this specification, the term “these combinations” as used in any expression in Markush form means one or more mixtures or combinations selected from the group of components described in the Markush form, and includes one or more of those components.

[0038] Throughout this specification, terms such as “First,” “Second,” or “A,” “B” are used to distinguish identical terms from one another. Furthermore, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0039] In this specification, the term "~" may mean that the compound contains a compound corresponding to "~" or a derivative of "~".

[0040] In this specification, the meaning of B being located on A means either B being in direct contact with A, or B being located on A with other layers located between them, and is not limited to B being in contact with the surface of A.

[0041] In this specification, the meaning of B being connected to A means either that A and B are directly connected, or that A and B are connected through other components between them, and is not limited to the direct connection of A and B unless otherwise specified.

[0042] In this specification, unless otherwise specified, singular expressions are interpreted to include singular or plural, as interpreted in the context.

[0043] In the process of developing a semiconductor device that is more integrated, thinner, and capable of high performance, the inventors recognized that not only the element itself but also the packaging is a crucial factor in improving performance, and continued their research in this area. Unlike conventional methods that applied two or more core layers as packaging substrates on motherboards, such as interposers and organic substrates, the inventors confirmed that by applying a single layer of glass core and a cavity structure, it is possible to make the packaging substrate even thinner and improve the electrical characteristics of the semiconductor device.

[0044] The RDL formation process involves forming an insulating layer, such as an ABF (Ajinomoto Build-up Film). The insulating layer can be formed through a fluidization process that moves the insulating material to the surface of the glass core and into holes such as core vias, a pre-curing process that partially solidifies the fluidized insulating material without completely solidifying it, and a post-curing process that completely solidifies the insulating material afterward. However, it was found that the positional alignment of the metal pattern and vias decreases during this process, and the need for improvement was recognized.

[0045] As a result of our research, we have confirmed that the resistance to shrinkage and hardening of the insulating layer can be increased by subdividing the hardening step and repeatedly exposing the insulating layer to heat during the hardening of the insulating material for layer buildup, and we present an example of this.

[0046] Figure 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate in an example; Figure 2 shows a conceptual diagram illustrating the cross-sectional structure of a packaging substrate in another example; and Figures 3(a) and 3(b) are conceptual diagrams illustrating a cross-sectional portion of a packaging substrate in an example, respectively.

[0047] To achieve the above objective, the semiconductor device 100 according to the embodiment includes a semiconductor element section 30 on which one or more semiconductor elements 32, 34, and 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20, which transmits external electrical signals to the semiconductor elements 32, 34, and 36 and connects them to each other.

[0048] A packaging substrate 20 according to one example includes a core layer 22, an upper layer 26 located on one surface of the core layer 22, and a cavity portion 28 in which an electrical element 40 can be positioned.

[0049] The semiconductor element portion 30 refers to an element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connecting electrodes or the like. Specifically, the semiconductor element portion 30 may be, for example, a computing element such as a CPU or GPU (first element: 32, second element: 34), a memory element such as a memory chip (third element: 36), etc., but any semiconductor element mounted on a semiconductor device can be applied without limitation.

[0050] The motherboard 10 may be a printed circuit board, a printed wiring board, or the like.

[0051] The packaging substrate 20 may further include a lower layer (not shown) selectively located below the core layer.

[0052] The core layer 22 may include a glass core 21 having a first area 221 with a first thickness 211 and a second area 222 adjacent to the first area 221 and having a second thickness 212 thinner than the first thickness; a number of core vias 23 penetrating the glass core 21 in the thickness direction; and a core distribution layer 24 located on the surface of the glass core 21 or the core vias 23, which electrically connects a first surface 213 of the glass core 21 and a second surface 214 facing the first surface via the core vias 23. That is, the core layer 22 may refer to a glass structure comprising a glass core 21 including a first surface 213 and a second surface 214 facing each other, core vias 23, a cavity 28, or all of these.

[0053] The second region 222 of the core layer 22 can function as a cavity structure.

[0054] Within the same area, the glass core 21 has a first surface 213 and a second surface 214 that face each other, and since these two surfaces are generally parallel to each other, the glass core 21 has a constant thickness throughout.

[0055] The internal space 281 formed by the difference in thickness between the first area 221 and the second area 222 serves to accommodate part or all of the electrical elements 40.

[0056] The glass core 21 may include core vias 23 that penetrate the first surface 213 and the second surface 214. The core vias 23 may be formed in both the first area 221 and the second area 222 and may be formed with an intended pitch and pattern.

[0057] Conventionally, packaging substrates for semiconductor devices have been applied in a form where silicon substrates and organic substrates are stacked. In the case of silicon substrates, due to their semiconductor properties, there is a risk of parasitic elements occurring when applied to high-speed circuits, which is a disadvantage as it results in relatively large power losses. In the case of organic substrates, a large area is required to form even more complex distribution patterns, which does not fit with the trend towards manufacturing ultra-miniaturized electronic devices. In order to form complex distribution patterns within a given size, it is practically necessary to miniaturize the pattern, but due to the properties of materials such as polymers used in organic substrates, there are practical limitations to the miniaturization of the pattern.

[0058] In this concrete example, a glass core 21 is used as a support for the core layer 22 to solve these problems. Furthermore, by applying core vias 23 formed through the glass core 21 together with the glass core 21, the length of the electrical current is further shortened, resulting in a more compact packaging substrate 20 with faster response and lower loss characteristics.

[0059] The glass core 21 is preferably made of plate glass used in semiconductors, and may, but is not limited to, borosilicate plate glass or alkali-free plate glass.

[0060] The core via 23 penetrates the glass core 21. The core via 23 may be formed by removing a predetermined area of ​​the glass core 21, specifically by etching a plate of glass by physical and / or chemical methods.

[0061] Specifically, the formation of the core via 23 may involve, but is not limited to, a method of forming defects (scratches) on the surface of the glass core using a laser or the like, followed by chemical etching, or laser etching.

[0062] The core vias 23 may be positioned in a number of 100 to 3,000, 100 to 2,500, or 225 to 1,024 locations per unit area (1 cm × 1 cm) of the glass core 21. When these pitch conditions are met, the formation of electrically conductive layers and the performance of the packaging substrate can be improved.

[0063] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass core via through vias, and a core insulating layer 223 that covers the core distribution pattern. The core layer 22, having an electrically conductive layer formed inside it via core vias, acts as an electrical passage across the glass core 21, and by connecting the upper and lower parts of the glass core over a relatively short distance, it can have faster electrical signal transmission and low loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0064] The cavity portion 28 is not limited in shape, and can be substantially circular, triangular, square, hexagonal, octagonal, cross-shaped, or any other shape.

[0065] The electrical element 40 may have a shape that is generally cylindrical, rectangular, or polygonal.

[0066] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the electrical element 40 and the core distribution layer 24, and an insulating layer that covers the cavity distribution pattern.

[0067] On the other hand, the cavity portion according to other embodiments may be embodied in a form that penetrates the first surface 213 and the second surface 214 of the glass core 21. In this case, the cavity portion may be formed by the same process as the core via 23 formation process, and the area and shape that penetrate the glass core 21 may differ from those of the core via 23.

[0068] In such an embodiment, an insulating layer may be formed after the electrical elements 40 are arranged in the cavity. That is, an insulating layer may be formed in the cavity through the process by which the core insulating layer 223 described above is formed.

[0069] The core distribution pattern 241 may be formed in such a way that it can be electrically connected to the electrical element 40.

[0070] The electrical element 40 may include an active element such as a transistor, or a power transmission element such as a multilayer ceramic capacitor (MLCC), i.e., a passive element.

[0071] When an element such as a transistor, which plays a role in converting electrical signals between the motherboard and the semiconductor element section to an appropriate level, is used as the electrical element 40, the transistor and the like are applied to the passages of the packaging substrate 20, thereby providing a semiconductor device 100 that is more efficient and has a higher speed.

[0072] Furthermore, power transfer elements such as multilayer ceramic capacitors (MLCCs) play a crucial role in the performance of semiconductor devices. These passive power transfer elements are typically applied in quantities of at least 200 to a semiconductor device, and their performance is influenced by the characteristics of the electrical conductive layer surrounding the element. In one example, non-circular core vias can be applied where a low-resistance electrical conductive layer is required, such as in these power transfer elements.

[0073] On the other hand, the electrical element 40 may be applied by individually inserting passive elements such as capacitors, or a group of elements containing numerous passive elements embedded between insulating layers (cavity insulating layers) may be formed so that the electrodes are exposed and then inserted into the electrical element. In the latter case, the workability of manufacturing the packaging substrate can be further streamlined and it is even more advantageous to ensure that the insulating layer is positioned sufficiently and with high reliability in the complex spaces between elements.

[0074] The glass core 21 plays an intermediate or mediating role in connecting the semiconductor element section 30 and the motherboard 10 to its upper and lower parts, respectively, and the core via 23 acts as a passage for transmitting these electrical signals, thereby ensuring smooth signal transmission. To distinguish it from the core vias of the second area 222 described later, the core vias located in the first area 221 are referred to as first area core vias.

[0075] The upper layer 26 is located on the first surface 213.

[0076] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25, and the uppermost surface of the upper layer 26 may be protected by a cover layer 60 having openings formed therein that allow the connection electrodes of the semiconductor element to make direct contact.

[0077] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface and an upper distribution pattern 251 embedded in the upper insulating layer 253, which is an electrically conductive layer having a predetermined pattern and to which the core distribution layer 24 and at least a portion thereof are electrically connected. The upper distribution layers 25, which are arranged vertically relative to each other, may be connected to each other via blind vias.

[0078] The upper insulating layer 253 can be any material that is applied as an insulating layer to semiconductor elements or packaging substrates. For example, an epoxy resin containing a filler may be used, but it is not limited to this.

[0079] The insulating layer may be formed by forming a coating layer and curing it, or by laminating an in-cured or semi-cured insulating film onto the core layer 22 and curing it. In this case, if a vacuum lamination method or the like is applied, the insulating material can be embedded into the space inside the core via 23, enabling efficient process execution.

[0080] In one embodiment, even when multiple insulating layers are laminated and applied, it may become difficult to substantially distinguish between the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Also, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case it may become substantially difficult to distinguish their boundaries. Alternatively, in other embodiments, the boundaries between the insulating layers can be created by setting different pressures and temperatures for curing the multiple insulating layers.

[0081] The upper distribution pattern 251 refers to an electrically conductive layer located within the upper insulating layer 253 in a predetermined configuration, and may be formed, for example, by a build-up layer method. Specifically, by forming an insulating layer, removing unnecessary portions of the insulating layer, forming an electrically conductive layer by a method such as copper plating, selectively removing unnecessary portions of the electrically conductive layer, forming another insulating layer on this electrically conductive layer, removing unnecessary portions again, and then forming another electrically conductive layer by a method such as plating, an upper distribution pattern 251 can be formed in which electrically conductive layers are formed vertically or horizontally in the desired pattern.

[0082] Since the upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, it is formed to include a fine pattern in at least a part of it so that electrical signals can be transmitted smoothly with the semiconductor element portion 30 and the intended complex pattern can be adequately accommodated. In this case, the fine pattern may have a width and spacing of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 2.3 μm or less, respectively. The spacing may be 1 μm or more (the description of the fine pattern is the same hereafter).

[0083] The upper connection layer 27 includes an upper connection pattern 272 located on the upper insulating layer 253, to which the upper distribution pattern 251 and at least a portion thereof are electrically connected, and an upper connection electrode 271 that electrically connects the semiconductor element portion 30 and the upper connection pattern 272. The upper connection pattern 272 may be located on one surface of the upper insulating layer 253, or at least a portion thereof may be embedded while being exposed on the upper insulating layer. For example, if the upper connection pattern is located on one surface of the upper insulating layer, the upper insulating layer can be formed by a method such as plating, and if the upper connection pattern is embedded while a portion thereof is exposed on the upper insulating layer, a copper plating layer or the like may be formed, and then a portion of the insulating layer or electrically conductive layer may be removed by methods such as surface polishing or surface etching.

[0084] The top connection pattern 272, like the top distribution pattern 251 described above, can include a fine pattern in at least part of its structure. A top connection pattern 272 including such a fine pattern allows even more elements to be electrically connected in a small area, making the connection of electrical signals between elements or to the outside smoother and enabling more integrated packaging.

[0085] The upper connection electrode 271 may be directly connected to the semiconductor element portion 30 with a terminal or the like, or it may be connected via an element connection portion 51 such as a solder ball.

[0086] The cavity portion 28 is located above and / or below the second region 222 and includes an internal space 281 in which a cavity distribution layer 282 and an electrical element 40 are located, which are electrically connected to the core distribution pattern 241. The cavity distribution layer 282 may be formed via a second region core via.

[0087] Specifically, the glass core 21 in the second region 222 is even thinner than that in the first region 221, and the internal space 281 formed by this difference in thickness allows for the placement of electrical elements 40. Furthermore, the core vias 23 and core distribution layer 24 formed in the glass core 21 serve as electrical connection structures that connect the electrical elements 40 to external elements.

[0088] Furthermore, as described above, a cavity can be generated not in the second area 222, but in the first area 221, that is, a cavity that penetrates the first surface 213 and the second surface 214 of the glass core 21, and electrical elements 40 can be arranged in the cavity.

[0089] The packaging substrate 20 is also connected to the motherboard 10. The motherboard 10 may be directly connected to the terminals of the motherboard 10 by the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, or it may be electrically connected via a board connection part 52 such as a solder ball. Alternatively, the core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 via a lower layer (not shown) located below the core layer 22. The element connection part 51 and the board connection part 52 are collectively referred to as the connection part 50.

[0090] For example, the packaging substrate 20 located between the semiconductor element section 30 and the motherboard 10 may not have any substantially additional substrates applied other than the glass core 21.

[0091] Conventionally, when connecting elements to a motherboard, an interposer and an organic substrate were stacked together between them. This multi-layered configuration was applied for at least two reasons: firstly, there were scaling issues in directly bonding the fine patterns of the elements to the motherboard; and secondly, there was a risk of wiring damage due to differences in thermal expansion coefficients during the bonding process or the operation of the semiconductor device. In this example, these problems were solved by applying a glass core with a thermal expansion coefficient similar to that of the semiconductor element, and by forming a fine pattern with a scale small enough to support the element on the first surface of the glass core and the upper layer thereof.

[0092] The following describes a method for manufacturing a substrate on which a packaging substrate according to an embodiment of the present invention is arranged.

[0093] A method for manufacturing a substrate according to one embodiment includes: a preparation step of preparing a glass core which is a glass plate having a large number of core vias; a first-first step of forming a first metal layer on the glass core; a first-second step of laminating a first insulating material layer on the first metal layer; a first-third step of curing the first insulating material layer to provide a first insulating layer; a second-first step of forming a second metal layer on top of the first insulating material layer which is electrically connected to the first metal layer; a second-second step of laminating a second insulating material layer on the second metal layer; and a second-third step of curing the second insulating material layer to provide a second insulating layer.

[0094] The first to third steps may include a pre-curing step of pre-curing the first insulating material layer at a temperature of 80°C or higher and less than 175°C, and a post-curing step of post-curing the first insulating material layer at a temperature of 175°C or higher and 230°C or lower.

[0095] By including such steps, it is possible to manufacture a substrate that is divided into a product area where a large number of products, which are the packaging substrates, are arranged, and a dummy area other than the product area.

[0096] The manufacturing process of the circuit board will be explained in more detail below.

[0097] Figures 4 to 6 are flowcharts illustrating the manufacturing process of a substrate on which a packaging substrate, as shown in the concrete example, is arranged, in cross-section.

[0098] Figure 4 is a flowchart illustrating the process of generating the core layer in the manufacturing process of a substrate in a concrete example, shown in cross-section.

[0099] As shown in Figure 4(a), a glass core 21a having core vias 23 is prepared (preparation step). The core vias 23 may be formed by physically or chemically etching the glass core 21a. This etching process is called the etching step.

[0100] Prior to chemical etching, defects (grooves) (not shown) may be formed on the glass surface of the glass core 21a, which has flat first and second surfaces, at predetermined positions for the formation of core vias. The glass core may be a glass core used for substrates of electronic devices, and may, for example, an alkali-free glass core, but is not limited to this. Commercial products manufactured by companies such as Corning, Schott, and AGC may be used. Methods such as mechanical etching and laser irradiation may be used to form the defects (grooves).

[0101] During the etching process, the glass core may form vias at the defective areas, and at the same time, the surface of the glass core 21a may also be etched. To prevent such etching of the glass surface, a masking film can be applied, but considering the inconvenience of applying and removing the masking film, the defective glass core itself may be etched. In this case, the thickness of the glass core with core vias may be slightly thinner than the thickness of the original glass core.

[0102] Subsequently, an electrically conductive layer may be formed covering the first and second surfaces of the core via 23 and the glass core 21a. The electrically conductive layer may typically be a metal layer containing copper, but is not limited to this.

[0103] Subsequently, a step of forming a metal layer (metal layer formation step) may be performed. This step can be exemplified as follows: if performed on a glass core, it may be referred to as step 1-1; if performed on a first redistribution layer, it may be referred to as step 2-1; and if performed on a second redistribution layer, it may be referred to as step 3-1.

[0104] The metal layer formation step includes the process of forming an electrically conductive layer (metal layer) after the formation of the seed layer / primer layer, and may further include the process of partially removing the seed layer / primer layer or the electrically conductive layer in order to form the electrically conductive layer (metal layer) in a predetermined form and shape.

[0105] Specifically, as shown in Figure 4(b), a seed layer 21c can be generated on the surface of the glass core 21a and on the inner diameter of the core via 23.

[0106] The adhesion between the glass surface (including the glass core surface and core via surface) and the copper metal surface is inferior due to their differing properties. In practical applications, the adhesion between the glass surface and the metal can be improved using two methods: a dry method and a wet method.

[0107] The dry method is a method that applies sputtering, that is, a method that forms a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. For the formation of the seed layer, dissimilar metals such as titanium, chromium, and nickel may be sputtered together with copper, etc. In such cases, the adhesion between the glass and the metal can be improved by an anchoring effect caused by the interaction between the surface morphology of the glass and the metal particles.

[0108] The wet method is a method of primer treatment in which a primer layer (not shown) is formed by pretreatment with a compound having a functional group such as an amine. Depending on the desired degree of adhesion, pretreatment with a silane coupling agent can be performed, followed by primer treatment with a compound or particles having an amine functional group. As mentioned above, the support substrate in the embodiment needs to be high-performance enough to form a fine pattern, and this must be maintained even after primer treatment. Therefore, when such a primer contains nanoparticles, it is preferable to use nanoparticles having an average diameter of 150 nm or less, and for example, it is preferable to use nanoparticles for particles having an amine group. The primer layer may be formed by applying an adhesion improver manufactured by MEC's ​​CZ series, for example.

[0109] The seed layer / primer layer can selectively form a metal layer with or without removing portions where the formation of an electrically conductive layer is unnecessary. Furthermore, the seed layer / primer layer can be treated in a state where the formation of an electrically conductive layer is necessary or unnecessary, either by activating or deactivating it with metal plating, before proceeding to subsequent steps. For example, the activation or deactivation treatment may include light irradiation treatment such as a laser of a certain wavelength, or chemical treatment. For the formation of the metal layer, copper plating methods used in the manufacture of semiconductor devices may be used, but are not limited to these.

[0110] The seed layer 21c is a layer for improving the adhesion between the glass core 21a and the electrically conductive layer 21d, and may include a metal that has good adhesion to copper, which is commonly available in the art. For example, dissimilar metals such as chromium (Cr), titanium (Ti), silver (Ag), copper (Cu), nickel (Ni), nichrome (Nichrome), and palladium (Pd) can be sputtered together with copper as the seed layer 21c. In such cases, the glass-metal adhesion can be improved by an anchoring effect, such as the interaction between the surface morphology of the glass core 21a and the metal particles.

[0111] Such a seed layer 21c functions as a seed to enable copper to be effectively plated when forming a copper metal layer in the plating process. For example, the metal that functions as a seed is preferably one selected from the group that includes at least copper (Cu), silver (Ag), and nickel (Ni). Preferably, it is copper (Cu). In this case, there is an advantage that the formation of metal electrodes through processes such as plating and etching (wet processes) is more favorable than when using other metals such as silver (Ag). In particular, when copper plating is performed on the copper formed on the seed layer 21c, the thickness of the copper wire can be increased more easily compared to other metal materials, thereby easily reducing the resistance of the copper wire.

[0112] For example, titanium and copper may be sequentially sputtered as a seed layer 21c, and the titanium and copper may be laminated in a thickness range of approximately 200 μm to 400 μm.

[0113] Forming a seed layer 21c to improve the adhesion between the glass core 21a and the electrically conductive layer 21d is a dry method, but a wet method, which involves pretreatment with a compound, is also applicable, as is another example.

[0114] Referring to Figure 4(c), an electrically conductive layer 21d can be formed on the glass core 21a based on such a seed layer 21c. The seed layer 21c can be formed as an electrically conductive metal layer with or without removing portions where the formation of the electrically conductive layer 21d is unnecessary. This metal layer may be the first metal layer.

[0115] Furthermore, the electrically conductive layer 21d may be formed with unnecessary portions removed from the seed layer 21c. Alternatively, after the electrically conductive layer 21d is formed, a portion of it may be removed along a predetermined pattern (21e).

[0116] For removal, a seed layer 21c or an electrically conductive layer 21d may have a photoresist layer formed on top of it.

[0117] The photoresist layer may be formed by coating with a photoresist solution, or by laminating a dry film photoresist (DFR) onto the seed layer 21c. In addition, various conventional photoresists capable of forming circuit patterns via photosensitivity are widely applicable. Depending on the design, either a positive or negative type photoresist may be used. The dry film photoresist can then be exposed to ultraviolet (UV) light and developed.

[0118] For example, the dry film photoresist beneath the UV-blocking portion of the dry film photoresist remains unexposed. In the UV-irradiated region, the dry film photoresist is exposed to ultraviolet (UV) light, and development occurs on the exposed dry film photoresist, while the unexposed portions of the photoresist layer are removed.

[0119] After development, the dry film photoresist that was beneath the UV-blocking area and not exposed to UV light is washed away by water, leaving only the dry film photoresist areas that were exposed to UV light.

[0120] A metal layer can be formed by plating the areas where the dry film photoresist has been removed with a metal such as copper.

[0121] In the areas where the unexposed dry film photoresist has been removed, the seed layer 21c can be exposed. Due to the characteristics of metal plating, when the exposed seed layer 21c is plated with the same metal as the seed layer 21c, it becomes possible to form thicker metal wiring more easily than by growing the metal layer by sputtering. Furthermore, since the metal of the seed layer 21c and the metal of the electrically conductive layer 21d are the same, the plated seed layer 21c and the electrically conductive layer 21d can form an integrated wiring.

[0122] Subsequently, the remaining portion of the dry film photoresist can be stripped.

[0123] By peeling off the dry film photoresist, the seed layer 21c, made of metal material, is exposed to the etching solution, and the areas in the seed layer 21c where the metal layer is not formed are removed by etching. Any etching solution that can peel off photoresist can be widely used.

[0124] After the above steps, when the seed layer 21c in the region where the metal layer is not formed is finally removed, an electrically conductive layer 21d on the glass core 21a can be formed through which an electric current can flow.

[0125] As shown in Figure 4(c), if a portion of the core distribution layer is unnecessary, it may be removed, or after a portion of the seed layer is removed or deactivated, a metal plating may be performed to form an electrically conductive layer in a predetermined pattern, thereby forming the etching layer 21e of the core distribution layer.

[0126] The step of forming an insulating material layer is the step of placing a layer of insulating material on the electrically conductive layer (metal layer) (insulating material layer formation step). Exemplarily, the step of laminating a first insulating material layer on a first metal layer can be called the first-second step; the step of laminating a second insulating material layer on a second metal layer can be called the second-second step; and the step of laminating a third insulating material layer on a third metal layer can be called the third-second step.

[0127] The step of forming an insulating layer is the step of curing an insulating material layer to provide an insulating layer (curing step). Exemplarily, the step of curing the first insulating material layer to provide a first insulating layer may be referred to as the 1st-3rd step; the step of curing the second insulating material layer to provide a second insulating layer may be referred to as the 2nd-3rd step; and the step of curing the third insulating material layer to provide a third insulating layer may be referred to as the 3rd-3rd step.

[0128] Specifically, an insulating material layer 23pa can be formed.

[0129] The core via can undergo an insulating material layer formation step in which the empty space is filled with insulating material after the formation of the core distribution layer, which is the electrically conductive layer 21d. At this time, the insulating material layer formed as the core insulating layer or insulating layer 23a in Figure 4 can be formed by coating with a resin composition or by laminating an insulating film. For simplicity, the method of laminating an insulating film is preferred. Lamination of the insulating film can be performed by a process of laminating the insulating film, and at this time, if a reduced-pressure lamination method is applied, the insulating material can be sufficiently embedded even in the parts of the core via where the electrically conductive layer has not been formed. By performing reduced-pressure lamination in this way, the insulating material is sufficiently embedded even in the empty space inside the core via, so that a core insulating layer with substantially no voids can be obtained. It is preferable that the glass core and the insulating layer (after curing) have properties that satisfy an adhesion strength test value of 4B or higher according to ASTM D3359.

[0130] The step of curing the insulating material may include a pre-cure process (pre-curing process) in which the fluidized insulating material, which has been placed in a predetermined location, is partially cured without being completely solidified, and a full cure (full cure or post cure) process (post-curing process) in which the insulating material is completely solidified.

[0131] Specifically, an insulating material in the form of a film is laminated onto the first and / or second surfaces of the glass core 21a. Then, the bonding strength with the glass core 21a is increased using a reduced-pressure lamination method, so that the insulating material can be positioned so that substantially no voids are formed inside the core. Subsequently, pre-curing can be performed using a thermosetting method. In this case, pre-curing means that the insulating film is not completely cured, but rather cured to an intermediate stage, and this can be controlled by adjusting the curing temperature, etc.

[0132] Exemplary, the curing step may include a pre-curing process in which the insulating material layer is pre-cured at a pre-curing temperature of 80°C or more and less than 175°C, and a post-curing process in which the insulating material layer is post-cured at a post-curing temperature of 175°C or more and 230°C.

[0133] For example, the pre-curing temperature may be 80°C or higher, 90°C or higher, 100°C or higher, 110°C or higher, or 120°C or higher. The pre-curing temperature may also be less than 175°C or 170°C or lower.

[0134] For example, the heat treatment time in the pre-curing process may be 20 minutes or more, 30 minutes or more, 40 minutes or more, or 50 minutes or more. The heat treatment time may be 150 minutes or less, 130 minutes or less, 110 minutes or less, 90 minutes or less, 80 minutes or less, or 70 minutes or less.

[0135] For example, the post-curing temperature may be 175°C or higher, 180°C or higher, 185°C or higher, or 190°C or higher. The post-curing temperature may also be 230°C or lower, 220°C or lower, 210°C or lower, or 205°C or lower.

[0136] For example, the heat treatment time in the post-curing process may be 30 minutes or more, 40 minutes or more, 50 minutes or more, or 60 minutes or more. The heat treatment time may be 130 minutes or less, 120 minutes or less, 100 minutes or less, or 90 minutes or less.

[0137] Referring to Figures 4(d) and 4(e), the insulating layer 23a can be formed through a pre-curing process in which an insulating material layer 23pa is formed on the first surface, followed by a post-curing process in which the insulating material layer is completely cured to obtain the insulating layer.

[0138] Insulating layers formed from multiple layers may undergo pre-curing after the insulating material for each layer is arranged and the insulating material layer is formed, and this process may be repeated several times before post-curing is performed all at once in the final step to ensure that the entire insulating material layer is completely cured. In such cases, each insulating layer that has only undergone pre-curing may have low thermal resistance because it has not undergone complete curing shrinkage. This can cause the insulating material layer filling the core vias to shrink during the curing process, potentially reducing the coherence of each layer (e.g., the coherence of the metal layers).

[0139] In concrete examples, to improve the instability of such insulating layers, post-curing for the formation of each insulating layer can be performed multiple times. Through this process, the insulating layer is repeatedly exposed to heat during layer build-up, which can increase its resistance to shrinkage and hardening.

[0140] In this case, the temperature applied during the post-curing step can be higher than the temperature applied during the pre-curing step, and the curing time applied during the post-curing step can be longer than the curing time applied during the pre-curing step. The temperature and time for pre-curing and post-curing are as described above. However, these temperatures and times can be changed depending on the insulating material being applied.

[0141] The difference between the pre-curing temperature and the post-curing temperature may be 30°C or more, 35°C or more, or 40°C or more. In such cases, it may further help to improve the consistency of each layer.

[0142] The aforementioned pre-curing process can proceed to the second step after the first step.

[0143] The first step may be a heat treatment performed at a temperature of 110°C or higher but less than 150°C for 10 minutes or more, and the second step may be a heat treatment performed at a temperature of 150°C or higher but less than 175°C for 10 minutes or more.

[0144] Specifically, the temperature in the first step may be 110°C or higher, 115°C or higher, 120°C or higher, or 125°C or higher. The temperature in the first step may be less than 150°C, 145°C or lower, 140°C or lower, or 135°C or lower. The heat treatment time in the first step may be 10 minutes or more, 15 minutes or more, or 20 minutes or more. The heat treatment time may also be 50 minutes or less, 45 minutes or less, 40 minutes or less, or 35 minutes or less.

[0145] Specifically, the temperature in the second step may be 150°C or higher, 155°C or higher, or 160°C or higher. The temperature in the second step may be less than 175°C, 170°C or lower, or 165°C or lower. The heat treatment time in the second step may be 10 minutes or more, 15 minutes or more, or 20 minutes or more. The heat treatment time may also be 50 minutes or less, 45 minutes or less, 40 minutes or less, or 35 minutes or less.

[0146] To summarize the manufacturing method of the packaging substrate described in Figure 4, a first metal layer, such as an electrically conductive layer, can be formed covering the first and second surfaces of the core via 23 and the glass core 21a, and an insulating layer can be formed on top of the first metal layer. Such an insulating layer can be formed through a pre-curing step in which an insulating film is laminated onto the first surface and then pre-cured, and a post-curing step in which the insulating film is completely cured.

[0147] In the embodiments described above, when an insulating layer 23a is formed on the upper or lower surface of the glass core 21a, a multilayer metal distribution pattern and an insulating layer can be formed on top of the insulating layer 23a. That is, an upper layer 26, as shown in Figures 2 and 3, can be formed on top of the insulating layer 23a, and a lower layer (not shown) can also be formed on top of the lower insulating layer (not shown).

[0148] A second metal layer may be formed on top of the insulating layer, which is electrically connected to the first metal layer.

[0149] Figure 5 is a flowchart illustrating, in cross-section, the process of forming the second redistribution layer on the first redistribution layer, which is part of the manufacturing process of a packaging substrate in a concrete example.

[0150] The first redistribution layer includes the first metal layer and the first insulating layer, and the second redistribution layer includes the second metal layer and the second insulating layer.

[0151] In this embodiment, the second redistribution layer may refer to the first layer included in the upper layer formed on top of the core layer. The second redistribution layer may include a second metal layer which is an upper distribution pattern, and a second insulating layer 23e formed on the second metal layer.

[0152] First, as shown in Figure 5(a), blind vias 23b for forming the second metal layer can be formed in the first insulating layer 23a. To form the blind vias 23b, dry etching methods such as laser etching and plasma etching, or wet etching methods using a masking layer and etching solution may be applied.

[0153] A second metal layer can be formed by performing a plating process after forming blind vias 23b (Figures 5(b) and (c)).

[0154] The second metal layer can be formed by repeatedly forming an electrically conductive layer 23c on the first insulating layer 23a in a predetermined pattern, and then etching away the unnecessary parts to form an etched layer 23d of the electrically conductive layer.

[0155] Subsequently, a step may be performed to form a second insulating material layer 23pe on top of the second metal layer. The second insulating material layer 23pe is formed through a pre-curing process (Figure 5(d)) and a post-curing process (Figure 5(e)) to completely cure the insulating material layer after laminating the insulating material layer onto the second metal layer.

[0156] According to this embodiment, the first insulating layer formed in Figure 4, i.e., the core insulating layer that covers the first or second surface while filling the core vias, is formed through pre-curing and post-curing, and then the second insulating layer 23e of the second redistribution layer formed in the upper layer can also be formed through pre-curing and post-curing. In other words, by performing pre-curing and post-curing at each step in the formation of the insulating layer, resistance to shrinkage can be increased.

[0157] Figure 6 is a flowchart illustrating, in cross-section, the process of generating the second redistribution layer in the manufacturing process of a packaging substrate related to another concrete example.

[0158] According to this embodiment, the first insulating layer 23a is cured through pre-curing and post-curing as shown in Figures 6(a) and (b), and the second insulating layer 23e can be formed in the state of the second insulating material layer 23pe through only the pre-curing step (Figure 6(c)).

[0159] Subsequently, a third metal layer, which is part of the third redistribution layer, may be formed on top of the second insulating material layer 23pe. The third metal layer, like the second metal layer, may include an electrically conductive layer 23f and an etchable portion. A third insulating material layer 23pg may be formed on top of the third metal layer.

[0160] In this embodiment, the third insulating material layer 23pg is formed by laminating an insulating material such as an insulating film onto the third metal layer, followed by a pre-curing process (Figure 6(d)) and a post-curing process (Figure 6(e)) to completely cure the laminated insulating material layer.

[0161] In summary, the packaging substrate according to this embodiment may include a second insulating material layer 23pe formed on top of the second metal layer, a third metal layer formed on top of the second insulating material layer 23pe and electrically connected to the second metal layer, and a third insulating material layer 23pg formed on top of the third metal layer. The second insulating material layer 23pe is formed by laminating an insulating material onto the second metal layer and then pre-curing it, and the third insulating material layer 23pg can be formed by laminating an insulating material onto the third metal layer and then pre-curing it, and then post-curing it to completely cure the insulating film.

[0162] In other embodiments, the second insulating layer 23e may also be formed by pre-curing and post-curing steps.

[0163] In other words, in a packaging substrate in which multiple layers are formed and each layer includes an insulating layer, each insulating layer may be formed through pre-curing and post-curing each time a layer is formed, or it may be formed through pre-curing and post-curing with an interval of two to three layers between them. For example, if the insulating layer included in the first redistribution layer is formed through pre-curing and post-curing, then the insulating layers included in the second redistribution layer and the third layer may be pre-cured only, and then the insulating layer included in the fourth layer may be formed again through pre-curing and post-curing.

[0164] Subsequently, although not shown in the diagram, an upper connecting layer and a cover layer may be formed.

[0165] The top connection pattern and top connection electrodes can also be formed by a process similar to that of the top distribution layer. Specifically, they may be formed by forming an etching layer of the insulating layer on the top insulating layer, then forming an electrically conductive layer thereon, and then forming an etching layer of the electrically conductive layer. Alternatively, a method may be applied that selectively forms only the electrically conductive layer without applying an etching method. The cover layer may be formed so that openings (not shown) are formed at positions corresponding to the top connection electrodes, exposing the top connection electrodes and allowing direct connection to the element connection part or the terminals of the element.

[0166] Once the upper layer is generated, the process of forming the lower connecting layer and cover layer to generate the lower layer can be carried out. The lower distribution layer and / or lower connecting layer, and selectively a cover layer (not shown) can be formed in a manner similar to the upper connecting layer and cover layer formation steps described above.

[0167] Once the upper or lower layer is finally formed, an additional full curing step may be performed to fully cure the insulating film of the core insulating layer and the multilayer insulating layer.

[0168] Between the pre-curing and post-curing processes described above, a process to planarize the substrate surface may be carried out. That is, the upper surface of the insulating layer can be guided to be planarized. For example, a method of positioning a planarizing film (e.g., PET film) on the insulating layer during the reduced-pressure lamination process may be applied. However, the method of planarization is not limited to this.

[0169] Figure 7 is a diagram illustrating the alignment marks on a packaging substrate in a concrete example.

[0170] In the manufacturing process of packaging substrates, when each layer is generated, alignment marks are formed on the packaging substrate for each layer to ensure proper alignment of the metal layers formed on each layer.

[0171] The substrate may include a predetermined dummy area.

[0172] The substrate is divided into a product area where a large number of products, which are the packaging substrate, are arranged, and a dummy area other than the product area. Alignment marks can be formed outside the product area or inside the packaging substrate (e.g., on the edges).

[0173] For example, alignment marks may be generated in the above-described embodiment during the steps of forming the first metal layer and the second metal layer, i.e., when forming the metal layers of each layer.

[0174] Figure 7 shows the first redistribution layer 26a and the second redistribution layer 26b formed on the glass core 21a, and shows the alignment marks 90 formed on each layer.

[0175] Alignment marks serve as an indicator that allows for the measurement and examination of the degree of alignment of wiring in each layer, the degree of shift between layers, and accuracy. The smaller the positional deviation d of the alignment marks in each layer, the less shift there is between layers, and the higher the accuracy of the wiring.

[0176] As an example, Figure 7 illustrates that the alignment marks are arranged vertically, but the alignment marks of the first redistribution layer 26a and the second redistribution layer 26b do not necessarily have to be arranged vertically; it is sufficient if they are arranged in predetermined positions. However, shrinkage of the material may occur during processes such as insulating layer formation, which may cause the position of the alignment marks to differ from the predetermined position. The concrete example minimizes this.

[0177] Specifically, the first redistribution layer 26a includes the first metal layer and the first insulating layer, the second redistribution layer 26b includes the second metal layer and the second insulating layer, a first alignment mark is placed on the first redistribution layer in the dummy region, and a second alignment mark is placed on the second redistribution layer in the dummy region.

[0178] The first alignment mark may be part of the first metal layer.

[0179] The second alignment mark may be part of the second metal layer.

[0180] The distance between the position of the first alignment mark and the position of the second alignment mark on the substrate may have a difference of 5 μm or less from a predetermined distance. The difference may be 5 μm or less, 4 μm or less, 3.5 μm or less, or 3 μm or less. The difference may be 0.1 μm or more, 1 μm or more, or 2 μm or more.

[0181] Exemplary, the first redistribution layer 26a includes the first metal layer and the first insulating layer, the second redistribution layer 26b includes the second metal layer and the second insulating layer, a first alignment mark is placed on the first redistribution layer in the dummy region, and a second alignment mark is placed on the second redistribution layer in the dummy region.

[0182] In step 2-1, the distance between the first alignment mark and the second alignment mark is D1, and in step 2-3, the distance between the first alignment mark and the second alignment mark is D2. In this case, the difference between D1 and D2 may be 5 μm or less. The difference may be 5 μm or less, 4 μm or less, 3.5 μm or less, or 3 μm or less. The difference may be 0.1 μm or more, 1 μm or more, or 2 μm or more. In the embodiment, during heat treatment, the degree of thermal shrinkage of the first insulating layer may be less than the degree of thermal shrinkage of the first insulating material layer.

[0183] A manufacturing method for a packaging substrate according to another embodiment includes a process of singulating the product portion from a substrate manufactured by the substrate manufacturing method described above. Since the packaging substrate manufactured in this way has excellent fine alignment, it is possible to realize a thin line-space and a more integrated packaging substrate.

[0184] The manufacturing method for a substrate, including the packaging substrate according to the embodiment described above, and the packaging substrate using the same, can increase the resistance of the insulating layer to shrinkage and hardening by repeatedly exposing the insulating layer to heat during layer build-up, thereby minimizing or preventing the movement of silica filler and filler. Through this, steps and surface bending of the insulating layer that occur due to the mobility of the filler when pre-cured can be minimized. In other words, the manufacturing method for a packaging substrate according to the embodiment can minimize the fluidity of RDL and improve the consistency and positional stability of the alignment marks formed in the build-up layer.

[0185] The present invention described above has been explained with reference to the embodiments shown in the drawings, but these are merely illustrative, and a person with ordinary skill in the art will understand that various modifications and variations of the embodiments are possible. In other words, the scope of the present invention is not limited to the embodiments described above, and various modifications and improvements made by persons skilled in the art using the basic concepts of the embodiments as defined in the attached claims also fall within the scope of the embodiments. Therefore, the true technical scope of protection of the present invention must be determined by the technical idea of ​​the attached claims. [Explanation of symbols]

[0186] 100 Semiconductor Devices 10 Motherboards 30 Semiconductor element section 32 First Semiconductor Element 34. Second Semiconductor Element 36 Third Semiconductor Device 20 Packaging substrates 21,21a Glass core 22 core layers 223 Core insulating layer 213 Page 1 214 2nd page 23 Corevia 24-core distribution layer 241 Core Distribution Pattern 26 Upper layer 26a 1st redistribution layer 26b Second redistribution layer 25 Upper distribution layer 251 Upper distribution pattern 253 Upper insulating layer 27 Top connecting layer 271 Top connecting electrode 272 Top connection pattern 28 Cavity section 281 Interior space 282 Cavity Distribution Layer 40 Click the electrical button 50 Connection part 51 Element connection section 52 Board connection section 60 Cover layer 90 Align Mark

Claims

1. A method for manufacturing a substrate on which a packaging substrate is arranged, A preparation step involves preparing a glass core, which is a glass plate having a large number of core vias. Step 1-1 involves forming a first metal layer on the glass core, Steps 1 and 2 involve laminating a first insulating material layer made of a thermosetting resin onto the first metal layer, Steps 1-3 include curing the first insulating material layer to provide the first insulating layer, Step 2-1 involves forming a second metal layer on top of the first insulating material layer, which is electrically connected to the first metal layer. Step 2-2 involves laminating a second insulating material layer made of a thermosetting resin onto the second metal layer, The process includes a second to third step of curing the second insulating material layer to provide a second insulating layer, Steps 1-3 described above are: A pre-curing process in which the first insulating material layer is pre-cured at a pre-curing temperature of 80°C or higher and less than 175°C, The invention includes a post-curing process in which the first insulating material layer is post-cured at a post-curing temperature of 175°C to 230°C. Steps 2-3 described above are: A pre-curing process in which the second insulating material layer is pre-cured at a temperature of 80°C or higher and less than 175°C, The process includes a post-curing step in which the second insulating material layer is post-cured at a temperature of 175°C to 230°C. The aforementioned pre-curing process proceeds from the first step to the second step, The first step is a heat treatment performed at a temperature of 110°C or higher and less than 150°C for 10 minutes or more. The second step is a heat treatment performed at a temperature of 150°C or higher and less than 175°C for 10 minutes or more. A method for manufacturing a substrate, comprising a product area on which a large number of products, which are the packaging substrates, are arranged, and a dummy area other than the product area.

2. The first redistribution layer includes the first metal layer and the first insulating layer, The second redistribution layer includes the second metal layer and the second insulating layer, The first redistribution layer located in the dummy region is provided with a first alignment mark. The second redistribution layer located in the dummy region is provided with a second alignment mark. The method for manufacturing a substrate according to claim 1, wherein the distance between the position of the first alignment mark and the position of the second alignment mark on the substrate is less than or equal to a predetermined distance of 5 μm.

3. The first alignment mark is part of the first metal layer, The method for manufacturing a substrate according to claim 2, wherein the second alignment mark is part of the second metal layer.

4. The first redistribution layer includes the first metal layer and the first insulating layer, The second redistribution layer includes the second metal layer and the second insulating layer, The first redistribution layer located in the dummy region is provided with a first alignment mark. The second redistribution layer located in the dummy region is provided with a second alignment mark. In step 2-1 described above, the distance between the first alignment mark and the second alignment mark is D1. In the above steps 2-3, the distance between the first alignment mark and the second alignment mark is D2. The method for manufacturing a substrate according to claim 1, wherein the difference between D1 and D2 is 5 μm or less.

5. The method for manufacturing the substrate is as follows: The process further includes, after step 2-2 above, step 3-1, step 3-2, and step 3-3, The 3-1 step is to form a third metal layer on top of the second insulating material layer, which is electrically connected to the second metal layer. The above step 3-2 is the step of laminating a third insulating material layer on the third metal layer, The above step 3-3 is a step of curing the above third insulating material layer to provide a third insulating layer, Step 3-3 above is, A pre-curing process in which the third insulating material layer is pre-cured at a temperature of 80°C or higher and less than 175°C, A method for manufacturing a substrate according to claim 1, comprising a post-curing step of post-curing the third insulating material layer at a temperature of 175°C to 230°C.

6. The method for manufacturing a substrate according to claim 1, wherein the degree of thermal shrinkage of the first insulating layer is smaller than the degree of thermal shrinkage of the first insulating material layer.

7. The steps include: preparing a substrate manufactured by the manufacturing method described in claim 1, A method for manufacturing a packaging substrate, comprising a singulation step of separating the product placed in the product area from the substrate.

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