Power amplification semiconductor devices

Abstract

A semiconductor device (1) for power amplification comprises: a substrate (10); a lower surface electrode (64); a semiconductor layer (20); a source electrode (60); a drain electrode (50); a gate electrode (40); and a field plate (80). The semiconductor layer (20) is partitioned into active regions (31) and element separation regions (30). A channel region is composed of a plurality of unit channel regions (90) divided by the element separation regions (30) and arranged side by side in the Y-axis direction in a plan view. The source electrode (60) is composed of a plurality of unit source electrodes facing the respective unit channel regions (90). The field plate (80) is composed of a plurality of unit plates (81) facing the respective unit channel regions (90). A plurality of plate driving lines (82) extend in the X-axis direction and electrically connect the plurality of unit source electrodes and the plurality of unit plates (81). At least one of the plate driving lines (82) is provided to each of the unit plates (81) in the range of the element separation regions (30).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device for power amplification. Background Art

[0002] Patent Document 1 discloses a High Electron Mobility Transistor (HEMT) that uses two-dimensional electron gas (2DEG) as a channel. Prior Art Documents Patent Documents

[0003] [Patent Document 1] Japanese Patent No. 5390768 Summary of the Invention Problems to be Solved by the Invention

[0004] Semiconductor devices such as high electron mobility transistors have a problem that characteristics are deteriorated by heat generated during operation.

[0005] Accordingly, the present disclosure provides a semiconductor device for power amplification that can suppress characteristic deterioration caused by heat. Means for Solving the Problems

[0006] A power amplification semiconductor device according to one aspect of the present disclosure includes a substrate, a bottom electrode provided below the substrate, a semiconductor layer provided above the substrate and comprising a plurality of active layers of group III nitride, wherein a two-dimensional electron gas is generated at the heterointerface of the plurality of active layers, a source electrode and a drain electrode provided above the semiconductor layer at intervals and each electrically connected to the two-dimensional electron gas, a gate electrode provided at intervals from the source electrode and the drain electrode and in contact with the semiconductor layer, a field plate provided between the gate electrode and the drain electrode above the semiconductor layer and set to the same potential as the source electrode, a gate finger above a plurality of gate electrodes arranged linearly in a first direction and in contact with and covering all of the plurality of gate electrodes, and above a plurality of drain electrodes arranged linearly in a first direction, The semiconductor layer comprises drain fingers that contact and cover the plurality of drain electrodes, wherein the semiconductor layer is divided in plan view of the substrate into an active region having the two-dimensional electron gas and an element isolation region not having the two-dimensional electron gas, the channel region which is the overlapping portion of the active region and the gate electrode in the plan view is divided in the first direction by the element isolation region and arranged in a plurality of unit channel regions, the source electrode is a plurality of unit source electrodes facing each of the plurality of unit channel regions, the field plate is a plurality of unit plates facing each of the plurality of unit channel regions, and a plurality of plate drive lines extending in a second direction orthogonal to the first direction and electrically connecting the plurality of unit source electrodes and the plurality of unit plates are provided at one or more for each unit plate within the range of the element isolation region. [Effects of the Invention]

[0007] The power amplification semiconductor device described herein can suppress performance degradation caused by heat. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a plan view of a power amplification semiconductor device according to an embodiment. [Figure 2]Figure 2 is a cross-sectional view of the power amplification semiconductor device according to an embodiment, taken along the line II-II in Figure 1. [Figure 3] Figure 3 is a cross-sectional view of the power amplification semiconductor device according to an embodiment, taken along the line III-III in Figure 1. [Figure 4] Figure 4 is a cross-sectional view of the power amplification semiconductor device according to an embodiment, taken along the line IV-IV in Figure 1. [Figure 5] Figure 5 is a plan view showing an enlarged view of the characteristic parts of a power amplification semiconductor device according to an embodiment. [Figure 6] Figure 6 is a cross-sectional view of the power amplification semiconductor device according to the embodiment, taken along the line VI-VI in Figure 5. [Figure 7] Figure 7 is a cross-sectional view of the power amplification semiconductor device according to the embodiment, taken along the line VII-VII in Figure 5. [Figure 8] Figure 8 is a plan view of a power amplification semiconductor device according to a comparative example. [Figure 9] Figure 9 is a cross-sectional view of the power amplification semiconductor device according to the comparative example, taken from IX-IX in Figure 8. [Figure 10] Figure 10 is a plan view of an application example of a power amplification semiconductor device according to an embodiment. [Figure 11] Figure 11 is a cross-sectional view of the application example of the power amplification semiconductor device according to the embodiment, taken from XI to XI in Figure 10. [Figure 12] Figure 12 is a cross-sectional view of a power amplification semiconductor device according to a modified example 1 of the embodiment. [Figure 13] Figure 13 is an XZ cross-sectional view of a power amplification semiconductor device according to a modified example 2 of the embodiment, passing through the plate drive line. [Figure 14] Figure 14 is a cross-sectional view of a power amplification semiconductor device according to a modified example 3 of the embodiment. [Figure 15] Figure 15 is a cross-sectional view of a power amplification semiconductor device according to a modified example 4 of the embodiment. [Figure 16] Figure 16 is a plan view of a power amplification semiconductor device according to a modified example 5 of the embodiment. [Figure 17]FIG. 17 is a plan view showing another example of a source via in the power amplification semiconductor device according to the embodiment and modified examples 1 to 5. [Figure 18] FIG. 18 is a plan view showing another example of a source via in the power amplification semiconductor device according to the embodiment and modified examples 1 to 5. [Figure 19] FIG. 19 is a plan view showing another example of a source via in the power amplification semiconductor device according to the embodiment and modified examples 1 to 5. [Figure 20] FIG. 20 is a plan view showing another example of a source via in the power amplification semiconductor device according to the embodiment and modified examples 1 to 5. [Figure 21] FIG. 21 is a plan view showing another example of a source via in the power amplification semiconductor device according to the embodiment and modified examples 1 to 5. [Figure 22] FIG. 22 is a plan view showing another example of a source via in the power amplification semiconductor device according to the embodiment and modified examples 1 to 5. [Figure 23] FIG. 23 is a plan view showing another example of a source via in the power amplification semiconductor device according to the embodiment and modified examples 1 to 5. [Figure 24] FIG. 24 is a plan view showing another example of source via conduction in the power amplification semiconductor device according to the embodiment and modified examples 1 to 5. [Figure 25] FIG. 25 is a plan view showing another example of a source via in the power amplification semiconductor device according to the embodiment and modified examples 1 to 5. [Figure 26] FIG. 26 is a plan view showing another example of a plate drive line in the power amplification semiconductor device according to the embodiment and modified examples 1 to 5. [Figure 27] FIG. 27 is a plan view showing another example of a plate drive line in the power amplification semiconductor device according to the embodiment and modified examples 1 to 5. [Figure 28] FIG. 28 is a plan view showing another example of a plate drive line in the power amplification semiconductor device according to the embodiment and modified examples 1 to 5. [Figure 29]Figure 29 is a plan view showing another example of plate drive lines and source vias in a power amplification semiconductor device according to Embodiments and Modifications 1 to 5. [Figure 30A] Figure 30A is a cross-sectional view illustrating one step in the manufacturing process of a power amplification semiconductor device according to Embodiments and Modifications 1 to 5. [Figure 30B] Figure 30B is a cross-sectional view illustrating one step in the manufacturing process of a power amplification semiconductor device according to Embodiments and Modifications 1 to 5. [Figure 30C] Figure 30C is a cross-sectional view illustrating one step in the manufacturing process of a power amplification semiconductor device according to Embodiments and Modifications 1 to 5. [Figure 30D] Figure 30D is a cross-sectional view illustrating one step in the manufacturing process of a power amplification semiconductor device according to the embodiments and modifications 1 to 5. [Figure 30E] Figure 30E is a cross-sectional view illustrating one step in the manufacturing process of a power amplification semiconductor device according to Embodiments and Modifications 1 to 5. [Figure 30F] Figure 30F is a cross-sectional view illustrating one step in the manufacturing process of a power amplification semiconductor device according to the embodiments and modifications 1 to 5. [Figure 30G] Figure 30G is a cross-sectional view illustrating one step in the manufacturing process of a power amplification semiconductor device according to the embodiments and modifications 1 to 5. [Figure 30H] Figure 30H is a cross-sectional view illustrating one step in the manufacturing process of a power amplification semiconductor device according to Embodiments and Modifications 1 to 5. [Modes for carrying out the invention]

[0009] (Summary of this disclosure) The embodiments will be described in detail below with reference to the drawings.

[0010] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0011] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. Also, for example, the thickness and size of components in each figure may be exaggerated to make the explanation easier to understand. In addition, substantially identical components are given the same reference numerals in each figure, and redundant explanations are omitted or simplified.

[0012] Furthermore, in this specification, terms indicating relationships between elements such as parallel or orthogonal, terms indicating the shape of elements such as rectangles or circles, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0013] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in a stacked configuration. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other.

[0014] In this specification and in the drawings, the X, Y, and Z axes represent the three axes of a three-dimensional Cartesian coordinate system. In each embodiment, the Z-axis direction is the thickness direction of the substrate. In this specification, "thickness direction" means the thickness direction of the substrate and is the direction perpendicular to the main surface of the substrate. The Y-axis direction is an example of a first direction and is the direction in which the gate finger and drain finger extend. The X-axis direction is an example of a second direction and is the direction in which the source electrode, gate electrode, and drain electrode are arranged in order. In addition, "plan view" means the view from a direction perpendicular to the main surface of the substrate, unless otherwise specified.

[0015] Furthermore, in this specification, a Group III nitride layer is a semiconductor layer containing one or more Group III elements and nitrogen. Examples of Group III elements include aluminum (Al), gallium (Ga), and indium (In). Examples of Group III nitrides include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. Group III nitrides may also contain one or more elements other than Group III, such as silicon (Si) and phosphorus (P). In the following description, unless otherwise specified, when a Group III nitride is written as AlInGaN, it means that the Group III nitride contains Al, In, Ga, and N. The same applies to other notations such as AlGaN and GaN.

[0016] Furthermore, a group III nitride layer means that the layer substantially contains only group III nitrides. However, the layer may contain other elements as impurities, such as elements that are unavoidably introduced during manufacturing, in a proportion of 1% or less.

[0017] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., do not mean the number or order of components unless otherwise specified, but are used to avoid confusion and to distinguish similar components.

[0018] (Embodiment) [1. Structure] First, the configuration of the power amplification semiconductor device according to the embodiment will be explained using Figures 1 to 7.

[0019] Figure 1 is a plan view of the power amplification semiconductor device according to this embodiment. Figures 2 to 4 are cross-sectional views of the power amplification semiconductor device according to this embodiment. Specifically, Figure 2 shows a cross-section along line II-II in Figure 1. Figure 3 shows a cross-section along line III-III in Figure 1. Figure 4 shows a cross-section along line IV-IV in Figure 1.

[0020] Figure 5 is a plan view showing an enlarged view of the characteristic parts of the power amplification semiconductor device according to this embodiment. Figure 5 shows the positional relationship of each component in more detail than Figure 1. Figures 6 and 7 are cross-sectional views of the power amplification semiconductor device according to this embodiment. Specifically, Figure 6 shows the cross-section along the line VI-VI in Figure 5. Figure 7 shows the cross-section along the line VII-VII in Figure 5.

[0021] The power amplification semiconductor device 1 shown in Figures 1 to 4 is a HEMT formed using a GaN (gallium nitride) semiconductor material, and is sometimes called a GaN HEMT. A GaN semiconductor material is a semiconductor material containing Ga (gallium) and N (nitrogen). In addition to Ga and N, GaN semiconductor materials may also contain Al (aluminum), In (indium), etc. GaN semiconductor materials are characterized by a large band gap, a high dielectric breakdown field, and a fast saturation drift rate. Therefore, GaN HEMTs can achieve characteristics such as low on-resistance, high breakdown voltage, and fast switching speed.

[0022] The power amplification semiconductor device 1 according to this embodiment can be used, for example, as a high-frequency transistor. For example, the power amplification semiconductor device 1 can be used as a power amplifier in communication equipment such as mobile phones and base stations.

[0023] The power amplification semiconductor device 1 has a configuration in which the unit components of a transistor are repeatedly arranged in a matrix in a two-dimensional plane (specifically, the XY plane). The unit components of a transistor refer to the part that includes the unit channel region 90 shown in Figure 5, the gate electrode 40, the drain electrode 50, and the unit source region 92 (specifically, the source electrode 60 and source via 70, etc.), and represent the smallest unit capable of operating as a transistor.

[0024] As shown in Figures 1 to 4, the power amplification semiconductor device 1 comprises a substrate 10, a semiconductor layer 20, a gate electrode 40, a gate finger 42, a gate bus 44, a drain electrode 50, a drain finger 52, a drain bus 54 (see Figure 10), a source electrode 60, a source connection portion 62, a bottom electrode 64, a source via 70, a field plate 80, and a plate drive line 82. In plan view, the semiconductor layer 20 is divided into an element isolation region 30 and an active region 31. Multiple gate electrodes 40, gate fingers 42, drain electrodes 50, drain fingers 52, source electrodes 60, source vias 70, field plate 80, and plate drive lines 82 are provided.

[0025] The substrate 10 is a Si (silicon) substrate, but is not limited to this. The substrate 10 may be a sapphire substrate, a SiC (silicon carbide) substrate, or a GaN substrate.

[0026] The semiconductor layer 20 is provided above the substrate 10 and includes multiple active layers of group III nitride. The group III nitride is, for example, a GaN-based nitride. A two-dimensional electron gas 22 is generated at the heterointerface of the multiple active layers. In Figure 2, the two-dimensional electron gas 22 is schematically represented by a dashed line.

[0027] The multiple active layers are, for example, two GaN-based semiconductor layers with different band gaps. As shown in Figures 6 and 7, the two GaN-based semiconductor layers are specifically a GaN layer 24 and an AlGaN layer 26. The GaN layer 24 and AlGaN layer 26 are stacked in that order from the substrate 10 side. A two-dimensional electron gas 22 is generated at the heterointerface between the AlGaN layer 26 with a large band gap and the GaN layer 24 with a small band gap. In a plan view, the semiconductor layer 20 is divided into an active region 31 where the two-dimensional electron gas 22 is present and an element isolation region 30 where the two-dimensional electron gas 22 is absent.

[0028] The semiconductor layer 20 has a channel region containing at least a portion of the two-dimensional electron gas 22. The channel region is the overlapping portion of the active region 31 and the gate electrode 40 in a plan view. The channel region is part of the current path between the drain electrode 50 and the source electrode 60 in the power amplification semiconductor device 1, and is a region whose conduction and non-conductivity are controlled by the gate electrode 40. The channel region consists of a plurality of unit channel regions 90 that are divided and arranged in the X-axis direction by the element isolation region 30.

[0029] The semiconductor layer 20 may include layers other than the active layer. For example, the layers other than the active layer may be made of GaN, AlGaN, InGaN, InAlGaN, AlN, or InN. For example, the semiconductor layer 20 may include a buffer layer placed between the substrate 10 and the GaN layer 24. By providing a buffer layer, the film quality of the GaN layer 24 and the AlGaN layer 26 can be improved. Each layer included in the semiconductor layer 20 is formed by an epitaxial growth method.

[0030] The element isolation region 30 is a region where the two-dimensional electron gas 22 is absent. The element isolation region 30 divides the channel region of the semiconductor layer 20 into multiple unit channel regions 90 aligned in the Y-axis direction. These unit channel regions are sometimes called divided channel regions. As shown in Figures 5 and 6, the unit channel region 90 is the region that overlaps with the gate electrode 40 in a plan view, that is, the region directly beneath the gate electrode 40. The gate length Lg (see Figure 6), which is the length of the gate electrode 40 in the X-axis direction, corresponds to the length of the unit channel region 90 in the X-axis direction. In Figure 5, the contour of the unit channel region 90 is represented by a thick dashed line.

[0031] The device isolation region 30 is formed in a region that includes at least the heterointerface of the epitaxially grown GaN layer 24 and AlGaN layer 26, that is, in a region where a two-dimensional electron gas 22 is generated. The device isolation region 30 is formed by deactivating a part of the semiconductor layer 20 by ion implantation. For example, the device isolation region 30 is formed by ion implanting Ar (argon), B (boron), He (helium), etc., into a region that includes at least the heterointerface of the epitaxially grown GaN layer 24 and AlGaN layer 26. No two-dimensional electron gas 22 is generated within the device isolation region 30.

[0032] Alternatively, the device isolation region 30 may be formed by etching away the epitaxially grown GaN layer 24 and AlGaN layer 26 to a depth at least to which a two-dimensional electron gas 22 is generated. For example, the device isolation region 30 may be an insulating layer formed in the portion where the GaN layer 24 and AlGaN layer 26 have been removed.

[0033] The gate electrode 40 is provided at a distance from the source electrode 60 and the drain electrode 50, and contacts the semiconductor layer 20. The gate electrode 40 is also electrically connected to the gate finger 42 and positioned between the gate finger 42 and the semiconductor layer 20. Specifically, the gate electrode 40 is an electrode that makes Schottky contact with the semiconductor layer 20. The gate electrode 40 is a control electrode for the power amplification semiconductor device 1. Specifically, it can switch between conduction and non-conductivity of the unit channel region 90 according to the gate potential applied to the gate electrode 40 via the gate finger 42. When the power amplification semiconductor device 1 is operating, for example, a gate potential of approximately -1.5V to -3V is applied to the gate electrode 40. However, the magnitude of the gate potential is not particularly limited as long as the power amplification semiconductor device 1 can be operated.

[0034] In this embodiment, multiple gate electrodes 40 are provided in a linear arrangement along the Y-axis. Each of the multiple gate electrodes 40 has an elongated shape along the Y-axis and is arranged in a straight line along the Y-axis. That is, the multiple gate electrodes 40 have a configuration in which a single long gate electrode extending along the Y-axis is divided into multiple parts spaced apart from each other. For this reason, the gate electrodes 40 can also be called divided gate electrodes or unit gate electrodes.

[0035] Furthermore, multiple gate electrodes 40 are provided for each gate finger 42. In other words, the multiple gate electrodes 40 are arranged not only in the Y-axis direction but also in the X-axis direction. To put it another way, the gate electrodes 40 are repeatedly arranged in a matrix within a two-dimensional plane (specifically, the XY plane).

[0036] The gate electrode 40 is formed using a conductive material. For example, the gate electrode 40 is a single layer or laminate of a single metal, an alloy, or a conductive metal nitride. As the metal, you can use Ti (titanium), Ta (tantalum), W (tungsten), Ni (nickel), Pd (palladium), Au (gold), Al, etc. As the conductive metal nitride, you can use TiN, TaN, etc. The gate electrode 40 is formed in a predetermined shape by, for example, deposition by vapor deposition or sputtering and patterning by etching, etc.

[0037] The gate finger 42 is located above the semiconductor layer 20 and extends in the Y-axis direction. The gate finger 42 is located above a plurality of gate electrodes 40 arranged linearly in the Y-axis direction and contacts and covers all of the plurality of gate electrodes 40. In this embodiment, as shown in Figure 3, the gate finger 42 is located above the plate drive line 82, spaced apart from it. The gate finger 42 is a wiring for supplying gate potential to the gate electrodes 40. The gate finger 42 can be called a gate drive line that drives the gate electrodes 40.

[0038] The gate finger 42 has, for example, a larger cross-sectional area in the XZ region than the gate electrode 40. For example, as shown in Figures 5 and 6, the gate finger 42 has a longer length in the X-axis direction than the gate electrode 40. This can reduce the gate resistance Rg. For example, it can suppress variations in gate potential in the plane and stabilize transistor operation.

[0039] The gate finger 42 is formed using a conductive material. For example, the gate finger 42 may be formed using a material with higher conductivity than the gate electrode 40. This can further reduce the gate resistance Rg. As an example, the gate finger 42 is formed using Al, Au, or Cu (copper). The gate finger 42 is formed in a predetermined shape by, for example, film deposition by vapor deposition or sputtering and patterning by etching.

[0040] In this embodiment, a plurality of gate fingers 42 are arranged in the X-axis direction and are set to the same potential relative to each other. For example, the plurality of gate fingers 42 are arranged parallel to each other and spaced apart from each other. As an example, the plurality of gate fingers 42 are arranged so that the gate pitch (see Figure 11) is equally spaced. The negative Y-axis end of each of the plurality of gate fingers 42 is connected to the gate bus 44.

[0041] The gate bus 44 is an aggregated wiring that aggregates multiple gate fingers 42 and extends in the X-axis direction. The gate bus 44 may be integrally formed using the same material as the multiple gate fingers 42. The gate bus 44 is formed in a predetermined shape by, for example, film deposition by vapor deposition or sputtering and patterning by etching.

[0042] In this embodiment, the gate bus 44 is provided on the negative side of the Y-axis direction, but it may also be provided on the positive side of the Y-axis direction, or on both the positive and negative sides of the Y-axis direction.

[0043] The drain electrode 50 is located above the semiconductor layer 20 and is electrically connected to the two-dimensional electron gas 22. The drain electrode 50 is also electrically connected to the drain finger 52 and is positioned between the drain finger 52 and the semiconductor layer 20. Specifically, the drain electrode 50 is an electrode that makes an ohmic connection to the two-dimensional electron gas 22 of the semiconductor layer 20. The drain potential is supplied to the drain electrode 50 via the drain finger 52. When the power amplification semiconductor device 1 is operating, for example, a drain potential of up to approximately 150V may be applied to the drain electrode 50. However, the magnitude of the drain potential is not particularly limited as long as the power amplification semiconductor device 1 can be operated.

[0044] In this embodiment, multiple drain electrodes 50 are provided, arranged in a straight line along the Y-axis. Each of the multiple drain electrodes 50 has an elongated shape along the Y-axis and is arranged in a straight line along the Y-axis. That is, the multiple drain electrodes 50 have a configuration in which one long drain electrode extending along the Y-axis is divided into multiple parts spaced apart from each other. For this reason, the drain electrodes 50 can also be called divided drain electrodes or unit drain electrodes.

[0045] Furthermore, multiple drain electrodes 50 are provided for each drain finger 52. In other words, the multiple drain electrodes 50 are arranged not only in the Y-axis direction but also in the X-axis direction. To put it another way, the drain electrodes 50 are repeatedly arranged in a matrix within a two-dimensional plane (specifically, the XY plane).

[0046] The drain electrode 50 is formed using a conductive material. For example, the drain electrode 50 is a single layer or laminate of a single metal or alloy. As the metal, Ti, Al, Au, etc., can be used. The drain electrode 50 is formed in a predetermined shape by, for example, deposition by vapor deposition or sputtering and patterning by etching.

[0047] The drain finger 52 is located above the semiconductor layer 20 and extends in the Y-axis direction. The drain finger 52 is located above a plurality of drain electrodes 50 that are arranged linearly in the Y-axis direction, and contacts and covers all of these drain electrodes 50. The drain finger 52 is a wiring for supplying drain potential to the drain electrodes 50. In other words, the drain finger 52 can be called a drain drive line that drives the drain electrodes 50.

[0048] The drain finger 52 has, for example, a larger cross-sectional area in the XZ region than the drain electrode 50. For example, as shown in Figures 5 and 6, the drain finger 52 has a longer length in the X-axis direction than the drain electrode 50. This can reduce the drain resistance Rd. For example, it can suppress variations in the drain potential in the plane and stabilize the transistor operation.

[0049] The drain finger 52 is formed using a conductive material. For example, the drain finger 52 may be formed using a material with higher conductivity than the drain electrode 50. This can further reduce the drain resistance Rd. As an example, the drain finger 52 is formed using Al, Au, or Cu. The drain finger 52 is formed in a predetermined shape by film deposition by vapor deposition, sputtering, etc., and patterning by etching, etc.

[0050] In this embodiment, multiple drain fingers 52 are arranged in the X-axis direction and are set to the same potential relative to each other. For example, the multiple drain fingers 52 are parallel to each other and arranged at equal intervals. The positive Y-axis end of each of the multiple drain fingers 52 is connected to a drain bus 54 (see Figure 10).

[0051] The drain bus 54 shown in Figure 10 is an aggregated wiring that extends in the X-axis direction by aggregating multiple drain fingers 52 (not shown in Figure 10). The drain bus 54 may be integrally formed using the same material as the multiple drain fingers 52. The drain bus 54 is formed, for example, by plating or the like in the same process as the metal-filled portion 72 of the source via 70. Alternatively, the drain bus 54 may be formed by a different process than the metal-filled portion 72, for example, by film deposition by vapor deposition or sputtering and patterning by etching or the like to form a predetermined shape.

[0052] In this embodiment, the drain bus 54 is provided on the positive side of the Y-axis direction, but it may also be provided on the negative side of the Y-axis direction, or on both the positive and negative sides of the Y-axis direction. The drain bus 54 may also be provided on the same side as the gate bus 44.

[0053] The source electrode 60 is provided above the semiconductor layer 20, spaced apart from the drain electrode 50, and is electrically connected to the two-dimensional electron gas 22. The source electrode 60 is positioned so as to sandwich the gate electrode 40 between it and the drain electrode 50. Specifically, the source electrode 60 is an electrode that makes an ohmic connection to the two-dimensional electron gas 22 of the semiconductor layer 20. The source potential is supplied to the source electrode 60 via the bottom electrode 64, source via 70, and source connection portion 62. The source potential is, for example, lower than the drain potential. When the power amplification semiconductor device 1 is operating, for example, a source potential of 0V is applied to the source electrode 60. Note that the magnitude of the source potential is not particularly limited as long as the power amplification semiconductor device 1 can be operated.

[0054] In this embodiment, multiple source electrodes 60 are provided in a line along the Y-axis. Each of the multiple source electrodes 60 has an elongated shape in the Y-axis direction and is arranged in a straight line along the Y-axis. That is, the multiple source electrodes 60 have a configuration in which a single long source electrode extending along the Y-axis is divided into multiple parts spaced apart from each other. For this reason, the source electrodes 60 can also be called divided source electrodes or unit source electrodes.

[0055] Multiple source electrodes 60 are provided for each unit channel region 90. Specifically, a source electrode 60 is provided for each unit source region 92 facing the unit channel region 90. In this embodiment, the multiple source electrodes 60 are arranged not only in the Y-axis direction but also in the X-axis direction. In other words, the source electrodes 60 are repeatedly arranged in a matrix in a two-dimensional plane (specifically, the XY plane).

[0056] Here, "facing" means that when viewed from the unit channel region 90 in the direction along the gate length, i.e., in the X-axis direction, it is located directly in front. Specifically, the length and position of the unit source region 92 in the Y-axis direction coincide with the length and position of the unit channel region 90 in the Y-axis direction. The positive and negative X-axis contours of the unit source region 92 are defined by the positive X-axis contour of the source electrode 60 and the most negative X-axis contour of either the source via 70 or the source connector 62. For example, the unit source region 92 is defined as a rectangular area as shown by the thick dashed line in Figure 5.

[0057] The source electrode 60 is formed using a conductive material. For example, the source electrode 60 is a single layer or laminate of a single metal or alloy. Examples of metals that can be used include Ti, Al, and Au. The source electrode 60 is formed in a predetermined shape by, for example, film deposition by vapor deposition or sputtering, and patterning by etching. The source electrode 60 can be formed using the same material and process as the drain electrode 50.

[0058] The source electrode 60 may be provided so as to span from the semiconductor layer 20 to the element isolation region 30. In other words, a portion of the source electrode 60 may be provided on the element isolation region 30.

[0059] The source connection section 62 is provided for connecting multiple source electrodes 60. The source connection section 62 is wiring for supplying source potential to the source electrodes 60. The source connection section 62 can also be called a source drive line that drives the source electrodes 60.

[0060] In this embodiment, as shown in Figure 1, the source connection portion 62 extends along the Y-axis direction and is provided to cover a plurality of source vias 70, at least a portion of a plurality of source electrodes 60, and a portion of a plurality of plate drive lines 82. As shown in Figures 2 and 3, the source connection portion 62 is in contact with at least a portion of the upper surface of the plurality of source electrodes 60 and a portion of the upper surface of the plurality of plate drive lines 82, and is electrically conductive.

[0061] The source connection portion 62 includes a portion that overlaps with the source via 70 and a portion that does not overlap with the source via 70 in a plan view. In this case, the portion that overlaps with the source via 70 in a plan view is considered to be the portion above the upper surface of the metal coating 74 of the source via 70. If the source via 70 does not have a metal coating 74, the portion that overlaps with the source via 70 in a plan view is considered to be the portion above the upper surface of the element isolation region 30.

[0062] The source connection portion 62 is provided to electrically connect each of the multiple source vias 70, the multiple source electrodes 60, and the multiple plate drive lines 82. For example, in a plan view, the source connection portion 62 may be provided so as not to overlap with any of the source vias 70, source electrodes 60, or plate drive lines 82, but to contact a part of the side surface of the source vias 70, a part of the side surface of the source electrodes 60, and a part of the side surface of the plate drive lines 82. If the source electrodes 60 and the plate drive lines 82 are in contact with each other and electrically connected, the source connection portion 62 may contact one of the source electrodes 60 and the plate drive lines 82 but not the other.

[0063] The source connection portion 62 is formed using a conductive material. For example, the source connection portion 62 is a single layer or laminate of a single metal or alloy. Examples of metals that can be used include Ti, Al, and Au. The source connection portion 62 can be formed using the same material and process as the metal filling portion 72 of the source via 70, for example, by plating. Alternatively, the source connection portion 62 may be formed using the same material and process as the metal coating 74 of the source electrode 60 or source via 70. For example, the source connection portion 62 may be formed into a predetermined shape by film deposition by vapor deposition or sputtering, and patterning by etching.

[0064] The bottom electrode 64 is located below the substrate 10. The bottom electrode 64 is sometimes called the back source electrode. Specifically, the bottom electrode 64 is located across the entire bottom surface of the substrate 10. The bottom electrode 64 is set to the same potential as the source electrode 60. Specifically, the bottom electrode 64 is connected to the source via 70 and supplies the source potential to each of the multiple source electrodes 60 via the source via 70 and the source connection part 62.

[0065] The bottom electrode 64 is formed using a conductive material. For example, the bottom electrode 64 is a single layer or laminate of a single metal or alloy. Examples of metals that can be used include Au (gold), Sn (tin), and Ag (silver). The power amplification semiconductor device 1 is mounted on a submount substrate using, for example, silver paste, solder, or metal bonding material. The bottom electrode 64 also functions as a connection electrode to the submount substrate.

[0066] The source via 70 includes a conductor that penetrates the substrate 10 and the semiconductor layer 20 and contacts the bottom electrode 64. The source via 70 electrically connects the bottom electrode 64 and the source electrode 60. The source via 70 is provided in at least one of the multiple unit source regions 92. In this embodiment, the source vias 70 and the unit source regions 92 are provided in a one-to-one correspondence. That is, one source via 70 is provided in each of the multiple unit source regions 92. In other words, the number of source vias 70 in a unit source region 92 is 1. A single source via 70 provided in a single unit source region 92 can be called a single source via.

[0067] The source via 70 includes a conductor filled in a via hole 71 that penetrates the substrate 10, the semiconductor layer 20, and the element isolation region 30. As shown in Figures 1 and 2, the source via 70 includes a metal filling portion 72 and a metal coating 74. The metal filling portion 72 and the metal coating 74 are examples of conductors that contact the lower electrode 64.

[0068] The metal-filled portion 72 is a conductive member that fills the via hole 71. The metal-filled portion 72 is also called a filled via. In this embodiment, the metal-filled portion 72 is provided to completely fill the via hole 71.

[0069] The metal film 74 is a conductive thin film that contacts and covers the side surface of the via hole 71. As shown in Figures 2 and 3, the metal film 74 further covers the upper surfaces of the semiconductor layer 20 and the element isolation region 30 at the edges of the opening of the via hole 71. The metal film 74 is also called a lined via. Note that the cross-section shown in Figure 3 (XZ cross-section passing through the plate drive line 82) shows an example in which only the metal film 74 is provided inside the via hole 71, but this is not the only example. In the XZ cross-section passing through the plate drive line 82, a metal-filled portion 72 may also be provided, similar to Figure 2.

[0070] The source via 70 is formed, for example, by first forming via holes 71 by etching, and then sequentially forming a metal coating 74 and a metal filling portion 72 by plating. The via holes 71 may be formed from either the upper or lower side of the substrate 10.

[0071] Furthermore, the source via 70 may comprise only one of the metal-filled portion 72 and the metal coating 74. That is, it is not necessary to fill the via hole 71 with a metal material after forming the metal coating 74. Alternatively, the metal-filled portion 72 may be formed by filling the via hole 71 with a metal material without forming the metal coating 74.

[0072] The field plate 80 is located above the semiconductor layer 20 and between the gate electrode 40 and the drain electrode 50 in a plan view. The field plate 80 is the source electrode 60 It is set to the same potential. The field plate 80 is provided to mitigate the electric field between the gate electrode 40 and the drain electrode 50 by being fixed at the source potential.

[0073] In this embodiment, the field plate 80 consists of a plurality of unit plates 81 facing a plurality of unit channel regions 90. The plurality of unit plates 81 can also be called a divided field plate electrode, which is a division of the field plate 80. In this embodiment, as shown in Figures 1 and 5, the unit plates 81 do not overlap the gate fingers 42 in a plan view, but are not limited to this. A portion of the unit plates 81 may overlap the gate fingers 42 in a plan view.

[0074] The field plate 80 is formed using a conductive material. For example, the field plate 80 is a single layer or laminate of a single metal or alloy. As the metal, Al, Au, or Cu can be used. The field plate 80 is formed into a predetermined shape by film deposition by vapor deposition, sputtering, etc., and patterning by etching, etc.

[0075] The plate drive wire 82 is wiring for supplying source potential to the field plate 80. One or more plate drive wires 82 are provided for each unit plate 81. In this embodiment, as shown in Figures 5 and 7, two plate drive wires 82 are provided for each unit plate 81. The two plate drive wires 82 are connected to both ends of the unit plate 81 in the Y-axis direction.

[0076] The plate drive wire 82 extends and connects to the corresponding unit plate 81 in the X-axis direction from the corresponding source electrode 60 side. The plate drive wire 82 electrically connects the corresponding unit plate 81 and the source connection portion 62. The plate drive wire 82 supplies source potential to each of the multiple unit plates 81. As shown in Figure 3, the plate drive wire 82 is in contact with the metal coating 74 and the source connection portion 62 at the end on the source via 70 side. The contact area is increased by the source connection portion 62 contacting the upper surface of the plate drive wire 82, thereby reducing contact resistance. This allows the source potential of the field plate 80, i.e., the multiple unit plates 81, to be stabilized.

[0077] The plate drive wire 82 is located within the range of the element isolation region 30 in a plan view. Specifically, the plate drive wire 82 is located above the element isolation region 30. In this embodiment, as shown in Figures 3 and 7, the plate drive wire 82 is in contact with the element isolation region 30.

[0078] The plate drive wire 82 extends in the X-axis direction. As shown in Figure 3, the plate drive wire 82 is provided so as to rise toward the positive Z-axis direction at the end on the drain finger 52 side, and is connected to the unit plate 81 of the field plate 80 at the tip portion toward the positive Z-axis direction.

[0079] The plate drive wire 82 is formed using a conductive material. For example, the plate drive wire 82 is a single layer or laminate of a single metal or alloy. The plate drive wire 82 may also be formed using the same material as the field plate 80. The plate drive wire 82 is formed in a predetermined shape by film deposition by vapor deposition, sputtering, etc., and patterning by etching, etc.

[0080] [2. Characteristic composition and effects, etc.] Next, the characteristic configuration and effects of the power amplification semiconductor device 1 according to this embodiment will be explained in comparison with the comparative example.

[0081] [2-1. Structure of the Comparative Example and its Problems] First, the configuration and problems of the power amplification semiconductor device in the comparative example will be explained using Figures 8 and 9. Figures 8 and 9 are a plan view and a cross-sectional view of the power amplification semiconductor device 1x in the comparative example, respectively. Figure 9 shows the cross-section at IX-IX in Figure 8.

[0082] As shown in Figures 8 and 9, the power amplification semiconductor device 1x according to the comparative example comprises a substrate 10x, a semiconductor layer 20x, a gate electrode 40x, a gate bus 44x, a drain electrode 50x, a drain bus 54x, a source electrode 60x, a bottom electrode 64x, and a source via 70x. The substrate 10x, semiconductor layer 20x, gate bus 44x, drain bus 54x, and bottom electrode 64x are the same as the substrate 10, semiconductor layer 20, gate bus 44, drain bus 54, and bottom electrode 64 provided in the power amplification semiconductor device 1 according to the embodiment.

[0083] In the comparative example power amplification semiconductor device 1x, as shown in Figure 8, both the gate electrode 40x and the drain electrode 50x extend along the Y-axis direction and are not divided. That is, the gate electrode 40x and the drain electrode 50x have the same configuration as the gate finger 42 and drain finger 52 of the power amplification semiconductor device 1 according to the embodiment.

[0084] Furthermore, in the comparative example, the power amplification semiconductor device 1x does not have an element isolation region 30. That is, the channel region of the semiconductor layer 20 is not divided into multiple unit channel regions 90.

[0085] Furthermore, the source electrode 60x extends along the Y-axis direction and is not divided. One source via 70x is provided at each negative Y-axis end of the source electrode 60x.

[0086] In the power amplification semiconductor device 1x, the channel region and its vicinity become heat sources. Specifically, the heat source can be considered to be the region from directly below the gate electrode 40x towards the drain electrode 50x. In Figure 8, the heat source is shown by a thick dashed line. The region directly below the two drain electrodes 50x that sandwich the gate electrode 40x becomes the heat source.

[0087] Figure 9 schematically illustrates the spread of heat from the heat source using dot shading and white arrows. The generated heat is diffused through the semiconductor layer 20x and then spreads laterally (in the X-axis and Y-axis directions) through the substrate 10x and the bottom electrode 64x. The heat that reaches the bottom electrode 64x is released to the outside via a submount substrate (not shown) on which the power amplification semiconductor device 1x is mounted.

[0088] Heat generated near the gate electrode 40x diffuses through the semiconductor layer 20x in the thickness direction (Z-axis direction) and also spreads laterally (X-axis and Y-axis directions). The angle of heat spread can be schematically considered to be 45°. Because the gate electrodes 40x are aligned in the X-axis direction, if the heat generated near two adjacent gate electrodes 40x overlaps before reaching the substrate 10x, a region of locally high temperature is created. For this reason, it is necessary to ensure a large spacing between the gate electrodes 40x in the X-axis direction (called the gate pitch). In Figure 9, the gate pitch is the distance (distance in the X-axis direction) between two adjacent gate electrodes 40x with the source electrode 60x in between, without the drain electrode 50x in between.

[0089] From the above, in the power amplification semiconductor device 1x of the comparative example, a large gate pitch is secured and multiple gate electrodes 40x are arranged, resulting in a longer length of the gate bus 44x in the X-axis direction. As the gate bus 44x lengthens, the gate resistance Rg and parasitic inductance components increase, degrading the high-frequency characteristics of the power amplification semiconductor device 1x. For example, the gain, efficiency, and saturation power of the power amplification semiconductor device 1x decrease.

[0090] Furthermore, since the source via 70x is located at the negative end in the Y-axis direction, the source potential is supplied to the source electrode 60x from an uneven position. As a result, variations in the source potential are more likely to occur within the plane, which may cause the transistor operation of the power amplification semiconductor device 1x to become unstable.

[0091] Furthermore, if a field plate is placed between the gate electrode 40x and the drain electrode 50x, the source potential supplied to the field plate also becomes unstable. The impedance of the field plate becomes higher in the part of the field plate that is far from the power supply, which weakens the potential fixation of the field plate. As a result, the electric field relaxation between the gate electrode 40x and the drain electrode 50x may not be sufficient, and the characteristics and reliability of the power amplification semiconductor device 1x will decrease.

[0092] To suppress variations in source potential, it is necessary to limit the length of the source electrode 60x in the Y-axis direction. In this case, the gate width (channel width) becomes shorter, so in order to secure the required amount of drain current, it is necessary to increase the number of gate electrodes 40x, drain electrodes 50x, and source electrodes 60x. As a result, the length of the gate bus 44x in the X-axis direction becomes longer, and as described above, the high-frequency characteristics of the power amplification semiconductor device 1x deteriorate.

[0093] As will be explained in more detail later in the description of the effects of the source via 70, the source via 70x can also contribute to heat dissipation. However, in the power amplification semiconductor device 1x, the source via 70x is located in an off-center position, so it can hardly contribute to improving heat dissipation.

[0094] To address the above problems, the power amplification semiconductor device 1 according to this embodiment improves the high-frequency characteristics of the power amplification semiconductor device 1 by providing a plurality of unit channel regions 90, a plurality of source vias 70 that are long in the X-axis direction, and a plurality of plate drive lines 82 that extend in the X-axis direction. In this embodiment, at least one of the source vias 70 and the plate drive lines 82 is not an essential component. The effects of each of the unit channel regions 90, source vias 70 and plate drive lines 82 will be described in detail below.

[0095] [2-2. Unit Channel Region] First, the effects of the unit channel region 90 will be explained using Figure 10. Figure 10 is a plan view of an application example of a power amplification semiconductor device according to the embodiment.

[0096] In the power amplification semiconductor device 1 according to this embodiment, the unit channel region 90 and its vicinity serve as heat sources. Specifically, the heat source can be considered to be the region from directly below the gate electrode 40 towards the drain electrode 50. In the following explanation, for the sake of simplicity, the unit channel region 90 may be considered as the heat source.

[0097] In this embodiment, multiple unit channel regions 90 correspond one-to-one with multiple gate electrodes 40 and are arranged in a line along the Y-axis. Between two adjacent unit channel regions 90 in the Y-axis direction, an element isolation region 30 is provided that does not function as a channel, i.e., does not become a current path. Therefore, as shown by the thick dashed line in Figure 10, multiple heat sources are also separated and arranged. By separating the heat sources in the Y-axis direction, heat can be efficiently diffused by utilizing the region between adjacent heat sources (specifically, the element isolation region 30). In other words, the thermal resistance in the Y-axis direction can be reduced, and the heat dissipation of the power amplification semiconductor device 1 can be improved. By improving heat dissipation, characteristic degradation due to heat can be suppressed.

[0098] [2-3. Source Beer] Next, the effects of the source via 70 will be explained using Figures 10 and 11. Figure 11 is a cross-sectional view of an application example of the power amplification semiconductor device according to the embodiment. Specifically, Figure 11 shows the cross-section at XI-XI in Figure 10.

[0099] The source via 70 is located in the unit source region 92 (see Figure 5) facing the unit channel region 90. In other words, the source via 70 is positioned very close to the heat source. Simply put, the source via 70 is positioned at the shortest distance from the heat source in the X-axis direction. As shown in Figure 11, the heat spreading in the X-axis direction reaches the source via 70 before reaching the substrate 10. The source via 70 is made of metal and has higher heat transfer properties than the semiconductor layer 20. Therefore, heat is efficiently transferred to the substrate 10 and the bottom electrode 64 via the source via 70, thereby improving the heat dissipation of the power amplification semiconductor device 1.

[0100] As a result, the gate pitch can be narrowed, thus shortening the length of the gate bus 44 in the X-axis direction. The "gate pitch" is the distance (distance in the X-axis direction) between two adjacent gate electrodes 40 that are separated by the source electrode 60 without the drain electrode 50 in between.

[0101] This reduces the gate resistance Rg and parasitic inductance components, thereby suppressing the degradation of the high-frequency characteristics of the power amplification semiconductor device 1. For example, it can suppress a decrease in the gain, efficiency, and saturation power of the power amplification semiconductor device 1.

[0102] Furthermore, as shown in Figure 5, the source via 70 has an elongated shape in the X-axis direction when viewed from above. That is, if the length of the source via 70 in the X-axis direction is Lvx and the length of the source via 70 in the Y-axis direction is Lvy, then Lvx > Lvy is satisfied. This promotes the spread of heat transmitted from the unit channel region 90 in the X-axis direction, thereby improving heat dissipation. Note that the length of the source via 70 in the X-axis direction is the length of the opening contour of the source via 70 in the X-axis direction. The length of the opening contour in the X-axis direction corresponds to the maximum distance in the X-axis direction of the opening contour on the semiconductor layer 20 side of the via hole 71 for filling the conductor (metal filling portion 72 and metal film 74) of the source via 70. The same applies to the Y-axis direction. In other words, when it is written as "length of the contour in a certain direction", it refers to the straight-line distance in a certain direction, not the length along the contour.

[0103] Furthermore, as shown in Figure 5, in the Y-axis direction, the length of the opening contour of the source via 70 is longer than the corresponding unit source region 92. In other words, the source via 70 is located outside the unit source region 92. To put it another way, the source via 70 extends beyond the unit source region 92 in the Y-axis direction.

[0104] Specifically, when Lcy is the length of the unit channel region 90 in the Y-axis direction, Lvy > Lcy is satisfied. That is, source vias 70 wider than the width of the heat source are placed near the heat source. Therefore, the heat generated in the unit channel region 90, including the heat that spreads in the Y-axis direction, can be efficiently dissipated by the source vias 70.

[0105] In this embodiment, the source vias 70 are provided in a one-to-one correspondence with the unit channel region 90. That is, one source via 70 is provided to correspond to each of the multiple heat sources. Therefore, the source vias 70 are provided without being unevenly distributed in the plane, so that local deterioration of heat dissipation can be suppressed. Thus, the heat dissipation of the power amplification semiconductor device 1 can be improved.

[0106] Furthermore, the source potential can be supplied to each of the multiple source electrodes 60 from the bottom electrode 64 at substantially the shortest distance. This allows the source potential of each of the multiple source electrodes 60 to be stabilized. In addition, parasitic inductance components can be reduced, thereby reducing high-frequency losses.

[0107] As described above, the power amplification semiconductor device 1 according to this embodiment includes a substrate 10, a bottom electrode 64 provided below the substrate 10, a semiconductor layer 20 provided above the substrate 10 and containing a plurality of active layers of group III nitride, where a two-dimensional electron gas 22 is generated at the heterointerface of the plurality of active layers, a source electrode 60 and a drain electrode 50 provided above the semiconductor layer 20 at intervals and each electrically connected to the two-dimensional electron gas 22, a gate electrode 40 provided at intervals from the source electrode 60 and the drain electrode 50 and in contact with the semiconductor layer 20, a gate finger 42 above the plurality of gate electrodes 40 arranged linearly in the Y-axis direction and in contact with and covering all of the plurality of gate electrodes 40, and a drain finger 52 above the plurality of drain electrodes 50 arranged linearly in the Y-axis direction and in contact with and covering all of the plurality of drain electrodes 50. The gate fingers 42 are provided in a plurality, arranged in the X-axis direction perpendicular to the Y-axis direction and set to the same potential. The semiconductor layer 20 is divided into an active region 31 containing a two-dimensional electron gas 22 and an element isolation region 30 without the two-dimensional electron gas 22 in a plan view of the substrate 10. In a plan view, the channel region, which is the overlapping portion of the active region 31 and the gate electrode 40, is divided in the Y-axis direction by the element isolation region 30 and arranged as a plurality of unit channel regions 90. The source electrode 60 is a plurality of unit source electrodes facing each of the plurality of unit channel regions 90. The plurality of unit source regions 92, each containing a plurality of unit source electrodes, have one or more source vias 70, which are through-openings between the substrate 10 and the semiconductor layer 20 and contain a conductor that contacts a bottom electrode 64 set to the same potential as the source electrode 60. In a plan view, the side length of the smallest rectangular region surrounding one or more source vias 70 is longer in the X-axis direction than in the Y-axis direction.

[0108] As a result, multiple unit channel regions 90 are arranged in the Y-axis direction, so that the heat sources are distributed in the Y-axis direction, thereby improving heat dissipation in the Y-axis direction. In addition, since the source vias 70 are arranged in the unit source region 92 facing the unit channel region 90, heat dissipation in the X-axis direction can also be improved. Therefore, the heat dissipation of the power amplification semiconductor device 1 can be improved, and characteristic degradation due to heat can be suppressed.

[0109] Furthermore, by arranging the source electrode 60 and source via 70 in close proximity, the source potential of the source electrode 60 can be stabilized. In addition, the parasitic inductance component of the source wiring can be reduced. Therefore, the high-frequency loss of the power amplification semiconductor device 1 can be reduced.

[0110] In this embodiment, the number of source vias 70 is 1. In a plan view, the length of the opening contour of the source via 70 in the X-axis direction is longer than the length in the Y-axis direction. Therefore, the lengths in the X-axis and Y-axis directions of the minimum rectangular region surrounding one or more source vias 70 are equal to the length Lvx in the X-axis direction and the length Lvy in the Y-axis direction of the opening contour of the source via 70 shown in Figure 5. Thus, the length Lvx in the X-axis direction of the opening contour of the source via 70 is longer than the length Lvy in the Y-axis direction of the opening contour of the source via 70.

[0111] This further enhances heat dissipation in the X-axis direction.

[0112] Furthermore, for example, in the Y-axis direction, the length of the opening contour of the source via 70 is longer than the length of the unit channel region 90.

[0113] This further enhances heat dissipation in the Y-axis direction. Additionally, the increased area of ​​the source via 70 contributes to improved source potential stability and a reduction in parasitic inductance components.

[0114] Furthermore, for example, one or more source vias 70 are provided in all of the multiple unit source regions 92.

[0115] As a result, the source vias 70 are evenly distributed across the plane, which suppresses localized heat concentration. It also suppresses in-plane variations in source potential.

[0116] [2-4. Plate drive wires] Next, we will explain the effects and other aspects of the plate drive wire 82.

[0117] As shown in Figure 5, the plate drive wire 82 extends in the X-axis direction and electrically connects the source electrode 60 to the unit plate 81 of the field plate 80. One or more plate drive wires 82 are provided for each of the multiple unit plates 81.

[0118] As described above, the source electrode 60 is stably supplied with source potential from the bottom electrode 64 via source vias 70 and source connectors 62 provided in the corresponding unit source region 92. Therefore, a stable source potential can be supplied to each unit plate 81 by the plate drive lines 82 provided for each unit plate 81. In other words, the variation in the potential of the unit plates 81 in the XY plane is suppressed, making it easier to uniformly relax the electric field between the gate electrode 40 and the drain electrode 50 in the plane. As a result, the saturation power of the power amplification semiconductor device 1 can be increased.

[0119] Furthermore, since the source potential is supplied to the unit plate 81 from the X-axis direction, a large number of unit plates 81 can be arranged in the Y-axis direction while maintaining the stability of the source potential. In other words, the length of the gate finger 42 in the Y-axis direction can be increased. As a result, the length of the gate bus 44 in the X-axis direction can be shortened, and the number of drain fingers 52 can be reduced. Therefore, the capacitance Cds between the drain electrode 50 and the source electrode 60 can be reduced, thereby improving the efficiency performance of the power amplification semiconductor device 1.

[0120] As described above, the power amplification semiconductor device 1 according to this embodiment comprises a substrate 10, a bottom electrode 64 provided below the substrate 10, a semiconductor layer 20 provided above the substrate 10 and including a plurality of active layers of group III nitride, wherein a two-dimensional electron gas 22 is generated at the heterointerface of the plurality of active layers, a source electrode 60 and a drain electrode 50 provided above the semiconductor layer 20 at intervals and each electrically connected to the two-dimensional electron gas 22, a gate electrode 40 provided at intervals from the source electrode 60 and the drain electrode 50 and in contact with the semiconductor layer 20, a field plate 80 provided between the gate electrode 40 and the drain electrode 50 above the semiconductor layer 20 and set to the same potential as the source electrode 60, a gate finger 42 above the plurality of gate electrodes 40 arranged linearly in the Y-axis direction and in contact with and covering all of the plurality of gate electrodes 40, and a drain finger 52 above the plurality of drain electrodes 50 arranged linearly in the Y-axis direction and in contact with and covering all of the plurality of drain electrodes 50. The semiconductor layer 20 is divided into an active region 31 containing a two-dimensional electron gas 22 and an element isolation region 30 without the two-dimensional electron gas 22, in a plan view of the substrate 10. In a plan view, the channel region, which is the overlapping portion of the active region 31 and the gate electrode 40, is divided in the Y-axis direction by the element isolation region 30 and arranged as a plurality of unit channel regions 90. The source electrode 60 is a plurality of unit source electrodes facing each of the plurality of unit channel regions 90. The field plate 80 is a plurality of unit plates 81 facing each of the plurality of unit channel regions 90. A plurality of plate drive lines 82, extending in the X-axis direction perpendicular to the Y-axis direction and electrically connecting the plurality of unit source electrodes and the plurality of unit plates 81, are provided within the range of the element isolation region 30, with one or more lines for each unit plate 81.

[0121] As a result, multiple unit channel regions 90 are arranged in the Y-axis direction, so that the heat sources are distributed in the Y-axis direction, thereby improving heat dissipation in the Y-axis direction. Therefore, the heat dissipation of the power amplification semiconductor device 1 can be improved, and performance degradation due to heat can be suppressed.

[0122] Furthermore, a stable source potential can be supplied to each of the multiple unit plates 81 from the X-axis direction via the plate drive line 82. The impedance of the field plate 80 (unit plate 81) can be reduced, and the variation in the potential of the unit plate 81 in the XY plane is suppressed, making it easier to evenly relax the electric field between the gate electrode 40 and the drain electrode 50 in the plane. As a result, the saturation power of the power amplification semiconductor device 1 can be increased.

[0123] Furthermore, since a large number of unit plates 81 can be arranged in the Y-axis direction while maintaining the stability of the source potential, the Y-axis length of the gate finger 42 can be increased. As a result, the X-axis length of the gate bus 44 can be shortened, and the number of drain fingers 52 can be reduced. Since the capacitance Cds between the drain electrode 50 and the source electrode 60 can be reduced, the efficiency performance of the power amplification semiconductor device 1 can be improved.

[0124] Furthermore, for example, multiple plate drive lines 82 are in contact with the element isolation region 30.

[0125] As a result, the plate drive line 82 is located near the unit channel region 90 and can be used as a path for heat dissipation. Therefore, the heat dissipation performance of the power amplification semiconductor device 1 can be improved.

[0126] Furthermore, for example, the gate finger 42 is positioned above and spaced apart from the multiple plate drive lines 82.

[0127] This makes it easier to increase the distance between the gate finger 42 and the plate drive wire 82 to which the source potential is supplied, thereby reducing the gate-source capacitance Cgs. For example, when the thickness of the plate drive wire 82 is 0.2 μm, the distance between the lower surface of the gate finger 42 and the upper surface of the plate drive wire 82 is 0.8 μm. By reducing the gate-source capacitance Cgs, the gain performance of the power amplification semiconductor device 1 can be improved.

[0128] Furthermore, by ensuring a longer distance, it becomes easier to increase the cross-sectional area of ​​the gate finger 42, for example. As a result, the gate resistance Rg can be reduced, which in turn suppresses variations in the gate potential within the plane and stabilizes the transistor operation.

[0129] Furthermore, for example, each of the multiple unit source regions 92, which include multiple unit source electrodes, has one or more source vias 70 that are through-openings in the substrate 10 and semiconductor layer 20 and contain a conductor that contacts a bottom electrode 64 set to the same potential as the source electrode 60.

[0130] As a result, the source via 70 is positioned in the unit source region 92 facing the unit channel region 90, thereby improving heat dissipation in the X-axis direction. Therefore, the heat dissipation of the power amplification semiconductor device 1 can be improved, and performance degradation due to heat can be suppressed.

[0131] Furthermore, by arranging the source electrode 60 and plate drive line 82 and the source via 70 in close proximity, the source potential of the source electrode 60 and the source potential of each unit plate 81 supplied via the plate drive line 82 can be stabilized. In addition, the parasitic inductance component of the source wiring can be reduced. Therefore, the high-frequency loss of the power amplification semiconductor device 1 can be reduced.

[0132] Furthermore, for example, there is a one-to-one correspondence between the unit plate 81 and the unit channel region 90.

[0133] This makes it possible to suppress variations in in-plane electric field relaxation performance, thereby improving the uniformity of transistor operation of the power amplification semiconductor device 1.

[0134] [3. Variant] Next, several modified examples of the power amplification semiconductor device 1 according to the embodiment will be described. In the following description, the differences from the embodiment will be the main focus, and the explanation of the common points will be omitted or simplified.

[0135] [3-1. Variation 1] Figure 12 is a cross-sectional view of a power amplification semiconductor device 2 according to modified example 1.

[0136] As shown in Figure 12, in the power amplification semiconductor device 2, the drain electrode 50 and the source electrode 60 each have a recess structure. Specifically, the semiconductor layer 20 is provided with recesses 50r and 60r that penetrate the AlGaN layer 26 and reach the GaN layer 24. The recesses 50r and 60r can be formed by etching away the GaN layer 24 and the AlGaN layer 26 to a depth to which at least the two-dimensional electron gas 22 is generated. On the sides of each of the recesses 50r and 60r, the heterointerface between the AlGaN layer 26 and the GaN layer 24 is exposed, and the edges of the two-dimensional electron gas 22 are exposed.

[0137] The drain electrode 50 is positioned to contact the side surface of the recess 50r. The source electrode 60 is positioned to contact the side surface of the recess 60r. In the example shown in Figure 12, both the drain electrode 50 and the source electrode 60 are positioned to fill the recesses 50r and 60r, respectively. As a result, each of the drain electrode 50 and the source electrode 60 is in contact with the two-dimensional electron gas 22, which reduces contact resistance and thus reduces the resistance between the drain and source.

[0138] Note that only one of the recesses 50r and 60r may be provided. For example, the drain electrode 50 may be placed on the surface of the semiconductor layer 20, as in the embodiment, without the recess 50r. Alternatively, the source electrode 60 may be placed on the surface of the semiconductor layer 20, without the recess 60r.

[0139] [3-2. Variation 2] Figure 13 teeth, Power amplification semiconductor device 3 according to modified example 2 Disconnection This is a top view. Figure 13, like Figure 3, shows the XZ cross-section passing through the plate drive line 82.

[0140] As shown in Figure 13, the plate drive wire 82 is provided away from the element isolation region 30. Specifically, the plate drive wire 82 is provided above the gate finger 42.

[0141] This makes it easier to ensure a longer distance between the plate drive line 82 and the gate finger 42. As a result, the gate-source capacitance Cgs can be reduced, and the gain characteristics of the power amplification semiconductor device 3 can be improved.

[0142] [3-3. Modified Example 3] Figure 14 is a cross-sectional view of a power amplification semiconductor device 4 according to modified example 3.

[0143] As shown in Figure 14, in the power amplifier semiconductor device 4, the semiconductor layer 20 includes contact layers 28d and 28s. The contact layer 28d is in contact with the drain electrode 50 and the two-dimensional electron gas 22. The contact layer 28s is in contact with the source electrode 60 and the two-dimensional electron gas 22. The contact layers 28d and 28s have lower resistance than both the GaN layer 24 and the AlGaN layer 26.

[0144] The contact layers 28d and 28s are formed by reducing the resistance of a portion of the semiconductor layer 20 by ion implantation. Specifically, they are formed by ion implanting Si or the like into a region containing at least the heterointerface of the epitaxially grown GaN layer 24 and AlGaN layer 26, i.e., the region where the two-dimensional electron gas 22 is generated. After ion implantation, annealing is performed to form the contact layers 28d and 28s.

[0145] Alternatively, the contact layers 28d and 28s may be formed by crystal regrowth after etching away the epitaxially grown GaN layer 24 and AlGaN layer 26 to a depth where at least a two-dimensional electron gas 22 is generated. For example, the contact layers 28d and 28s may be low-resistance semiconductor layers epitaxially grown in the areas where the GaN layer 24 and AlGaN layer 26 have been removed.

[0146] After the contact layers 28d and 28s are formed, the drain electrode 50 and the source electrode 60 are formed. Specifically, the drain electrode 50 is provided in contact with the upper surface of the contact layer 28d. The source electrode 60 is provided in contact with the upper surface of the contact layer 28s.

[0147] As described above, in the power amplification semiconductor device 4 according to this modified example, the semiconductor layer 20 includes a contact layer 28s that electrically connects the two-dimensional electron gas 22 and the source electrode 60 on the surface of the semiconductor layer 20.

[0148] As described above, the presence of the contact layer 28s effectively shortens the gate-source distance Lgs, thereby reducing the source resistance. If the sole purpose is to shorten the gate-source distance Lgs, one could consider positioning the source electrode 60 closer to the gate electrode 40. However, in this case, the gate-source capacitance Cgs increases, degrading the high-frequency characteristics. According to this modified example, the presence of the contact layer 28s allows for a reduction in source resistance while suppressing an increase in gate-source capacitance Cgs.

[0149] Furthermore, in this modified example, since a contact layer 28d is provided, the same applies to the drain electrode 50 side. On the drain electrode 50 side, a field plate 80 to which the source potential is supplied is provided, so the drain resistance can be reduced while suppressing the increase in source-drain capacitance Cds.

[0150] In addition, only one of the contact layers 28s and 28d may be provided. For example, the contact layer 28s may be provided, but the contact layer 28d may not be provided.

[0151] [3-4. Modification 4] Figure 15 is a cross-sectional view of the power amplification semiconductor device 5 according to modified example 4.

[0152] As shown in Figure 15, the power amplification semiconductor device 5 has a configuration that combines the drain electrode 50 and source electrode 60 of the power amplification semiconductor device 2 according to Modification 1 and the contact layers 28d and 28s of the power amplification semiconductor device 4 according to Modification 3. That is, the power amplification semiconductor device 5 comprises recessed drain electrode 50 and source electrode 60 and contact layers 28d and 28s.

[0153] In this modified example, as in Modification Example 3, the source resistance can be reduced while suppressing the increase in gate-source capacitance Cgs. Furthermore, the drain resistance can be reduced while suppressing the increase in source-drain capacitance Cds.

[0154] [3-5. Variation 5] Figure 16 is a plan view of the power amplification semiconductor device 6 according to modified example 5.

[0155] As shown in Figure 16, in the power amplification semiconductor device 6, the lengths of the element isolation regions 30 in the Y-axis direction are not uniform. Specifically, the power amplification semiconductor device 6 includes an element isolation region 32 whose length in the Y-axis direction is different from that of the element isolation region 30. The length L in the Y-axis direction of the element isolation region 32 IM The length L in the Y-axis direction of the element isolation region 30 is... IN Longer.

[0156] The element isolation region 32 is located, for example, in the center of the power amplification semiconductor device 6 in the Y-axis direction when viewed from above. In the power amplification semiconductor device 6, heat tends to concentrate more in the center than on the outer periphery. By increasing the size of the element isolation region 32 in the area where heat tends to concentrate, heat concentration can be mitigated and heat dissipation can be improved.

[0157] [4. Variations of Source Beer] Next, several variations of Sourcevia 70 will be explained using Figures 17 to 25.

[0158] Figures 17 to 25 are plan views showing other examples of source vias in a power amplification semiconductor device according to Embodiments and Modifications 1 to 5, respectively.

[0159] [4-1. Low-fill sauce beer] First, we will explain low-fill source vias using Figure 17.

[0160] A low-filling source via is a source via that does not completely fill the via hole 71 that penetrates the substrate 10 and the semiconductor layer 20, i.e., has a filling rate of less than 100%. The filling rate is the ratio of the volume of metallic material placed in the via hole 71 to the total volume of the via hole 71.

[0161] As shown in Figure 17, in the source via 70, the metal filling portion 72 does not completely fill the area surrounded by the metal coating 74. Specifically, the metal filling portion 72, like the metal coating 74, is provided in an annular shape along the side surface of the via hole 71 in a plan view. In other words, the source via 70 has a space 75.

[0162] The space 75 extends, for example, from the upper surface of the semiconductor layer 20 to the lower surface of the substrate 10. The opening of the space 75 on the lower surface of the substrate 10 is covered by the lower electrode 64. Note that a portion of the metal material constituting the metal filler portion 72 or the metal film 74 may be discretely present in the space 75. As will be described in detail later, the method for manufacturing the power amplification semiconductor device includes a step of polishing the lower surface of the substrate 10. A portion of the metal filler portion 72 or the metal film 74 that is removed during polishing may remain in the space 75. The metal filler portion 72 may have a porous structure.

[0163] Furthermore, Figure 17 shows an example where the space 75 is visible in a plan view, that is, an example where the space 75 opens to the upper surface of the semiconductor layer 20, but the invention is not limited to this. The space 75 may not open to the upper surface of the semiconductor layer 20, but may be closed by the metal filling portion 72. In other words, the entire periphery of the space 75 may be covered by any of the metal filling portion 72, the metal coating 74, and the lower electrode 64.

[0164] In this modified example, the filling rate of the source via 70 is 50% or more. That is, the conductor inside the source via 70 occupies more than half of the opening volume of the source via 70.

[0165] This allows for improved heat dissipation by utilizing metal components with high thermal conductivity. For example, a Si substrate has higher thermal resistance than a SiC substrate. However, by using source vias 70 made of filled metal components, heat dissipation can be improved, so that even when a Si substrate is used as the substrate 10, the characteristics of the power amplification semiconductor device 1 can be fully realized.

[0166] [4-2. Linked Source Beer] Next, we will explain connected source vias using Figure 18.

[0167] A linked source via has a configuration in which two or more adjacent source vias are linked together. Specifically, as shown in Figure 18, a via linking section 76 is provided to link two source vias 70. Figure 18 shows an example in which four source vias 70 are linked, but the number of linked vias is not particularly limited. For example, all source vias 70 aligned in the Y-axis direction may be linked, or N source vias 70 (where N is a natural number of 2 or more) may be linked together.

[0168] The method for forming connected source vias 70 and via connection portions 76 is the same as the method for forming multiple individually separated source vias 70, except that the shape of the via holes 71 penetrating the semiconductor layer 20 and the substrate 10 is different. For example, after forming a via hole 71 having an elongated shape in the Y-axis direction that spans multiple unit source regions 92, the side surface is covered with a metal film 74. Then, by filling the area surrounded by the metal film 74 with a metal material, connected source vias 70 and via connection portions 76 can be formed.

[0169] As described above, the source vias 70 contained within each of the adjacent unit source regions 92 (not shown in Figure 18) are connected to each other. In other words, in a plan view, the opening contours of the source vias 70, i.e., the contours of the openings of the via holes 71, are continuous.

[0170] In this way, by connecting the source vias 70, the volume occupied by the highly thermally conductive metal can be increased, thereby further improving heat dissipation.

[0171] [4-3. Group Source Beers] Next, group source vias will be explained using Figures 19 to 25. Note that in Figures 19 to 29, via holes 71 are not shown for the sake of readability. In each figure, the plan view shape of the opening contour of the via hole 71 is equivalent to that of the source via in each figure (specifically, it is equivalent to the plan view shape of the metal coating 74, but slightly smaller).

[0172] A group source via has a configuration in which multiple source vias are provided in a single unit source region 92. The multiple source vias are arranged in a two-dimensional array in a planar view.

[0173] In the examples shown in Figures 19 to 21, multiple rectangular source vias 70A, whose plan view shape is elongated in the X-axis direction, are provided within a single unit source region 92 (not shown in each figure). Note that a portion of each of the multiple source vias 70A may be located outside the unit source region 92.

[0174] In the example shown in Figure 19, two source vias 70A are arranged side by side along the Y-axis. In the example shown in Figure 20, four source vias 70A are arranged in a 2x2 matrix.

[0175] In the example shown in Figure 21, five source vias 70A are arranged in a checkerboard pattern. Specifically, one source via 70A is at the center, and four source vias 70A are arranged diagonally opposite it. No source vias 70A are positioned above, below, to the left, or to the right of the central source via 70A (positive and negative sides in the X-axis direction, and positive and negative sides in the Y-axis direction).

[0176] The plan view shape of a source via provided in a single unit source region 92 does not have to be a rectangle that is long in the X-axis direction. In the example shown in Figures 22 and 23, multiple source vias 70B with a circular plan view shape are provided in a single unit source region 92. Source vias 70B with a circular plan view shape have no anisotropy in shape, making them easy to fill with metal. This improves the accuracy of metal filling, which in turn contributes to improved heat dissipation.

[0177] In the example shown in Figure 22, 10 source vias 70B are arranged in a 2x5 matrix. In the example shown in Figure 23, 11 source vias 70B are arranged so that the center position of each row is shifted along the X-axis. Specifically, the source vias 70B are arranged such that connecting the centers of three adjacent source vias 70B forms an isosceles triangle.

[0178] Note that the arrangements shown in Figures 21 and 23 are examples of staggered arrangements. A staggered arrangement means that two adjacent source vias are offset from each other in at least one of the x-axis and y-axis directions. The amount of offset can be small, such that parts of them face each other, or large, such that parts of them do not face each other at all (they do not overlap when viewed from one direction). In addition to source vias being offset by one, sets of multiple source vias arranged in a matrix may also be arranged in a staggered pattern.

[0179] The examples shown in Figures 19 to 23 illustrate cases where multiple source vias contained within a single unit source region 92 have the same shape and size, but the examples are not limited to this. Multiple source vias contained within a single unit source region 92 may include source vias with different shapes and sizes.

[0180] In the example shown in Figure 24, four source vias 70A, which have a rectangular shape elongated in the X-axis direction in plan view, and one source via 70C, which has a rectangular shape elongated in the Y-axis direction in plan view, are arranged side by side. The four source vias 70A are arranged in a 2x2 matrix, with source via 70C positioned between the columns.

[0181] In the example shown in Figure 25, nine source vias 70A and two source vias 70C are arranged side by side. The nine source vias 70A are arranged in a 3x3 matrix, with one source via 70C placed between each column.

[0182] As described above, for example, the number of source vias 70A, 70B, or 70C in a unit source region 92 may be multiple. In this case, the minimum rectangular region 94 is the region that surrounds all source vias 70A, 70B, or 70C provided within the unit source region 92 in a plan view.

[0183] This reduces the size of each source via 70A, 70B, and 70C, making metal filling easier. The increased metal filling rate of each source via 70A, 70B, and 70C further enhances heat dissipation.

[0184] In the examples shown in Figures 19 to 25, the minimum rectangular region 94 is indicated by a thick dashed line. The minimum rectangular region 94 is a rectangular region that encloses all source vias 70A, 70B and / or 70C that are at least partially contained within a single unit source region 92, and has sides parallel to the X-axis and Y-axis directions, respectively, and has the smallest area.

[0185] Let Lmx be the length of the minimum rectangular region 94 in the X-axis direction, and Lmy be the length of the minimum rectangular region 94 in the Y-axis direction. In this case, Lmx > Lmy holds true. This allows for improved heat dissipation in the X-axis direction, similar to the case of a single source via (specifically, source via 70).

[0186] Furthermore, for example, one or more source vias 70A, 70B, or 70C are arranged in a two-dimensional array in a planar view.

[0187] This makes it less likely for localized heat to concentrate, thereby improving heat dissipation.

[0188] The examples shown in Figures 19 to 25 merely illustrate examples of the shapes and arrangements of multiple source vias, and are not limited to the above examples. A source via with a rectangular shape in plan view does not have to have its longest side parallel to the X or Y axis, and may have a longest side extending in a direction that intersects the X or Y axis at an angle. Furthermore, the shape of each of the multiple source vias may be a polygon other than a rectangle, such as a square or hexagon, or it may be an ellipse, etc. Also, the multiple source vias do not have to be arranged regularly, but may be arranged randomly. For example, in plan view, the total area of ​​source vias within a unit source area 92 may be more than half of the unit source area 92, or less than half. The number, shape, arrangement, etc. of source vias may be changed as appropriate based on conditions such as ease of processing.

[0189] [5. Variations of plate drive wires] Next, several modified examples of the plate drive wire 82 will be explained using Figures 26 to 29.

[0190] Figures 26 to 29 are plan views showing another example of a plate drive line in a power amplification semiconductor device according to Embodiments and Modifications 1 to 5, respectively.

[0191] In the example shown in Figure 26, a connecting wire 84 is provided to connect two adjacent unit plates 81 of the field plate 80. The connecting wire 84 is located between the gate finger 42 and the drain finger 52. The connecting wire 84 is provided aligned with the unit plates 81 of the field plate 80 in the Y-axis direction. The length of the connecting wire 84 in the X-axis direction is the same as the length of the unit plate 81 in the X-axis direction.

[0192] The connecting wiring 84 is formed using a conductive material. For example, the connecting wiring 84 can be integrally formed using the same material as the plate drive wire 82. Alternatively, the connecting wiring 84 may be integrally formed using the same material as the field plate 80. In other words, the connecting wiring 84 can be considered as part of the plate drive wire 82, or as part of the field plate 80.

[0193] The example shown in Figure 27 is a configuration in which the number of plate drive lines 82 per unit plate 81 is reduced by one compared to the example shown in Figure 26. In other words, there is a one-to-one correspondence between the unit plate 81 and the plate drive line 82. By reducing the number of plate drive lines 82, the gate-source capacitance Cgs can be reduced. By reducing the gate-source capacitance Cgs, the gain performance of the power amplification semiconductor device can be improved.

[0194] As described above, the power amplification semiconductor device according to the embodiment or each modified example may include a connecting wire 84 that connects two adjacent unit plates 81 to each other. The connecting wire 84 may be located between the gate finger 42 and the drain finger 52 in a plan view.

[0195] By connecting multiple unit plates 81 in the Y-axis direction, the wiring resistance of the field plate 80 can be reduced. This makes it easier to maintain in-plane uniformity of the source potential of the field plate 80.

[0196] In the example shown in Figure 28, the position of the connecting wire 84 is different from that of the example shown in Figure 26. Specifically, the connecting wire 84 is located on the opposite side of the drain finger 52, relative to the gate finger 42. More specifically, the connecting wire 84 is located so as to be in contact with the source connection portion 62.

[0197] This increases the surface area that contributes to heat dissipation, thus further enhancing the heat dissipation effect.

[0198] In the example shown in Figure 28, the position of the source via 70 may be different. Specifically, as shown in Figure 29, the center position of the source via 70 and the center position of the element isolation region 30 between adjacent unit channel regions 90 are the same in the Y-axis direction. Specifically, the center of the source via 70 in the Y-axis direction and the center of the element isolation region 30 in the Y-axis direction are located on a straight line L extending in the X-axis direction. In this case, the connecting wiring 84 is in contact with the source via 70.

[0199] This makes it easier for the heat diffused through the connecting wiring 84 to be transferred to the source via 70, thereby further enhancing the heat dissipation effect.

[0200] In the examples shown in Figures 26 to 29, the source via 70 may be a low-fill source via as shown in Figure 17, a connected source via as shown in Figure 18, or a group source via as shown in Figures 19 to 25.

[0201] [6. Manufacturing method] Next, the manufacturing method of the power amplification semiconductor device according to the above-described embodiment and its various modifications will be explained using Figures 30A to 30H. Figures 30A to 30H are cross-sectional views illustrating each step of the manufacturing method of the power amplification semiconductor device according to the embodiment and its various modifications. Each cross-sectional view represents the cross-section corresponding to the line II-II in Figure 1, that is, the cross-section passing through the source electrode 60, the gate electrode 40, and the drain electrode 50. The film thickness and materials used in the following explanation are merely examples and are not limited to those shown.

[0202] First, as shown in Figure 30A, a semiconductor layer 20 is formed on the main surface of the substrate 10. The semiconductor layer 20 is formed by depositing a GaN-based semiconductor film while adjusting the deposition conditions using an epitaxial growth method. The substrate 10 used for forming the semiconductor layer 20 is thicker than the substrate 10 after manufacturing, for example, with a thickness of 1000 μm. The thickness of the semiconductor layer 20 is, for example, 2 μm.

[0203] Although not shown in the figure, an element isolation region 30 is formed by ion implantation in a predetermined region of the grown semiconductor layer 20. Alternatively, contact layers 28d and 28s shown in Figure 14 may be formed by ion implantation in a predetermined region of the grown semiconductor layer 20.

[0204] Next, as shown in Figure 30B, the gate electrode 40, drain electrode 50, source electrode 60, gate finger 42, and field plate 80 are formed. For example, after forming a metal film by vapor deposition or sputtering, the gate electrode 40, drain electrode 50, source electrode 60, gate finger 42, and field plate 80 are formed by etching to a predetermined shape. The lift-off method may be used to form the electrodes, etc. If the same metal material can be used for the drain electrode 50 and source electrode 60, they can be formed in the same process. In addition, before forming the gate finger 42 and the field plate 80, an insulating film (not shown) is formed by plasma CVD (Chemical Vapor Deposition) or the like. The thickness of the electrodes, etc. is, for example, 0.2 μm. After forming the electrodes, etc., an insulating film to protect the electrodes, etc. may be formed by plasma CVD or the like.

[0205] Next, via holes 71 are formed as shown in Figure 30C. The via holes 71 are formed, for example, by etching. The via holes 71 penetrate the semiconductor layer 20 and are formed to engrave at least a portion of the substrate 10. The depth of the via holes 71 is, for example, 150 μm. The planar shape of the via holes 71 is, for example, a rectangle with a short side of 20 μm or less. The shape and number of via holes 71 are adjusted according to the shape and number of source vias 70. Not only the example shown in Figure 1, but also the examples shown in Figures 18 to 25 are applicable.

[0206] Next, as shown in Figure 30D, a metal film 74 is formed along the side surface of the via hole 71. The metal film 74 is formed, for example, by plating. As an example, an Au film with a thickness of 5 μm is formed. The metal film 74 is formed with a substantially uniform thickness along the side and bottom surface of the via hole 71. The metal film 74 is also provided on the edge portion of the opening on the semiconductor layer 20 side of the via hole 71. In the example shown in Figure 30D, the metal film 74 is in contact with the source electrode 60, but it does not have to be in contact with the source electrode 60.

[0207] Next, as shown in Figure 30E, a metal-filled portion 72 is formed. The metal-filled portion 72 is formed, for example, by plating. As an example, an Au or Cu film with a thickness of 5 μm is formed. This allows the via hole 71 with a short side of 20 μm to be filled. By adjusting the film thickness of the metal coating 74 and the metal-filled portion 72 according to the size of the via hole 71, the via hole 71 can be filled. Note that, as shown in Figure 17, it is not necessary to completely fill the via hole 71, so the metal coating 74 and the metal-filled portion 72 may be formed with a constant film thickness regardless of the size of the via hole 71. This forms the source via 70.

[0208] Furthermore, in the example shown in Figure 30E, the drain finger 52 and the source connecting portion 62 are formed in the same process as the formation of the metal-filled portion 72. The source connecting portion 62 is formed integrally with the metal-filled portion 72. In this case, a recess may be formed on the upper surface of the source connecting portion 62 in the portion that overlaps with the via hole 71 in a plan view, with the recess extending downward from the upper surface. In other words, the upper surface of the source connecting portion 62 does not have to be flat in the portion that overlaps with the via hole 71 in a plan view.

[0209] Next, as shown in Figure 30F, the bottom (back) surface of the substrate 10 is polished. Polishing is continued until at least the source vias 70 are exposed. For example, polishing is continued until the thickness from the top surface of the semiconductor layer 20 to the bottom surface of the substrate 10 is approximately 100 μm. This makes it possible to thin the semiconductor device for power amplification.

[0210] Next, as shown in Figure 30G, the bottom electrode 64 is formed. For example, a metal film made of a single metal or alloy containing at least one of Ti, Ni, Cr, W, Au, and Ag is formed as the bottom electrode 64 by vapor deposition or plating to cover the entire bottom surface of the substrate 10. Since the source vias 70 are exposed on the bottom surface of the substrate 10 during the polishing process, contact and electrical conductivity occur between the bottom electrode 64 and the source vias 70. The thickness of the bottom electrode 64 is, for example, about 1 μm. As an example, a metal laminate is formed as the bottom electrode 64 by stacking a Ti film with a thickness of 100 nm, a Ni film with a thickness of 600 nm, and an Au film with a thickness of 200 nm in that order from the substrate 10 side.

[0211] Through the above steps, a power amplification semiconductor device according to the above-described embodiment and each of its modifications is manufactured.

[0212] The manufactured power amplification semiconductor device may be packaged as needed, as shown in Figure 30H. Specifically, it is fixed to a package material made of resin, metal, or ceramic using a die bond material 66 such as AuSn or Ag.

[0213] (Other embodiments) Although a power amplification semiconductor device according to one or more embodiments has been described above based on embodiments and modifications, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to these embodiments that a person skilled in the art could conceive, as well as configurations constructed by combining components from different embodiments, are also included within the scope of this disclosure.

[0214] For example, an example has been shown in which multiple gate electrodes 40, drain electrodes 50, and source electrodes 60 are arranged in the Y-axis direction, but the invention is not limited to this. In other words, the gate electrodes, drain electrodes, and source electrodes do not necessarily have to be separated in the Y-axis direction. For example, multiple gate electrodes 40 arranged in the Y-axis direction may be connected to each other and form a single gate electrode. That is, a single gate electrode may be provided not only on the semiconductor layer 20 but also on the element isolation region 30. The same applies to the drain electrodes 50 and source electrodes 60.

[0215] Furthermore, while an example has been shown in which one source via 70 or multiple source vias 70A, 70B, or 70C are provided in all of the multiple unit source regions 92, the example is not limited to this. There may be unit source regions 92 in which no source vias 70, 70A, 70B, or 70C are provided.

[0216] Alternatively, source vias may not be provided in any of the multiple unit source regions 92. For example, as in the power amplification semiconductor device 1x in the comparative example, source vias 70x may be provided outside the source region.

[0217] Furthermore, although source vias 70, 70A, 70B, and 70C are shown as examples that include a metal-filled portion 72 and a metal coating 74, they are not limited to this. Source vias 70, 70A, 70B, and 70C may include only the metal-filled portion 72, or only the metal coating 74.

[0218] Furthermore, if multiple unit plates 81 are connected to each other, multiple plate drive lines 82 may not be provided. In other words, the supply of source potential to each of the multiple unit plates 81 may be performed along the Y-axis direction.

[0219] Furthermore, each of the above embodiments may be modified, replaced, added, or omitted in various ways within the scope of the claims or equivalent thereof. [Industrial applicability]

[0220] This disclosure can be used as a power amplification semiconductor device that can suppress thermal degradation of its properties, and can be used, for example, as a high-frequency transistor, or in various electronic devices such as communication equipment. [Explanation of Symbols]

[0221] 1, 2, 3, 4, 5, 6 Semiconductor devices for power amplification 10 circuit boards 20 Semiconductor Layers 22 Two-dimensional electron gas 24 GaN layers 26 AlGaN layers 28d, 28s Contact layer 30, 32 element isolation regions 31 Active area 40 Gateway 42 Gate Finger 44 Gate Bus 50 Drain electrode 50r, 60r recessed section 52 Drain Finger 54 Drain Bath 60 source electrodes 62 Source connection section 64 Bottom electrode 66 Die Bond Materials 70, 70A, 70B, 70C Source Beer 71 Beer Hall 72 Metal filling part 74 Metal coating 75 Space 76 Via connection section 80 Field Plate 81 Unit Plate 82 Plate drive wire 84 Connecting Wiring 90-unit channel region 92 Unit Source Area 94 Minimum rectangular area

Claims

1. circuit board and A lower electrode provided below the substrate, A semiconductor layer provided above the substrate, comprising a plurality of active layers of group III nitride, wherein a two-dimensional electron gas is generated at the heterointerface of the plurality of active layers, A source electrode and a drain electrode are provided above the semiconductor layer at intervals, and each is electrically connected to the two-dimensional electron gas, A gate electrode is provided at a distance from the source electrode and the drain electrode, and contacts the semiconductor layer, A field plate is provided between the gate electrode and the drain electrode above the semiconductor layer and is set to the same potential as the source electrode, A gate finger is positioned above a plurality of gate electrodes arranged linearly in a first direction, and contacts and covers all of the plurality of said gate electrodes. The device comprises drain fingers positioned above a plurality of drain electrodes arranged linearly in the first direction, which contact and cover all of the plurality of drain electrodes, The semiconductor layer is divided, in a plan view of the substrate, into an active region where the two-dimensional electron gas is present and an element isolation region where the two-dimensional electron gas is absent. In the plan view, the channel region, which is the overlapping portion of the active region and the gate electrode, is a plurality of unit channel regions that are divided and arranged in the first direction by the element isolation region. The source electrode is a plurality of unit source electrodes facing each of the plurality of unit channel regions, The field plate is a plurality of unit plates facing each of the plurality of unit channel regions, Multiple plate drive lines, extending in a second direction perpendicular to the first direction and electrically connecting multiple unit source electrodes and multiple unit plates, are provided within the element isolation region, one or more for each unit plate. The aforementioned plurality of unit plates are provided with connecting wiring that connects two adjacent unit plates to each other. The aforementioned connecting wiring is located between the gate finger and the drain finger in the plan view. A semiconductor device for power amplification.

2. The plurality of plate drive lines are in contact with the element isolation region. The power amplification semiconductor device according to claim 1.

3. The gate finger is positioned above and spaced apart from the plurality of plate drive lines. The power amplification semiconductor device according to claim 1.

4. Each of the multiple unit source regions, including each of the multiple unit source electrodes, has one or more source vias, through which the substrate and the semiconductor layer are opened and which contain a conductor that contacts the bottom electrode set to the same potential as the source electrode. The power amplification semiconductor device according to claim 1.

5. In the first direction, the center position of the source via and the center position of the element isolation region between adjacent unit channel regions are the same. The power amplification semiconductor device according to claim 4.

6. The semiconductor layer includes a contact layer that electrically connects the two-dimensional electron gas and the source electrode at the surface of the semiconductor layer. The power amplification semiconductor device according to claim 1.

7. The unit plate and the unit channel region correspond one-to-one. The power amplification semiconductor device according to claim 1.

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