Contact formation within a semiconductor chip having a pillar-based memory array

Abstract

Disclosed is an approach to provide a semiconductor structure that provides a self-leveling, flowable dielectric material for gap-fill material between vertical structures in many emerging non-volatile memory devices formed with vertical structures to increase memory device density. The semiconductor structure provides a planar dielectric surface between a plurality of contacts in a back-end-of-the-line metal layer in both memory and logic regions of the semiconductor structure. The semiconductor structure includes a first portion of a plurality of contacts, each of which connects to a pillar-based memory device in an array of pillar-based memory devices. The first portion of the plurality of contacts, each of which connects to a pillar-based memory device in the array of pillar-based memory devices, reside in a conventional interlayer dielectric material below the self-leveling dielectric material. The flowable, self-leveling material provides a planar dielectric surface during contact formation.

Description

Technical Field

[0001] The present invention relates generally to the field of semiconductor technology, and more specifically, to forming contacts in a semiconductor chip having a pillar-based memory array adjacent to a logic device.

Background Art

[0002] Nowadays, increasing computing functionality requires both more device circuits and higher processing speeds for computer systems and applications. In particular, the use of deep neural networks is becoming widespread in many end-user computer applications. Deep neural networks are typically used in artificial intelligence (AI) applications. Training of deep neural networks places tremendous demands on memory systems in computer systems that run AI applications using deep neural networks. The growing demand for high-performance memory systems continues to drive the development of new and advanced memory devices in memory chips.

[0003] Non-volatile memory (NVM) or non-volatile storage is a type of computer memory that can retain stored information even after power is removed. Non-volatile memory generally refers to storage in semiconductor memory chips, which typically store data in floating gate memory cells consisting of floating gate metal-oxide-semiconductor field-effect transistors (MOSFETs), and includes flash memory storage such as NAND flash and solid-state drives (SSD).

[0004] Developments in advanced memory devices for NVMs include several new technological developments in NVM memory devices. Magnetoresistive random-access memory (MRAM) is a type of non-volatile random-access memory that stores data within magnetic domains using magnetic tunnel junctions (MTJs) formed with multiple thin layers of magnetic and non-magnetic stacking materials. Resistive random-access memory (RRAM or ReRAM) devices work by varying resistance across dielectric solid-state materials. Phase-change random-access memory (PCRAM or PCM) uses phase-change materials, which have at least two phases, a crystalline phase and an amorphous phase, that have very different electrical properties for set and reset states for storing and retrieving data.

[0005] The demand for high-performance memory systems in current computer applications is also driving the increase in memory device density. Reducing the pitch or space between memory devices increases the number of available memory devices within a memory chip and improves memory chip performance. Many emerging NVM memory devices are formed using a vertical structure or pillars in pursuit of increasing memory device density. [Overview of the Initiative]

[0006] Embodiments of the present invention provide a self-leveling, fluid dielectric material for dielectric gap filling material between vertical structures for many emerging non-volatile memory devices formed using vertical structures or pillars to increase memory device density. Embodiments of the present invention use a self-leveling dielectric material to provide a flat dielectric surface within the memory region and logic region of a semiconductor structure prior to and after device contact formation. Multiple contacts of a first portion each connect to a pillar-based memory device in an array of pillar-based memory devices residing within the memory region of a semiconductor structure. Embodiments of the present invention disclose that the array of pillar-based memory devices consists of one of the following: an array of magnetoresistive random access memory devices, an array of resistive random access memory devices, or an array of phase-change random access memory devices. The self-leveling dielectric material provides a flat dielectric surface without a back-end-of-the-line metal layer within the memory region, within the logic region, and within the transition region between the memory region and the logic region of the semiconductor structure.

[0007] The second conventional interlayer dielectric material rests on the self-horizontal dielectric material. Multiple contacts in the first portion within the memory region have vertical sides covered by the second conventional interlayer dielectric material, while contacts within the logic region of the semiconductor structure reside within the self-horizontal dielectric material. The wedge-shaped portion of the self-horizontal dielectric material lies between the sides of the second dielectric material surrounding each contact of multiple contacts with adjacent pillar-based memory devices in an array of pillar-based memory devices.

[0008] Embodiments of the present invention provide a semiconductor structure having one or more portions of a first metal layer within a first dielectric material. One or more portions of the first metal layer are present within the logic region and the memory region of the semiconductor structure. The first portion of the first metal layer within the first dielectric material is beneath each pillar-based memory device in an array of pillar-based memory devices in the memory region. Embodiments of the present invention include an array of pillar-based memory devices, each array comprising one of magnetoresistive random-access memory devices, resistive random-access memory devices, or phase-change random-access memory devices. Embodiments of the present invention provide a semiconductor structure including a sealing dielectric material surrounding each pillar-based memory device in the array of pillar-based memory devices in the memory region. The sealing dielectric material is also present above one or more portions of the first metal layer in the logic region and above the first dielectric material.

[0009] Embodiments of the present invention include a second conventional interlayer dielectric material located on top of a sealing dielectric material and between adjacent contacts for each pillar-based memory device in an array of pillar-based memory devices. Each contact for each pillar-based memory device is formed within a second metal layer located above the array of pillar-based memory devices. The second conventional interlayer dielectric material is located on top of the sealing dielectric material in the logic region and surrounds the lower portion of the contacts formed from the second metal layer in the logic region of the semiconductor structure. Furthermore, embodiments of the present invention include a self-horizontal dielectric material located on top of the second conventional interlayer dielectric material in the logic region. The self-horizontal dielectric material surrounds the upper portion of the contacts in the logic region of the semiconductor structure. The self-horizontal dielectric material provides a flat dielectric surface for the semiconductor structure prior to contact formation.

[0010] Embodiments of the present invention provide another semiconductor structure having a first interlayer dielectric material having a flat surface between a plurality of portions of a back-end-of-the-line metal layer. Each portion of the plurality of portions of the back-end-of-the-line metal layer in the memory region of the semiconductor structure connects to a pillar-based memory device in an array of pillar-based memory devices. The self-horizontal dielectric material lies beneath the first interlayer dielectric material and the plurality of portions of the back-end-of-the-line metal layer. The self-horizontal dielectric material lies beneath the plurality of portions of the back-end-of-the-line metal layer and the first interlayer dielectric material. Embodiments of the present invention provide a fluid dielectric material for the self-horizontal dielectric material. The self-horizontal dielectric material lies on a sealing dielectric material in the logic region and memory region of the semiconductor structure. The self-horizontal dielectric material on the sealing dielectric material fills the gaps between adjacent pillar-based memory devices. The self-horizontal dielectric material provides a flat surface for the deposition of the first interlayer dielectric material during contact formation to prevent smeared contact metal on the first interlayer dielectric material after contact formation. The fluid, self-horizontal dielectric material provides a flat dielectric surface for void-free gap filling and contact formation between pillar-base memory devices in an array of pillar-base memory devices.

[0011] Embodiments of the present invention provide a method for forming a semiconductor structure having a flat upper surface of a self-horizontal dielectric material between multiple contacts to an array of pillar-based memory devices, and for surrounding one or more contacts to one or more logic devices within the logic region of the semiconductor structure. The method includes depositing a first dielectric material on a sealing dielectric material covering the logic region and the memory region of the semiconductor structure. The memory region includes one or more pillar-based memory devices, each resting on a portion of a first metal layer. The method includes depositing a self-horizontal dielectric material on the first dielectric material. The second self-horizontal dielectric material is deposited using a vacuum plasma chemical vapor deposition process with one or both of an origanosilicon precursor and / or an oxygen precursor to deposit the second self-horizontal dielectric material. The second self-horizontal dielectric material is a fluid low-k dielectric material. The method includes performing chemical mechanical polishing to remove the upper portion of the second self-horizontal dielectric material and the upper portion of the first dielectric material within the memory region. After chemical mechanical polishing, the upper surfaces of the first dielectric material and the second self-horizontal dielectric material are flat and horizontal. The method includes forming one or more contacts within the second metal layer. One or more contacts in the first portion and one or more contacts in the second portion within the memory region are formed within the second self-horizontal dielectric material within the logic region of the semiconductor structure. The upper surface of the second self-horizontal dielectric material is flat and free from residual back-end-of-the-line metal material.

[0012] The above and other embodiments, features, and advantages of various embodiments of the present invention will become more apparent from the following description, in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0013] [Figure 1] This is a cross-sectional view of a portion of a semiconductor structure having a logic region and a memory region according to one embodiment of the present invention. [Figure 2]This is a cross-sectional view of a portion of a semiconductor structure after depositing a fluid low-k dielectric material for a self-leveling (SL) dielectric material according to one embodiment of the present invention. [Figure 3] This is a cross-sectional view of a portion of a semiconductor structure after chemical mechanical polishing (CMP) has been performed according to one embodiment of the present invention. [Figure 4] This is a cross-sectional view of a semiconductor structure after a contact point for an NVM pillar, a line in a metal layer formed above a logic device region, and a via have been formed, according to one embodiment of the present invention. [Figure 5] This is a cross-sectional view of a semiconductor structure after an interlayer dielectric (ILD) material layer has been deposited on a sealing dielectric material according to a second embodiment of the present invention. [Figure 6] This is a cross-sectional view of a semiconductor structure after depositing a sacrificial self-horizontal dielectric material on an ILD material, according to a second embodiment of the present invention. [Figure 7] This is a cross-sectional view of a semiconductor structure after chemical mechanical polishing (CMP) has been performed according to a second embodiment of the present invention. [Figure 8] This is a cross-sectional view of a semiconductor structure after forming a contact point for an NVM pillar, a line in a metal layer deposited on a logic device region, and a via, according to a second embodiment of the present invention. [Figure 9] This is a cross-sectional view of a semiconductor structure after a layer of self-horizontal dielectric material has been deposited on a sealing dielectric material according to a third embodiment of the present invention. [Figure 10] This is a cross-sectional view of a semiconductor structure after CMP has been performed according to a third embodiment of the present invention. [Figure 11] This is a cross-sectional view of a semiconductor structure according to one embodiment of the present invention, after a layer of ILD material has been deposited on the exposed surface of a self-horizontal dielectric material and on the upper surface of an NVM pillar. [Figure 12]This is a cross-sectional view of a semiconductor structure after forming contacts with an NVM pillar, lines within a deposited metal layer, and vias according to a third embodiment of the present invention. [Figure 13] This figure shows an example of a method using a maskless interlayer dielectric removal process and a self-horizontal dielectric material to form an embedded pillar-based NVM device according to multiple embodiments of the present invention. [Modes for carrying out the invention]

[0014] In embodiments of the present invention, it is recognized that using a vertical pillar-based memory structure having non-pillar-based logic devices, circuits, and macros during the formation of advanced memory devices presents challenges in providing a horizontal surface of interlayer dielectric material during back-end-of-the-line (BEOL) interconnection layer formation. In embodiments of the present invention, it is recognized that it is difficult to provide a horizontal interlayer dielectric material surface height within a semiconductor structure having one or more arrays of pillar-based memory structures and one or more adjacent regions of logic devices, circuits, or macros or combinations thereof that are not formed by the vertical pillar-based structure.

[0015] In embodiments of the present invention, it is recognized that the inability to provide horizontal or flat surfaces of interlayer dielectric material between and within areas having arrays of pillar-based memory devices, as well as in adjacent areas above non-pillar-based logic devices, can lead to BEOL metal short circuits after contact formation with respect to the array of pillar-based memory devices. Non-horizontal or non-uniform surfaces of the interlayer dielectric material can cause puddling or smearing of the BEOL metal material after contact formation in the metal layer directly above, and connections to the pillars within the array of pillar-based memory devices. In particular, using chemical mechanical polishing to planarize the metal layer deposited on the interlayer dielectric material during contact formation above each pillar-based memory device and during line and contact formation above logic device areas can cause smearing or incomplete removal of the contact metal. Incomplete removal of the BEOL metal forming the contacts typically occurs when the surface of the interlayer dielectric material above the array of pillar-based memory structures is higher than the surface of the interlayer dielectric material above adjacent logic devices. When the upper surface of the interlayer dielectric material is non-uniform prior to and during contact formation for a pillar-based memory device or array of cells, or cell and line formation above a logic device, a given portion of the BEOL metal forming the contacts may be trapped in a dip within the interlayer dielectric material between the non-uniform interlayer dielectric surface, or between the higher surface of the interlayer dielectric material above the array of pillar-based memory structures and the lower surface of the interlayer dielectric material above a logic device adjacent to the array of pillar-based memory devices. Smeared BEOL metal within the non-uniform region of the interlayer dielectric material may cause one or more hard shorts after BEOL interconnect layer formation (e.g., after planarization of the BEOL metal layer for contact and line formation).

[0016] Embodiments of the present invention recognize that a method for forming a flat or horizontal surface of interlayer dielectric material within a semiconductor structure having an array of pillar-based memory structures adjacent to a region of non-pillar-based logic devices is further complicated by the different densities or inter-pillar pitches within various arrays of pillar-based memory devices. Embodiments of the present invention recognize a method and structure for providing coplanar interlayer dielectric surfaces inside and outside an array of pillar-based memory structures prior to and after forming contacts that connect to each pillar-based memory cell or device array. Furthermore, embodiments of the present invention recognize that a method and semiconductor structure for consistently providing horizontal dielectric material surfaces or flat interlayer dielectric material surfaces across different types of pillar-based memory structures using different design ground rules and different inter-pillar pitches during BEOL interconnect formation would be desirable.

[0017] Embodiments of the present invention provide semiconductor structures and methods for forming semiconductor structures having a flat or horizontal interlayer dielectric (ILD) material surface prior to and during the creation of contacts in an interlayer dielectric material immediately above and connected to one or more pillar-based memory structures, adjacent logic devices, circuits, and macros. In embodiments, the method for forming parts of various semiconductor structures uses low-temperature self-horizontal, fluid chemical vapor deposition (CVD) of SiCOH as a self-horizontal low-k dielectric material in combination with conventional or non-self-horizontal dielectric materials. The self-horizontal low-k dielectric material is not limited to SiCOH and, in other embodiments, can be another low-k dielectric material (e.g., a dielectric material having a dielectric constant of less than 4). In embodiments of the present invention, the self-horizontal low-k dielectric material can be considered as an interlayer dielectric material.

[0018] Embodiments of the present invention provide a deposition process for a self-planarizing low-k dielectric material, comprising depositing the self-planarizing low-k dielectric material using a vacuum plasma chemical vapor deposition process. Vacuum plasma chemical vapor deposition may utilize one or both of organosilicon and an oxygen precursor at a low temperature (e.g., 50°C to 100°C) to maintain the self-planarizing property and flowability of the low-k dielectric material. Material hardening of the self-planarizing low-k dielectric material is achieved by UV curing at a high temperature (e.g., 150°C to 450°C) in embodiments of the present invention. Further, embodiments of the present invention include chemical mechanical polishing (CMP) of the self-planarizing low-k dielectric material to provide a horizontal or flat top surface for a semiconductor structure prior to contact formation for a pillar-based memory structure and contact formation over one or more logic devices of a logic device. The pillar-based memory structure may be present on a portion of a back end of line (BEOL) or middle of the line (MOL) metal layer, which may be an Mx metal layer (e.g., an M1 metal layer, an M2 metal layer, etc.).

[0019] The provided method includes a maskless process for ILD topography removal using a self-horizontal and fluid dielectric material together with a conventional interlayer dielectric material (e.g., not a self-horizontal dielectric material deposited by plasma CVD, etc.) to provide a horizontal or planar ILD upper surface above a pillar-based memory structure. In one embodiment, the maskless process includes first depositing a conventional non-horizontal ILD material around the NVM pillars to a thickness that extends the upper surface of the conventional ILD above the NVM pillars. A second sacrificial self-planarizing (e.g., fluid) dielectric material is deposited on top of the conventional ILD to improve planarity within and outside the NVM array. A subsequent CMP of the sacrificial self-planarizing dielectric material is performed to polish away the self-horizontal dielectric material. The CMP stops within the conventional ILD at an appropriate distance from the NVM pillars, as determined by integration requirements / process assumptions, to form contacts with the NVM pillars. The method does not require the use of a mask or further mask levels. The termination of the method does not change the conventional ILD height or thickness and the next horizontal metal layer above and in contact with the pillar base memory structure.

[0020] Embodiments of the present invention provide several methods of forming a semiconductor structure having a planar ILD surface immediately above and between one or more arrays of pillar-based memory devices and adjacent to an area above non-pillar-based logic devices prior to forming contacts and lines in a metal layer overlying the pillar-based memory structure and the logic devices. The method for producing a semiconductor structure having a planar or horizontal ILD surface prior to forming BEOL metal contacts on pillars of a pillar-based memory structure reduces BEOL metal smearing during a CMP process that may occur in BEOL contact formation. As discussed above, the planar ILD surface prevents hard shorts caused by smeared BEOL metal during memory device contact formation, where the smeared BEOL metal can be trapped in a dip or transition area between a higher ILD surface above the array of pillar-based memory structures and a lower ILD surface in memory devices formed by conventional methods without a planar ILD surface prior to and during contact formation.

[0021] Embodiments of the present invention provide a semiconductor structure having a surface height such that the ILD immediately above one or more arrays of pillar-based memory structures is the same as the ILD surface height above an area having one or more non-pillar-based logic devices. The use of a self-horizontal low-k dielectric material within the semiconductor structure enables the formation of horizontal ILD surfaces having the same surface height within arrays of pillar-based memory structures, within transition areas between arrays of pillar-based memory structures and logic devices, and within the ILD surface above logic device areas. Embodiments of the present invention provide a semiconductor structure in which the pillar-based memory structure can be any type of pillar-based memory device, including magnetoresistive random access memory (MRAM) devices, phase-change random access memory (PCM) devices, resistive random access memory (RRAM) devices, and other pillar-based memory devices. Embodiments of the present invention include a pillar-based memory structure for MRAM devices. PCM devices and RRAM devices can be used as non-volatile memory in semiconductor devices.

[0022] Embodiments of the present invention provide a method for forming a semiconductor structure that is free from hard short circuits caused by smeared BEOL metal on a non-uniform ILD surface between a pillar-based memory structure and a logic device. The method creates a horizontal ILD surface both inside and outside the pillar-based memory structure. The method includes using a conventional BEOL metallization process or damascene process to form lower contacts or lines within a portion of a BEOL or MOL metal layer, such as an Mx metal layer, which can be an M1 metal layer or an M2 metal layer. One or more contacts may be formed within each portion of the Mx metal layer in the memory region of the semiconductor structure on a semiconductor substrate.

[0023] Embodiments of the present invention utilize conventional pillar formation processes for memory devices, such as depositing layers of material for the lower electrodes and material for one or more magnetic tunneling junctions (MTJs), or layers of material for one or more phase-change memory cells, or layers of material for RRAM devices, and selectively etching the layers of material (e.g., using patterning and reactive ion etch). After selective etching, pillar-based memory structures for one of MRAM, PCM, or RRAM memory cells or devices are formed in various embodiments of the present invention. In embodiments of the present invention, a encapsulating material is deposited on top of a semiconductor structure (e.g., on top of the pillar-based memory structures within the memory region of the semiconductor structure and on areas adjacent to the logic region of the semiconductor structure).

[0024] Embodiments of the present invention include a method for forming a semiconductor structure by depositing a thinner layer of ILD material, a thicker layer of ILD material, or a self-horizontal dielectric material on a encapsulating material which is located on one or more pillar-based memory structures that may be in an array of pillar-based memory structures and above one or more logic devices in a region adjacent to the pillar-based memory structures. The surface of the ILD material is higher than the surface of the ILD above the logic devices in the memory region above the pillar-based memory structures.

[0025] In embodiments of the present invention having the deposited ILD material, the layer of self-horizontal dielectric material is deposited by a chemical vapor deposition process after the ILD material has been deposited. The self-horizontal dielectric material is a fluid low-k dielectric material that provides a more horizontal surface compared to the ILD material.

[0026] After depositing the self-horizontal dielectric material, CMP (Chemical Manufacturing) is performed to planarize or horizontalize the surface of the semiconductor structure. In embodiments of the present invention having a thicker deposited ILD material, CMP is performed to remove all of the self-horizontal dielectric material. In embodiments of the present invention having a thinner ILD material, CMP is performed to remove predetermined portions of the self-horizontal dielectric material above the logic device and the upper portion of the self-horizontal dielectric material above the array of pillar-based memory structures, while leaving portions of the self-horizontal dielectric material above the logic device region and between adjacent pillars in the array of pillar-based memory structures (see Figure 3).

[0027] In embodiments of the present invention, CMP is performed with the self-horizontal dielectric material on the sealing material rather than on the ILD material, removing the upper portion of the self-horizontal dielectric material above the logic device while leaving the lower portion of the self-horizontal dielectric material within the logic device region, removing the upper portion of the self-horizontal dielectric material above the pillars within the memory region, and then depositing a layer of ILD material on the remaining self-horizontal dielectric material. In each embodiment of these embodiments, CMP is performed after the deposition of the self-horizontal dielectric material, and after CMP, the upper surface of the semiconductor structure (e.g., the upper surface of the remaining self-horizontal dielectric material and ILD material or the upper surface of the self-horizontal dielectric material or both) is flat. In each embodiment, using a known BEOL metallization process, contacts for each pillar for each memory device are formed in the ILD material with a flat upper surface. The contacts formed on the ILD material are formed without BEOL metal smear, which could cause hard short circuits in the metal layer.

[0028] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not constitute a complete process flow for manufacturing integrated circuits, such as semiconductor devices. These embodiments may be implemented in conjunction with the integrated circuit fabrication techniques currently used in the prior art for advanced semiconductor devices, such as advanced semiconductor devices using design features of 25 nanometers or less, and only a limited number of commonly implemented process steps are included as necessary for understanding the embodiments described. The figures show cross-sectional portions of the logic and memory regions of the fabricated semiconductor devices and are not drawn according to a constant proportional scale, but rather to illustrate the features of the embodiments described. Certain structural and functional details disclosed herein are to be construed not as limitations, but merely as representative grounds to teach those skilled in the art how to use the methods and structures of this disclosure in various ways. In the description, well-known features and technical details may be omitted to avoid unnecessarily obscuring the embodiments presented.

[0029] The deposition processes used herein include, but are not limited to, chemical vapor deposition (CVD), plasma vapor deposition (PVD), electroplating, ionized plasma vapor deposition (iPVD), atomic layer deposition (ALD), and plasma-enhanced chemical vapor deposition (PECVD).

[0030] As is known to those skilled in the art, the common BEOL processes discussed herein include dual damascene, single damascene, and subtractive metal etching processes. Dual damascene processes are most commonly used for BEOL patterning and metallization processes. Dual damascene processes typically involve patterning vias and trenches within a dielectric material such as an interlayer dielectric material, filling the vias, holes, and trenches with a layer of deposited metal (BEOL metals including, but not limited to, copper, tungsten, cobalt, or ruthenium), and leveling the metal using a chemical mechanical process (CMP) to remove overload or excess metal. A single damascene process includes patterning via holes in a first dielectric material, filling the via holes with a deposited metal layer, then performing CMP to remove overload or excess metal, then depositing a second dielectric material, then performing a second etching process to form trenches, filling the trenches with a metal layer, and then performing CMP to remove the overload metal layer. In some embodiments, a subtractive metallization process is used, in which a metal layer is deposited, patterned, and etched, and a dielectric material is deposited on top of the upper surface. CMP exposes the upper surface of the patterned metal.

[0031] The patterning processes discussed herein include, but are not limited to, lithography, photolithography, extreme ultraviolet (EUV) lithography, or any other known semiconductor patterning processes following one or more of the etching processes discussed below.

[0032] The etching processes discussed herein, which remove portions of material patterned or masked by a lithography process, include, but are not limited to, dry etching processes using reactive ion etching (RIE) or ion beam etching (IBE), wet chemical etching processes, or combinations thereof.

[0033] References herein to “one embodiment,” “other embodiment,” “another embodiment,” and “an embodiment” indicate that the embodiments described may include certain features, structures, or characteristics, but not all embodiments may necessarily include certain features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiments. Moreover, when certain features, structures, or characteristics are described in relation to one embodiment, it is understood that, whether explicitly described or not, such features, structures, or characteristics may be affected in relation to other embodiments, and this is within the knowledge of those skilled in the art.

[0034] For the purposes of the following explanation, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives are related to the structures and methods disclosed, as oriented in the drawings. The terms “overling,” “atop,” “over,” “positioned on,” or “positioned atop” mean that the first element is located on the second element, and that intervening elements, such as interface structures, may be located between the first and second elements. The term “direct contact” means that the first and second elements are connected at the interface between the two elements without an intervening conductive, insulating, or semiconductor layer.

[0035] To avoid ambiguity in the presentation of embodiments of the present invention, some processing steps, materials, or operations known in the art may be combined for presentation and illustration purposes in the following detailed description, and in some cases, may not be described in detail. Furthermore, in order to remain concise and to continue focusing on the distinctive features of the elements of the present invention, descriptions of materials, processes, and structures discussed above may not be repeated with respect to the subsequent figures. In other cases, some known processing steps or operations may not be described. It should be understood that the following description focuses rather on the distinctive features or elements of various embodiments of the present invention.

[0036] Figure 1 is a cross-sectional view of a portion of a semiconductor structure 100 having a logic region A and a memory region B according to one embodiment of the present invention. As shown, Figure 1 includes a predetermined portion of the logic region A, memory region B, Mx metal 10, interlayer dielectric (ILD) 9, cap 11, sealing dielectric 13, lower contact 12, non-volatile memory (NVM) pillar 15, and ILD 3. The lower contact 12 and NVM pillar 15 can form a pillar-based memory device (e.g., MRAM, PCM, or RRAM). In various embodiments, each of the NVM pillars 15 includes an upper electrode (not shown in Figure 1).

[0037] H1 is also labeled in Figure 1. H1 indicates the difference in height from the upper surface of the ILD3 above the NVM pillar 15 to the upper surface of the ILD3 in logic region A. For example, a typical value for H1 between the upper surface of the ILD3 above the NVM pillar 15 and the upper surface of the ILD3 in logic region A is usually in the range of 20-300 nm. H1 indicates the change in height of the upper surface of the ILD3 in the transition area between logic region A and memory region B. Observed and discussed above, in the formation of semiconductor devices having an array of NVM pillars 15 adjacent to a region of non-pillar logic devices, the non-uniform surface of the ILD3 (shown in Figure 1 as H1 indicating the difference in height between the upper surface of the ILD3 in logic region A and the upper surface of the ILD3 in memory region B) can cause copper padding or smearing during contact formation with the NVM pillar 15, via formation in logic region A, and Mx+1 metal line formation in later process steps. As discussed above, in a conventionally formed semiconductor device having an array of pillar-based semiconductor memory devices, when there is a significant difference in the height of the upper surface of ILD3 in logic region A and memory region B (e.g., H1 is large), a hard short circuit may occur in the transition region between logic region A and memory region B due to smeared copper or other BEOL metal.

[0038] Each Mx metal 10 is part of a back-end-of-the-line (BEOL) or middle-of-the-line (MOL) metal layer. In various embodiments, Mx metal 10 is part of an M1 metal layer. In other embodiments, Mx metal 10 is another metal layer (e.g., an M2 metal layer). ILD9 is a dielectric material that forms an interlayer dielectric around the Mx metal 10. For example, ILD9 can be a low-k dielectric material such as SiCOH, but is not limited to this ILD material.

[0039] The cap 11 is located on a predetermined portion of the ILD9 and Mx metal 10. In various embodiments, the cap 11 is a low-k dielectric material composed of a combination of silicon (Si), carbon (C), nitrogen (N), and hydrogen (H), such as SiNC, SiCNO, nitrogen-doped silicon carbide, SiN, boron nitride (BN), or any other suitable low-k dielectric cap material for NVM memory devices.

[0040] As shown, the sealing dielectric 13 covers the exposed surfaces of the cap 11 and lower contact 12 and the NVM pillar 15 within the memory region B. In various embodiments, the sealing dielectric 13 is composed of SiN, but it can be any dielectric material suitable for covering or sealing the NVM pillar 15, lower contact 12, and cap 11.

[0041] ILD3 is a dielectric material. For example, ILD3, which is an Mx+1 metallic ILD, may be composed of SiCOH (silicon, carbide, oxygen, and hydrogen), but is not limited to this low-k dielectric material and can be any suitable low-k dielectric material used for the ILD in the formation of an NVM device. ILD3 may be deposited using, for example, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or CVD. In this embodiment, ILD3 is a thin layer of ILD material compared to ILD53 shown in Figure 5. For example, the thickness of ILD3 is about 50% to 150% of the NVM pillar height, including the height of the NVM pillar 15 and the lower contact 12.

[0042] The lower contact 12 may be composed of any metal typical of BEOL contact metals, such as copper (Cu), tantalum (Ta), titanium (Ti), cobalt (Co), or ruthenium (Ru), but is not limited to these metallic materials. The lower contact 12 may be formed together with the NVM pillar 15 using known semiconductor processes for memory device pillar formation (e.g., lower contact deposition, pillar material deposition, and selective etching processes).

[0043] The NVM pillar 15 can be formed from various material layers for NVM memory device formation. In some examples, the NVM pillar 15 can be formed by one or more magnetic tunnel junctions (MTJs). In other examples, the NVM pillar 15 includes a pillar formed with one or more layers of phase-change material and other materials or liners used in PCM memory device pillar formation. The NVM pillar 15 can be present in the formation of magnetoresistive random-access memory (MRAM) devices, phase-change memory (PCM) devices, resistive random-access memory (ReRAM or RRAM) devices, or any other current or emerging non-volatile memory device technology. For example, the typical height of the NVM pillar 15 can range from 25 to 300 nm, but is not limited to this range. In various embodiments, the NVM pillar 15 can form one or more arrays of pillars that are densely packed or closely spaced (e.g., less than 40 nm between adjacent NVM pillars 15).

[0044] Figure 2 is a cross-sectional view of a semiconductor structure 200 after a layer of self-horizontal (SL) dielectric 4 has been deposited on an LD3 according to one embodiment of the present invention. As shown, Figure 2 includes the elements of Figure 1 and the self-horizontal (SL) dielectric 4. In various embodiments, the SL dielectric 4 may be deposited using a vacuum plasma chemical vapor deposition process that further utilizes organosilicon and oxygen precursors at low temperatures (50 to 100 degrees Celsius), followed by UV curing at high temperatures (150 to 450 degrees Celsius) to provide dielectric material hardening, but embodiments of the present invention are not limited to this deposition method.

[0045] In various embodiments, the SL dielectric 4 is composed of a self-horizontal and fluid low-k dielectric material. For example, the SL dielectric 4 is composed of a fluid SiOCH (silicon, oxygen, carbide, hydrogen) material, but the SL dielectric 4 is not limited to this fluid low-k dielectric material and can be any other fluid low-k dielectric material suitable for forming a semiconductor device having NVM pillars 15. The fluidity of the dielectric material provides the SL dielectric 4 with the ability to planarize or self-planarize the surface of the low-k dielectric material. After deposition and curing, the SL dielectric 4 provides a relatively flat and uniform upper surface. After deposition of the SL dielectric 4, a small difference exists between the height of the upper surface of the SL dielectric 4 in logic region A and the height of the upper surface of the SL dielectric 4 in memory region B, as shown by H2 in Figure 2 (for example, H2 is usually less than half the height of the NVM pillars 15). The deposition of the SL dielectric 4 reduces the difference in the height of the upper surfaces of logic region A and memory region B within the semiconductor structure 200. In various embodiments, the SL dielectric 4 can be deposited by the fluid chemical vapor deposition process discussed above with a typical thickness in the range of 20 to 500 nm, but it can also be deposited by other deposition processes and other thicknesses. The thickness of the SL dielectric 4 may vary depending on the structure (e.g., the height of the NVM pillars 15) and the dimensions of the pitch between pillars in the array of NVM pillars 15. The thickness of the SL dielectric 4 can be approximately the same as or greater than the height of the combined NVM pillars 15 and ILD 3, but is not limited to this thickness.

[0046] Figure 3 is a cross-sectional view of a semiconductor structure 300 after CMP has been performed according to one embodiment of the present invention. As shown, Figure 3 includes the elements of Figure 2, but with the upper portion of the SL dielectric 4 and a predetermined portion of the ILD3 removed by CMP. CMP removes the upper portions of the SL dielectric 4 and ILD3 in order to flatten or level the upper surface of the semiconductor structure 300. In particular, CMP removes the upper portions of the SL dielectric 4 and ILD3 in memory region B and the upper portion of the SL dielectric 4 in logic region A. As shown, after CMP, a predetermined portion of the SL dielectric 4 remains in a valley or dip in the ILD3 created between adjacent NVM pillars 15 in memory region B, and a predetermined portion of the SL dielectric 4 remains above the ILD3 in logic region A.

[0047] After CMP, the upper surface of the semiconductor structure 300 above the memory region B above the logic region A and the NVM pillar 15 is nearly horizontal or essentially horizontal. After CMP, there is little to no dip on the upper surface of the SL dielectric 4 in the transition area between logic region A and memory region B. In other words, there is a minimum height difference on the upper surface of the semiconductor structure 300 within logic region A and memory region B. The nearly flat or horizontal surface of the semiconductor structure 300 reduces or prevents BEOL metal smearing or padding in the transition area (indicated as H1 in Figure 1) in subsequent processing steps that form contacts with lines and Mx+1 metal.

[0048] Figure 4 is a cross-sectional view of a semiconductor structure 400 after the formation of contacts 44, 45, and vias 46 according to one embodiment of the present invention. Using a known damascene process, contact 44 may be formed above the NVM pillar 15 in memory region B, and contact 45 may be formed above the vias 46 in logic region A.

[0049] In various embodiments, selective etching (e.g., using lithography patterning and reactive ion etching) removes predetermined portions of the SL dielectric 4 and ILD3 above at least one of the Mx metal 10 in logic area A to form via holes and trenches, and also removes predetermined portions of the ILD3 above the NVM pillar 15. A layer of BEOL metal material, such as copper, cobalt, tungsten, or ruthenium, may be deposited in the via holes to form vias 46 that contact the Mx metal 10, and fill trenches in logic area A above the via holes to form contacts 45 after CMP removes excess BEOL above the SL dielectric 4 and any remaining exposed ILD3. In some embodiments, the contacts 45 are lines within the Mx+1 metal layer. The BEOL metal also fills openings or holes in the ILD3 above each of the NVM pillars 15 to form contacts 44 after CMP. As shown, contact 44 is located within the ILD3 and adjacent to the residual portion of the SL dielectric 4 in the memory region B. Contact 45 is located within the SL dielectric 4, and via 46 extends through the ILD3, the sealing dielectric 13, and the cap 11 to contact one of the Mx metals 10. In various embodiments, the sides of the ILD3 form a wedge-shaped gap between adjacent NVM pillars 15. In these embodiments, the residual portion of the SL dielectric 4 forms a wedge-shaped or v-shaped portion of the SL dielectric 4 that abuts against the ILD3, and the ILD3 abuts against each contact of contact 44 in the memory region B and lies between each contact.

[0050] As discussed above, and as shown in Figure 4, BEOL metal padding of the Mx+1 metal layer forming contacts 44 and 45 does not occur on the SL dielectric 4 within the upper surface of the semiconductor structure 400. The SL dielectric 4 provides a relatively flat surface before contacts 44 and 45 are formed. As shown, the transition area between logic area A and memory area B (indicated as H1 in Figure 1) has a clean dielectric surface on the SL dielectric 4 (e.g., smeared BEOL metal above the SL dielectric 4 near contacts 44 and 45; therefore, short circuits do not occur within the Mx+1 metal layer due to the formation of contacts 44 and 45).

[0051] Figure 5 is a cross-sectional view of a semiconductor structure 500 after depositing an ILD53 on a sealing dielectric according to one embodiment of the present invention. As shown, Figure 5 includes a logic region A, a memory region B, an Mx metal 10, an ILD9, a cap 11, a sealing dielectric 13, a lower contact 12, an NVM pillar 15, and an ILD53. The Mx metal 10, ILD9, sealing dielectric 13, lower contact 12, and NVM pillar 15 are essentially the same elements as those discussed with respect to Figure 1. H3 indicates the height difference between the upper surface of the ILD53 on the NVM pillar 15 in memory region B and the upper surface of the ILD53 on logic region A. H3 can be approximately the same height as H1 shown in Figure 1 (e.g., within 15-25% of H1). The ILD53 may be made of the same or similar material as the ILD3, however, the thickness of the ILD53 is slightly greater than that of the ILD3. For example, the thickness of ILD53 can be greater than 70% to 170% of the height of NVM pillar 15.

[0052] Figure 6 is a cross-sectional view of a semiconductor structure 600 after depositing an SL dielectric 54 on an ILD 53 according to one embodiment of the present invention. As shown, Figure 6 includes the elements of Figure 5 and the SL dielectric 54. The SL dielectric 54 is essentially the same as the SL dielectric 4. The SL dielectric 54 can be deposited by the same or similar process as the SL dielectric 4, which is deposited to a thickness that covers and extends over the upper surface of the ILD 53 in the memory region B. H4 indicates the difference in height between the upper surface of the SL dielectric 54 in the memory region B above the NVM pillar 15 and the upper surface of the SL dielectric 54 in the logic region A. H4 can be approximately the same as or greater than H2 shown in Figure 2. As shown, H4 indicates that a slight dip or change in the height of the upper surface of the SL dielectric 54 occurs in the transition area between the logic region A and the memory region B.

[0053] Figure 7 is a cross-sectional view of a semiconductor structure 700 after CMP has been performed according to one embodiment of the present invention. As shown, Figure 7 includes the elements of Figure 6, but with a portion of the SL dielectric 54 missing. CMP makes the upper surface of the semiconductor structure 600 horizontal and removes the upper portion of the SL dielectric 54 in the logic region A and the upper portion of the ILD 53 in the memory region B above the NVM pillar 15. As shown, the upper surface of the semiconductor structure 700 is flat and consists of the SL dielectric 54 in the logic region A and the ILD 53 in the memory region B.

[0054] After CMP, the amount of ILD53 removed by CMP in memory region B leaves a residual layer of ILD53 with sufficient thickness to form contacts (not shown in Figure 7) that connect to the NVM pillar 15 in a later process. As shown in Figure 7, after CMP, the upper surface of ILD53 in memory region B is essentially flat and horizontal. The upper surface of the semiconductor structure 700 (e.g., the upper surfaces of ILD53 and SL dielectric 54) is flat and horizontal across logic region A, memory region B, and in the transition area between logic region A and memory region B. In some embodiments, the SL dielectric 54 (not shown in Figure 7) is removed within logic region A.

[0055] Figure 8 is a cross-sectional view of a semiconductor structure 800 after forming contacts 84, 85, and via 46 according to one embodiment of the present invention. As shown, Figure 8 includes contacts 84, 85, via 46, ILD 53, sealing dielectric 13, NVM pillar 15, lower contact 12, cap 11, Mx metal 10, and ILD 9.

[0056] Using a known damascene process, trenches or openings for contacts 84 and 85, as well as via holes for via 46, are patterned and etched onto the ILD 53 and SL dielectric 54. BEOL metal (e.g., copper, tungsten, ruthenium, cobalt, etc.) is deposited as an Mx+1 metal layer on the ILD 53 in memory region B and on the SL dielectric 54 in logic region A. For example, the Mx+1 metal layer is deposited on the exposed surface of the NVM pillar 15 in the trench in memory region B, in the via holes, and on the exposed surface of the Mx metal 10 and above the trench in logic region A to form contact 85 above contacts 84 and via 46. In some embodiments, contact 85 is a circuit line within the Mx+1 metal layer. CMP is performed to remove excess BEOL metal from the upper surfaces of the ILD 53 and SL dielectric 54. After CMP is performed, the upper surface of the semiconductor structure 800 is flat, and no residual or smeared BEOL metal remains on the ILD 53, on the SL dielectric 54, or on the upper surface of the semiconductor structure 700 in the transition region between logic region A and memory region B.

[0057] The ability of the deposited SL dielectric 54 in Figure 6 to flow and self-level, providing a relatively flat surface with only slight variations on the upper surface of the SL dielectric 54 in the transition area between logic region A and memory region B, allows for the creation of a relatively or essentially flat surface within the semiconductor structure 700 after CMP removes predetermined portions of the SL dielectric 54 and ILD 53. As a result of creating a relatively flat surface in the semiconductor structure 700, smearing of the BEOL metal does not occur during CMP when CMP removes overloaded or excess BEOL metal (e.g., excess Mx+1 metal layer). As shown, using the SL dielectric 54 deposited on the ILD 53 before forming the BEOL metal does not leave predetermined portions of the BEOL metal on the ILD 53, on the upper surface of the SL dielectric 54, or within the transition area between logic region A and memory region B. The flat or horizontal dielectric surface of the semiconductor structure 700 prevents or reduces short circuits due to padding or smearing of the Mx+1 metal during contact 84, contact 85, and via 46 formation. As is known to those skilled in the art, in various embodiments, the BEOL process may be continued, and further BEOL interconnect layers and semiconductor device contacts may be formed to complete the semiconductor device.

[0058] Figure 9 is a cross-sectional view of a semiconductor structure 900 after depositing an SL dielectric 114 on a encapsulating dielectric 13 according to one embodiment of the present invention. As shown, Figure 9 includes a logic region A, a memory region B, an SL dielectric 114, a encapsulating dielectric 13, an NVM pillar 15, a lower contact 12, a cap 11, an Mx metal 10, and an ILD 9. The encapsulating dielectric 13, NVM pillar 15, lower contact 12, cap 11, Mx metal 10, and ILD 9 are essentially the same as the elements discussed in detail with reference to Figure 1. Figure 9 does not include an ILD 3 and instead includes a thick layer of SL dielectric 114. The SL dielectric 114 may be composed of the same material as the SL dielectric 4 and may be deposited using the same or similar process used for the SL dielectric 4 discussed above with reference to Figure 2. The SL dielectric 114 covers the encapsulating dielectric 13 and extends above the top of the encapsulating dielectric 13 above the NVM pillar 15 in the memory region B.

[0059] In this embodiment, the SL dielectric 114 is deposited on the encapsulating dielectric 13 and flows over the surface of the encapsulating dielectric 13. Small dips or changes in the upper surface height of the SL dielectric 114 labeled H5 occur within the transition region between the logic region A and the memory region B. The difference in height between the upper surface of the SL dielectric 114 above the NVM pillar 15 and the upper surface of the SL dielectric 114 above the logic region A can be less than half the pillar height of the NVM pillar 15. The height of the NVM pillar 15 can be 25 to 300 nm, but is not limited to these heights.

[0060] Figure 10 is a cross-sectional view of a semiconductor structure 1000 after CMP has been performed according to one embodiment of the present invention. As shown, Figure 10 includes the elements of Figure 9, but the upper portion of the SL dielectric 114 over the logic region A and memory region B has been removed by CMP, along with the upper portion of the sealing dielectric 13 over the NVM pillar 15 in memory region B. After CMP, the upper surface of the semiconductor structure 1000 is essentially horizontal or flat.

[0061] As shown, the lower portion of the SL dielectric 114 remains on top of the sealing dielectric 13 in logic region A and between the remaining portion of the sealing dielectric 13 around the NVM pillars 15 in memory region B. In various embodiments, the SL dielectric 114 is on top of the sealing dielectric 13 and fills the gaps between the NVM pillars 15, respectively. In some examples, the SL dielectric 114 fills the small gaps between the lower contacts 12. In various embodiments, the CMP stop is a hard mask (not shown in Figure 10) located on the upper surface of the NVM pillars 15. In these embodiments, the SL dielectric 114 is removed from the upper surface of the NVM pillars 15.

[0062] In some embodiments, the CMP stop is the upper surface of the sealing dielectric 13 above the NVM pillar 15 (not shown). In one embodiment, a portion of the sealing dielectric 13 is exposed on the upper surface of the semiconductor structure 1100 between the NVM pillar 15 and the SL dielectric 114. In this case, the upper surface of the SL dielectric 114 is horizontal to the highest portion of the sealing dielectric 13 above the NVM pillar 15. In a later step discussed with respect to Figure 12, in order to form a contact above the NVM pillar 15, the etching process of the Mx+1 metal layer in the BEOL damascene process will involve etching both the ILD 120 (see Figures 11 and 12) and the remaining portion of the sealing dielectric 13 above the NVM pillar 15.

[0063] Figure 11 is a cross-sectional view of a semiconductor structure 1100 after depositing an ILD 120 on the exposed surface of an SL dielectric 114 and an NVM pillar 115 according to one embodiment of the present invention. As shown, Figure 11 includes the elements of Figure 10 and the ILD 120. The upper surface of the ILD 120 deposited on the flat surface of the SL dielectric 114 is also flat due to the flat surface of the deposited SL dielectric 114 and the flat upper surface of the semiconductor structure 1100 shown in Figure 11 after CMP.

[0064] ILD120 can be deposited by deposition methods known for interlayer dielectric materials (e.g., CVD, PVD, etc.). In various embodiments, ILD120 consists of a low-k dielectric material or a low-k dielectric material having another dielectric material (e.g., SiCNO, SiCN, porous SiCN, SiCOH, porous SiCOH, AIOx under one of porous SiCN or porous SiCOH). In the BEOL interconnect structure, ILD120 is deposited with a thickness greater than the contact height of the Mx+1 metal layer (e.g., the next metal layer deposited for contact formation, which will be discussed later with respect to Figure 12). For example, the thickness of ILD120 can range from 20 nm to 500 nm when Mx metal 10 is the M1 metal layer.

[0065] Figure 12 is a cross-sectional view of a semiconductor structure 1200 after forming contacts 134, 85, and a via 46 according to one embodiment of the present invention. As shown, Figure 12 includes contacts 134, 85, a via 46, an ILD 120, an SL dielectric 114, an NVM pillar 15, a lower contact 12, a sealing dielectric 13, a cap 11, an Mx metal 10, and an ILD 9. Contact 134 is formed above and connected to the NVM pillar 15.

[0066] Using a conventional BEOL process (e.g., damascene process), contacts 85, a via 46 below contact 85, and a contact 134 connecting to an NVM pillar 15 are formed within the ILD 120 (e.g., Mx+1 metal layer ILD) as shown in the semiconductor structure 1200. In some embodiments, contact 85 is a line within the Mx+1 metal layer. After patterning and etching the ILD 120 to form trenches for the contacts and forming via holes for the via 46, a BEOL metal layer is deposited, and a CMP process removes excess BEOL metal from the upper surface of the ILD 120 to form contacts 134, contact 85, and via 46, followed by CMP removing excess BEOL metal from the upper surface of the ILD 120, and in some cases, removing the upper surface of the ILD 120. As shown, contacts 134 and 85 may be formed within the ILD 120, with contact 134 located on and connecting to the NVM pillar 15. A predetermined portion of the SL dielectric 114 remains between the NVM pillars 15 around the sealing dielectric 13 in memory region B. The upper portion of the via 46 is located within the cap 11, which is in contact with the residual SL dielectric 114, the sealing dielectric 13, and the Mx metal 10 in logic region A.

[0067] As shown in Figure 12, the upper surfaces of ILD120 and SL dielectric 114 are relatively flat, and dips or drops within the upper surface of ILD120 or SL dielectric 114 do not occur in the transition area between logic region A and memory region B. Due to the flat surface of ILD120, after CMP removes any overload or excess BEOL metal above ILD120, the transition area between logic region A and memory region B is free of BEOL metal. Due to the inherently flat surface of ILD120, smearing BEOL metal and paddling of BEOL metal do not occur on ILD120. Thus, depositing SL dielectric 114 to create a flat surface prior to forming contacts for connecting to NVM pillar 15 and for logic devices in logic region A, followed by CMP and ILD120 deposition, prevents short circuits due to residual BEOL metal after the formation of contacts 134 within the semiconductor structure 1200. Contact 134 is formed without the occurrence of BEOL padding and without the use of further mask levels. Furthermore, an Mx+1 ILD surface height for ILD120 is achieved using a conventional BEOL process, providing contact 134 with a typical contact height in an Mx+1 metal layer contact.

[0068] Figure 13 shows examples of methods, according to several embodiments of the present invention, for using a maskless interlayer dielectric removal process and a self-horizontal dielectric material to form an embedded pillar-based NVM device. In various embodiments, the method is performed on one or more arrays of pillars for a non-volatile memory device on a predetermined portion of a BEOL metal layer within a semiconductor structure. The method ultimately provides a horizontal upper surface of the dielectric layer immediately above the array of pillars and within other adjacent logic device regions of the semiconductor structure (e.g., logic devices, macros, or other non-pillar-based semiconductor devices and circuits or combinations thereof).

[0069] In step 1302, the method includes forming a non-volatile memory pillar on a predetermined portion of a BEOL layer having a predetermined portion of Mx metal covered by a sealing dielectric material on top of a cap material. Using known memory device formation processes, each pillar in the array of pillars is formed on a lower contact that connects to a portion of the BEOL metal layer (e.g., Mx metal 10 shown in Figure 1). The pillars may be formed from any set of materials suitable for creating pillars for one of MRAM devices, PCM devices, RRAM devices, or other pillar-based non-volatile memory devices, forming an array of two or more vertical pillar structures. For example, the pillars may include one or more MTJs in a phase-change memory cell. The pillars in the array of pillar-based memory structures are adjacent to areas having logic devices, macros, or other non-pillar-based circuits above the semiconductor substrate.

[0070] In step 1304, the method includes depositing an ILD layer on top of a encapsulating dielectric material. The ILD material deposited by CVD, PVD, or ALD covers the encapsulating dielectric material on top of the pillar array and the logic devices. The method includes forming an upper surface of the ILD that extends higher above the pillar array and lower within the logic device region adjacent to the pillar array. The upper surface of the ILD may have bump or raised regions above each pillar in the pillar array and a flatter surface within the logic device region. In various embodiments, the ILD material is a low-k dielectric material.

[0071] In various practical embodiments, the thickness of the ILD material deposited on the encapsulating dielectric material can range from 50% to 150% of the pillar height in the pillar array. In other embodiments, thicker deposition of the ILD material is performed, resulting in an ILD thickness greater than 150% of the pillar height. In one embodiment, instead of the ILD material being deposited on the encapsulating dielectric material, a layer of fluid, self-horizontal dielectric material with a low-k dielectric constant is deposited by CVD.

[0072] In step 1306, the method includes depositing a self-horizontal and fluid low-k dielectric material. For example, the self-horizontal low-k dielectric material may be deposited using a vacuum plasma chemical vapor deposition process with organosilicon and oxygen precursors at low temperatures for the self-horizontal and fluid properties of the dielectric material, prior to heating the self-horizontal low-k dielectric material for UV curing at high temperatures (e.g., 150–450 degrees Celsius) for material hardening, but is not limited to this deposition method. In another example, the self-horizontal dielectric material is a spin-on dielectric material.

[0073] Using a self-leveling low-k dielectric material having a composition that allows the surface of the low-k dielectric material to flow and self-level, thereby producing a flat or level dielectric surface. Self-leveling low-k dielectric materials reduce variations in the height of the upper surface of the semiconductor structure before forming contacts for each pillar in an array of pillar-based memory structures used to create non-volatile memory devices, thereby reducing or avoiding the occurrence of smearing or paddling caused by non-uniform surfaces during subsequent BEOL metal layer processing.

[0074] Regions of the semiconductor structure having logic devices with lower device profiles and regions of the semiconductor structure having arrays of pillars with higher device profiles are uniformed using a self-horizontal, fluid low-k dielectric material to create a horizontal dielectric surface of the semiconductor structure prior to contact formation for the pillar-based memory structure.

[0075] The self-horizontal low-k dielectric material can be a material or compound containing SiOCH or another similar self-horizontal low-k dielectric material. In various embodiments, the deposited self-horizontal low-k dielectric material completely covers the ILD material and extends above the ILD material. In one embodiment, there is no ILD material, and the self-horizontal low-k dielectric material is deposited directly above the sealing dielectric material above the pillar array and above the logic device region adjacent to the pillar array. In some cases, slight variations occur in the upper surface of the self-horizontal low-k dielectric material. The height variation or dip in the transition area between the logic device and the pillar array can be less than half the height of the pillar in the pillar array. In these cases, the surface of the self-horizontal low-k dielectric material is lower above the logic device region adjacent to the pillar array compared to the surface of the self-horizontal low-k dielectric material above the pillar array.

[0076] In step 1308, CMP is performed. In various embodiments, CMP removes the upper portion of the self-horizontal low-k dielectric material, leaving the lower portion of the self-horizontal low-k dielectric material above the logic device and the lower portion of the self-horizontal low-k dielectric material between adjacent pillars in the pillar array. The upper portion of the ILD material above the pillars in the pillar array may be removed by CMP. In these embodiments, certain portions of the self-horizontal low-k dielectric material and some portions of the ILD above the pillars are exposed on the upper surface of the semiconductor structure after CMP. In various embodiments, the upper surface of the semiconductor structure, composed of one or more dielectric materials, is flat after CMP is performed.

[0077] In other embodiments, when a thicker layer of ILD material is deposited on the sealing dielectric material, no self-horizontal low-k dielectric material remains after CMP. In these embodiments, a hard mask within the pillar array or the upper surface of the sealing dielectric material on the pillar array can be used as a CMP stop.

[0078] In one embodiment, no ILD material is present, and CMP removes the upper portion of the self-horizontal low-k dielectric material, leaving the lower portion of the self-horizontal low-k dielectric material above the sealing dielectric material above both the pillar array and the adjacent logic device region. The hard mask within the pillars of the pillar array or the upper surface of the sealing dielectric material above the pillar array can be used as a CMP stop.

[0079] In step 1310, the method includes using a known BEOL process to form non-volatile memory device contacts and (circuit?) lines within the Mx+1 metal layer. In some embodiments, the method uses a known damascene process to form non-volatile memory device contacts above each pillar in the array of pillars within the non-volatile memory device and connections to each pillar. The damascene process is also used to form contacts or Mx+1 metal lines, or both, and vias, connecting the logic device and the Mx metal layer to lines or contacts in the Mx+1 metal layer. In various embodiments, after the contacts to the array of pillars are formed using a thinner ILD, a small portion of the self-horizontal low-k dielectric material remains above the sealing dielectric material between each contact to the pillars in the array of pillars and above the logic device region. The BEOL metal is not smeared in the region adjacent to the array of pillars and on the surface of the resulting semiconductor structure.

[0080] In other embodiments, when a thicker layer of ILD material is deposited on the sealing dielectric material, the self-horizontal low-k dielectric material is completely absent after CMP. In these cases, contacts, vias, or Mx+1 metal lines, or a combination thereof, are formed within the ILD material above the sealing dielectric material, as shown in Figure 8.

[0081] In one embodiment, with no ILD material deposition on the sealing dielectric material, only the self-horizontal low-k dielectric material covers the pillar array. After CMP is performed on the self-horizontal low-k dielectric material in step 1308, another layer of ILD material (e.g., an Mx+1 ILD layer) is deposited on top of the self-horizontal low-k dielectric material, and contacts, vias, or Mx+1 metal lines or a combination thereof for the pillars and logic devices are formed within the Mx+1 ILD layer, as shown in Figure 12.

[0082] The methods described herein may be used in the fabrication of integrated circuit chips or semiconductor chips. The resulting semiconductor chips may be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the semiconductor chips are mounted in a single-chip package (such as a plastic carrier or other higher-level carrier with leads fixed to a motherboard) or in multiple packages (such as a ceramic carrier with either or both surface interconnects and embedded interconnects). In either case, the semiconductor chips are then integrated with other semiconductor chips, discrete circuit elements, or other signal processing devices or combinations thereof as part of (a) an intermediate product such as a motherboard or (b) a final product. The final product may be any product containing semiconductor chips, ranging from toys and other low-end applications to displays, memory, keyboards, or input devices, and advanced computer products with central processors.

Claims

1. An array of multiple pillar-based memory devices within the memory region, Multiple memory contacts for each of the aforementioned multiple pillar-based memory devices, Within the logical domain, there is one or more logical connections, Equipped with, The plurality of memory contacts are located within the second dielectric material and are in contact with the second dielectric material, and the second dielectric material is also located beneath one or more logic contacts. The wedge-shaped portion of the third dielectric material is located within the second dielectric material between adjacent contacts of the plurality of memory contacts. The one or more logic contacts are located within the third dielectric material. The one or more logic contacts and the plurality of memory contacts are located within a second metal layer, and the second metal layer has the same thickness. Semiconductor structure.

2. The semiconductor structure further comprises one or more connecting portions of a first metal layer within a first dielectric material, wherein the one or more connecting portions of the first metal layer are located within the logic region and the memory region of the semiconductor structure. The sealing dielectric material surrounds each of the pillar-based memory devices in the array of pillar-based memory devices within the memory region, and is located above the one or more connecting portions of the first metal layer and the first dielectric material. The second dielectric material is located on top of the sealing dielectric material. The third dielectric material is located on top of the second dielectric material, and the third dielectric material forms the wedge-shaped portion of the third dielectric material within the second dielectric material between adjacent contacts of the plurality of memory contacts. The semiconductor structure according to claim 1.

3. The semiconductor structure according to claim 1, wherein the third dielectric material is a self-horizontal fluid dielectric material.

4. The semiconductor structure according to claim 1, wherein the array of pillar-based memory devices is composed of one or more pillar-based non-volatile memory devices.

5. The semiconductor structure according to claim 1, wherein the array of pillar-based memory devices is selected from the group consisting of an array of magnetoresistive random access memory devices, an array of resistive random access memory devices, and an array of phase-change random access memory devices.

6. The one or more connecting portions of the first metal layer in the first dielectric material are The first metal layer is further provided with one or more connecting portions and a dielectric cap material on the first dielectric material, The first connection portion of the one or more connection portions of the first metal layer in the first dielectric material is located beneath each of the pillar-based memory devices in the array of pillar-based memory devices. The second connection portion of the one or more connection portions of the first metal layer is located above one or more logic devices in the logic region of the semiconductor structure, and the second connection portion of the one or more connection portions of the first metal layer is adjacent to the first connection portion of the one or more connection portions of the first metal layer. The semiconductor structure according to claim 2.

7. The semiconductor structure according to claim 6, wherein the second metal layer on the first metal layer is located within a back-end-of-the-line metal layer.

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