Defect-free channel multilayer nanosheet transistor

Abstract

The present embodiment is directed to a method and resulting structure for a nanosheet device having a defect-free channel. In a non-limiting embodiment of the present invention, a nanosheet stack is formed on a substrate. The nanosheet stack includes alternating first and second sacrificial layers. One of the first sacrificial layers has a thickness greater than the remaining first sacrificial layers. The first sacrificial layers are removed and a semiconductor layer is formed on a surface of the second sacrificial layer. The semiconductor layer includes a first set of semiconductor layers and a second set of semiconductor layers. The second sacrificial layer is removed and an isolation dielectric is formed between the first set of semiconductor layers and the second set of semiconductor layers.

Description

[[Technical Field]]

[0001] The present invention generally relates to a method for manufacturing a semiconductor device and a resulting structure, and more particularly to an improved method for manufacturing a nanosheet transistor having a defect-free channel and a resulting structure. [[Background Art]]

[0002] Known metal oxide semiconductor field effect transistor (MOSFET) manufacturing techniques include a process flow for constructing planar field effect transistors (FETs). A planar FET comprises a substrate (also called a silicon slab), a gate formed on the substrate, source and drain regions formed at both ends of the gate, and a channel region near the surface of the substrate below the gate. The channel region electrically connects the source region to the drain region, while the gate controls the current in the channel. The gate voltage controls whether the path from the drain to the source is an open circuit ("off") or a resistive path ("on").

[0003] In recent years, research has been directed to the development of non-planar transistor architectures. For example, nanosheet FETs include a non-planar architecture that provides higher device density and somewhat higher performance than lateral devices. In a nanosheet FET, in contrast to conventional planar FETs, the channel is implemented as a plurality of stacked and spaced apart nanosheets. The gate stack wraps around the entire circumference of each nanosheet, thus allowing more complete depletion of the channel region, resulting in a steeper subthreshold swing (SS) and smaller drain induced barrier lowering (DIBL), thereby reducing short channel effects. [[Summary of the Invention]]

[0004] Embodiments of the present invention relate to a method for forming a nanosheet transistor having a defect-free channel. Non-limiting examples of the method include forming a nanosheet stack on a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and a semiconductor layer is formed on the surface of the second sacrificial layer. The semiconductor layer includes a first set of semiconductor layers and a second set of semiconductor layers. The second sacrificial layer is removed and an isolation dielectric is formed between the first set of semiconductor layers and the second set of semiconductor layers.

[0005] Embodiments of the present invention relate to semiconductor structures. Non-limiting examples of semiconductor structures include nanosheet stacks on a substrate. The nanosheet stack includes a first set of semiconductor layers and a second set of semiconductor layers. An isolation dielectric is placed between the first set of semiconductor layers and the second set of semiconductor layers. A first source and drain region is formed on the sidewall of the first set of semiconductor layers, and a second source and drain region is formed on the sidewall of the second set of semiconductor layers. The first source and drain region includes a first dopant type, and the second source and drain region includes a second dopant type. Lower source and drain contacts are formed on the sidewall of the first source and drain region, and upper source and drain contacts are formed on the upper surface of the second source and drain region.

[0006] Additional technical features and advantages are realized by the technology of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered part of the subject matter claimed. For a better understanding, please refer to the detailed description and drawings.

[0007] Details of the exclusive rights described herein are specifically pointed out and explicitly claimed in the last claim herein. The aforementioned and other features and advantages of embodiments of the present invention are evident from the following detailed description in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0008] [Figure 1] This is a top reference view and a cross-sectional view of a semiconductor structure along line X in the reference figure after the first series of processing operations according to one or more embodiments of the present invention. [Figure 2A] This is a cross-sectional view of a semiconductor structure along line X in the reference figure according to one or more embodiments of the present invention. [Figure 2B] This is a cross-sectional view of a semiconductor structure along line Y1 in the reference figure according to one or more embodiments of the present invention. [Figure 3A] This is a cross-sectional view of a semiconductor structure along line X in the reference figure according to one or more embodiments of the present invention. [Figure 3B] This is a cross-sectional view of a semiconductor structure along line Y1 in the reference figure according to one or more embodiments of the present invention. [Figure 4A] This is a cross-sectional view of a semiconductor structure along line X in the reference figure according to one or more embodiments of the present invention. [Figure 4B] This is a cross-sectional view of a semiconductor structure along line Y1 in the reference figure according to one or more embodiments of the present invention. [Figure 5A] This is a cross-sectional view of a semiconductor structure along line X in the reference figure according to one or more embodiments of the present invention. [Figure 5B] This is a cross-sectional view of a semiconductor structure along line Y1 in the reference figure according to one or more embodiments of the present invention. [Figure 6A] This is a cross-sectional view of a semiconductor structure along line X in the reference figure according to one or more embodiments of the present invention. [Figure 6B] This is a cross-sectional view of a semiconductor structure along line Y1 in the reference figure according to one or more embodiments of the present invention. [Figure 7A] This is a cross-sectional view of a semiconductor structure along line X in the reference figure according to one or more embodiments of the present invention. [Figure 7B] This is a cross-sectional view of a semiconductor structure along line Y1 in the reference figure according to one or more embodiments of the present invention. [Figure 8]FIG. 1 is a cross-sectional view of a semiconductor structure along line Y2 of a reference diagram in accordance with one or more embodiments of the present invention. [Figure 9] FIG. 1 is a cross-sectional view of a semiconductor structure along line Y2 of a reference diagram in accordance with one or more embodiments of the present invention. [Figure 10] FIG. 1 is a cross-sectional view of a semiconductor structure along line Y2 of a reference diagram in accordance with one or more embodiments of the present invention. [Figure 11] FIG. 1 is a cross-sectional view of a semiconductor structure along line Y2 of a reference diagram in accordance with one or more embodiments of the present invention. [Figure 12] FIG. 1 is a cross-sectional view of a semiconductor structure along line Y2 of a reference diagram in accordance with one or more embodiments of the present invention. [Figure 13] FIG. 1 is a cross-sectional view of a semiconductor structure along line Y2 of a reference diagram in accordance with one or more embodiments of the present invention. [Figure 14] FIG. 1 is a cross-sectional view of a semiconductor structure along line Y2 of a reference diagram in accordance with one or more embodiments of the present invention. [Figure 15] FIG. 1 is a flow diagram illustrating a method in accordance with one or more embodiments of the present invention. DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0009] The diagrams presented herein are exemplary. Many modifications may be made to the diagrams or operations described herein without departing from the scope of the present invention. For example, actions may be performed in a different order, or actions may be added, deleted or modified.

[0010] In the accompanying drawings and the following detailed description of the described embodiments of the present invention, various elements shown in the drawings are assigned two-digit or three-digit reference numerals. With a few exceptions, the leftmost digit of each reference numeral corresponds to the figure in which the element is first shown.

[0011] While exemplary embodiments of the present invention are described with reference to specific transistor architectures, it should be understood in advance that embodiments of the present invention are not limited to the specific transistor architectures or materials described herein. Rather, embodiments of the present invention can be implemented in conjunction with any other type of transistor architecture or material that is currently known or hereafter developed.

[0012] For the sake of brevity, conventional techniques related to the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, the various tasks and process steps described herein can be incorporated into more comprehensive procedures or processes that have additional steps or functions not described in detail herein. In particular, various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned herein, or are entirely omitted without providing details of well-known processes.

[0013] Turning now to an overview of technologies that are more specifically relevant to aspects of the present invention, several candidates exist for scaling non-planar transistors beyond the 7nm node, but each is currently limited by various factors. One candidate is the nanosheet transistor architecture. To increase available computational power per unit area, nanosheet devices stack channels vertically on the footprint of a shared substrate.

[0014] Currently, in nanosheet devices, each channel is predefined in the early stages of manufacturing by alternately growing silicon layers and silicon-germanium layers (Si layers / SiGe layers). One of the Si or SiGe layers is a sacrificial layer that is removed to expose the surface of the remaining layer that defines the channel. However, because selective removal between the two materials (Si vs. SiGe) is required, the minimum percentage of germanium used is about 25% (lower Ge% reduces the removal selectivity between Si and SiGe). At this germanium concentration, the bulk critical thickness of a stable SiGe film epitaxially grown on Si is 10 nm. Below this thickness (sometimes called the critical thickness), the Si / SiGe can remain defect-free, but above this thickness (the critical thickness), defects can form and spread. This imposes practical limitations on the maximum height of the nanosheet stack, and ultimately on its computational power and performance. Therefore, fabricating stacked nanosheet devices of arbitrary height with defect-free channels using conventional nanosheet manufacturing processes is difficult, if not impossible.

[0015] Turning to an overview of the embodiments of the present invention, one or more embodiments of the present invention address the aforementioned shortcomings of known nanosheet structures and manufacturing methods by providing a novel nanosheet structure and method for manufacturing the same that guarantees defect-free channels for any number of channels at any stack height. According to embodiments of the present invention, a novel nanosheet manufacturing technique is utilized in which the entirety of the initial Si and SiGe layers serve as sacrificial layers. The final channels are grown on the defect-free silicon layer after the silicon-germanium sacrificial layer has been removed.

[0016] The nanosheet structure formed in this manner offers several technical advantages compared to conventional nanosheets. For example, the thickness of the SiGe layer can be maintained within the critical dimension threshold without compromising the total number or height of channels, and without introducing defects into the stack. The proposed structure does not impair the scaling of device performance because it can include more channel layers within the structure by guaranteeing defect-free channels. This will provide a way to further increase the bits / area of ​​future technology nodes.

[0017] Now, turning to a more detailed description of the manufacturing process and the resulting structure according to the embodiments of the present invention, Figures 1 to 14 show semiconductor structures 100 after various manufacturing processes according to the embodiments of the present invention. It should be understood that the cross-sectional views shown in Figures 1 to 14 represent two-dimensional structures, while the cross-sectional views shown in Figures 1 to 14 represent three-dimensional structures. The top reference figure 101 shown in Figure 1 provides reference points for various cross-sectional views, namely the X cross-sectional view (crossing the gate of the channel region), the Y1 cross-sectional view (along the gate of the channel region), and the Y2 cross-sectional view (along the gate of the source / drain region) shown in Figures 1 to 14.

[0018] Figure 1 shows a cross-sectional view of a semiconductor structure 100 taken along line X of reference Figure 101 after an initial set of manufacturing operations has been applied as part of a method for manufacturing a final semiconductor device according to one or more embodiments of the present invention. In some embodiments of the present invention, one or more nanosheet stacks 102 are formed on a substrate 104.

[0019] The substrate 104 can be fabricated from any suitable substrate material, such as single-crystal Si, silicon-germanium (SiGe), III-V compound semiconductors, II-VI compound semiconductors, or semiconductor-on-insulator (SOI). III-V compound semiconductors include materials having at least one group III element and at least one group V element, such as aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN), aluminum arsenide (AlAs), aluminum indium arsenide (AlInAs), aluminum nitride (AlN), gallium antimony (GaSb), gallium aluminum antimony (GaAlSb), gallium arsenide (GaAs), gallium arsenide antimony (GaAsSb), gallium nitride (GaN), indium antimony (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium gallium arsenide phosphorus (InGaAsP), indium gallium nitride (InGaN), indium nitride (InN), indium phosphorus (InP), and one or more combinations of alloys containing at least one of the aforementioned materials. The alloy combinations can include binary alloys (two elements, e.g., gallium(III) arsenide (GaAs)), ternary alloys (three elements, e.g., InGaAs), and quaternary alloys (four elements, e.g., aluminum-gallium-indium-phosphorus (AlInGaP)).

[0020] In some embodiments of the present invention, the substrate 104 may include a silicon-on-insulator (SOI) embedded oxide layer (not shown separately). The embedded oxide layer can be fabricated from any suitable dielectric material, such as silicon oxide. In some embodiments of the present invention, the embedded oxide layer is formed to a thickness of about 10 to 200 nm, but other thicknesses are also within the range intended by the present invention. In some embodiments of the present invention, the semiconductor structure 100 may also be formed without an embedded oxide layer. In that case, shallow trench isolation (STI) is formed to separate the devices.

[0021] In some embodiments of the present invention, each nanosheet stack 102 may include one or more first sacrificial layers 106 arranged alternately with one or more second sacrificial layers 108. In some embodiments of the present invention, one of the first sacrificial layers 106 is formed or grown to a greater thickness than the remaining first sacrificial layers 106, defining a thick sacrificial layer 110. In some embodiments of the present invention, the thick sacrificial layer 110 is grown from the centralmost layer of the first sacrificial layers 106 (as shown), although other relative positionings are also possible. The inclusion of the thick sacrificial layer 110 allows for later isolation between the channels of two stacked FETs (which will be described in more detail later with respect to Figure 5A).

[0022] In some embodiments of the present invention, the first sacrificial layer 106 and the second sacrificial layer 108 are epitaxially grown layers. For the sake of ease of discussion, we will refer to the work performed on a nanosheet stack having four first sacrificial layers 106, four second sacrificial layers 108, and a thick sacrificial layer 110. However, it will be understood that the nanosheet stack 102 may include any number of semiconductor layers alternating with the corresponding number of sacrificial layers, and may or may not include thick semiconductor layers. For example, the nanosheet stack 102 may include two semiconductor layers, five semiconductor layers, eight semiconductor layers, thirty semiconductor layers, or any number of semiconductor layers, along with the corresponding number of sacrificial layers (i.e., alternating with thick semiconductor layers, if present).

[0023] The first sacrificial layer 106 (and the thicker sacrificial layer 110) can be fabricated from any suitable material, such as single-crystal silicon. Alternative materials are also possible, as long as they exhibit etching selectivity for silicon-germanium and can be deposited or grown to the required height without generating defects. In some embodiments of the present invention, the first sacrificial layer 106 has a thickness of about 4 nm to about 10 nm, for example, 6 nm, but other thicknesses are also within the intended range of the present invention. In some embodiments of the present invention, the thicker sacrificial layer 110 has a thickness of about 10 nm to about 50 nm, for example, 25 nm, but other thicknesses are also within the intended range of the present invention. In some embodiments of the present invention, the substrate 104 and the first sacrificial layer 106 can be fabricated from the same semiconductor material. In other embodiments of the present invention, the substrate 104 can be fabricated from the first semiconductor material, and the first sacrificial layer 106 can be fabricated from the second semiconductor material. The thicker sacrificial layer 110 can be the same material as the first sacrificial layer 106, or a different material. In some embodiments, the bottom layer of the sacrificial layer 106 can be a silicon layer on the initial silicon-on-insulator (SOI) substrate.

[0024] In some embodiments of the present invention, the second sacrificial layer 108 is a silicon-germanium layer having a higher germanium concentration than the first sacrificial layer 106 (if present). For example, if the first sacrificial layer 106 is a silicon-germanium layer (sometimes called SiGe5) with a germanium concentration of 5 percent, the second sacrificial layer 108 can be a silicon-germanium layer (SiGe25) with a germanium concentration of about 25 percent, although other germanium concentrations are also within the range intended by the present invention. In embodiments where the first sacrificial layer 106 is a silicon layer, the second sacrificial layer 108 can include a silicon-germanium layer having a germanium concentration of about 5% to about 60%. Advantageously, the second sacrificial layer 108 has a maximum thickness below the critical thickness of SiGe defects, for example, less than about 10 nm.

[0025] Figures 2A and 2B show cross-sectional views of the semiconductor structure 100 taken along lines X and Y1 of reference figure 101 after processing according to one or more embodiments of the present invention. As shown in cross-sectional view X of Figure 2A, a portion of the nanosheet stack 102 can be removed to expose the surface of the substrate 104 and define the width of the nanosheet stack. This process is sometimes called fin cutting. In some embodiments of the present invention, the width of the nanosheet stack 102 after fin cutting is approximately 10 to 100 nm, but other widths are also within the range intended by the present invention.

[0026] As shown in Figure 2B, dielectric layers 202 are formed on each end of the nanosheet stack 102 on the substrate 104. The dielectric layers 202 can be fabricated from any suitable dielectric material, such as oxides, low-k dielectrics, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN. Any known method for forming the dielectric layers 202 can be utilized, such as CVD, PECVD, ALD, fluid CVD, spin-on dielectrics, or PVD.

[0027] Figures 3A and 3B show cross-sectional views of the semiconductor structure 100 taken along lines X and Y1 of reference figure 101 after processing according to one or more embodiments of the present invention. As shown in cross-sectional view X of Figure 3A, the first sacrificial layer 106 and the thick sacrificial layer 110 are removed, exposing the surface of the second sacrificial layer 108. In some embodiments of the present invention, the first sacrificial layer 106 and the thick sacrificial layer 110 are selectively removed relative to the second sacrificial layer 108. The first sacrificial layer 106 and the thick sacrificial layer 110 can be selectively removed using wet etching, dry etching, or a combination of wet etching and / or dry etching. For example, silicon can be selectively removed relative to silicon germanium by utilizing the chemical reaction of aqueous hydroxide solutions containing ammonium hydroxide and potassium hydroxide. As shown in Figure 3B, dielectric layers 202 on each end of one or more nanosheet stacks 102 fix each nanosheet stack 102 onto the substrate 104.

[0028] Figures 4A and 4B show cross-sectional views of the semiconductor structure 100 taken along lines X and Y1 of reference figure 101 after processing according to one or more embodiments of the present invention. As shown in cross-sectional view X of Figure 4A, the semiconductor layer 402 (also called the channel layer) is formed on the exposed surfaces (top and bottom) of the second sacrificial layer 108. In some embodiments of the present invention, the semiconductor layer 402 is epitaxially grown from the surface of the second sacrificial layer 108. As previously mentioned, the thickness of the second sacrificial layer 108 can be kept below the critical thickness of defects, ensuring a defect-free surface from which the semiconductor layer 402 can be epitaxially grown.

[0029] The semiconductor layer 402 can be fabricated from any suitable semiconductor material, such as single-crystal silicon or silicon-germanium. Substitute materials are also acceptable, as long as they exhibit etching selectivity to silicon-germanium at the germanium concentration present in the second sacrificial layer 108. In some embodiments of the present invention, the first sacrificial layer 106 has a thickness of approximately 4 nm to 10 nm, for example, 6 nm, but other thicknesses are also within the intended range of the present invention. In some embodiments of the present invention, the semiconductor layer 402, the substrate 104, or the first sacrificial layer 106, or a combination thereof, can be fabricated from the same semiconductor material. In other embodiments of the present invention, the semiconductor layer 402 is fabricated from a different semiconductor material.

[0030] Figures 5A and 5B show cross-sectional views of the semiconductor structure 100 taken along lines X and Y1 of reference figure 101 after processing according to one or more embodiments of the present invention. As shown in cross-sectional view X of Figure 5A, the second sacrificial layer 108 is removed and the surface of the semiconductor layer 402 is exposed. In embodiments of the present invention having a thick sacrificial layer 110, the first portion 502 of the semiconductor layer 402 is separated from the second portion 504 of the semiconductor layer 402 by a stack separation distance that can be increased or decreased by changing the thickness of the thick sacrificial layer 110 (see Figure 2A).

[0031] In some embodiments of the present invention, the second sacrificial layer 108 is selectively removed from the semiconductor layer 402. The second sacrificial layer 108 can be selectively removed using wet etching, dry etching, or a combination of wet etching, dry etching, or both. For example, silicon germanium can be selectively removed from silicon using hydrogen chloride (HCl) gas or an aqueous solution containing a mixture of ammonia and hydrogen peroxide. As shown in Figure 5B, dielectric layers 202 on each end of the semiconductor layer 402 fix each semiconductor layer 402 of the nanosheet stack 102 onto the substrate 104.

[0032] Figures 6A and 6B show cross-sectional views of the semiconductor structure 100 taken along lines X and Y1 of reference figure 101 after processing according to one or more embodiments of the present invention. As shown in cross-sectional view X of Figure 6A, a dielectric layer 602 is formed on the exposed surface of the semiconductor layer 402. The stack isolation distance is reduced by approximately twice the thickness of the dielectric layer 602, but not completely eliminated. This reserves space for the isolation dielectric to be formed later (see Figure 7B).

[0033] The dielectric layer 602 can be fabricated from any suitable dielectric material, such as oxides, low-k dielectrics, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCn, and SiBCN. Any known method for forming the dielectric layer 602, such as CVD, PECVD, and ALD, can be utilized. In some embodiments of the present invention, the dielectric layer 602 is conformally deposited on the semiconductor layer 402 using, for example, ALD. In some embodiments of the present invention, the dielectric layer 602 is an ALD silicon oxide layer. The dielectric layer 602 can be formed to a thickness of about 2 nm to about 15 nm, for example, 5 nm, but other thicknesses are also within the range intended by the present invention.

[0034] Figures 7A and 7B show cross-sectional views of the semiconductor structure 100 taken along lines X and Y1 of reference Figure 101 after processing according to one or more embodiments of the present invention. As shown in cross-sectional view X of Figure 7A, an isolation dielectric 702 is formed on the dielectric layer 602. In particular, the isolation dielectric 702 fills the remaining space (defined by the stack isolation distance) between the first portion 502 and the second portion 504 of the semiconductor layer 402. In this way, the isolation dielectric 702 functions to electrically isolate the first portion 502 from the second portion 504, allowing these portions to later function as separate FETs (see, for example, Figure 14). Furthermore, although the isolation dielectric 702 surrounds the semiconductor layer 402, it is physically separated from those layers by the presence of the dielectric layer 602. As a result, the isolation dielectric 702 acts as a dielectric shell that favorably ensures a uniform gate stack during the downstream RMG process (i.e., a uniform space for the gate dielectric and gate work function metal around the nanosheet 402 when the dielectric layer 602 is replaced by the gate dielectric and gate work function metal, as described with respect to Figure 13).

[0035] In some embodiments of the present invention, a shallow trench isolation (STI) 704 is formed on the remainder of the substrate 104. The STI 704 can be fabricated from any suitable isolation material, such as silicon nitride, silicon oxide, SiON, SiC, SiOCn, and SiBCN. In some embodiments of the present invention, the semiconductor structure 100 is planarized, for example, using a chemical mechanical planarization (CMP) process.

[0036] Figure 8 shows a cross-sectional view of the semiconductor structure 100 taken along line Y2 in reference Figure 101 after processing according to one or more embodiments of the present invention. In some embodiments of the present invention, the sidewalls of the nanosheet stack 102 are exposed and a sacrificial gate 802 (sometimes called a dummy gate) is formed on the nanosheet stack 102.

[0037] The portion of the nanosheet stack where the gate is formed is called the channel region. The sacrificial gate 802 can be fabricated from any suitable material, such as amorphous silicon or polysilicon. Any known method for patterning the sacrificial gate can be used, such as wet etching, dry etching, or a combination of continuous wet etching or dry etching.

[0038] In some embodiments of the present invention, a hard mask 804 is formed on a sacrificial gate 802. In some embodiments of the present invention, the sacrificial gate 802 is formed by patterning the hard mask 804 and selectively removing the portion of the sacrificial gate 802 not covered by the patterned hard mask 804 using a wet or dry etching process. The hard mask 804 can be made of any suitable material, such as silicon nitride. In some embodiments of the present invention, a second hard mask (not shown) is formed on the hard mask 804 to form a two-layer hard mask. In some embodiments, the second hard mask contains an oxide, such as silicon dioxide.

[0039] Figure 9 shows a cross-sectional view of the semiconductor structure 100 taken along line Y2 of reference Figure 101 after processing according to one or more embodiments of the present invention. In some embodiments of the present invention, a spacer 902 (also known as a sidewall spacer or gate spacer) is formed on the sidewall of the sacrificial gate 802. In some embodiments of the present invention, the spacer 902 is formed using CVD, PECVD, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, ALD, PVD, chemical solution deposition, MBE, or other similar processes combined with wet or dry etching processes. For example, the spacer material can be conformally deposited on the semiconductor structure 100 and selectively removed using RIE to form the spacer 902.

[0040] The spacer 902 can be fabricated from any suitable material, such as low-k dielectrics, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the present invention, the spacer 902 contains silicon nitride. The spacer 902 can be formed to a thickness of about 5 to 40 nm, but other thicknesses are also within the range intended by the present invention.

[0041] In some embodiments of the present invention, a portion of the nanosheet stack 102 can be removed (also called a stack recess) to expose the surface of the substrate 104 (or the embedded oxide layer, if present). The nanosheet stack 102 can be patterned, for example, using wet etching, dry etching, or a combination of wet etching and / or dry etching. In some embodiments of the present invention, the nanosheet stack 102 is patterned using RIE. In some embodiments of the present invention, the nanosheet stack 102 is selectively patterned with respect to the spacer 902.

[0042] In some embodiments of the present invention, the dielectric layer 602 can be recessed, and internal spacers 904 can be formed on the recessed sidewalls of the dielectric layer 602. For example, the sidewalls of the dielectric layer 602 can be recessed to form cavities (not shown) within the nanosheet stack 102. In some embodiments of the present invention, the internal spacers 904 are formed on the recessed sidewalls of the dielectric layer 602 by filling these cavities with dielectric material. In some embodiments of the present invention, portions of the internal spacers 904 that extend beyond the sidewalls of the nanosheet stack 102 are removed, for example, using an isotropic etching process. In this way, the sidewalls of the internal spacers 904 become coplanar with the sidewalls of the semiconductor layer 402. In some embodiments of the present invention, the internal spacers 904 are formed using CVD, PECVD, ALD, PVD, chemical solution deposition, or other similar processes combined with wet or dry etching processes. The internal spacer 904 can be made from any suitable material, such as low-k dielectrics, nitrides, silicon nitride, silicon dioxide, SiON, SiC, SiCN, or SiBCN.

[0043] Figure 10 shows a cross-sectional view of the semiconductor structure 100 taken along line Y2 in reference Figure 101 after processing according to one or more embodiments of the present invention. In some embodiments of the present invention, the source and drain regions 1002 are formed on the exposed sidewalls of the semiconductor layer 402. In some embodiments of the present invention, a gap 1004 remains between the upper (1002a) and lower (1002b) portions of the source and drain regions 1002 due to the presence of an isolation dielectric 702 that does not provide a surface for epitaxial growth. To ensure device isolation, the gap 1004 can later be filled with a dielectric (see, for example, Figure 11).

[0044] The source and drain regions 1002 can be epitaxially grown using, for example, gas-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. The source and drain regions 1002 can be semiconductor materials epitaxially grown from a gaseous or liquid precursor. In some embodiments of the present invention, the gas source for epitaxial deposition of the semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, a silicon layer can be epitaxially deposited (or grown) from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. The germanium layer can be epitaxially deposited from a germanium gas source selected from the group consisting of germanine, digermanine, halogermanine, dichlorogermanine, trichlorogermanine, tetrachlorogermanine, and combinations thereof. Using such gas source combinations, silicon-germanium alloy layers can be epitaxially formed. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used. In some embodiments of the present invention, the epitaxial semiconductor material includes carbon-doped silicon (Si:C). This Si:C layer can be grown in the same chamber used for other epitaxy steps, or in a dedicated Si:C epitaxy chamber. The Si:C can contain carbon ranging from about 0.2 percent to about 3.0 percent.

[0045] Epitaxially grown silicon and silicon-germanium can be doped by adding n-type dopants (e.g., P or As) or p-type dopants (e.g., Ga, B, BF2, or Al). In some embodiments of the present invention, the source and drain regions 1002 can be epitaxially formed and doped by various methods, such as in-situ doping epitaxy (doping during deposition), post-epitaxing, or injection and plasma doping. The dopant concentration in the doped region is 1 × 10⁻⁶ 19 cm -3 ~2×10 21 cm -3 , or 1 × 10 20 cm -3 ~1 × 10 21 cm -3 It can be set to the range of

[0046] In some embodiments of the present invention, the source and drain regions 1002 are made from silicon or silicon-germanium. In some embodiments of the present invention, the source and drain regions 1002 are p-type source / drain regions made from boron-doped silicon-germanium to a boron concentration of about 1 to about 15 percent, for example, 2 percent, although other boron concentrations are also within the range intended by the present invention.

[0047] Figure 11 shows a cross-sectional view of the semiconductor structure 100 taken along line Y2 of reference Figure 101 after processing according to one or more embodiments of the present invention. In some embodiments of the present invention, a liner 1102 is formed on the source and drain regions 1002. In some embodiments of the present invention, the liner 1102 fills the gap 1004 (i.e., contacts the sidewall of the isolation dielectric 702).

[0048] In some embodiments of the present invention, the liner 1102 is conformally deposited on the semiconductor structure 100. In some embodiments of the present invention, the liner 1102 has a thickness sufficient to completely fill the gap 1004, for example, about 10 nm to about 60 nm, but other thicknesses are also within the range intended for the present invention.

[0049] In some embodiments of the present invention, the liner 1102 is formed using chemical vapor deposition (CVD), plasma CVD (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermochemical vapor deposition (RTCVD), metal-organic CVD (MOCVD), low-pressure CVD (LPCVD), limited-reaction CVD (LRPCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical solution deposition, molecular beam epitaxy (MBE), or other similar processes combined with wet or dry etching processes. The liner 1102 can be made from any suitable dielectric material, such as silicon nitride, but other materials are also within the scope intended for the present invention.

[0050] As further shown in Figure 11, an interlayer dielectric (ILD) 1104 is formed on the substrate 104. The ILD 1104 can be fabricated from any suitable dielectric material, such as oxides, low-k dielectrics, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN. In some embodiments of the present invention, the ILD 1104 is deposited on the semiconductor structure 100 and then recessed (as shown) to expose the upper part 1002a of the source and drain regions 1002. In some embodiments of the present invention, the ILD 1104 is selectively recessed relative to the liner 1102.

[0051] Figure 12 shows a cross-sectional view of the semiconductor structure 100 taken along line Y2 in reference Figure 101 after processing according to one or more embodiments of the present invention. In some embodiments of the present invention, the exposed portion of the liner 1102 (e.g., the portion above the isolation dielectric 702) is removed to expose the upper surface 1002a of the source and drain region 1002. In some embodiments of the present invention, the liner 1102 is selectively removed with respect to the ILD 1104 or the spacer 902 or both. The liner 1102 can be selectively removed using wet etching, dry etching, or a combination of wet etching and / or dry etching.

[0052] The upper portion 1002a of the source and drain region 1002, when exposed, is removed and replaced by the source and drain region 1202. The upper portion 1002a of the source and drain region 1002 can be removed, for example, using hydrogen chloride (HCl) gas or an aqueous solution containing a mixture of ammonia and hydrogen peroxide. Once removed, the source and drain region 1202 can be formed on the sidewall of the semiconductor layer 402 in a similar manner to the source and drain region 1002. For example, the source and drain region 1202 can be epitaxially grown from the sidewall of the semiconductor layer 402.

[0053] In some embodiments of the present invention, the source and drain regions 1202 have a doping type opposite to that of the source and drain regions 1002. For example, in embodiments where the source and drain regions 1002 are p-type regions such as boron-doped silicon-germanium (SiGe:B), the source and drain regions 1202 may include n-type regions such as phosphorus-doped silicon (Si:P). Similarly, if the source and drain regions 1002 are n-type regions, the source and drain regions 1202 can be p-type regions. The dopant concentration can range from about 1 to about 15 percent, for example, 2 percent, but other dopant concentrations are also within the range intended for the present invention.

[0054] Figure 13 shows a cross-sectional view of the semiconductor structure 100 taken along line Y2 in reference Figure 101 after processing according to one or more embodiments of the present invention. In some embodiments of the present invention, a liner 1302 is formed on the source and drain regions 1202. The liner 1302 can be formed in the same manner as the liner 1102 and from the same material. The liner 1302 can be fabricated from the same dielectric as the liner 1102 or from a different dielectric.

[0055] In some embodiments of the present invention, the height of the ILD1104 is increased by depositing an additional dielectric material on top of the semiconductor structure 100. In some embodiments of the present invention, the ILD1104 is planarized, for example, using CMP. In some embodiments of the present invention, the ILD1104 is planarized to the surface of the spacer 902.

[0056] As further shown in Figure 13, the hard mask 804, sacrificial gate 802, and dielectric layer 602 are removed to expose the semiconductor layer 402 (not shown separately). The hard mask 804, sacrificial gate 802, and dielectric layer 602 can then be replaced with an active gate 1304 (sometimes called a metallic gate or conductive gate). In some embodiments of the present invention, the gate 1304 includes a first portion 1304a and a second portion 1304b (as shown).

[0057] The gate 1304 can be a high-k metal gate (HKMG) formed on the channel region of the nanosheet stack 102, for example, using a known substitutional metal gate (RMG) process or a so-called gate-first process. As used herein, “channel region” refers to a portion of the semiconductor layer 402 on which the gate 1304 is formed, and through this layer the current passes from source to drain in the final device.

[0058] In some embodiments of the present invention, the first portion 1304a of gate 1304 includes a PFET gate stack, and the second portion 1304b of gate 1304 includes an NFET gate stack (or vice versa). For example, the first portion 1304a and the second portion 1304b of gate 1304 may include a known gate dielectric (not shown) and a known work function metal stack (not shown) suitable for an NFET device or a PFET device.

[0059] In some embodiments of the present invention, the gate dielectric is a high-k dielectric film formed on the surface (sidewall) of the semiconductor layer 402. The high-k dielectric film can be made from, for example, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, a high-k material, or any combination of these materials. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium-silicon oxide, hafnium-silicon oxynitride, lanthanum oxide, lanthanum-aluminum oxide, zirconium oxide, zirconium-silicon oxide, zirconium-silicon oxynitride, tantalum oxide, titanium oxide, barium-strontium-titanium oxide, barium-titanium oxide, strontium-titanium oxide, yttrium oxide, aluminum oxide, lead-scandium-tantalum oxide, and lead-zinc niobate. The high-k material may further contain dopants such as lanthanum and aluminum. In some embodiments of the present invention, the high-k dielectric film may have a thickness of about 0.5 nm to about 4 nm. In some embodiments of the present invention, the high-k dielectric film contains hafnium oxide and has a thickness of about 1 nm, but other thicknesses are also within the range intended by the present invention.

[0060] In some embodiments of the present invention, one or more work function layers are arranged between the high-k dielectric film and the bulk gate material. In some embodiments of the present invention, the gate 1304 includes one or more work function layers but does not include the bulk gate material.

[0061] If present, the work function layer can be fabricated from, for example, aluminum, lanthanum oxide, magnesium oxide, strontium titanate, strontium oxide, titanium nitride, tantalum nitride, hafnium nitride, tungsten nitride, molybdenum nitride, niobium nitride, hafnium-silicon nitride, titanium-aluminum nitride, tantalum-silicon nitride, titanium-aluminum carbide, tantalum carbide, and combinations thereof. The work function layer can play a role in modifying the work function of gate 1304, enabling adjustment of the device's threshold voltage. The work function layer can be formed to a thickness of about 0.5 to 6 nm, but other thicknesses are also within the range intended by the present invention. In some embodiments of the present invention, each of the work function layers can be formed to a different thickness.

[0062] In some embodiments, the gate 1304 includes a body formed from a bulk conductive gate material deposited on a work function layer or a gate dielectric, or both. The bulk gate material may include any suitable conductive material, such as metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metallic compound materials (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), conductive carbon, graphene, or any suitable combination of these materials. The conductive gate material may further include dopants incorporated during or after deposition.

[0063] Figure 14 shows a cross-sectional view of the semiconductor structure 100 taken along line Y2 in reference Figure 101 after processing according to one or more embodiments of the present invention. In some embodiments of the present invention, a portion of the ILD 1104 is removed (patterned) to form a source / drain contact trench (not shown) which can be filled with a conductive material. In some embodiments of the present invention, the source / drain contact trench exposes the surfaces of the source and drain regions 1002b and 1202. The ILD 1104 can be patterned using wet etching, dry etching, or a combination of continuous wet etching or dry etching or both.

[0064] In some embodiments of the present invention, the lower source / drain contact 1402 is formed or deposited within the source / drain contact trench so as to be in electrical contact with the source and drain region 1002b. Similarly, the upper source / drain contact 1404 is formed or deposited within the source / drain contact trench so as to be in electrical contact with the source and drain region 1202.

[0065] The source / drain contacts 1402 / 1404 can be formed from conductive materials including copper or other metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, aluminum, platinum), their alloys, conductive metal compound materials (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium-aluminum carbide, tungsten silicide, tungsten nitride, cobalt silicide, nickel silicide), conductive carbon, or any suitable combination of these materials. In some embodiments of the present invention, the source / drain contacts 1402 / 1404 are formed from the same conductive material, e.g., cobalt, copper, ruthenium, or tungsten. In some embodiments of the present invention, the source / drain contacts 1402 / 1404 are made from different conductive materials. In some embodiments of the present invention, the source / drain contacts 1402 / 1404 each include a barrier liner (sometimes called a metal liner or barrier metal liner) to prevent diffusion into the surrounding dielectric (not shown).

[0066] Figure 15 shows a flowchart 1500 illustrating a method for forming a semiconductor device according to one or more embodiments of the present invention. As shown in block 1502, a nanosheet stack is formed on a substrate. The nanosheet stack may include alternating first and second sacrificial layers. In some embodiments of the present invention, the first sacrificial layer contains silicon, and the second sacrificial layer contains silicon-germanium. In some embodiments of the present invention, the maximum thickness of the second sacrificial layer is below the critical thickness of the defect.

[0067] In some embodiments of the present invention, one of the first sacrificial layers is formed to be thicker than the remaining first sacrificial layers. In some embodiments of the present invention, the thicker layer is the central layer of the first sacrificial layers.

[0068] In block 1504, the first sacrificial layer is removed, exposing the surface of the second sacrificial layer. In block 1506, a semiconductor layer is formed on the exposed surface of the second sacrificial layer. The semiconductor layer includes a first set of semiconductor layers and a second set of semiconductor layers. In some embodiments of the present invention, the semiconductor layer is epitaxially grown from the exposed surface of the second sacrificial layer.

[0069] In block 1508, the second sacrificial layer is removed. In block 1510, an isolation dielectric is formed between the first set of semiconductor layers and the second set of semiconductor layers. The method may further include forming a dielectric layer on the exposed surface of the semiconductor layers.

[0070] In some embodiments of the present invention, a first source and drain region is formed on the sidewall of a first pair of semiconductor layers, and a second source and drain region is formed on the sidewall of a second pair of semiconductor layers. In some embodiments of the present invention, the first source and drain region includes a first dopant type, and the second source and drain region includes a second different dopant type. In some embodiments of the present invention, the first source and drain region includes a p-type dopant, and the second source and drain region includes an n-type dopant.

[0071] In some embodiments of the present invention, a first dielectric liner is formed on a first source and drain region, and a second dielectric liner is formed on a second source and drain region. In some embodiments of the present invention, the second dielectric liner is formed directly on the upper surface of the first dielectric liner.

[0072] In some embodiments of the present invention, a lower source and drain contact is formed on the side wall of a first source and drain region. In some embodiments of the present invention, an upper source and drain contact is formed on the upper surface of a second source and drain region.

[0073] In some embodiments of the present invention, a gate is formed on a channel region of a semiconductor layer. In some embodiments of the present invention, the gate comprises a first portion and a second portion. In some embodiments of the present invention, the first portion comprises a p-type gate stack, and the second portion comprises an n-type gate stack.

[0074] The methods described herein and the resulting structures can be used to manufacture IC chips. The resulting IC chips can be distributed by the manufacturer in the form of a raw wafer (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads fixed to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier with either or both surface interconnects or embedded interconnects). In either case, the chips are integrated with other chips, discrete circuit elements, or other signal processing devices or combinations thereof as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing an IC chip, ranging from toys and other low-end applications to displays, keyboards or other input devices, and advanced computer products with a central processor.

[0075] Various embodiments of the present invention are described herein with reference to the relevant drawings. Alternative embodiments can be devised without departing from the scope of the present invention. Various connections and positional relationships (e.g., above, below, adjacent, etc.) are described between elements in the following description and drawings, but those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent, even if the orientation changes, as long as the described function is maintained. These connections or positional relationships, or both, may be direct or indirect unless otherwise specified, and the present invention is not intended to limit them in this respect. Similarly, the term “joined” and its variations describe having a communication path between two elements, and do not mean a direct connection between elements without an intervening element / connection between them. All these variations are considered part of this specification. Thus, the joining of entities can refer to either a direct or indirect joining, and the positional relationships between entities can be direct or indirect positional relationships. As an example of an indirect positional relationship, the reference herein to forming layer "A" on layer "B" includes situations where one or more intermediate layers (e.g., layer "C") are located between layer "A" and layer "B," provided that the relevant properties and functionalities of layer "A" and layer "B" are not substantially altered by the intermediate layers.

[0076] The following definitions and abbreviations are used for the purposes of the claims and interpretation of this specification. Where used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains,” or “containing,” or any other variation thereof, are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus comprising a list of elements is not necessarily limited to those elements alone and may include other elements not expressly enumerated or that are specific to such composition, mixture, process, method, article, or apparatus.

[0077] Furthermore, the term “exemplary” is used herein to mean “acting as an example, case, or illustration.” Any embodiment or design described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other embodiments or designs. The terms “at least one” and “one or more” are understood to include any integer one or more, i.e., 1, 2, 3, 4, etc. The term “more” is understood to include any integer two or more, i.e., 2, 3, 4, 5, etc. The term “connection” may include indirect “connections” and direct “connections.”

[0078] References in this specification to “one embodiment,” “embodiment,” and “exemplary embodiment” indicate that the embodiments described may include certain features, structures, or characteristics, but not all embodiments may include or not include those features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, where certain features, structures, or characteristics are described in relation to an embodiment, it is presented that any influence of such features, structures, or characteristics in relation to other embodiments, whether explicitly stated or not, is within the knowledge of those skilled in the art.

[0079] For the purposes of the following explanation, the terms “up,” “down,” “right,” “left,” “vertical,” “horizontal,” “upper,” and “lower,” and their derivatives, are used in relation to the structures and methods described, as they are oriented in the drawings. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is located on a second element, such as a second structure, and that an intervening element, such as an interface structure, may be located between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without an intermediate conductive, insulating, or semiconductor layer.

[0080] Spatially relative terms, such as “directly below,” “downward,” “below,” “up,” and “top,” are used herein to describe the relationship between one element or feature and another, as shown in the figures, for the sake of ease of explanation. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. For example, if the device in the figure is turned over, an element described as “below” or “directly below” another element or feature will be oriented “up” of the other element or feature. Thus, the term “downward” can encompass both upward and downward orientations. The device may be oriented in other ways (e.g., rotated by 90 degrees or other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0081] The terms “about,” “substantially,” and “approximately,” and their variations, are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time of filing this application. For example, “about” may include a range of ±8%, 5%, or 2% of a given value.

[0082] For example, the phrase "selective to" in "a first element selective to a second element" means that the first element can be etched and the second element can act as an etch stop.

[0083] The term “conformal” (e.g., conformal layer or conformal deposit) means that the thickness of a layer is substantially the same on all surfaces, or that the thickness variation is less than 15% of the nominal thickness of the layer.

[0084] The terms "epitaxial growth or deposition or both" and "epitaxially formed or grown or both" refer to the growth of one semiconductor material (crystalline material) on the deposition surface of another semiconductor material (crystalline material), where the growing semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material on the deposition surface (seed material). In the epitaxial deposition process, the chemical reactants provided by the source gas can be controlled, and system parameters can be set so that the deposited atoms reach the deposition surface of the semiconductor substrate with enough energy to move around on the surface so that the deposited atoms are oriented in accordance with the crystalline arrangement of atoms on the deposition surface. The epitaxially grown semiconductor material can have substantially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed. For example, <100> Epitaxially grown semiconductor material deposited on an oriented crystal surface is <100> Orientation can be achieved. In some embodiments of the present invention, the epitaxial growth process or the epitaxial deposition process or both may be selective for formation on a semiconductor surface, and the material may or may not be deposited on other exposed surfaces such as silicon dioxide or silicon nitride surfaces.

[0085] As used herein, "p-type" refers to the addition of impurities to an intrinsic semiconductor that creates valence electron deficiencies. In silicon-containing substrates, examples of p-type dopants, or impurities, include, but are not limited to, boron, aluminum, gallium, and indium.

[0086] As used herein, "n-type" refers to the addition of impurities that provide free electrons to an intrinsic semiconductor. In silicon-containing substrates, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus.

[0087] As previously stated herein, for the sake of brevity, prior art relating to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. However, as background, a more general description of semiconductor device manufacturing processes that may be used when carrying out one or more embodiments of the present invention is provided here. While specific manufacturing operations used when carrying out one or more embodiments of the present invention may be known individually, the described combination of operations of the present invention or the resulting structure, or both, is unique. Thus, the unique combination of operations described in relation to the manufacture of semiconductor devices according to the present invention utilizes various individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the following paragraphs.

[0088] Generally, the various processes used to form microchips that are packaged into ICs are classified into four common categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include, among others, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process that removes material from a wafer. Examples include etching processes (either wet or dry) and chemical mechanical planarization (CMP). For example, reactive ion etching (RIE) is a type of dry etching that removes material, such as semiconductor material in a masked pattern, by using a chemically reactive plasma to expose the material to an ion shock that removes part of the material from the exposed surface. The plasma is typically generated by an electromagnetic field under low pressure (vacuum). Semiconductor doping is the modification of electrical properties by doping, for example, the source and drain of a transistor, generally by diffusion, ion implantation, or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing activates the implanted dopants. Both conductive (e.g., polysilicon, aluminum, copper, etc.) and insulating (e.g., various forms of silicon dioxide, silicon nitride, etc.) films are used to connect and isolate transistors and their components. By selectively doping different areas of a semiconductor substrate, the conductivity of the substrate can be changed by applying a voltage. By creating the structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate and then transferring that pattern to the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photoresist.Multiple lithography and etching pattern transfer steps are repeated to construct the complex structure that makes up the transistor and the numerous wires that connect the millions of transistors in the circuit. Each pattern printed on the wafer is aligned with a pre-formed pattern, and conductors, insulators, and selectively doped areas are gradually built up to form the final device.

[0089] The flowcharts and block diagrams in the figures illustrate possible embodiments of a manufacturing method or a work method, or both, according to various embodiments of the present invention. Various functions / works of the method are represented in the flowcharts by blocks. In some alternative embodiments, the functions indicated in the blocks may be performed in an order different from that shown in the figures. For example, two consecutively shown blocks may actually be performed substantially simultaneously, or blocks may sometimes be performed in reverse order, depending on the functions involved.

[0090] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the embodiments described. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the embodiments described. The terminology used herein has been chosen to best describe the principles, practical applications, or technical improvements of the embodiments, or to enable those else skilled in the art to understand the embodiments described herein.

Claims

1. A method for forming a semiconductor device, The method involves forming a nanosheet stack on a substrate, wherein the nanosheet stack comprises alternatingly arranged first sacrificial layers and second sacrificial layers, and one of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. Removing the first sacrificial layer, Forming a semiconductor layer on the surface of the second sacrificial layer, wherein the semiconductor layer includes a first set of semiconductor layers and a second set of semiconductor layers. Removing the aforementioned second sacrificial layer, Forming an isolation dielectric between the first set of semiconductor layers and the second set of semiconductor layers Methods that include...

2. The method according to claim 1, wherein the first sacrificial layer contains silicon and the second sacrificial layer contains silicon-germanium.

3. The method according to claim 1, wherein the one layer having a greater thickness than the one described above includes the centralmost layer of the first sacrificial layer.

4. The method according to claim 1, wherein the maximum thickness of the second sacrificial layer is less than the critical thickness of the defect.

5. The method according to claim 4, wherein the semiconductor layer is epitaxially grown from the exposed surface of the second sacrificial layer.

6. The method according to claim 1, further comprising forming a dielectric layer on the exposed surface of the semiconductor layer.

7. The method according to claim 1, further comprising forming a first source and drain region on the sidewall of the first set of semiconductor layers and forming a second source and drain region on the sidewall of the second set of semiconductor layers.

8. The method according to claim 7, wherein the first source and drain region includes a first dopant type, and the second source and drain region includes a second dopant type.

9. The method according to claim 8, wherein the first source and drain region includes a p-type dopant, and the second source and drain region includes an n-type dopant.

10. The method according to claim 7, further comprising forming a first dielectric liner on the first source and drain region and forming a second dielectric liner on the second source and drain region.

11. The method according to claim 10, wherein the second dielectric liner is located on the upper surface of the first dielectric liner.

12. The method according to claim 10, further comprising forming lower source and drain contacts on the side walls of the first source and drain region.

13. The method according to claim 12, further comprising forming an upper source and drain contact on the upper surface of the second source and drain region.

14. The method according to claim 1, further comprising forming a gate on the channel region of the semiconductor layer.

15. The method according to claim 14, wherein the gate comprises a first portion and a second portion, the first portion comprising a p-type gate stack and the second portion comprising an n-type gate stack.

16. A nanosheet stack on a substrate, comprising a first set of semiconductor layers and a second set of semiconductor layers, A dielectric material is isolated between the first set of semiconductor layers and the second set of semiconductor layers, A first source and drain region forming an integral on the sidewall of the first set of semiconductor layers and a second source and drain region forming an integral on the sidewall of the second set of semiconductor layers, wherein the integral first source and drain region includes a first dopant type and the integral second source and drain region includes a second dopant type, A lower source and drain contact on a side wall adjacent to the side wall of the first integrated source and drain region, An upper source and drain contact on the upper surface adjacent to the upper surface of the upper surface of the second integrated source and drain region, The first dielectric liner on the side wall adjacent to the side wall of the second source and drain region which form a single unit A semiconductor device equipped with the following features.

17. The semiconductor device according to claim 16, wherein the first integrated source and drain region includes a p-type dopant, and the second integrated source and drain region includes an n-type dopant.

18. The semiconductor device according to claim 16, further comprising a gate, wherein a first portion of the gate is formed on the channel region of the first set of semiconductor layers, and a second portion of the gate is formed on the channel region of the second set of semiconductor layers.

19. The semiconductor device according to claim 16, further comprising an interlayer dielectric between the sidewalls of the lower source and drain contacts and the sidewalls of the upper source and drain contacts.

20. The semiconductor device according to claim 16, further comprising a second dielectric liner between the upper surface of the first integral source and drain region and the bottom surface of the second integral source and drain region.

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