Semiconductor equipment

Abstract

To provide a transistor structure and a manufacturing method of the same which achieve a normally-off switching element; and provide a constitution and a manufacturing method of the same which achieve high-speed response and high-speed drive of a semiconductor device; and provide a semiconductor device having high reliability while improving ON characteristics of a transistor.SOLUTION: In a transistor where a semiconductor layer, a source electrode layer or a drain electrode layer, a gate insulation film and a gate electrode layer are sequentially laminated, an oxide semiconductor layer which contains at least four elements such as indium, gallium, zinc and oxygen and when composition ratios of the four elements are represented by atomic percentages, a ratio of indium is equal to or larger than twice the ratio of each of gallium and zinc is used as the semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Note that in this specification, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics in general, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background Art]

[0003] A technique for forming a transistor (also referred to as a thin film transistor or TFT) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to integrated circuits ( ICs) and electronic devices such as image display devices (display devices). As a semiconductor thin film applicable to a transis tor, silicon-based semiconductor materials are widely known; however, oxide semiconductors have attracted attention as other materials therefor.

[0004] For example, a transistor using an amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) for an active layer of the transistor is disclosed (see Patent Document 1 ). [Prior Art Document] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 [Summary of Invention] [Problem to be Solved by the Invention]

[0006] It is an object to shift the threshold voltage of electrical characteristics of a transistor using an oxide semiconductor for a channel formation region to a posit can be obtained, and an object is to provide a transistor structure and a method for manufacturing the same that realizes a so-called normally-off switching element .

[0007] Another object is to improve on-characteristics (for example, on-state current and field-effect mobility) of a transistor to achieve high-speed response and high-speed driving of a semiconductor device, thereby realizing a higher-performance semiconductor device , and to provide a structure thereof and a method for manufacturing the same .

[0008] Another object is to provide a highly reliable semiconductor device in which threshold voltage hardly fluctuates even when used for a long period of time .

[0009] An object of the present invention is to solve at least one of the above problems Means for Solving the Problem

[0010] In a transistor in which a semiconductor layer, a source electrode layer or a drain electrode layer, a gate insulating film, and a gate electrode layer are stacked in this order, the semiconductor layer contains at least four elements of indium, gallium, zinc, and oxygen , and when the composition ratio of the four elements is expressed in atomic percentage, an oxide semiconductor layer in which the proportion of indium is twice or more the proportion of gallium and the proportion of zinc is used

[0011] One embodiment of the invention disclosed in this specification includes an oxide semiconductor layer including a channel formation region provided over an oxide insulating layer, a gate insulating film over the oxide semiconductor layer, and a gate electrode layer overlapping with the oxide semiconductor layer over the gate insulating film the oxide semiconductor layer contains at least four elements of indium, gallium, zinc, and oxygen, and when the composition ratio of the four elements is expressed in atomic percentage , the proportion of indium is twice or more the proportion of gallium and the proportion of zinc​​​​ .

[0012] One embodiment of the invention disclosed herein is a channel-forming region provided on an oxide insulating layer. An oxide semiconductor layer containing a region, a source electrode layer and a drain electrode layer on the oxide semiconductor layer, and A gate insulating film is provided on the drain electrode layer and the drain electrode layer, and an oxide semiconductor layer is provided on the gate insulating film. It has an overlapping gate electrode layer, and the oxide semiconductor layer is made of indium, gallium, zinc, and oxygen It contains at least four elements, and when the composition ratio of these four elements is expressed as an atomic percentage, indium The semiconductor device has a ratio of gallium to zinc that is more than twice the ratio of gallium to zinc.

[0013] One embodiment of the invention disclosed herein is a configuration in which a gap is provided on an oxide insulating layer. A pair of first oxide semiconductor layers, an oxide insulating layer, and a pair of first oxide semiconductor layers in contact with each other. A second oxide semiconductor layer including a channel-forming region, an oxide insulating layer and a second oxide A gate insulating film is placed on the oxide semiconductor layer, and a gate insulating film is placed on the gate insulating film, overlapping with a second oxide semiconductor layer. The device has an electrode layer and a second oxide semiconductor layer made of indium, gallium, zinc, and oxygen. It contains at least one element, and when the composition ratio of the four elements is expressed as atomic percentages, the proportion of indium However, the semiconductor device has a ratio of gallium and zinc that is more than twice the ratio of gallium.

[0014] The oxide semiconductor layer or the second oxide semiconductor layer is a non-single crystal semiconductor with c-axis oriented bonds. It may include a crystal region.

[0015] The oxide semiconductor layer or the second oxide semiconductor layer is a non-single-crystal semiconductor, and is composed of indium:gal It can be fabricated using an oxide target with a zinc:zinc composition ratio of 3:1:2.

[0016] In the oxide semiconductor layer or the second oxide semiconductor layer, the region that does not overlap with the gate electrode layer is: The deck may also include a Dopant.

[0017] Furthermore, in the oxide semiconductor layer or the second oxide semiconductor layer, the source electrode layer or drain The region not overlapping with the electrode layer is higher than the region overlapping with the source electrode layer or drain electrode layer. A configuration with a high oxygen concentration may also be used.

[0018] Furthermore, by using the gate electrode layer as a mask, a dopant is introduced into the oxide semiconductor layer in a self-aligned manner. In an oxide semiconductor layer, the resistance is lower in the region between the channel formation region and the channel formation region. A low-resistance region including a dopant may be formed. The dopant improves the conductivity of the oxide semiconductor layer. These are impurities that cause alteration. Methods for introducing dopants include ion implantation and ion doping. Methods such as the ion implantation method and plasma immersion ion implantation method can be used. .

[0019] The oxide semiconductor layer has a channel formation region sandwiched between low-resistance regions in the channel length direction. As a result, the transistor has high on-characteristics (e.g., on-current and field-effect mobility). This enables high-speed operation and fast response.

[0020] Furthermore, a heat treatment (dehydration or dehydrogenation treatment) is performed to release hydrogen or moisture from the oxide semiconductor layer. The following procedure may be performed. Also, when using a crystalline oxide semiconductor layer as the oxide semiconductor layer, Heat treatment may be performed to induce crystallization.

[0021] Furthermore, dehydration or dehydrogenation treatment removes oxygen, which is the main component material constituting oxide semiconductors. There is a risk that oxygen will be simultaneously desorbed and reduced. In oxide semiconductor films, oxygen is desorbed. In the affected area, an oxygen deficiency exists, which causes fluctuations in the transistor's electrical characteristics. This can result in a donor level being created.

[0022] Therefore, it is preferable to supply oxygen to the oxide semiconductor layer that has undergone dehydration or dehydrogenation treatment. It is possible to supply oxygen to the oxide semiconductor layer to fill in oxygen deficiencies in the film. Cut.

[0023] For example, an oxide insulating film containing a large amount (excess) of oxygen, which serves as an oxygen source, is used as an oxide semiconductor layer. By providing them in contact, oxygen can be supplied from the oxide insulating film to the oxide semiconductor layer. Yes, it is possible. In the above configuration, the oxide semiconductor that has been subjected to heat treatment as a dehydration or dehydrogenation treatment. By performing heat treatment with the body layer and the oxide insulating film in contact with at least a portion of them, oxidation Oxygen may be supplied to the semiconductor layer.

[0024] Furthermore, in the oxide semiconductor layer that has undergone dehydration or dehydrogenation treatment, oxygen (at least oxygen radio) You can supply oxygen into the membrane by introducing (containing either CAL, oxygen atoms, or oxygen ions). Methods for introducing oxygen include ion implantation, ion doping, and plasma immersion. Ion implantation and plasma treatment can be used.

[0025] Furthermore, preferably, the oxide semiconductor layer provided in the transistor is made of crystalline oxide semiconductor. This refers to a membrane that contains a region with an excess of oxygen relative to the stoichiometric composition ratio in its state. This is preferable. In this case, the oxygen content should exceed the stoichiometric composition ratio of the oxide semiconductor. Alternatively, the oxygen content should exceed the amount of oxygen in the case of a single crystal. Oxygen may also be present between the lattice of the conductor.

[0026] Hydrogen or water is removed from the oxide semiconductor, and it is purified to the highest possible purity with as few impurities as possible. By supplying oxygen and compensating for the oxygen deficiency, a type I (intrinsic) oxide semiconductor is produced, or type I It is possible to create an oxide semiconductor that is very close to (intrinsic). By doing so, oxide To raise the Fermi level (Ef) of a semiconductor to the same level as the intrinsic Fermi level (Ei). Therefore, by using this oxide semiconductor layer in a transistor, oxygen vacancies can be eliminated. Reduces the variation in the threshold voltage Vth of transistors and the threshold voltage shift ΔVth. It is possible.

[0027] One embodiment of the present invention has a transistor or a circuit comprising a transistor. This relates to semiconductor devices. For example, in an oxide semiconductor, a channel formation region is formed, This relates to a semiconductor device having a circuit that includes a star or transistor. LSIs, CPUs, power devices mounted in power supply circuits, memory, thyristors, Semiconductor integrated circuits including converters and image sensors, and electronic displays such as liquid crystal displays. This relates to electronic equipment that incorporates light-emitting display devices, such as gas-optical devices and light-emitting elements, as components. [Effects of the Invention]

[0028] The threshold voltage of the electrical characteristics of a transistor using an oxide semiconductor in the channel formation region is... This allows for the realization of a transistor structure that enables a so-called normally-off switching element. We can provide a structure and a method for manufacturing it.

[0029] Furthermore, in order to realize a higher-performance semiconductor device, the on-characteristics of the transistor (for example, on A configuration that improves current and field-effect mobility to achieve high-speed response and high-speed drive of semiconductor devices. We can also provide a method for producing the same.

[0030] Furthermore, the threshold voltage is less likely to shift even during long-term use, making it a highly reliable semiconductor device. We can provide a place for you. [Brief explanation of the drawing]

[0031] [Figure 1] A diagram illustrating one form of semiconductor device and a method for manufacturing a semiconductor device. [Figure 2] A diagram illustrating one form of semiconductor device. [Figure 3] A diagram illustrating one form of semiconductor device. [Figure 4] A diagram illustrating one form of semiconductor device and a method for manufacturing a semiconductor device. [Figure 5] A cross-sectional view, plan view, and circuit diagram showing one form of a semiconductor device. [Figure 6] Circuit diagram and perspective view showing one form of a semiconductor device. [Figure 7] A cross-sectional view and a plan view showing one embodiment of a semiconductor device. [Figure 8] A circuit diagram showing one form of a semiconductor device. [Figure 9] A block diagram showing one form of a semiconductor device. [Figure 10] A block diagram showing one form of a semiconductor device. [Figure 11] A block diagram showing one form of a semiconductor device. [Figure 12] A diagram showing the energy band diagram of an oxide semiconductor. [Figure 13] A figure showing the results of XRD measurements of an oxide semiconductor film. [Figure 14] A diagram showing the electrical characteristics evaluation of transistor 1. [Figure 15]A diagram showing the electrical characteristics and reliability evaluation of transistor 2. [Figure 16] TEM image of an oxide semiconductor film. [Figure 17] A diagram illustrating the leakage current of a transistor. [Modes for carrying out the invention]

[0032] Hereinafter, embodiments of the invention disclosed herein will be described in detail with reference to the drawings. However, the inventions disclosed herein are not limited to the following description, and their forms and details may vary. It will be readily apparent to those skilled in the art that this can be changed. This shall not be interpreted as being limited to the descriptions of the embodiments shown below. The ordinal number 2 is used for convenience only and does not indicate the order of processes or stacking. Furthermore, in this specification, a specific name is not used to identify the invention. do not have.

[0033] (Embodiment 1) In this embodiment, one form of semiconductor device and a method for manufacturing a semiconductor device is shown using Figures 1 and 3. Let me explain. In this embodiment, as an example of a semiconductor device, a transistor having an oxide semiconductor film is used. Show the indicator.

[0034] Even in a single-gate transistor structure where one channel formation region is formed, or where two are formed... It may be a double-gate structure or a triple-gate structure with three gates formed. It has two gate electrode layers arranged above and below the channel region with a gate insulating film in between. A dual-gate type would also be acceptable.

[0035] The transistor 440a shown in Figures 1(A) to (E) is a plate having a top gate structure. This is an example of a type N transistor.

[0036] The transistor 440a is provided on a substrate 400 having an insulating surface on which an oxide insulating layer 436 is provided. On top of that, an oxide semiconductor layer 4 including a channel-forming region 409 and low-resistance regions 404a and 404b. 03, Source electrode layer 405a, Drain electrode layer 405b, Gate insulating film 402, Gate electrode It has an extreme layer 401. An insulating film 407 is formed on the transistor 440a.

[0037] Figure 1 shows the source electrode layer 405a and the drain electrode layer on the oxide semiconductor layer 403. Although 405b and the gate electrode layer 401 do not overlap, the transient shown in Figure 2(A) Like sta440b, the source electrode layer 405a, the drain electrode layer 405b and the gate electrode The structure may partially overlap with layer 401.

[0038] The oxide semiconductor layer 403 contains at least four elements: indium, gallium, zinc, and oxygen. When the composition ratio of these four elements is expressed as atomic percentages, the proportion of indium is equal to the proportion of gallium. This is an oxide semiconductor layer (also called an IGZO layer) where the proportion of ammonium compounds and zinc is more than twice that of ammonium compounds.

[0039] The oxide semiconductor layer 403 is an oxide with an indium:gallium:zinc composition ratio of 3:1:2. It can be fabricated by sputtering using a GET.

[0040] Oxide semiconductors are non-single crystals and can be amorphous or polycrystalline. The structure may include crystalline portions or be amorphous.

[0041] Amorphous oxide semiconductors can be made relatively easily to obtain a flat surface, This can reduce interfacial scattering when fabricating transistors, and it can be done relatively easily and relatively high You can obtain a high degree of mobility.

[0042] Furthermore, in crystalline oxide semiconductors, bulk defects can be reduced even further, and surface By improving the flatness, it is possible to obtain mobility higher than that of an amorphous oxide semiconductor. To improve surface flatness, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Alternatively, it is preferable to form it on a surface with a nm or smaller.

[0043] Furthermore, Ra can be applied to a surface using the arithmetic mean roughness defined in JIS B0601. This is a three-dimensional extension, and it involves "averaging the absolute values ​​of the deviations from the reference plane to the specified plane." It can be expressed as "value" and is defined by the following formula.

[0044]

number

[0045] In the above, S0 is the measurement surface (coordinates (x1,y1)(x1,y2)(x2,y1 Z0 refers to the area of ​​the rectangle enclosed by the four points represented by (x2, y2), and Z0 is This refers to the average height of the measurement surface. Ra stands for Atomic Force Microscope (AFM). It can be evaluated using a microscope.

[0046] The oxide semiconductor layer 403 is an oxide semiconductor layer containing crystals and having crystalline properties (crystalline oxide A crystalline oxide semiconductor layer can be used. The crystalline state in the crystalline oxide semiconductor layer is the crystal axis. The direction may be disordered or it may be in a state with a certain orientation.

[0047] For example, as a crystalline oxide semiconductor layer, an acid containing crystals having a c-axis approximately perpendicular to the surface. A semiconductor layer can be used.

[0048] An oxide semiconductor layer containing crystals having a c-axis roughly perpendicular to the surface does not have a single-crystal structure. It is not an amorphous structure, but a crystal with c-axis orientation (C Axis Aligned) It is an oxide semiconductor (CAAC-OS) layer containing crystal (also called CAAC). .

[0049] CAAC-OS is a c-axis oriented and viewed from a direction perpendicular to the ab-plane, surface, or interface. It has a horn-shaped or hexagonal atomic arrangement, and in the direction perpendicular to the c-axis, the metal atoms are layered. Alternatively, metal atoms and oxygen atoms are arranged in layers, and the ab plane (or surface or interface) In this case, the crystal has a different orientation for the a-axis or b-axis (rotated around the c-axis). A thin film containing AC is a thin film that is crystallized with respect to the c-axis, and not necessarily crystallized with respect to the ab-plane. Not arranged.

[0050] In a broad sense, CAAC refers to a non-single crystal, and when viewed from a direction perpendicular to its ab-plane, it also has a triangular shape. Alternatively, it has an atomic arrangement that is hexagonal, or equilateral triangle or regular hexagonal, and perpendicular to the c-axis direction. The material contains a phase in which metal atoms are arranged in layers or in layers of metal atoms and oxygen atoms when viewed from a particular direction.

[0051] Thin films containing CAAC are not single crystals, but they are not formed solely from amorphous materials either. Furthermore, thin films containing CAAC include crystalline portions (crystalline parts), but one crystalline portion and others In some cases, the boundaries of the crystalline portion cannot be clearly identified.

[0052] Some of the oxygen in the CAAC may be replaced with nitrogen. Also, a thin film containing CAAC The c-axis of each constituent crystal portion is in a specific direction (for example, the substrate surface on which CAAC is formed or the C-axis). The surfaces, film surfaces, interfaces, etc. of the AAC may be aligned perpendicular to each other. Alternatively, the CAAC may be aligned perpendicular to each other. The normals of the ab-planes of the individual crystal portions constituting the thin film are in a specific direction (e.g., substrate surface, surface). It may be oriented perpendicular to the film surface, interface, etc.

[0053] By using this crystalline oxide semiconductor layer, the electrical properties of the transistor when irradiated with visible light or ultraviolet light are reduced. This allows for further suppression of changes in specific characteristics, resulting in a more reliable semiconductor device.

[0054] There are three methods for obtaining a crystalline oxide semiconductor layer having c-axis orientation. The first is The oxide semiconductor layer was deposited at a deposition temperature of 200°C to 500°C, and a rough pattern was applied to the surface. This method involves vertically oriented along the c axis. The second method involves depositing a thin film and then heating it at 200°C or higher for 70°C. This method involves heat treatment at temperatures below 0°C to orient the c axis roughly perpendicular to the surface. The third method is After forming a thin film for the first layer, a heat treatment is performed at 200°C to 700°C to form the second layer. This method involves creating a film and orienting it along the c-axis approximately perpendicular to the surface.

[0055] The thickness of the oxide semiconductor layer 403 is 1 nm to 30 nm (preferably 5 nm to 10 nm). (m or less), sputtering method, MBE (Molecular Beam Epitaph) xy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Deposition) The spar method and other methods can be used as appropriate. In addition, the oxide semiconductor layer 403 is spa Film deposition is carried out with multiple substrate surfaces set approximately perpendicular to the surface of the tarring target. The film may also be deposited using a sputtering apparatus.

[0056] CAAC-OS films are used, for example, for polycrystalline oxide semiconductor sputtering targets. The film is deposited using a sputtering method. Ions are directed onto the sputtering target. Upon collision, the crystalline region contained in the sputtering target cleaves from the ab plane, and a -The sputtering particles are exfoliated as flat or pellet-shaped sputtering particles having a surface parallel to the -b surface. In this case, the flat sputtering particles maintain their crystalline state and form a base By reaching the plate, the CAAC-OS film can be deposited.

[0057] Furthermore, it is preferable to apply the following conditions for forming the CAAC-OS film.

[0058] By reducing the inclusion of impurities during film formation, it is possible to suppress the disruption of the crystalline state due to impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, and nitrogen, etc.) present in the deposition chamber. It would be good to reduce it. Also, it would be good to reduce the impurity concentration in the film formation gas. Specifically, the dew point is A film-forming gas with a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0059] Furthermore, by increasing the substrate heating temperature during film deposition, the sputtering particles can be prevented from migrating after reaching the substrate. A reaction occurs. Specifically, the substrate heating temperature is preferably between 100°C and 740°C. The film is deposited at a temperature between 200°C and 500°C. By increasing the substrate heating temperature during film deposition, the flat When plate-shaped sputtering particles reach the substrate, migration occurs on the substrate. The flat surface of the sputtered particles adheres to the substrate.

[0060] Furthermore, by increasing the oxygen content in the deposition gas and optimizing the power, plasma damage during film deposition can be reduced. It is preferable to reduce this. The oxygen content in the film-forming gas is 30% by volume or more, preferably 100% by volume. Let the product be %.

[0061] As an example of a target for sputtering, an In-Ga-Zn-O compound target is used. The following is an example.

[0062] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a predetermined molar ratio and then subjected to pressure treatment. Furthermore, by heat treatment at a temperature between 1000°C and 1500°C, polycrystalline In-G is produced. The target is an a-Zn-O compound. Note that X, Y, and Z are arbitrary positive numbers. So, a given mole ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powder 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 mo This is the ratio of l values. Note that the type of powder and the ratio in which they are mixed will be determined by the sputtering process being manufactured. You can modify it as needed depending on the target.

[0063] Figures 1(A) to (E) show an example of the fabrication method using transistor 440a.

[0064] First, an oxide insulating layer 436 is formed on a substrate 400 having an insulating surface.

[0065] There are no major restrictions on the substrates that can be used for the substrate 400 having an insulating surface, however In both cases, it is necessary to have sufficient heat resistance to withstand subsequent heat treatment. For example, burrs Glass substrates such as umborosilicate glass and aluminoborosilicate glass, ceramic substrates, Quartz substrates, sapphire substrates, etc. can be used. Also, silicon and silicon carbide can be used. Which single-crystal semiconductor substrates, polycrystalline semiconductor substrates, and compound semiconductor groups such as silicon germanium Boards, SOI substrates, etc., can also be used, and semiconductor elements are provided on these substrates. This may be used as substrate 400.

[0066] Furthermore, a flexible substrate may be used as the substrate 400 to fabricate a semiconductor device. To fabricate such a semiconductor device, a transistor containing an oxide semiconductor layer 403 is placed on a flexible substrate. The 440a may be fabricated directly, or a trans containing the oxide semiconductor layer 403 may be fabricated on another substrate. Zista 440a may be fabricated, then peeled off and transferred to a flexible substrate. To peel and transfer the material onto a flexible substrate, the fabricated substrate and the oxide semiconductor film are used to create a transistor 4. It is preferable to provide a release layer between 40a and the other layer.

[0067] As the oxide insulating layer 436, an oxide layer is formed by plasma CVD or sputtering, etc. Ricon, silicon oxide nitride, aluminum oxide, aluminum oxide nitride, hafnium oxide It can be formed using gallium oxide, or a mixture thereof.

[0068] The oxide insulating layer 436 may be a single layer or a multilayer. For example, a silicon oxide film on the substrate 400. The In-Hf-Zn oxide film and the oxide semiconductor layer 403 may be stacked in order, and the substrate 4 On top of 00 is a silicon oxide film, with an atomic ratio of In:Zr:Zn = 1:1:1 In-Zr-Zn The silicon oxide film and the oxide semiconductor layer 403 may be stacked in order, or silicon oxide film may be placed on the substrate 400. In-Gd-Zn oxide film, with an atomic ratio of In:Gd:Zn=1:1:1, oxide The semiconductor layers 403 may be stacked in sequence.

[0069] In this embodiment, the oxide insulating layer 436 is formed using the sputtering method. Use a cone film.

[0070] Alternatively, a nitride insulating film may be provided between the oxide insulating layer 436 and the substrate 400. Nitride insulating films are produced by plasma CVD or sputtering, etc., using silicon nitride and nitride Using silicon oxide, aluminum nitride, aluminum oxide nitride, or mixtures thereof It can be formed by [doing something].

[0071] Next, an oxide semiconductor layer 403 is formed on the oxide insulating layer 436.

[0072] Because the oxide insulating layer 436 is in contact with the oxide semiconductor layer 403, it is present in small amounts in the film (bulk). In both cases, it is preferable that an amount of oxygen exceeding the stoichiometric composition ratio is present. For example, oxide insulation When using a silicon oxide film as layer 436, SiO 2+α (However, α > 0) By using such an oxide insulating layer 436, oxygen is supplied to the oxide semiconductor layer 403. This allows for the supply of oxygen, thereby improving its properties. Oxygen is supplied to the oxide semiconductor layer 403. This allows us to compensate for oxygen deficiencies in the membrane.

[0073] For example, an oxide insulating layer 436 containing a large amount (excess) of oxygen, which serves as an oxygen source, is used as an oxide semiconductor insulating layer. By providing it in contact with the body layer 403, the oxide insulating layer 436 and the oxide semiconductor layer 40 Oxygen can be supplied to 3. The oxide semiconductor layer 403 and the oxide insulating layer 436 are reduced. By performing heat treatment while at least a portion is in contact, oxygen is transferred to the oxide semiconductor layer 403. You may supply it.

[0074] In the process of forming the oxide semiconductor layer 403, hydrogen or water is formed in the oxide semiconductor layer 403. To minimize the inclusion of certain substances, a pretreatment is performed on the oxide semiconductor layer 403 before deposition. In the preheating chamber of the taring apparatus, the substrate on which the oxide insulating layer 436 has been formed is preheated, and the substrate and It is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the oxide insulating layer 436. Furthermore, a cryopump is preferred as the exhaust means to be installed in the preheating chamber.

[0075] In the region where the oxide semiconductor layer 403 is in contact with the oxide insulating layer 436, a planarization treatment is applied. A planarization treatment may be performed. The planarization treatment is not particularly limited, but polishing treatment (for example, chemical Chemical Mechanical Polishing (CMP) Methods such as dry etching and plasma treatment can be used.

[0076] Plasma processing can be performed, for example, by introducing argon gas to generate plasma. Sputtering can be performed. Reverse sputtering is a process where RF is applied to the substrate side under an argon atmosphere. This method involves applying a voltage using a power supply to form plasma near the substrate and modify its surface. Note that nitrogen, helium, oxygen, etc. may be used instead of an argon atmosphere. (Reverse sputtering) When the cleaning is performed, powdery substances (particles, dust) adhering to the surface of the oxide insulating layer 436 are removed. It can remove (also known as).

[0077] For planarization, polishing, dry etching, and plasma treatment can be performed multiple times. Furthermore, these can be combined. Also, when combining them, the order of the steps is not particularly limited. It is not fixed and should be set appropriately according to the uneven surface condition of the oxide insulating layer 436.

[0078] Furthermore, the oxide semiconductor layer 403 is formed under conditions that contain a large amount of oxygen (for example, oxygen The film is deposited by sputtering in a 100% atmosphere, and the oxygen content is high. Contains (preferably oxygen content relative to the stoichiometric composition ratio of the oxide semiconductor in the crystalline state) It is preferable to use a membrane that contains regions with an excessive amount of film.

[0079] In this embodiment, the oxide semiconductor layer 403 is fabricated by sputtering. The target composition ratio is In:Ga:Zn = 3:1:2 [atomic percentages]. An In-Ga-Zn oxide film (IGZO film) is formed using an oxide target.

[0080] Furthermore, the relative density (filling rate) of the metal oxide target is preferably 90% to 100%. The percentage is between 95% and 99.9%. Use a metal oxide target with a high relative density. As a result, the deposited oxide semiconductor film can be made into a dense film.

[0081] The sputtering gas used when depositing the oxide semiconductor layer 403 is hydrogen, water, hydroxyl group or It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0082] The substrate is held in a deposition chamber under reduced pressure. Then, any residual moisture in the deposition chamber is removed. Sputtered gas from which hydrogen and moisture have been removed is introduced, and the substrate 40 is cut using the target described above. An oxide semiconductor layer 403 is deposited on the 0. In order to remove residual moisture in the deposition chamber, adsorption Vacuum pumps of various types, such as cryopumps, ion pumps, and titanium sublimation pumps. It is preferable to use a turbo molecular pump. Furthermore, as an exhaust means, a cold turbo is used with a turbo molecular pump. A pump may be added. The deposition chamber, which has been evacuated using a cryopump, for example, Hydrogen atoms, water (H2O), and other compounds containing hydrogen atoms (more preferably compounds containing carbon atoms) Because substances such as [unclear material] are exhausted, impurities are contained in the oxide semiconductor layer 403 deposited in the deposition chamber. It can reduce the concentration of substances.

[0083] Furthermore, the oxide insulating layer 436 and the oxide semiconductor layer 403 are formed continuously without being exposed to the atmosphere. It is preferable to connect the oxide insulating layer 436 and the oxide semiconductor layer 403 without exposing them to the atmosphere. If formed subsequently, impurities such as hydrogen and moisture will be adsorbed onto the surface of the oxide insulating layer 436. It can be prevented.

[0084] The oxide semiconductor layer 403 is formed by a photolithography process on a film-like oxide semiconductor film into island-like structures. It can be formed by processing an oxide semiconductor layer.

[0085] Furthermore, a resist mask for forming island-shaped oxide semiconductor layers 403 is prepared by an inkjet method. It may also be formed by an inkjet method. If the resist mask is formed by an inkjet method, a photomask is used. Therefore, manufacturing costs can be reduced.

[0086] Note that etching of oxide semiconductor films can be done by either dry etching or wet etching. Both may be used. For example, the etching of oxide semiconductor films. As a quenching solution, a solution of phosphoric acid, acetic acid, and nitric acid can be used. O07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0087] Furthermore, excess hydrogen (including water and hydroxyl groups) is removed from the oxide semiconductor layer 403 (dehydration or Heat treatment may be performed to dehydrogenate the product. The heat treatment temperature should be 300°C or higher and 700°C or higher. The temperature should be below °C or below the substrate's strain point. Heat treatment should be performed under reduced pressure or in a nitrogen atmosphere. This is possible. For example, by introducing a substrate into an electric furnace, which is one of the heat treatment devices, an oxide semiconductor can be introduced. Layer 403 is subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere.

[0088] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction or heat from heat-generating elements such as resistance heating elements. A device that heats the object to be processed by radiation may also be used. For example, GRTA(Gas R apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Annealing) devices such as hermal annealing equipment al) equipment can be used. LRTA equipment uses halogen lamps, metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps This is a device that heats an object to be processed by radiating light (electromagnetic waves) from a lamp or similar light source. The GRTA device is a device that performs heat treatment using high-temperature gas. Noble gases such as argon, or nitrogen, which do not react with the material being treated by heat treatment. An active gas is used.

[0089] For example, as a heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C. Alternatively, after heating for several minutes, a GRTA (Ground Removal and Exposure) may be performed to remove the substrate from the inert gas.

[0090] In addition, during the heat treatment, water is added to nitrogen or a noble gas such as helium, neon, or argon. It is preferable that it does not contain hydrogen, etc. Alternatively, nitrogen or helium introduced into the heat treatment apparatus. The purity of noble gases such as lium, neon, and argon is preferably 6N (99.9999%) or higher. This is 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably 0.1 ppm). It is preferable that the amount be less than or equal to ppm.

[0091] Furthermore, after heating the oxide semiconductor layer 403 by heat treatment, high-purity oxygen gas is placed in the same furnace. Dinitrate gas or ultra-dry air (CRDS (cavity ring down laser) The moisture content measured using a light-based dew point meter was 20 ppm (equivalent to a dew point of -55°C). The following may be introduced: preferably air at 1 ppm or less, more preferably 10 ppb or less. It is preferable that the oxygen gas or nitrous oxide gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment apparatus should preferably be 6N or higher. The concentration is 7N or higher (i.e., the impurity concentration in oxygen gas or nitrous oxide gas is 1 ppm or less). Preferably, the concentration is 0.1 ppm or less. Through this process, impurities are simultaneously reduced by the dehydration or dehydrogenation treatment. By supplying oxygen, which is the main component material that makes up the oxide semiconductor, The semiconductor layer 403 can be made highly pure and electrically type I (intrinsic).

[0092] Furthermore, the heat treatment for dehydration or dehydrogenation is performed on the film-like acid before processing the oxide semiconductor layer 403. If the semiconductor film is formed but the insulating film 407 is not formed, the fabrication process for transistor 440a is performed. It can be done at any point in the process. For example, after the formation of a thin oxide semiconductor film, This can be done after the formation of the island-shaped oxide semiconductor layer 403.

[0093] Furthermore, the heat treatment for dehydration or dehydrogenation may be carried out multiple times, and may be combined with other heat treatments. You may sleep.

[0094] A heat treatment for dehydration or dehydrogenation is performed to process the oxide semiconductor layer 403 into island-like structures. Previously, when the thin oxide semiconductor film covers the oxide insulating layer 436, the oxide insulating layer 4 This is preferable because it prevents the oxygen contained in 36 from being released by the heat treatment. stomach.

[0095] Furthermore, in the oxide semiconductor layer that has undergone dehydration or dehydrogenation treatment, oxygen (at least oxygen radio) You can supply oxygen into the membrane by introducing (containing either CAL, oxygen atoms, or oxygen ions). stomach.

[0096] Oxygen is introduced into the oxide semiconductor layer 403 that has undergone dehydration or dehydrogenation treatment, thereby creating oxygen in the film. By supplying this material, the oxide semiconductor layer 403 is made highly pure and electrically type I (intrinsic). It is possible to have a highly purified and electrically type I (intrinsic) oxide semiconductor layer 403. Transistors that exhibit this characteristic have suppressed fluctuations in their electrical properties and are electrically stable.

[0097] Methods for introducing oxygen include ion implantation, ion doping, and plasma immersion. On-plantation methods, plasma treatment, and other similar techniques can be used.

[0098] The oxygen introduction process is performed when introducing oxygen into the oxide semiconductor layer 403. It can be introduced directly, or it can pass through other films such as the gate insulating film 402 or insulating film 407 before oxidation. It may also be introduced into the semiconductor layer 403. If oxygen is introduced by passing it through another film, ion injection may be used. Methods such as implantation, ion doping, and plasma immersion ion implantation. It is fine to use it, but if oxygen is directly introduced into the exposed oxide semiconductor layer 403, Processing methods such as M processing can also be used.

[0099] The introduction of oxygen into the oxide semiconductor layer 403 is permitted only after dehydration or dehydrogenation treatment. Furthermore, the oxide semiconductor layer 40 that has undergone the above-mentioned dehydration or dehydrogenation treatment The introduction of oxygen into the third system may be performed multiple times.

[0100] Next, on the oxide semiconductor layer 403, a source electrode layer and a drain electrode layer (in the same layer) A conductive film is formed (including the wiring that will be formed). The conductive film is able to withstand subsequent heat treatment. Materials are used. Examples of conductive films used for the source electrode layer and drain electrode layer include A A metal film containing an element selected from l, Cr, Cu, Ta, Ti, Mo, W, or the above Metal nitride films containing elements (titanium nitride film, molybdenum nitride film, tungsten nitride film) ) etc. can be used. Also, either the lower or upper side of a metal film such as Al or Cu or Both surfaces have high-melting-point metal films such as Ti, Mo, and W, or metal nitride films of those metals (titanium nitride film, A configuration in which molybdenum nitride film and tungsten nitride film are stacked is also possible. The conductive film used for the electrode layer and the drain electrode layer may be formed from a conductive metal oxide. Good. Examples of conductive metal oxides include indium oxide (In2O3) and tin oxide (SnO2). ), zinc oxide (ZnO), indium tin oxide (In2O3-SnO2), indium oxide Zium zinc oxide (In2O3-ZnO) or silicon oxide in these metal oxide materials It can be used if it contains something.

[0101] A resist mask is formed on a conductive film using a photolithography process, and then selectively etched. After performing the following steps to form the source electrode layer 405a and drain electrode layer 405b, a resist mask is then applied. Remove.

[0102] The source, oxide semiconductor layer 403, source electrode layer 405a, and drain electrode layer 405b are A covering gate insulating film 402 is formed (see Figure 1(C)).

[0103] Furthermore, in order to improve the coverage of the gate insulating film 402, an oxide semiconductor layer 403 and a source The planarization treatment may also be performed on the surfaces of the electrode layer 405a and the drain electrode layer 405b. In particular, when a thin insulating film is used as the gate insulating film 402, the oxide semiconductor layer 403, It is preferable that the surface flatness of the source electrode layer 405a and the drain electrode layer 405b is good. It seems so.

[0104] The thickness of the gate insulating film 402 shall be between 1 nm and 20 nm, and the method of sputtering or MBE shall be used. Methods such as CVD, pulsed laser deposition, and ALD can be used as appropriate. The insulating film 402 has multiple substrate surfaces arranged approximately perpendicular to the sputtering target surface. The film may also be deposited using a sputtering apparatus that performs film deposition while the film is in its assembled state.

[0105] The materials for the gate insulating film 402 include silicon oxide film, gallium oxide film, and aluminum oxide. Aluminum film, silicon nitride film, silicon oxide nitride film, aluminum oxide nitride film, or silicon nitride oxide film It can be formed using a silicon film. The gate insulating film 402 is an oxide semiconductor layer 40 It is preferable that oxygen is contained in the portion in contact with 3. In particular, the gate insulating film 402 has, in the film (in the bulk), it is preferable that oxygen is present in an amount that exceeds at least the stoichiometric composition ratio , for example, when a silicon oxide film is used as the gate insulating film 402, SiO 2+α (where α>0). In the present embodiment, as the gate insulating film 402, SiO 2+ α (where α>0) is used as the silicon oxide film. By using this silicon oxide film as the gate insulating film 402, oxygen can be supplied to the oxide semiconductor layer 403, and characteristics can be improved. Furthermore, the gate insulating film 402 is preferably formed in consideration of the size of the transistor to be manufactured and the step coverage of the gate insulating film 402.

[0106] Further, as a material for the gate insulating film 402, hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-added hafnium silicate (HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), lanthanum oxide and other high-k materials can be used to reduce gate leakage current. Furthermore, the gate insulating film 402 may have a single-layer structure or a stacked structure.

[0107] Then, the gate electrode layer 401 is formed on the gate insulating film 402 by plasma CVD, sputtering, or the like (see FIG. 1(B)). A material for the gate electrode layer 401 is molybdenum ​Titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, Scandinavian It can be formed using metallic materials such as um, or alloy materials mainly composed of these materials. Furthermore, a polycrystalline silicon film doped with impurity elements such as phosphorus is used as the gate electrode layer 401. Semiconductor films such as those represented by [specific example], or silicide films such as nickel silicide may be used. Gate The electrode layer 401 may have a single-layer structure or a multi-layer structure.

[0108] Furthermore, the material of the gate electrode layer 401 is indium tin oxide, tungsten oxide, and other indium oxides. Indium zinc oxide containing zinc oxide, tungsten oxide, and titanium oxide Indium oxide, titanium oxide-containing indium tin oxide, indium zinc oxide, silicon oxide Conductive materials such as indium tin oxide with added ions can also be applied. A laminated structure of an electrolytic material and the above-mentioned metallic material can also be used.

[0109] Furthermore, a nitrogen-containing metal acid is used as one layer of the gate electrode layer 401 that is in contact with the gate insulating film 402. These are phosphates, specifically In-Ga-Zn-O films containing nitrogen, and In-Sn-O films containing nitrogen. or nitrogen-containing In-Ga-O film, nitrogen-containing In-Zn-O film, nitrogen-containing Sn- O films, nitrogen-containing In-O films, and metal nitride films (InN, SnN, etc.) can be used. These films can be exposed to 5 eV (electron volts), preferably 5.5 eV (electron volts) or higher. It has a work function, and when used as a gate electrode layer, the threshold voltage of the transistor's electrical characteristics This allows for a positive voltage, enabling the realization of a so-called normally-off switching element.

[0110] Next, the gate electrode layer 401, source electrode layer 405a, and drain electrode layer 405b are mass As a result, a dopant 421 is introduced into the oxide semiconductor layer 403, and low-resistance regions 404a, 40 Forms 4b.

[0111] The film thickness of the source electrode layer 405a and the drain electrode layer 405b, and the introduction of the dopant 421. Depending on the conditions, the oxide semiconductor beneath the source electrode layer 405a and the drain electrode layer 405b may In layer 403, dopant 421 may or may not be introduced, and if it is introduced... Even if the concentration is low, the low-resistance region is located outside of the source electrode layer 405a or the drain electrode layer 405b. In some cases, this region may have higher resistance compared to the surrounding areas.

[0112] The transistor 440c shown in Figure 2(B) has a source electrode layer 405a and a drain electrode layer 40 As 5b, a thin tungsten film, for example, 10 nm thick, is formed. If the film thickness of the electrode layer 405a and the drain electrode layer 405b is thin, in order to form a low-resistance region When introducing a dopant into the oxide semiconductor layer 403, the source electrode layer 405a and the drain electrode The oxide semiconductor passes through the polar layer 405b and is located below the source electrode layer 405a and drain electrode layer 405b. A dopant can also be introduced into layer 403. Therefore, transistor 440c is The region of the oxide semiconductor layer 403 beneath the electrode layer 405a and drain electrode layer 405b also has low resistance. Regions 404a and 404b are formed.

[0113] Dopant 421 is an impurity that alters the conductivity of the oxide semiconductor layer 403. As for element 421, it is a group 15 element (typically phosphorus (P), arsenic (As), and antimicrobial compounds). Mon (Sb), Boron (B), Aluminum (Al), Nitrogen (N), Argon (Ar) Helium (He), Neon (Ne), Indium (In), Fluorine (F), Chlorine (Cl) ), titanium (Ti), and zinc (Zn) may be selected as one or more of the above. can.

[0114] Dopant 421 is injected into other films (e.g., insulating film 407, source electrode layer 405) by injection. It can also be introduced into the oxide semiconductor layer 403 by passing through (a) and the drain electrode layer 405b). Yes, it is possible. Methods for introducing dopant 421 include ion implantation, ion doping, and Methods such as raspmymerization ion implantation can be used. It is preferable to use the elemental ion of dopant 421 or the ions of its fluoride or chloride. It's nice.

[0115] The introduction process for dopant 421 involves injection conditions such as acceleration voltage and dose, as well as the membrane through which it passes. The film thickness can be appropriately set and controlled. In this embodiment, the dopant 421 is bo Using a dopant, boron ions are implanted by ion implantation. The quantity is 1 x 10 13 ions / cm 2 The above 5 x 10 16 ions / cm 2 If you do the following: stomach.

[0116] The concentration of dopant 421 in the low-resistance region is 5 × 10⁻⁶. 18 / cm 3 The above 1 x 10 22 / cm 3 The following is preferable:

[0117] When introducing dopant 421, the substrate 400 may be heated during the process.

[0118] The process of introducing the dopant 421 into the oxide semiconductor layer 403 may be performed multiple times. Multiple types of Dopants may be used.

[0119] Furthermore, after the introduction of dopant 421, heat treatment may be performed. The heating conditions are as follows: 300°C to 700°C, preferably 300°C to 450°C for 1 hour in an oxygen atmosphere It is preferable to carry out the process under gaseous conditions. Alternatively, heating can be performed under a nitrogen atmosphere, under reduced pressure, or under atmospheric (ultra-dry) air. You may proceed with the processing.

[0120] When the oxide semiconductor layer 403 is a crystalline oxide semiconductor film, the introduction of the dopant 421 In some cases, partial amorphous formation may occur. In this case, heat treatment should be performed after the introduction of dopant 421. By doing so, the crystallinity of the oxide semiconductor layer 403 can be restored.

[0121] Therefore, in the oxide semiconductor layer 403, the low-resistance region 40 is separated by the channel formation region 409. An oxide semiconductor layer 403 is formed, with 4a and 404b provided therein.

[0122] The transistor 440a of this embodiment is fabricated through the above process (see Figure 1(C)). It contains at least four elements: indium, gallium, zinc, and oxygen, and the composition ratio of these four elements is When expressed as atomic percentages, the proportion of indium is twice that of gallium and zinc. By using the oxide semiconductor layer 403 made of the IGZO film shown above, a transistor To provide 440A with high on-response characteristics (field-effect mobility), low off-current, and high reliability. This becomes possible.

[0123] source, oxide semiconductor layer 403, source electrode layer 405a, drain electrode layer 405b, g An insulating film 402 and an insulating film 407 are formed on the gate electrode layer 401 (see Figure 1(D)).

[0124] The insulating film 407 is deposited by plasma CVD, sputtering, or vapor deposition. This is possible. The insulating film 407 is typically a silicon oxide film, a silicon oxide nitride film, or a silicon oxide film. An aluminum oxide film or an inorganic insulating film such as a gallium oxide film can be used.

[0125] Furthermore, the insulating film 407 can be an aluminum oxide film, a hafnium oxide film, or magnesium oxide. A film, zirconium oxide film, lanthanum oxide film, barium oxide film), or metal nitride film (for example) Alternatively, an aluminum nitride film can also be used.

[0126] The insulating film 407 may be a single layer or a multilayer, for example, a silicon oxide film and an aluminum oxide film. Lamination can be used.

[0127] The insulating film 407 is made by methods such as sputtering, which introduces impurities such as water and hydrogen into the insulating film 407. It is preferable to form it using an appropriate method. Also, in the insulating film 407, the oxide semi If the insulating film in contact with the conductive layer 403 is a film containing an excess of oxygen, then to the oxide semiconductor layer 403 It is preferable as it serves as a source of oxygen.

[0128] In this embodiment, a silicon oxide film with a thickness of 100 nm is used as the insulating film 407, and sputtering The film is deposited using the sputtering method. The deposition of silicon oxide films by sputtering is performed using a rare gas (substitute). In general, under an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen... It can be done by doing so.

[0129] Similar to the deposition of oxide semiconductor films, in order to remove residual moisture in the deposition chamber of the insulating film 407 It is preferable to use an adsorption-type vacuum pump (such as a cryopump). The impurity concentration in the insulating film 407 formed in the deposition chamber evacuated by using a cryopump can be reduced. In addition, as an evacuation unit for removing residual moisture in the deposition chamber for the insulating film 407, a molecular pump combined with a cold trap may be used.

[0130] As a sputtering gas used for depositing the insulating film 407, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups or hydrides have been removed.

[0131] An aluminum oxide film that can be used as the insulating film 407 provided over the oxide semiconductor layer 403 has a high blocking effect (blocking effect) that prevents both impurities such as hydrogen and moisture and oxygen from passing through the film.

[0132] Therefore, the aluminum oxide film functions as a protective film that prevents hydrogen, which is a fluctuation factor during and after the manufacturing process, impurities such as moisture from entering the oxide semiconductor layer 403, and prevents oxygen, which is a main component material of the oxide semiconductor, from being released from the oxide semiconductor layer 403.

[0133] Alternatively, a planarization insulating film may be formed to reduce surface unevenness caused by the transistor. For the planarization insulating film, an organic material such as polyimide, acrylic, benzocyclobutene-based resin, or the like can be used. In addition to the above organic materials, a low dielectric constant material (low-k material) or the like can also be used. Note that the planarization insulating film may be formed by stacking a plurality of insulating films formed from these materials. The planarization insulating film may be formed in this way.

[0134] Furthermore, the gate insulating film 402 and insulating film 407 are connected to the source electrode layer 405a and the drain electrode layer 4 An opening is formed that reaches 05b, and the source electrode layer 405a and the drain electrode layer 405b are formed in the opening. Electrically connected wiring layers 465a and 465b are formed (see Figure 1(E)). Wiring layer 46 By using 5a and 465b to connect with other transistors, various circuits can be constructed. ru.

[0135] Furthermore, as shown in Figure 2(C), the source electrode layer 405a, the drain Without providing the electrode layer 405b, the wiring layers 465a and 465b are directly connected to the oxide semiconductor layer 403. They may be installed so as to be in contact with each other.

[0136] Wiring layer 465a and wiring layer 465b are gate electrode layer 401 and source electrode layers 405a and 405 It can be formed using the same materials and methods as in b. For example, wiring layer 465a, wiring Layer 465b consists of a lamination of a tantalum nitride film and a copper film, or a tantalum nitride film and a tungsten film. Lamination and other techniques can be used.

[0137] The oxide semiconductor layer 403, which has been purified and oxygen deficiencies have been filled, contains impurities such as hydrogen and water. It has been sufficiently removed, and the hydrogen concentration in the oxide semiconductor layer 403 is 5 × 10⁻⁶ 19 / cm 3 below Preferably 5 × 10 18 / cm 3 The following applies. Note that the hydrogen concentration in the oxide semiconductor layer 403 Secondary ion mass spectrometry (SIMS) It is measured using ectrometry.

[0138] Using this embodiment, an oxidation product was prepared that is highly purified and contains an excess of oxygen to compensate for oxygen deficiency. The transistor 440a, which uses a monocrystalline semiconductor layer 403, has an off-current value (off current) in the off state. The value is 100 zA / μm (1 zA (zeptoampere)) per 1 μm channel width at room temperature. is 1 x 10 -21 A) Preferably, the level should be reduced to 50 zA / μm or less. can.

[0139] As described above, the electrical characteristics of a transistor using an oxide semiconductor as the channel formation region This allows a positive voltage to be applied, realizing a so-called normally-off switching element. A transistor structure and a method for manufacturing the same can be provided.

[0140] Furthermore, in order to realize a higher-performance semiconductor device, the on-characteristics of the transistor (for example, on A configuration that improves current and field-effect mobility to achieve high-speed response and high-speed drive of semiconductor devices. We can also provide a method for producing the same.

[0141] Furthermore, the threshold voltage remains stable even during long-term use, making it a highly reliable semiconductor device. We can provide this.

[0142] (Embodiment 2) In this embodiment, another form of semiconductor device and method for manufacturing a semiconductor device is shown in Figures 3 and 4. This will be explained using [the following]. The same parts as or having similar functions as in the above embodiment, and the process are [the same parts as or similar functions as in the above embodiment]. This can be done in the same manner as in the above embodiment, and repeated explanations will be omitted. Also, the same part Detailed explanations will be omitted.

[0143] The transistor 450 shown in Figures 3(A) to (C) is a top-gate structure transistor. This is just one example. Figure 3(A) is a plan view, and the cross section is cut along the dashed line XY in Figure 3(A). corresponds to FIG. 3(B), and a cross-section taken along the dashed-dotted line V-W in FIG. 3(A) corresponds to FIG. 3(C).

[0144] As shown in FIG. 3(B), which is a cross-sectional view in the channel length direction, the transistor 450 includes an oxide over a substrate 400 having an insulating surface provided with an insulating layer 436, a first oxide semiconductor layer : oxide semiconductor layers 408a and 408b, a channel formation region 409, low-resistance regions 414a, an oxide semiconductor layer 403 which is a second oxide semiconductor layer including 414b, a source electrode layer 405 a, a drain electrode layer 405b, a gate insulating film 402, and a gate electrode layer 401. The oxide semiconductor layers 408a and 408b are formed in contact with and spaced apart from each other over the oxide insulating layer 436 , and the oxide semiconductor layer 403 is formed in contact with the oxide semiconductor layers 408a, 408b and the oxide insulating layer 436 .

[0145] FIG. 3(C) is a cross-sectional view in the channel width direction, and the oxide semiconductor layer 403 has a taper of 20° to 50° at an end portion thereof. If the end portion is vertical, oxygen is easily released and oxygen vacancies are likely to be generated however, providing a taper at the end portion suppresses oxygen vacancies and reduces leakage of the transistor 450 current (parasitic channel) generation.

[0146] By providing the oxide semiconductor layers 408a and 408b under the oxide semiconductor layer 403 having a thickness of 3 to 5 nm , contact resistance with the source electrode layer 405a and the drain electrode layer 405b can be reduced .

[0147] The low-resistance regions 414a and 414b can be formed by introducing a dopant into the oxide semiconductor layer 40 3 using the gate electrode layer 401 as a mask. Further, the low-resistance regions contain a metal element It can also be formed by diffusion. Using the diffusion of dopants and metal elements. By forming a low-resistance region, the contact resistance with the wiring layer can be further reduced. ru.

[0148] Furthermore, a sidewall insulating layer with a sidewall structure may be provided on the side surface of the gate electrode layer 401. The transistor 450 has thin sidewall insulating layers 412a and 41 on the side of the gate electrode layer 401. 2b is provided. The side wall insulating layers 412a and 412b cover the gate electrode layer 401. After forming the border film, this is then subjected to RIE (Reactive Ion Etching). The insulating film is fabricated by anisotropic etching using the ion etching method, and the gate electrode layer is formed. Self-aligned sidewall insulating layers 412a and 412b of the sidewall structure are formed on the sidewall of 401. This is sufficient. There are no particular limitations on the insulating film, but for example, TEOS (Tetra Ethyl-Ortho-Silicate) or silane, etc., and oxygen or sub-oxide Silicon oxide with good step-covering properties, formed by reacting with nitrogen or the like, can be used. The edge film was created using thermal CVD, plasma CVD, atmospheric pressure CVD, bias ECRCVD, and sputtering. It can be formed by methods such as those listed above. Also, low-temperature oxidation (LTO: Low Tempo Silicon oxide formed by the (ratio oxidation) method may also be used.

[0149] By providing side wall insulating layers 412a and 412b, the gate electrode layer 401 and the low-resistance region 404 a, this prevents a short circuit with 404b.

[0150] If a dopant is introduced throughout the oxide semiconductor layers 408a and 408b to create a low-resistance region, Electrical contact with other conductive layers is also made from the oxide insulating layer 436 side beneath the oxide semiconductor layers 408a and 408b. You can continue.

[0151] The oxide semiconductor layer 403 contains at least four elements: indium, gallium, zinc, and oxygen. Furthermore, when the composition ratio of these four elements is expressed as atomic percentages, the proportion of indium is equal to the proportion of gallium. And using an IGZO film with a high field-effect mobility, where the zinc content is more than twice, the film thickness is 3~ By keeping the thickness down to 5nm, the transistor normalization due to the short channel effect is reduced. - This can prevent it from turning on.

[0152] The oxide semiconductor layers 408a and 408b are indium oxide, tin oxide, zinc oxide, and dioxide. In-Zn oxides, Sn-Zn oxides, and Al-Zn oxides are oxides of the original metals. Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides In-Ga-Zn oxides (also written as IGZO), which are oxides of ternary metals, -Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al- Ga-Zn oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-L α-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd -Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd- Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Z n-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn In-Lu-Zn ​​oxides, In-Sn-Ga-Z oxides (quaternary metal oxides) n-based oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In -Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Z n-based oxides can be used.

[0153] The oxide semiconductor layers 408a and 408b are indium oxide, tin oxide, and zinc oxide, respectively. A highly conductive oxide semiconductor layer may also be used.

[0154] In this embodiment, the oxide semiconductor layers 408a and 408b are indium:gallium: An oxide semiconductor layer fabricated using an oxide target with a zinc composition ratio of 1:1:1 is used.

[0155] The film thickness of the oxide semiconductor layers 408a and 408b should be 20 to 50 nm.

[0156] An example of a method for fabricating transistor 450 is shown in Figures 4(A) to (E).

[0157] First, an oxide insulating layer 436 is formed on a substrate 400 having an insulating surface, and then an oxide insulating layer 43 An oxide semiconductor film 444 is formed on 6 (see Figure 4(A)). In this embodiment, an oxide semiconductor film is formed. The conductive film 444 is an oxide target with an indium:gallium:zinc composition ratio of 1:1:1. It is formed using the sputtering method.

[0158] Next, the oxide semiconductor film 444 is processed into an island shape by a photolithography process, and a pair of intervals Oxide semiconductor layers 408a and 408b are formed having the following. An oxide semiconductor layer 403 is formed in contact with 8a, 408b and the oxide insulating layer 436 (Figure 4). (See (B)). The oxide semiconductor layer 403 has an indium:gallium:zinc composition ratio of 3:1 Oxide semiconductor layer 40 is formed by sputtering using an oxide target of :2. The end of part 3 preferably has a tapered shape, and in this embodiment it has a 30-degree taper. It will be shaped like this.

[0159] Next, a gate insulating film 402, a gate electrode layer 401, and a gate electrode layer are placed on the oxide semiconductor layer 403. Sidewall insulating layers 412a and 412b are formed to cover the sides of the pole layer 401 (see Figure 4(C)). The gate insulating film 402 is formed on the oxide semiconductor layer 403, and the insulating film is used as the gate electrode. Formed by etching using layer 401 and side wall insulating layers 412a and 412b as masks. This is possible. However, a portion of the oxide semiconductor layer 403 will be exposed.

[0160] source, oxide semiconductor layer 403, source electrode layer 405a, drain electrode layer 405b, g A metal insulating film 402 is placed on the gate electrode layer 401, in contact with a portion of the oxide semiconductor layer 403. A film 417 containing the element is formed (see Figure 1(C)).

[0161] Examples of films 417 containing metal elements include metal films, metal oxide films, and metal nitride films. .

[0162] Examples of metallic elements in films containing metallic elements include aluminum (Al), titanium (Ti), and molybdenum. Butene (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthium N (La), barium (Ba), magnesium (Mg), zirconium (Zr), and ni One or more elements selected from Ni (Ni) can be used. As a film, a metal film, a metal oxide film, containing one or more of the above metal elements, Alternatively, a metal nitride film (for example, titanium nitride film, molybdenum nitride film, tungsten nitride film) It can be used. Also, doping of phosphorus (P), boron (B), etc. in a film containing a metal element. It may contain a component. In this embodiment, the film 417 containing the metal element is conductive. .

[0163] The film 417 containing the metal element is produced by plasma CVD, sputtering, or vapor deposition, etc. A thin film can be formed. The thickness of the film 417 containing the metal element is 5 nm or more and 30 nm or less. Yes.

[0164] In this embodiment, an aluminum film with a thickness of 10 nm is used as the film 417 containing a metal element. It is formed by the tarling method.

[0165] Next, the gate insulating film 402, gate electrode layer 401, and side wall insulating layers 412a and 412b are As a mask, the dopant 4 passes through the oxide semiconductor layer 403 via a film 417 containing a metal element. By selectively introducing 21, a low-resistance region is formed (see Figure 4(D)).

[0166] Dopant 421 is an impurity that alters the conductivity of the oxide semiconductor layer 403. As for element 421, it is a group 15 element (typically phosphorus (P), arsenic (As), and antimicrobial compounds). Mon (Sb), Boron (B), Aluminum (Al), Nitrogen (N), Argon (Ar) Helium (He), Neon (Ne), Indium (In), Fluorine (F), Chlorine (Cl) ), titanium (Ti), and zinc (Zn) may be selected as one or more of the above. can.

[0167] The above dopant may be included in a film 417 containing a metal element.

[0168] Dopant 421 is injected by the injection method, passing through the metal element-containing film 417 into the oxide semiconductor. It is introduced into layer 403. The method for introducing dopant 421 is ion implantation, ion dopant Methods such as the PING method and plasma immersion ion implantation method can be used. In that case, the elemental ions, hydrides, fluorides, and chlorides of dopant 421 are used. It is preferable to use ions of the following type.

[0169] The introduction process for dopant 421 involves injection conditions such as acceleration voltage and dose amount, as well as the gold that passes through. The thickness of the film 417 containing the group element can be appropriately set and controlled. For example, using boron, When implanting boron ions using the ion implantation method, the acceleration voltage is 15kV and the dose is 1 × 10⁻¹⁶. 15 ions / cm 2 This is how you should do it. The dose is 1 × 10 13 ions / cm 2 The above 5x 10 16 ions / cm 2 The following is correct.

[0170] The concentration of dopant 421 in the low-resistance region is 5 × 10⁻⁶. 18 / cm 3 The above 1 x 10 22 / cm 3 The following is preferable:

[0171] When introducing the dopant, the substrate 400 may be heated during the process.

[0172] The process of introducing the dopant 421 into the oxide semiconductor layer 403 may be performed multiple times. Multiple types of Dopants may be used.

[0173] Furthermore, after the introduction of dopant 421, heat treatment may be performed. The heating conditions are as follows: 300°C to 700°C, preferably 300°C to 450°C for 1 hour in an oxygen atmosphere It is preferable to carry out the process under gaseous conditions. Alternatively, heating can be performed under a nitrogen atmosphere, under reduced pressure, or under atmospheric (ultra-dry) air. You may proceed with the processing.

[0174] Next, a heat treatment is performed with the metal element-containing film 417 and a portion of the oxide semiconductor layer 403 in contact. The heat treatment is preferably carried out under an oxygen atmosphere. The heat treatment is carried out under reduced pressure and in a nitrogen atmosphere. It can also be done below. Furthermore, the heating temperature should be between 100°C and 700°C, preferably 200°C. The temperature should be between ℃ and 400℃.

[0175] For example, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and a film 417 containing a metal element and The oxide semiconductor layer 403 is subjected to a heat treatment at 200°C for 1 hour under an oxygen atmosphere.

[0176] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction or heat from heat-generating elements such as resistance heating elements. A device that heats the object to be processed by radiation may also be used. For example, GRTA(Gas R apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Annealing) devices such as hermal annealing equipment al) equipment can be used. LRTA equipment uses halogen lamps, metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps This is a device that heats an object to be processed by radiating light (electromagnetic waves) from a lamp or similar light source. The GRTA device is a device that performs heat treatment using high-temperature gas. Noble gases such as argon, or nitrogen, which do not react with the material being treated by heat treatment. An active gas is used.

[0177] For example, as a heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C. Alternatively, after heating for several minutes, a GRTA (Ground Removal and Exposure) may be performed to remove the substrate from the inert gas.

[0178] The heat treatment involves nitrogen, oxygen, and ultra-dry air (with a water content of 20 ppm or less, preferably 1 ppm). Air (m or less, preferably 10 ppb or less), or a noble gas (argon, helium, etc.) It is fine to do this in the atmosphere described above, but water in an atmosphere of nitrogen, oxygen, ultra-dry air, or noble gas. It is preferable that it does not contain hydrogen, etc. Also, nitrogen, oxygen, etc. are introduced into the heat treatment device. Alternatively, the purity of the rare gas should be 6N (99.9999%) or higher, preferably 7N (99.99999%). The impurity concentration must be 1 ppm or less, preferably 0.1 ppm or less. preferable.

[0179] Through heat treatment, the metal element is introduced from the film 417 containing the metal element into the oxide semiconductor layer 403. Thus, low-resistance regions 414a and 414b are formed in the oxide semiconductor layer 403. , with the channel-forming region 409 in between, a low-resistance region 414a containing the dopant and a metal element. , 414b is formed.

[0180] In this embodiment, boron was used as the dopant and aluminum as the metallic element. The low-resistance regions 414a and 414b contain boron and aluminum.

[0181] Next, the film 417 containing the metal element is removed by etching. In this embodiment, wet etching The film 417 containing metal elements is removed by the scratching method.

[0182] The transistor 450 of this embodiment is manufactured through the above process. Oxide semiconductor layer 403 containing low-resistance regions 414a and 414b, flanked by a flannel-forming region 409. By having this, the transistor 450 has on-characteristics (e.g., on-current and field effect). High mobility enables fast operation and fast response.

[0183] The low-resistance regions 414a and 414b can function as either the source region or the drain region. Yes, it is possible. By providing low-resistance regions 414a and 414b, the low-resistance regions 414a and 4 The electric field applied to the channel formation region 409 formed between 14b can be mitigated. Furthermore, in the low-resistance regions 414a and 414b, the oxide semiconductor layer 403 and the source electrode layer 4 By electrically connecting 05a and the drain electrode layer 405b, the oxide semiconductor To reduce the contact resistance between layer 403 and the source electrode layer 405a and drain electrode layer 405b. It is possible.

[0184] Furthermore, a planarizing insulating film may be formed to reduce surface irregularities caused by transistors. Organic materials such as polyimide, acrylic, and benzocyclobutene resins can be used as tanning insulators. In addition to the above organic materials, low dielectric constant materials (low-k materials), etc. can be used. It can be used. Furthermore, by stacking multiple insulating films formed from these materials, A planar insulating film may be formed.

[0185] In this embodiment, a planar insulating film 415 is formed on the transistor 450. An opening is formed in the insulating film 415 that reaches the oxide semiconductor layer 403, and the oxide semiconductor layer 40 A source electrode layer 405a and a drain electrode layer 405b are formed that are electrically connected to 3 (Figure 4). (See (E)).

[0186] As described above, the electrical characteristics of a transistor using an oxide semiconductor as the channel formation region This allows a positive voltage to be applied, realizing a so-called normally-off switching element. A transistor structure and a method for manufacturing the same can be provided.

[0187] Furthermore, in order to realize a higher-performance semiconductor device, the on-characteristics of the transistor (for example, on A configuration that improves current and field-effect mobility to achieve high-speed response and high-speed drive of semiconductor devices. We can also provide a method for producing the same.

[0188] Furthermore, the threshold voltage is less likely to shift even during long-term use, making it a highly reliable semiconductor device. We can provide a place for you.

[0189] This embodiment can be implemented in appropriate combination with other embodiments.

[0190] (Embodiment 3) In this embodiment, the transistor shown in Embodiment 1 or Embodiment 2 is used, and the power is Semiconductors can retain stored data even when power is unavailable, and have no limitations on the number of write cycles. An example of a device will be described using the drawings. Note that the semiconductor device of this embodiment is a transient The transistor described in Embodiment 1 or Embodiment 2 is used as st162. The transistor 162 is one of the transistors shown in Embodiment 1 or 2. The following structure can also be applied.

[0191] Transistor 162 has a low off-current, so by using it, it can be used for long-term recording. It is possible to retain the stored content. In other words, it does not require a refresh operation, or This makes it possible to create a semiconductor memory device with an extremely low refresh frequency, Power consumption can be significantly reduced.

[0192] Figure 5 shows an example of a semiconductor device configuration. Figure 5(A) shows a cross-sectional view of the semiconductor device, and Figure 5( Figure B) shows a plan view of the semiconductor device, and Figure 5(C) shows a circuit diagram of the semiconductor device. Figure 5(A) corresponds to the cross-sections at C1-C2 and D1-D2 in Figure 5(B).

[0193] The semiconductor device shown in Figures 5(A) and 5(B) has a transistor made of the first semiconductor material at the bottom. A device having a zista 160 and a transistor 162 on top of which is made of a second semiconductor material. The transistor 162 has the same configuration as shown in Embodiment 1 or Embodiment 2. It can be considered a success.

[0194] Here, the first semiconductor material and the second semiconductor material are materials with different band gaps. Desirable. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistor used is easy to operate at high speed. On the other hand, the transistor using oxide semiconductors Due to its properties, the sta allows for long-term charge retention.

[0195] The above explanation assumes that all transistors are n-channel transistors. However, it goes without saying that p-channel transistors can be used. The technical essence of the invention is to use an oxide semiconductor in transistor 162 to hold information. Since it is about the point of use, semiconductor devices include materials used in semiconductor devices and the structure of semiconductor devices. The specific configuration shown here does not need to be limited to what is presented here.

[0196] The transistor 160 in Figure 5(A) includes a semiconductor material (e.g., silicon). A channel formation region 116 provided on the substrate 185, and sandwiching the channel formation region 116 An impurity region 120 is provided therein, and a metal compound region 124 is in contact with the impurity region 120, A gate insulating layer 108 provided on the channel forming region 116, and on the gate insulating layer 108 It has a gate electrode 110 provided, and. Note that in the figure, the source electrode and Although it may not have a drain electrode, for convenience, we will include this state in the definition of a transistor. It may be called that. Also, in this case, in order to explain the connection relationship of the transistor, the source region The source electrode and drain electrode are sometimes referred to as including the region and drain region. In the specification, the term "source electrode" may include the source region.

[0197] An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 160. Furthermore, an insulating layer 130 is provided so as to cover the transistor 160. To achieve this, as shown in Figure 5(A), transistor 160 is located on the sidewall insulating layer It is desirable to have a configuration that does not have [this]. On the other hand, in situations where the characteristics of transistor 160 are important In this case, a sidewall insulating layer is provided on the side surface of the gate electrode 110, and regions with different impurity concentrations are provided. The impurity region 120, which includes the region, may also be used.

[0198] The transistor 162 shown in Figure 5(A) is a transistor that uses an oxide semiconductor as the channel formation region. It is a transistor. Here, the oxide semiconductor layer 144 contained in the transistor 162 is high purity It is desirable that it be purified. By using highly purified oxide semiconductors, This allows us to obtain a transistor 162 with excellent off-peak characteristics.

[0199] An insulating layer 150 is provided on the transistor 162 in a single layer or multi-layer configuration. A conductive layer is present in the region that overlaps with the electrode layer 142a of the transistor 162 via the edge layer 150. A 148b is provided, and the electrode layer 142a, the insulating layer 150, and the conductive layer 148b are This forms the capacitive element 164. In other words, the electrode layer 142a of transistor 162 is The conductive layer 148b functions as one electrode of the capacitive element 164, and the conductive layer 148b functions as the other electrode of the capacitive element 164. It functions as an electrode. Furthermore, if capacitance is not required, a configuration without the capacitive element 164 is available. It is also possible to provide the capacitive element 164 separately above the transistor 162. That's good too.

[0200] An insulating layer 152 is provided on the transistor 162 and the capacitive element 164. Then, on the insulating layer 152, there is a transistor 162 and wiring for connecting other transistors. A 156 is provided. Although not shown in Figure 5(A), the wiring 156 is connected to the insulating layer 150. Electricity is transmitted through electrodes formed in openings formed in the insulating layer 152 and the gate insulating film 146, etc. It is electrically connected to the polar layer 142b. Here, the electrode is connected to at least transistor 162 It is preferable that it be provided so as to overlap with a portion of the oxide semiconductor layer 144.

[0201] In Figures 5(A) and 5(B), transistor 160 and transistor 162 are, At least a portion of it is arranged to overlap, and the source region of transistor 160 and It is preferable that the drain region and a portion of the oxide semiconductor layer 144 overlap. Furthermore, transistor 162 and capacitive element 164 are at least as efficient as transistor 160. It is also provided so as to overlap with a part of it. For example, the conductive layer 143b of the capacitive element 164 is It is provided superimposed on the gate electrode 128 of transistor 160, at least in part. By adopting a planar layout like this, the occupied area of ​​the semiconductor device can be reduced. This allows for higher integration.

[0202] Furthermore, the electrical connection between the electrode layer 142b and the wiring 156 is as follows: This can be done by direct contact, or by providing electrodes in the insulating layer between the two parts and performing the action via those electrodes. Also, there may be multiple electrodes in between.

[0203] Next, Figure 5(C) shows an example of a circuit configuration corresponding to Figures 5(A) and 5(B).

[0204] In Figure 5(C), the first wiring (1st Line) and the source power of transistor 160 The poles are electrically connected to the second line and the transistor 160. The rain electrode is electrically connected. Also, the third wire (3rd Line) and One of the source or drain electrodes of the transistor 162 is electrically connected to the fourth The wiring (4th Line) and the gate electrode of transistor 162 are electrically connected. And the gate electrode of transistor 160 and the source electrode of transistor 162 One of the electrodes or drain electrodes is electrically connected to the other electrode of the capacitive element 164, and the fifth The wiring (5th Line) and the other electrode of the capacitive element 164 are electrically connected. .

[0205] In the semiconductor device shown in Figure 5(C), the potential of the gate electrode of transistor 160 can be maintained. By taking advantage of these characteristics, it is possible to write, store, and read information as follows.

[0206] This section will explain how to write and retain information. First, the potential of the fourth wire is set to the transistor. The potential is set so that transistor 162 is ON, thereby turning on transistor 162. The potential of the third wiring is applied to the gate electrode of transistor 160 and the capacitive element 164. This is how a predetermined charge is applied to the gate electrode of transistor 160. (Input). Here, a charge that gives two different potential levels (hereinafter referred to as Low-level charge, H) Let's assume that one of the following is given (referred to as a igh-level charge). Then, the power of the fourth wiring... The voltage is set to a level where transistor 162 is in the off state, and transistor 162 is turned off. By doing so, the charge applied to the gate electrode of transistor 160 is retained. Hold).

[0207] Because the off-current of transistor 162 is extremely small, the gate electrode of transistor 160 The electric charge is retained for a long period of time.

[0208] Next, we will explain how to read the information. The first wiring is under the condition that a predetermined potential (constant potential) is applied. Then, when the appropriate potential (readout potential) is applied to the fifth wire, the gate of transistor 160 Depending on the amount of charge held in the electrode, the second wiring takes on a different potential. Generally, If transistor 160 is an n-channel type, then a high-level current is applied to the gate electrode of transistor 160. Apparent threshold V when a load is given th_HThis is the gate of transistor 160. Apparent threshold V when a low level charge is applied to the electrode th_L Lower This is for the purpose of the apparent threshold voltage, which is the voltage when transistor 160 is in the "on state". This refers to the potential of the fifth wiring necessary to achieve this. Therefore, the potential of the fifth wiring V th_H and V th_L By setting the potential V0 to the intermediate potential, the gate of transistor 160 It is possible to determine the charge applied to the electrode. For example, in writing, High-level charge If a load is applied, the potential of the fifth wiring is V0 (>V th_H ) If that's the case, then, The inverter 160 will be in the "on state". If a low-level charge is applied, The potential of the wiring in section 5 is V0( <V th_L Even in this case, transistor 160 remains in the "off state". It remains as is. Therefore, by looking at the potential of the second wire, the retained information can be read out. It is possible.

[0209] When memory cells are arranged in an array, only the information of the desired memory cell is read. It is necessary to be able to output the information. If the information is not read in this way, the state of the gate electrode Regardless, the potential at which transistor 160 is in the "off state" is V th_H Yo A small potential can be applied to the fifth wire. Alternatively, regardless of the state of the gate electrode, The potential at which the converter 160 is in the "on state," that is, V th_L A higher potential It should be supplied to the fifth wire.

[0210] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-current By applying extremely small transistors, it is possible to retain memory contents for extremely long periods of time. This is possible. In other words, the refresh operation becomes unnecessary, or the refresh operation is eliminated. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. Furthermore, in the absence of power supply (however, it is desirable that the potential be fixed), However, it is possible to retain memory content over a long period of time.

[0211] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as deterioration of the gate insulating layer do not occur at all. In other words, the semiconductor according to the disclosed invention. The device does not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory, and Reliability improves dramatically. Furthermore, the on and off states of the transistors allow information to be transmitted. Because writing is performed, high-speed operation can be easily achieved.

[0212] Furthermore, transistor 162 uses less of the four elements indium, gallium, zinc, and oxygen. Including these, when the composition ratio of the four elements is expressed as atomic percentages, the proportion of indium is equal to that of gallium. Because an oxide semiconductor layer is used in which the ratio of and the ratio of zinc are more than twice, the threshold voltage is It can be a transistor. By using this transistor, semiconductor The device can achieve high performance. Furthermore, the semiconductor device of this embodiment can be used for a long period of time. Even when using it, a transistor that is less prone to threshold voltage shift is used, so semiconductor equipment This allows for increased reliability of the device.

[0213] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0214] (Embodiment 4) In this embodiment, the transistor shown in Embodiment 1 or Embodiment 2 is used. It can retain stored data even when power is not supplied, and there is no limit to the number of write cycles. Regarding the semiconductor device, Figures 6 and 7 show a configuration different from the one shown in Embodiment 3. The explanation will be given using [this]. Note that in this embodiment, the semiconductor device is actually [this] as transistor 162. It is constructed by applying the transistor described in Embodiment 1 or Embodiment 2. As for 162, either transistor structure shown in Embodiment 1 or 2 is applicable. It is possible.

[0215] Figure 6(A) shows an example of a semiconductor device circuit configuration, and Figure 6(B) shows an example of a semiconductor device. This is a conceptual diagram. First, we will explain the semiconductor device shown in Figure 6(A), and then we will continue with Figure 6( The semiconductor device shown in B) will be described below.

[0216] In the semiconductor device shown in Figure 6(A), the bit line BL and the source electrode of transistor 162 are shown. Alternatively, it is electrically connected to the drain electrode, and the word line WL and the gate of transistor 162 The electrodes are electrically connected to the source or drain electrode of transistor 162 and the capacitive element. It is electrically connected to the first terminal of 254.

[0217] The oxide semiconductor transistor 162 has the characteristic of having an extremely low off-current. Therefore, by turning off transistor 162, the first capacitive element 254 The potential of the terminal (or the charge accumulated in the capacitive element 254) over an extremely long period of time It is possible to hold it.

[0218] Next, information is written to and stored in the semiconductor device (memory cell 250) shown in Figure 6(A). This explains how to perform this action.

[0219] First, the potential of the word line WL is set to the potential at which transistor 162 turns ON. Turn on the zistor 162. This will change the potential of the bit line BL to that of the capacitive element 254. The first terminal is supplied (written). Then, the potential of the word line WL is set to transistor 1. By setting transistor 162 to the OFF state, which is the potential at which 62 is OFF, The potential of the first terminal of the quantitative element 254 is maintained (held).

[0220] Since the off-current of transistor 162 is extremely small, the potential of the first terminal of capacitive element 254 (Or the charge stored in a capacitive element) can be retained for a long period of time.

[0221] Next, we will explain how to read the information. When transistor 162 is turned on, floating In this state, the bit line BL and the capacitive element 254 are conductive, and the bit line BL and the capacitive element 254 Charge is redistributed between them. As a result, the potential of bit line BL changes. The change in position is the potential of the first terminal of the capacitive element 254 (or the potential stored in the capacitive element 254). It takes on different values ​​depending on the charge.

[0222] For example, let V be the potential of the first terminal of the capacitive element 254, C be the capacitance of the capacitive element 254, and let C be the bit line The capacitance component of BL (hereinafter also called bit line capacitance) is called CB, and the capacitance before charge redistribution. If the potential of bit line BL is VB0, then the potential of bit line BL after charge redistribution is: The formula becomes (CB*VB0+C*V) / (CB+C). Therefore, the memory cell state is 250. And, assuming that the potential of the first terminal of the capacitive element 254 takes two states, V1 and V0 (V1 > V0) Then, the potential of the bit line BL when the potential V1 is maintained is (=(CB*VB0+C*V1 ) / (CB+C)) is the potential of bit line BL when potential V0 is held (=(CB* It can be seen that this is higher than (VB0 + C * V0) / (CB + C)).

[0223] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. ru.

[0224] Thus, the semiconductor device shown in Figure 6(A) has an extremely low off-current for transistor 162. Due to this characteristic, the charge stored in the capacitive element 254 is retained for a long time. This means that refresh operations become unnecessary, or the frequency of refresh operations decreases. Because it becomes possible to make it extremely low, power consumption can be significantly reduced. Furthermore, it is possible to retain the contents of the memory for a long period of time even if there is no power supply. ru.

[0225] Next, we will explain the semiconductor device shown in Figure 6(B).

[0226] The semiconductor device shown in Figure 6(B) has a memory cell 2 shown in Figure 6(A) as a memory circuit at the top. It has memory cell arrays 251a and 251b having multiple 50s, and at the bottom, memory cell A Peripheral cycles required to operate Ray 251 (memory cell arrays 251a and 251b) It has a circuit 253. The peripheral circuit 253 is electrically connected to the memory cell array 251. It is being done.

[0227] By using the configuration shown in Figure 6(B), the peripheral circuit 253 is connected to the memory cell array 251. Because it can be installed directly below the memory cell arrays 251a and 251b, the semiconductor device It can be made smaller.

[0228] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material than transistor 162. It is preferable to use silicon, germanium, silicon germanium, Silicon carbide or gallium arsenide can be used, and single-crystal semiconductors can be used. Preferred. Alternatively, organic semiconductor materials may be used. The transistor is capable of high-speed operation. Therefore, the transistor enables high-speed operation. It is possible to suitably realize various circuits that require specific operation (logic circuits, drive circuits, etc.). ru.

[0229] In the semiconductor device shown in Figure 6(B), there are two memory cell arrays 251 (memory cells). Although an example was given of a configuration in which array 251a and memory cell array 251b are stacked, stacking The number of memory cells is not limited to this. good.

[0230] Next, the specific configuration of the memory cell 250 shown in Figure 6(A) will be explained using Figure 7. conduct.

[0231] Figure 7 shows an example of the configuration of the memory cell 250. Figure 7(A) shows the plan view of the memory cell 250. Figure 7(B) shows a cross-sectional view of the line segment AB in Figure 7(A).

[0232] The transistor 162 shown in Figures 7(A) and 7(B) is from Embodiment 1 or Embodiment 2. The configuration can be the same as the one shown.

[0233] As shown in Figure 7(B), transistors 162 are provided on electrodes 502 and 504. Electrode 502 is a wiring that functions as a bit line BL in Figure 6(A), and It is provided in contact with the low-resistance region of the transistor 162. Also, electrode 504 is located in Figure 6(A It functions as one electrode of the capacitive element 254 in the low-resistance region of transistor 162. It is provided in contact with the electrode 504. On transistor 162, in the region that overlaps with electrode 504 The provided electrode 506 functions as the other electrode of the capacitive element 254.

[0234] Furthermore, as shown in Figure 7(A), the other electrode 506 of the capacitive element 254 is connected to the capacitance line 508. Electrically connected. A gate insulating film 146 is provided on the oxide semiconductor layer 144. The electrode 148a is electrically connected to the word wire 509.

[0235] Furthermore, Figure 7(C) shows a cross-sectional view of the connection between the memory cell array 251 and the peripheral circuit. The peripheral circuitry includes, for example, an n-channel transistor 510 and a p-channel transistor. The configuration can include a 512 n-channel transistor and a p-channel transistor. The semiconductor material used in the 512 transistor is a semiconductor material other than an oxide semiconductor. It is preferable to use materials such as silicon. By using such materials, the peripheral circuitry is included This enables high-speed operation of transistors.

[0236] By adopting the planar layout shown in Figure 7(A), the occupied area of ​​the semiconductor device can be reduced. Because this can be achieved, high integration can be realized.

[0237] As described above, the multiple memory cells formed in multiple layers on top use an oxide semiconductor. It is formed by an ionizer. It contains in small amounts of the four elements indium, gallium, zinc, and oxygen. Including galvanic acid, when the composition ratio of these four elements is expressed as atomic percentages, the proportion of indium is... Transistors using oxide semiconductors where the proportion of aluminum and zinc is more than twice the proportion of other elements are off-voltage. Because the flow rate is low, it is possible to retain memory content over a long period of time by using this method. Yes. In other words, it becomes possible to make the refresh operation extremely infrequent, thus reducing power consumption. The force can be sufficiently reduced. Also, the capacitive element 254 is as shown in Figure 7(B) The electrode 504, oxide semiconductor layer 144, gate insulating film 146, and electrode 506 are stacked. Thus it is formed. The relative permittivity of the oxide semiconductor layer having the above composition is very high. (with a relative permittivity of 66), by using this as a dielectric film, a capacitive element 254 is required. The area to be reduced can be decreased.

[0238] Thus, transistors using materials other than oxide semiconductors (in other words, sufficiently high-speed operation) A peripheral circuit using transistors capable of operation, and a transistor using oxide semiconductors ( In a broader sense, it integrates a memory circuit using a transistor with a sufficiently low off-current. This makes it possible to realize a semiconductor device with unprecedented features. By using a stacked structure for the paths and memory circuits, it is possible to integrate semiconductor devices.

[0239] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0240] (Embodiment 5) In this embodiment, the semiconductor device shown in the previous embodiment is used in a mobile phone, smartphone, and other electronic devices. Examples of applications to portable devices such as children's books will be explained using Figures 8 to 11.

[0241] In mobile devices such as cell phones, smartphones, and e-readers, temporary storage of image data SRAM or DRAM is used in these applications. The reason is that flash memory has a slow response time and is unsuitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following characteristics apply: ru.

[0242] In a typical SRAM, as shown in Figure 8(A), one memory cell is connected to transistors 801-8 It consists of six 06 transistors, which are used for the X decoder 807 and the Y decoder. It is driven by transistors 808, 803, 805, and 80 4 and transistor 806 form an inverter, enabling high-speed drive. However, one Because the memory cell is composed of 6 transistors, it has the disadvantage of having a large cell area. When the minimum dimension of the design rule is F, the memory cell area of ​​SRAM is typically 100 ~150F 2 Therefore, SRAM has the highest cost per bit among all types of memory. stomach.

[0243] In contrast, DRAM has memory cells as shown in Figure 8(B) by transistor 811, It is composed of a capacity 812, which is driven by the X decoder 813 and Y decoder 814. It is working. Each cell has a configuration of 1 transistor and 1 capacitance, resulting in a small area. D The memory cell area of ​​RAM is typically 10F 2 The following applies. However, DRAM is always refreshed This requires power consumption, even if no rewriting is performed.

[0244] However, the memory cell area of ​​the semiconductor device described in the previous embodiment is 10F 2 Front and back Furthermore, frequent refreshing is unnecessary. Therefore, the memory cell area is reduced, and Power consumption can be reduced.

[0245] Figure 9 shows a block diagram of the portable device. The portable device shown in Figure 9 is an RF circuit 901, an analog base Baseband circuit 902, digital baseband circuit 903, battery 904, power supply circuit 905, Application processor 906, Flash memory 910, DisplayCo Controller 911, memory circuit 912, display 913, touch sensor 919, voice It consists of a circuit 917, a keyboard 918, etc. The display 913 is a display unit 9 14. It consists of a source driver 915 and a gate driver 916. The 906 is a processing processor consisting of CPU 907, DSP 908, and interface 909 (I It has F909). Generally, the memory circuit 912 is composed of SRAM or DRAM. By employing the semiconductor device described in the previous embodiment in this part, information It offers high-speed writing and reading, long-term memory retention, and sufficient power consumption. It can be reduced.

[0246] Figure 10 shows that the semiconductor device described in the previous embodiment is used in the memory circuit 950 of the display. An example of its use is shown. The memory circuit 950 shown in Figure 10 includes memory 952, memory 953, and switch It consists of a switch 954, a switch 955, and a memory controller 951. Furthermore, the memory circuit 950 has signal lines for image data (input image data), memory 952, and The disk reads and controls the data (storage image data) stored in memory 953. The display is generated by signals from the play controller 956 and the display controller 956. Display 957 is connected.

[0247] First, some image data is formed by an application processor (not shown). (Input image data A). Input image data A is sent to memory 952 via switch 954. It is stored. And the image data stored in memory 952 (stored image data A) is... The signal is sent to the display 957 via the switch 955 and the display controller 956. , it will be displayed.

[0248] If there are no changes to the input image data A, the stored image data A is typically stored at a frequency of about 30-60 Hz. During this period, the memory 952 is read from the display controller 956 via the switch 955. To be revealed.

[0249] Next, for example, when a user performs an operation to rewrite the screen (i.e., input image data A If there are any changes, the application processor will use the new image data (input image data). Form B). Input image data B is stored in memory 953 via switch 954. During this time, the stored image data A was periodically read from memory 952 via switch 955. It is being done. When the new image data (storage image data B) has finished being stored in memory 953, From the next frame on display 957, stored image data B is read out, and switch 95 5. The stored image data is sent to the display 957 via the display controller 956. Data B is sent and displayed. This read then memos new image data. This continues until it is stored in RI952.

[0250] In this way, memory 952 and memory 953 alternately write image data, and image data By reading from this, the display 957 will display the information. Note that memory 9 Memory 52 and memory 953 are not limited to separate memory locations, but can be used by dividing a single memory location. It may be used. The semiconductor device described in the previous embodiment can be used in memory 952 and memory 953. By adopting this method, information can be written and read at high speed, and long-term memory retention is possible. It is capable of significantly reducing power consumption.

[0251] Figure 11 shows a block diagram of the e-book. Figure 11 shows battery 1001 and power supply circuit 1002. Microprocessor 1003, flash memory 1004, audio circuit 1005, keyboard Code 1006, memory circuit 1007, touch panel 1008, display 1009, It is comprised of a display controller 1010.

[0252] Here, the memory circuit 1007 in Figure 11 uses the semiconductor device described in the previous embodiment. It is possible. The role of the memory circuit 1007 is to temporarily hold the contents of the book. Examples of features include when a user uses the highlighting function. Sometimes, when reading an ebook, you might want to mark a specific section. The highlighting function is also called the "coloring function," and it allows you to change the display color, underline, and bold text. This involves making something different from its surroundings by changing the font or typeface. This function stores and retains information from a specified location. If this information is to be stored for a long period of time... It is also acceptable to copy it to flash memory 1004. In this case as well, the previously performed By employing the semiconductor device described in the form, information writing and reading are highly efficient. It allows for rapid, long-term memory retention while significantly reducing power consumption.

[0253] As described above, the portable device shown in this embodiment is equipped with the semiconductor device according to the previous embodiment. It is listed. Therefore, it has high read speed, can retain data for long periods, and consumes low power. Portable devices with reduced noise levels will be realized.

[0254] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together. [Examples]

[0255] In this embodiment, an oxide semiconductor film (IGZO film) containing indium, gallium, and zinc is used. We fabricated the oxide semiconductor film, measured its ionization potential, and based on the results, we performed energy testing. The Ghee band diagram was calculated. In this specification, the value of the ionization potential is given by the band diagram. The band gap is the sum of the energy gap and electron affinity, and the band gap value is The values ​​obtained by spectroscopic ellipsometry of the single film of the material are used. A compositional analysis of the membrane was performed.

[0256] First, we will show the band gap results obtained by spectroscopic ellipsometry.

[0257] As the oxide semiconductor film to be used as the sample, a film with a thickness of 100n was created on a quartz substrate using the sputtering method. A m IGZO film was deposited. The deposition conditions were a substrate temperature of 300°C, and the target was An oxide target with an atomic ratio of In:Ga:Zn = 3:1:2 was used.

[0258] The band gap is between argon and oxygen (argon:oxygen = 30 sccm:15 sccm). For samples deposited under atmospheric conditions and without post-deposition heat treatment, the temperature was 2.83 eV, and at 450°C after deposition... The sample that underwent heat treatment (1 hour under a nitrogen atmosphere followed by 1 hour under an oxygen atmosphere) had a voltage of 2.90 eV. The sample that underwent heat treatment at 650°C after film formation (1 hour under a nitrogen atmosphere followed by 1 hour under an oxygen atmosphere) The film was deposited at 2.94 eV and under an oxygen atmosphere (100% oxygen), without post-deposition heat treatment. In the sample, the temperature was 2.82 eV, and after film formation, heat treatment was performed at 450°C (1 hour under a nitrogen atmosphere, followed by an oxygen atmosphere) The sample, after being exposed to air for 1 hour, reached 2.89 eV, and after film formation, it underwent heat treatment at 650°C (1 hour under a nitrogen atmosphere). The sample, after being incubated in an oxygen atmosphere for 1 hour, was 2.94 eV, approximately 2.8 eV to 2.9 eV. It was v.

[0259] Furthermore, on a single-crystal silicon substrate, under an oxygen atmosphere (100% oxygen), substrate temperature 300°C, I Sputtering method using an oxide target with n:Ga:Zn=3:1:2 [atomic ratio] The IGZO film obtained by forming a film with a thickness of 15 nm was sputtered from the surface side of the film. Ultraviolet photoelectron spectroscopy (UPS) The ionization potential was measured using tron ​​spectroscopy. The on-activation potential represents the energy difference between the vacuum level and the valence band.

[0260] Subtracting the band gap measured by spectroscopic ellipsometry from the ionization potential value. The energy of the conduction band is calculated using this, and this is In:Ga:Zn=3:1:2 [atomic ratio] The band structure of IGZO films deposited using an oxide target was created. The band gap of the O film was set to 2.8 eV. The results are shown in Figure 12.

[0261] Next, on a single-crystal silicon substrate, under an oxygen atmosphere (100% oxygen), substrate temperature 300°C, I Sputtering method using an oxide target with n:Ga:Zn=3:1:2 [atomic ratio] The composition of the IGZO film obtained by depositing a film thickness of 15 nm was determined by X-ray photoelectron spectroscopy (XPS): Determined by X-ray photoelectron spectroscopy analysis. The evaluation was done quantitatively.

[0262] In the IGZO film, indium (In) is 23.7 atomic%, and gallium (Ga) 7.5 atomic percent of ammonium compounds, 9 atomic percent of zinc (Zn), and 59.7 atomic percent of oxygen (O). It was omic%.

[0263] Furthermore, films were deposited using an oxide target with an atomic ratio of In:Ga:Zn=3:1:2. X-ray diffraction (XRD) measurements were performed on the IGZO film.

[0264] As a sample, an IGZO film with a thickness of 100 nm was deposited on a quartz substrate using the sputtering method. The film deposition conditions were as follows: substrate temperature at room temperature, 200°C, 300°C, or 400°C, and film deposition atmosphere The gases are argon and oxygen (argon:oxygen = 30 sccm:15 sccm), and the target is As the target, an oxide target with an atomic ratio of In:Ga:Zn=3:1:2 was used.

[0265] XRD spectra were obtained for each IGZO film using the out-of-plane method. The measurement results are shown in Figure 13. In Figure 13, the vertical axis represents the X-ray diffraction intensity (in arbitrary units). The horizontal axis represents a rotation angle of 2θ (deg.). Note that the XRD spectrum was measured by Bruke. A D8 ADVANCE X-ray diffractometer manufactured by AXS Corporation was used.

[0266] As shown in Figure 13, the IGZO film deposited at room temperature showed crystalline properties in the XRD spectrum. No marks were observed, confirming that it was an amorphous oxide semiconductor film. Furthermore, at 200°C and 300°C... IGZO films deposited at °C or 400°C show the following XRD spectra as shown in Figure 13: A peak is observed near 2θ=31°, indicating that it is a crystalline oxide semiconductor film. This was confirmed.

[0267] Next, the end face of the IGZO film was cut out and examined using a high-resolution transmission electron microscope (Hitachi High-Technologies Corporation) Using the H9000-NAR (TEM), the acceleration voltage was set to 300kV, and the cross-section of the IGZO film was observed. went.

[0268] As a sample, an IGZO film with a thickness of 100 nm was deposited on a quartz substrate using the sputtering method. The film deposition conditions were: substrate temperature 300°C, deposition atmosphere argon and oxygen (argon: acid Assuming element ratios of 30 sccm and 15 sccm, the target ratio is In:Ga:Zn = 3:1 A 2-atomic oxide target was used.

[0269] Figure 16(A) shows the result without post-deposition heat treatment, and Figure 16(B) shows the result after post-deposition heat treatment at 450°C (in a nitrogen atmosphere). After 1 hour under the atmosphere, then 1 hour under the atmosphere of oxygen, the film was deposited as shown in Figure 16(C) and then heat-treated at 650°C (under the atmosphere of nitrogen). The image shows a TEM image of a cross-section of an IGZO film after 1 hour under gas and 1 hour under an oxygen atmosphere.

[0270] As shown in Figures 16(A) to (C), the crystal has a c-axis that is roughly perpendicular to the surface (CAA An IGZO film containing C) was confirmed.

[0271] As described above, using an oxide target with an atomic ratio of In:Ga:Zn=3:1:2 It was confirmed that non-single-crystal IGZO films can be obtained. [Examples]

[0272] In this example, an oxide target with an atomic ratio of In:Ga:Zn=3:1:2 was used. Transistors with deposited IGZO films were fabricated, and their electrical characteristics and reliability were evaluated. Ta.

[0273] As transistors, transistor 1 has the structure of transistor 440a shown in Figure 1, and Figure A transistor 2 with the structure of transistor 440b shown in 2(A) was fabricated. The method for fabricating transistor 1 and transistor 2 is shown.

[0274] A silicon oxide layer with a thickness of 300 nm is created on a glass substrate using the sputtering method as an insulating layer. A film was formed (deposition conditions: under an oxygen atmosphere, at a pressure of 0.4 Pa, with a power supply of 1.5 kW, on a glass substrate). The distance between the substrate and the target is 60 mm, and the substrate temperature is 100°C.

[0275] After polishing the surface of the silicon oxide film, an oxide semiconductor film with In:Ga:Zn=3:1:2 A sputtering method using an oxide target of [atomic ratio] was used to create an IG with a film thickness of 20 nm. A ZO film was formed. The deposition conditions were argon and oxygen (argon:oxygen = 30 sccm:1). Under a 5 sccm atmosphere, pressure 0.4 Pa, power supply 1.5 kW, glass substrate and target The distance between them was set to 60 mm, and the substrate temperature to 200°C.

[0276] Next, the material is heat-treated at 450°C under a nitrogen atmosphere for 1 hour, followed by heat treatment under an oxygen atmosphere for 1 hour. The IGZO film was modified using ICP (Inductively Coupled Plasma: Etching is performed using an inductively coupled plasma etching method (etching conditions: etching gas (BCl3:Cl2=60sccm:20sccm), Power supply 450W, Bias current It was processed into an island shape using a force of 100W and a pressure of 1.9Pa.

[0277] A tungsten film with a thickness of 50 nm was deposited using the sputtering method (deposition conditions: under an argon atmosphere). A film (at a pressure of 0.8 Pa and a power supply of 1 kW) is deposited, and then etched by the ICP etching method ( Etching conditions: Etching gas (CF4:Cl2:O2 = 25 sccm:25 sccm) (10 sccm), power supply 500W, bias power 150W, pressure 1.0 Pa) A drain electrode layer and a drain electrode layer were formed.

[0278] Next, a 30 nm silicon oxide nitride film was deposited using the CVD method to form a gate insulating film.

[0279] A tantalum nitride film with a thickness of 15 nm was deposited by sputtering (deposition conditions: argon and nitrogen). Under an Ar:N2 atmosphere (50 sccm:10 sccm), pressure 0.6 Pa, power supply 1 kW. ) and a tungsten film with a thickness of 135 nm (deposition conditions: under an argon atmosphere, at a pressure of 2.0 Pa) A layer of film is formed using a power supply of 4kW, and then etched by an etching method (first etching). Conditions: Etching gas (Cl2:SF6:O2 = 33 sccm:33 sccm:10 sc) (cm, power supply 2000W, bias power 50W, pressure 0.67Pa) (2nd etching) Conditions: Etching gas (Cl2 = 100 sccm), power supply 2000W, bias power 5 A gate electrode layer was formed under 0W and a pressure of 0.67Pa.

[0280] For transistor 1 only, the gate electrode layer, source electrode layer, and drain electrode layer are used as a mask. Phosphorus (P) ions were implanted into the IGZO membrane using the on-implantation method. The injection conditions were an acceleration voltage of 40kV and a dose of 1.0 × 10⁻⁶. 15 ions / cm 2 That's what I decided.

[0281] As an insulating film, an aluminum oxide film is deposited on the gate electrode layer by sputtering (deposition conditions) Under an argon and oxygen (argon:oxygen = 25 sccm:25 sccm) atmosphere, at a pressure of 0 0.4 Pa, power supply 2.5 kW, distance between glass substrate and target 60 mm, substrate A film was deposited at a temperature of 250°C, and a 300 nm layer of silicon oxidizride film was stacked using the CVD method.

[0282] Next, an opening is formed in the gate insulating film and the insulating film that reaches the IGZO film, and sputtering is applied to the opening. A 50 nm thick titanium film was deposited using the argon deposition method (deposition conditions: argon (Ar=20 sccm) atmosphere). (Under air pressure, 0.1 Pa, power supply 12 kW), aluminum film with a thickness of 100 nm (deposited strip) Subject: Under an argon (Ar=50 sccm) atmosphere, pressure 0.4 Pa, power supply (1 kW), membrane A 50nm thick titanium film (deposition conditions: under an argon (Ar=20 sccm) atmosphere and at a pressure of 0. A layer of film (1 Pa, 12 kW power supply) is deposited and etched (etching conditions: etching). Gas (BCl3:Cl2 = 60 sccm:20 sccm), Power supply 450W, Bias A wiring layer was formed using a power of 100W and a pressure of 1.9Pa.

[0283] Transistor 1 and transistor 2 were fabricated using the above process. Note that transistor 1 In this case, the channel length (L) is 3.2 μm and the channel width (W) is 10.1 μm, and the oxide semi-oxide On the conductive film, it does not overlap with the source electrode layer, drain electrode layer, or gate electrode layer. The channel length (also called Loff) of the region was set to 0.15 μm. Furthermore, In transistor 2, the channel length (L) is 2.9 μm and the channel width (W) is 10 On a 0.1 μm oxide semiconductor film, the source electrode layer or drain electrode layer is connected to the gate electrode layer. The width of the overlapping region in the channel length direction (also called Lov) was set to 1.15 μm.

[0284] The electrical characteristics of the obtained transistors 1 and 2, and in transistor 1 Reliability evaluation was also performed. Transistor 2's drain voltage (Vd) was 3V and 0.1V. Gate voltage (Vg)-drain current (Id) characteristics, and drain voltage (Vd) when 0.1V Figure 14 shows the field-effect mobility at 3V, 0 Gate voltage (Vg)-drain current (Id) characteristics at 0.1V, and drain voltage (V d) The field-effect mobility at 0.1V is shown in Figure 15(A)(B).

[0285] As shown in Figures 14 and 15, transistors 1 and 2 exhibit high on-characteristics. Furthermore, the field effect mobility is 20 cm. 2 It is around / Vs, and for transistor 2 it is 20cm². 2 The field effect mobility was greater than / Vs.

[0286] One method for investigating the reliability of transistors is the bias-thermal stress test (hereinafter, It is called the GBT (Gate Bias Temperature) test. The test is a type of accelerated test that measures the changes in transistor characteristics that occur due to long-term use. It can be evaluated in a short time. In particular, the transistor threshold before and after GBT testing. The change in voltage is an important indicator for examining reliability. Before and after the GBT test, The smaller the change in the key voltage, the higher the reliability.

[0287] Maintain the substrate on which the transistor is formed at a constant temperature, and control the source and drain of the transistor. The inputs are set to the same potential, and the gate is given a different potential from the source and drain for a certain period of time. The temperature of the board should be set appropriately according to the purpose of the test. Note that in the "+GBT test", The potential applied to the source is greater than the potential of the source and drain (the source and drain are at the same potential). Also high, in the "-GBT test", the potential applied to the gate is the potential of the source and drain (saw The drain and the spool are at the same potential. (It is lower than the drain.)

[0288] The test intensity of the GBT test is determined by the substrate temperature, the electric field strength applied to the gate insulating layer, and the time the electric field is applied. It can be determined by the interval. The electric field strength in the gate insulating layer is determined by the gate, source and do It is determined by dividing the potential difference between the rain and the gate insulating layer by the thickness of the gate insulating layer.

[0289] In this embodiment, a GBT test was performed on transistor 1. First, as part of the +GBT test, the substrate temperature The temperature was set to 40°C and Vd to 3V, and the Vg-Id characteristics of transistor 1 were measured. The substrate temperature was set to 150°C and Vd to 0.1V. Next, the voltage applied to the gate insulating film was... Apply 6V to Vg so that the field intensity is 2MV / cm, and leave it in an atmospheric environment for 1 hour. It was held. Next, Vg was set to 0V. Next, the substrate temperature was set to 40°C, and Vd was set to 10V. Vg-Id measurements were performed on lungista 1. The +GBT test results are shown in Figure 15(A).

[0290] Similarly, for the GBT test, first the substrate temperature was set to 40°C, V(ds) to 10V, and the transistor... The Vg-Id characteristics of T1 were measured. Next, the substrate temperature was set to 150°C and Vd was set to 0.1V. Next, Vg was set so that the electric field strength applied to the gate insulating film was -2MV / cm. -6V was applied and held in an atmospheric environment for 1 hour. Next, Vg was set to 0V. The substrate temperature was set to 40°C, Vd to 10V, and the Vg-Id measurement of transistor 1 was performed. - The GBT test results are shown in Figure 15(B).

[0291] In Figures 15(A) and 15(B), the period before the GBT test is shown with a thick line, and the period after the test is shown with a thin line.

[0292] As shown in Figures 15(A) and (B), the +GBT and -GBT tests of transistor 1 are performed. Almost no fluctuation in the threshold voltage was observed. Therefore, the transistor in this embodiment This confirms that the threshold voltage fluctuations before and after the GBT test are small and highly reliable. Ta.

[0293] Furthermore, using the same fabrication process as transistor 1, the channel length (L) was set to 0.8 μm. A transistor was fabricated with a channel width (W) of 1000 μm and a Loff of 0.3 μm. The off-leak current of the transistor was measured. The measurement was performed at 125°C or 85°C. The measurements were taken under the specified conditions. The results are shown in Figure 17.

[0294] Figure 17 shows the case when the transistor according to this embodiment is operated at 85°C for 41.5 hours. The off-leak current was 0.5 zA / μm, which was an extremely low value.

[0295] Based on the above, the transistor in this embodiment has an extremely low off-current value and is a highly reliable transistor. It was shown to be a star.

Claims

1. It has multiple circuits arranged in a matrix, The aforementioned circuit is A first transistor having a first channel formation region containing silicon, A second transistor having a second channel-forming region containing an oxide semiconductor, The gate electrode of the first transistor is electrically connected to one of the source electrode and drain electrode of the second transistor, and is a semiconductor device. A first conductive layer provided above the first channel formation region and functioning as the gate electrode of the first transistor, A first insulating layer having a region in contact with the side surface of the first conductive layer, A second insulating layer above the first insulating layer, An oxide semiconductor layer having a region in contact with the upper surface of the second insulating layer and having the second channel forming region, A second conductive layer provided above the oxide semiconductor layer and having the function of the gate electrode of the second transistor, A third conductive layer is electrically connected to the oxide semiconductor layer and functions as one of the source and drain electrodes of the second transistor. A third insulating layer having a region located above the second conductive layer and a region located above the third conductive layer, A fourth conductive layer above the third insulating layer, A fourth insulating layer having a region located above the fourth conductive layer, The oxide semiconductor layer comprises In, Ga, and Zn. The second insulating layer comprises silicon oxide, In a plan view, the second conductive layer has a first region having a first length above the oxide semiconductor layer. In a plan view, the fourth conductive layer has a second region having a second length greater than the first length. The first length and the second length are the lengths of the second transistor in the channel length direction, The second region of the fourth conductive layer overlaps with the third conductive layer via the third insulating layer. In a plan view, the second channel formation region does not overlap with the first channel formation region, wherein the semiconductor device.

2. It has multiple circuits arranged in a matrix, The aforementioned circuit is A first transistor having a first channel formation region containing silicon, A second transistor having a second channel-forming region containing an oxide semiconductor, The gate electrode of the first transistor is electrically connected to one of the source electrode and drain electrode of the second transistor, and is a semiconductor device. A first conductive layer provided above the first channel formation region and functioning as the gate electrode of the first transistor, A first insulating layer having a region in contact with the side surface of the first conductive layer, A second insulating layer above the first insulating layer, An oxide semiconductor layer having a region in contact with the upper surface of the second insulating layer and having the second channel forming region, A second conductive layer provided above the oxide semiconductor layer and having the function of the gate electrode of the second transistor, A third conductive layer is electrically connected to the oxide semiconductor layer and functions as one of the source and drain electrodes of the second transistor. A third insulating layer having a region located above the second conductive layer and a region located above the third conductive layer, A fourth conductive layer above the third insulating layer, A fourth insulating layer having a region located above the fourth conductive layer, It comprises a fifth conductive layer above the fourth insulating layer, The oxide semiconductor layer comprises In, Ga, and Zn. The second insulating layer comprises silicon oxide, In a plan view, the second conductive layer has a first region having a first length above the oxide semiconductor layer. In a plan view, the fourth conductive layer has a second region having a second length greater than the first length. The first length and the second length are the lengths of the second transistor in the channel length direction, The second region of the fourth conductive layer overlaps with the third conductive layer via the third insulating layer. The fifth conductive layer has a region that overlaps with the first conductive layer, In a plan view, the second channel formation region does not overlap with the first channel formation region, wherein the semiconductor device.

3. It has multiple circuits arranged in a matrix, The aforementioned circuit is A first transistor having a first channel formation region containing silicon, A second transistor having a second channel-forming region containing an oxide semiconductor, The gate electrode of the first transistor is electrically connected to one of the source electrode and drain electrode of the second transistor, and is a semiconductor device. A first conductive layer provided above the first channel formation region and functioning as the gate electrode of the first transistor, A first insulating layer having a region in contact with the side surface of the first conductive layer, A second insulating layer above the first insulating layer, An oxide semiconductor layer having a region in contact with the upper surface of the second insulating layer and having the second channel forming region, A second conductive layer provided above the oxide semiconductor layer and having the function of the gate electrode of the second transistor, A third conductive layer is electrically connected to the oxide semiconductor layer and functions as one of the source and drain electrodes of the second transistor. A third insulating layer having a region located above the second conductive layer and a region located above the third conductive layer, A fourth conductive layer above the third insulating layer, A fourth insulating layer having a region located above the fourth conductive layer, The oxide semiconductor layer comprises In, Ga, and Zn. The second insulating layer comprises silicon oxide, In a plan view, the second conductive layer has a first region having a first length above the oxide semiconductor layer. In a plan view, the fourth conductive layer has a second region having a second length greater than the first length. The first length and the second length are the lengths of the second transistor in the channel length direction, The second region of the fourth conductive layer overlaps with the third conductive layer via the third insulating layer. A semiconductor device wherein, in a plan view, the oxide semiconductor layer does not overlap with the first conductive layer.

4. It has multiple circuits arranged in a matrix, The aforementioned circuit is A first transistor having a first channel formation region containing silicon, A second transistor having a second channel-forming region containing an oxide semiconductor, The gate electrode of the first transistor is electrically connected to one of the source electrode and drain electrode of the second transistor, and is a semiconductor device. A first conductive layer provided above the first channel formation region and functioning as the gate electrode of the first transistor, A first insulating layer having a region in contact with the side surface of the first conductive layer, A second insulating layer above the first insulating layer, An oxide semiconductor layer having a region in contact with the upper surface of the second insulating layer and having the second channel forming region, A second conductive layer provided above the oxide semiconductor layer and having the function of the gate electrode of the second transistor, A third conductive layer is electrically connected to the oxide semiconductor layer and functions as one of the source and drain electrodes of the second transistor. A third insulating layer having a region located above the second conductive layer and a region located above the third conductive layer, A fourth conductive layer above the third insulating layer, A fourth insulating layer having a region located above the fourth conductive layer, It comprises a fifth conductive layer above the fourth insulating layer, The oxide semiconductor layer comprises In, Ga, and Zn. The second insulating layer comprises silicon oxide, In a plan view, the second conductive layer has a first region having a first length above the oxide semiconductor layer. In a plan view, the fourth conductive layer has a second region having a second length greater than the first length. The first length and the second length are the lengths of the second transistor in the channel length direction, The fourth conductive layer overlaps with the third conductive layer via the third insulating layer. The fifth conductive layer has a region that overlaps with the first conductive layer, A semiconductor device wherein, in a plan view, the oxide semiconductor layer does not overlap with the first conductive layer.

5. In any one of claims 1 to 4, A semiconductor device wherein the fourth conductive layer has a region that overlaps with the first conductive layer via the third insulating layer and the third conductive layer.

6. In any one of claims 1 to 5, The oxide semiconductor layer is crystalline, and the semiconductor device is a semiconductor device.

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