Host device

Abstract

To speed up a communication interface.SOLUTION: A host device is provided having a connector, a transmitter, a receiver, a first AC coupling capacitor, and a second AC coupling capacitor. The connector includes a first group of connector contacts and a second group of connector contacts. The first connector contact group is connectable to the first terminal group. The second connector contact group is connectable to the second terminal group. The first connector contact group includes a terminal to which a differential clock signal compliant with the PCIe standard is assigned, a terminal to which a single-ended signal is assigned, and a terminal to which a first power supply voltage is assigned. The second connector contact group includes two terminals to which a first differential data signal is assigned, two terminals to which a second differential data signal is assigned, and a plurality of terminals to which ground is assigned.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment generally relates to a host device. [Background Art]

[0002] In memory cards, the amount of data transfer has increased along with the increase in storage capacity. In order to prevent an increase in data transfer time accompanying the increase in the amount of data transfer, higher speed communication interfaces mounted on memory cards are required. [Prior Art Document] [Patent Document]

[0003] [Patent Document 1] Japanese Unexamined Patent Publication No. 2016-29556 [Summary of the Invention] [Means for Solving the Problem]

[0004] According to one embodiment, a host device is provided having a connector, a transmitter, a receiver, a first AC coupling capacitor, and a second AC coupling capacitor. The connector is connectable to a memory card. The memory card has a first surface, a second surface, a first group of terminals, and a second group of terminals. The first surface includes a first row and a second row. The second surface faces away from the first surface. The first group of terminals is located in the first row. The second group of terminals is located in the second row. The transmitter transmits a first differential data signal to the connector via a first transmission line. The first differential data signal conforms to the PCIe standard. The receiver receives a second differential data signal from the connector via a second transmission line. The second differential data signal conforms to the PCIe standard. The first AC coupling capacitor is provided in the first transmission line. The second AC coupling capacitor is provided in the second transmission line. The connector includes a first contact group and a second contact group. The first contact group is connectable to a first terminal group. The second contact group is connectable to a second terminal group. The first contact group includes terminals to which a PCIe-compliant differential clock signal is assigned, terminals to which a single-ended signal is assigned, and terminals to which a first power supply voltage is assigned. The second contact group includes two terminals to which a first differential data signal is assigned, two terminals to which a second differential data signal is assigned, and a number of terminals to which ground is assigned. [Brief explanation of the drawing]

[0005] [Figure 1] Figure 1 is a plan view showing the schematic configuration of a memory card according to the first embodiment. [Figure 2] Figure 2 is a plan view showing the schematic configuration of a memory card according to the second embodiment. [Figure 3] Figure 3 is a plan view showing another schematic configuration of the memory card according to the second embodiment. [Figure 4A] Figure 4A is a plan view showing the schematic configuration of a memory card according to the third embodiment. [Figure 4B] Figure 4B is a plan view showing the schematic configuration of a memory card according to the fifth embodiment. [Figure 4C] Figure 4C is a plan view showing the schematic configuration of a memory card according to the fourth embodiment. [Figure 5] Figure 5 is a block diagram showing the schematic configuration of a memory card according to the sixth embodiment. [Figure 6] Figure 6 is a block diagram showing a schematic configuration of a host device equipped with a memory card according to the seventh embodiment. [Figure 7] Figure 7 is a block diagram showing a schematic configuration of an interface card with a memory card installed according to the eighth embodiment. [Figure 8] Figure 8 is a flowchart showing the operation of the host device when the bus mode of the memory card according to the ninth embodiment is set. [Figure 9] Figure 9 is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to the 10th embodiment. [Figure 10A] Figure 10A is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to the 11th embodiment. [Figure 10B] Figure 10B is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to the 12th embodiment. [Figure 11A] Figure 11A is a perspective view showing an example of a schematic configuration of a connector used in a memory card according to the 13th embodiment. [Figure 11B] Figure 11B is a cross-sectional view showing an example of a schematic configuration of a connector used in a memory card according to the 13th embodiment. [Figure 12A] Figure 12A is a cross-sectional view showing an example of the schematic configuration of the connector before the memory card is inserted according to the 14th embodiment. [Figure 12B] Figure 12B is a plan view showing an example of the schematic configuration of the connector before the memory card is inserted according to the 14th embodiment. [Figure 12C] FIG. 12C is a cross-sectional view illustrating an example of a schematic configuration of the connector after the memory card according to the fourteenth embodiment is inserted. [Figure 12D] FIG. 12D is a plan view illustrating an example of a schematic configuration of the connector after the memory card according to the fourteenth embodiment is inserted. [Figure 13A] FIG. 13A is a cross-sectional view illustrating an example of a schematic configuration of the adapter before the memory card according to the fifteenth embodiment is inserted. [Figure 13B] FIG. 13B is a plan view illustrating an example of a schematic configuration of the adapter before the memory card according to the fifteenth embodiment is inserted. [Figure 13C] FIG. 13C is a cross-sectional view illustrating an example of a schematic configuration of the adapter after the memory card according to the fifteenth embodiment is inserted. [Figure 13D] FIG. 13D is a plan view illustrating an example of a schematic configuration of the adapter after the memory card according to the fifteenth embodiment is inserted. [Figure 14A] FIG. 14A is a cross-sectional view illustrating an example of a schematic configuration of the adapter before the memory card according to the sixteenth embodiment is inserted. [Figure 14B] FIG. 14B is a plan view illustrating an example of a schematic configuration of the adapter before the memory card according to the sixteenth embodiment is inserted. [Figure 14C] FIG. 14C is a cross-sectional view illustrating an example of a schematic configuration of the adapter after the memory card according to the sixteenth embodiment is inserted. [Figure 14D] FIG. 14D is a plan view illustrating an example of a schematic configuration of the adapter after the memory card according to the sixteenth embodiment is inserted. [Figure 15A] FIG. 15A is a cross-sectional view illustrating an example of a schematic configuration of the adapter before the memory card according to the seventeenth embodiment is inserted. [Figure 15B] FIG. 15B is a plan view illustrating an example of a schematic configuration of the adapter before the memory card according to the seventeenth embodiment is inserted. [Figure 15C] FIG. 15C is a cross-sectional view illustrating an example of a schematic configuration of the adapter after the memory card according to the seventeenth embodiment is inserted. [Figure 15D]FIG. 15D is a plan view illustrating an example of a schematic configuration of an adapter after a memory card according to a seventeenth embodiment is mounted. [Figure 16A] FIG. 16A is a perspective view illustrating a schematic configuration of a memory card according to an eighteenth embodiment. [Figure 16B] FIG. 16B is a cross-sectional view illustrating an example of a schematic configuration of an adapter before a memory card according to a nineteenth embodiment is mounted. [Figure 16C] FIG. 16C is a perspective view illustrating a schematic configuration of a memory card according to a twentieth embodiment. [Figure 16D] FIG. 16D is a cross-sectional view illustrating a state of the adapter after the memory card of FIG. 16C is mounted. [Figure 17] FIG. 17 is a plan view illustrating an example of a schematic configuration of an adapter after a memory card according to a twenty-first embodiment is mounted. [Figure 18] FIG. 18 is a plan view illustrating a schematic configuration of a memory card according to a twenty-second embodiment. DESCRIPTION OF EMBODIMENTS

[0006] A memory card, a host device, a connector for a memory card, and an adapter for a memory card according to embodiments will be described in detail below with reference to the accompanying drawings. The present invention is not limited to these embodiments. In the following embodiments, an SD card is taken as an example of the memory card, but other cards such as a multimedia card may also be used.

[0007] (First Embodiment) FIG. 1 is a plan view illustrating a schematic configuration of a memory card according to a first embodiment. In FIG. 1, rows R1 and R2 are provided on the card surface of a memory card SD1. Terminal groups PA1 and PA2 are respectively provided in the rows R1 and R2. The row R1 can specify an area where terminals of the terminal group PA1 are arranged side by side in the lateral direction. The row R2 can specify an area where terminals of the terminal group PA2 are arranged side by side in the lateral direction.

[0008] The dimensions of the terminals in each terminal group PA1 and PA2 may be different, and the spacing between the terminals in each terminal group PA1 and PA2 may be different. In row R1, the position of each terminal in terminal group PA1 may be shifted vertically. In row R2, the position of each terminal in terminal group PA2 may be shifted vertically.

[0009] The form factor of this memory card SD1 can be made compatible with microSD cards. In this case, the vertical dimension A1 of the memory card SD1 can be set to 15mm, the horizontal dimension B1 to 11mm, and the thickness to 1.0mm.

[0010] Each row R1 and R2 is assigned a signal used for communication conforming to a single interface standard. In this case, it is possible to prevent a single row from being assigned signals used for communication conforming to multiple interface standards. However, a signal used for communication conforming to a single interface standard may be assigned to multiple rows.

[0011] Row R1 is assigned a signal used for communication in the first mode compliant with the SD standard. Single-ended signals can be used for communication in the first mode compliant with the SD standard. In other words, single-ended signals are compliant with the SD standard. In the first mode compliant with the SD standard, terminal group PA1 is assigned the power supply VDD, ground potential VSS, command CMD, clock CLK, and data DAT[3:0].

[0012] In the first mode, which is compliant with the SD standard, communication can be performed in accordance with DS (Default Speed), HS (High Speed), or UHS (Ultra High Speed)-I. The maximum transfer speed for DS is 12.5 MB / s, for HS it is 25 MB / s, and for UHS-I it is 104 MB / s.

[0013] Row R2 is assigned signals used for communication in a second mode compliant with the PCIe (Peripheral Component Interconnect express) standard. In this second mode compliant with the PCIe standard, differential signals can be used for data communication. In this second mode compliant with the PCIe standard, the terminal group PA2 is assigned the transmit differential signals TX0P and TX0N, and the receive differential signals RX0P and RX0N. Bidirectional communication can be performed using the transmit differential signals TX0P and TX0N and the receive differential signals RX0P and RX0N. In this case, in row R2, the GND terminals at ground potential are assigned to each of the terminals to which the differential signals are assigned, sandwiching them.

[0014] Furthermore, in row R2, one terminal of terminal group PA2 is assigned to power terminal VDD2 or power terminal VDD3, and another terminal of terminal group PA2 is assigned to power terminal VDD2. In addition, yet another terminal of terminal group PA2 is assigned to SWIO. SWIO can be used for NFC (Near Field Communication).

[0015] In the first mode, which is compliant with the SD standard, the clock CLK and data DAT[3:0] are assigned to separate terminals. Therefore, the clock CLK and data DAT[3:0] are transmitted via separate transmission paths.

[0016] In the second mode, which complies with the PCIe standard, data is transmitted serially, but the data is coded in units such that the same voltage level does not persist for long periods, so that the receiving circuit can generate a clock. Methods such as 8B10B and 128b / 130b are used for coding. The receiving side can receive data even if the voltage level fluctuates slightly by generating a clock from the points where the data changes. Even when there are multiple lanes (pairs of upstream and downstream differential data signals), lane skew can be canceled by configuring an independent receiving circuit for each lane and aligning the starting position of the received data.

[0017] For example, in the second mode, which complies with the PCIe 3.0 standard, the maximum transfer speed is 2 GB / second per lane (total of uplink and downlink). In the second mode, which complies with the PCIe standard, one lane can be configured with a pair of transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N. A pair of transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N can be placed in one row of the memory card SD1.

[0018] Therefore, by increasing the number of rows in the memory card SD1, the number of lanes in the second mode compliant with the PCIe standard can be increased, thereby improving the transfer speed of the second mode compliant with the PCIe standard. In the second mode compliant with the PCIe standard, a multi-lane configuration is recognized during initialization, and a single piece of data can be transferred using multiple lanes.

[0019] When communicating in a second mode compliant with the PCIe standard, the control signals used to control communication in this second PCIe mode are assigned to row R1. These control signals can be the reference differential clock signal REFCLKp / n, the reset signal PERST, or the power management control signal CLKREQ. Additionally, the wake-up signal PEWAKE may also be used. These control signals are assigned in place of the command CMD and data DAT[3:0] of row R1.

[0020] The reference differential clock signal REFCLKp / n, consisting of two signals, forms a differential clock. By sending the clock from the host device, the memory card SD1 can easily synchronize with the host device in which it is installed. However, the reference differential clock signal REFCLKp / n is assigned to row R1, while the transmit differential signals TX0P and TX0N and the receive differential signals RX0P and RX0N are assigned to rows R2 and beyond. Therefore, the reference differential clock signal REFCLKp / n is transmitted on a separate transmission path from the transmit differential signals TX0P and TX0N and the receive differential signals RX0P and RX0N.

[0021] The host device may be, for example, an information processing device such as a personal computer, a mobile phone, a digital camera, or an imaging device; it may also be a mobile terminal such as a tablet computer or a smartphone; it may also be a game console; or it may be an in-vehicle terminal such as a car navigation system.

[0022] Memory card SD1 generates a bit clock by multiplying the received reference differential clock. Data is output from the transmit differential signals TX0P and TX0N in synchronization with the bit clock, and data read from the receive differential signals RX0P and RX0N is aligned in synchronization with the bit clock. Even with multiple lanes, the data can be aligned as a single data set in synchronization with the bit clock.

[0023] The reset signal PERST can be used by a host device to reset the bus used for communication in the second mode compliant with the PCIe standard. This reset signal PERST can also be used by the host device to reinitialize the card in the event of an error.

[0024] The power management control signal CLKREQ can be used as a clock to return from power-saving mode. In power-saving mode, power consumption can be reduced by stopping the high-frequency bit clock used for data transfer.

[0025] If the wake-up signal PEWAKE is implemented on memory card SD1, it can be used by memory card SD1 to notify the host device of various events in power-saving mode. When the host device receives the wake-up signal PEWAKE from memory card SD1, it can exit power-saving mode and process the event. Some memory cards also implement I / O functionality and can be used as a means of notifying I / O interrupts.

[0026] In row R2, one terminal of terminal group PA2 is assigned to either power terminal VDD2 or power terminal VDD3. For power terminal VDD in row R1, the host device can supply power voltage VDD1. Power voltage VDD1 can be set to 3.3V. For power terminal VDD2 in row R2, power voltage VDD2 can be supplied. Power voltage VDD2 can be set to 1.8V. Alternatively, for power terminal VDD3 in row R2, power voltage VDD3 can be supplied. Power voltage VDD3 can be set to 1.2V. The power voltage notation indicates the median value, and a certain range of voltage fluctuation is acceptable. For example, the acceptable range for 3.3V is 2.7V to 3.6V, for 1.8V it is 1.70V to 1.95V, and for 1.2V it is 1.1V to 1.3V.

[0027] The explanation below assumes the existence of power terminal VDD3. However, if memory card SD1, which supports power voltage VDD3, does not have power terminal VDD3, it can use power terminal VDD2 of row R2 to supply power voltage VDD2 or power voltage VDD3. Specifically, power voltage VDD2 will be 1.8V or 1.2V. In other words, there are cases where memory card SD1 does not have power terminal VDD3, but the rest of the explanation remains the same, simply by changing the recipient of power voltage VDD3 to power terminal VDD2. The above explanation described how the signal used for communication in the second mode compliant with the PCIe standard is assigned to row R2, but the signal used for communication in UHS-II may also be assigned to row R2. The maximum transfer speed of UHS-II is 312 MB / second.

[0028] Here, to determine whether memory card SD1 communicates in a second mode compatible with the UHS-II standard or a second mode compatible with the PCIe standard, power supply voltage VDD2 or power supply voltage VDD3 can be used. If a power supply voltage is applied to power supply terminal VDD2 or power supply terminal VDD3 of terminal group PA2, memory card SD1 can communicate in PCIe bus mode if it supports the PCIe standard.

[0029] Alternatively, the system can detect and switch based on changes in the power supply voltage VDD2 or VDD3. When VDD2 or VDD3 changes from off to on, the system enters PCIe bus mode; when it changes from on to off, it exits PCIe bus mode. This allows the system to operate in SD mode regardless of whether VDD2 or VDD3 is on or off.

[0030] Host devices using the UHS-II standard apply power supply voltage VDD2 to power terminal VDD2, while host devices using the PCIe standard apply power supply voltage VDD2 to power terminal VDD2, or power supply voltage VDD3 to power terminal VDD3. The memory card SD1 can easily determine the bus mode expected by the host device based on the combination of the presence or absence of VDD2 / VDD3 voltages. Therefore, the memory card SD1 does not need to determine the bus mode based on the symbols sent to the data.

[0031] To enable the host device to recognize whether memory card SD1 supports the PCIe standard or the UHS-II standard, a PCIe-compatible host device can send a predetermined PCIe symbol to the PA2 pin group on row R2 to indicate PCIe support. If memory card SD1 responds to this symbol, the host device can recognize that memory card SD1 supports the PCIe standard. A UHS-II-compatible host device can send a UHS-II initialization symbol to the PA2 pin group on row R2. If memory card SD1 responds to this symbol, the host device can recognize that memory card SD1 supports UHS-II.

[0032] Here, by assigning the signal used for communication in the second mode compliant with the PCIe standard to row R2, the data transfer speed can be increased by enabling the memory card SD1 to support PCIe communication. As the storage capacity of the memory card SD1 increases, the time required to access the entire memory area increases, but this time can be shortened by further increasing the bus speed through methods such as a multi-lane configuration.

[0033] Furthermore, because the memory card SD1 supports PCIe communication, it can utilize the standard PCIe physical layer (PHY). This simplifies the design process for increasing the data transfer speed of the memory card SD1 and reduces development costs.

[0034] Furthermore, because the SD1 memory card supports PCIe communication, NVMe (Non-Volatile Memory Express) can be used for the PCIe data link layer. This reduces overhead during data transfer and improves data transfer efficiency.

[0035] (Second Embodiment) Figure 2 is a plan view showing the schematic configuration of a memory card according to the second embodiment.

[0036] In Figure 2, rows R1 to R4 are provided on the card surface of memory card SD2. Rows R1 and R2 are provided with terminal groups PA1 and PA2, respectively. Rows R1 and R2 can be used in the same way as memory card SD1 in Figure 1. For example, UHS-II can be supported on row R2, and PCIe standards can be supported on rows R3 and R4.

[0037] Rows R3 and R4 are provided with terminal groups PA3 and PA4, respectively. Row R3 can specify the area where the terminals of terminal group PA3 are arranged horizontally. Row R4 can specify the area where the terminals of terminal group PA4 are arranged horizontally. The form factor of this memory card SD2 can be made compatible with microSD cards. Note that if rows R3 and R4 are provided on the memory card SD2, row R2 can be optional (it may be omitted).

[0038] In Figure 2, rows R3 and R4 are shown as an example of a two-tiered configuration. However, each row represents a collection of terminals necessary for the configuration of one lane and does not restrict the placement of terminals on the memory card. For example, the two tiers of pads may be arranged in a staggered pattern, or rows R3 and R4 may be arranged in a single column in a U-shape.

[0039] The area of ​​each terminal in terminal groups PA3 and PA4 can be made smaller than the area of ​​each terminal in terminal groups PA1 and PA2. Depending on the connector contact method, the shapes of each terminal in terminal groups PA3 and PA4 can be made equal. By reducing the area of ​​each terminal in terminal groups PA3 and PA4, parasitic capacitance can be reduced, and the stub when contact is made with the terminal can be reduced, thereby improving the frequency characteristics. Here, "stub" refers to the piece of terminal that is created in the part that does not come into contact with the connector pin when contact is made with the terminal of the memory card SD2. In addition, by making the shapes of each terminal in terminal groups PA3 and PA4 equal, the symmetry of the electrical characteristics of the differential signals that make up the lanes can be improved.

[0040] Each row R3 and R4 is assigned signals used for PCIe communication. The PA3 terminal group of row R3 is assigned the transmit differential signals TX0P and TX0N, and the receive differential signals RX0P and RX0N. The PA4 terminal group of row R4 is assigned the transmit differential signals TX1P and TX1N, and the receive differential signals RX1P and RX1N.

[0041] Here, one row can constitute one lane of the PCIe standard. Therefore, by assigning the signals used for PCIe communication to rows R3 and R4, two PCIe lanes can be configured, doubling the data transfer speed compared to the method where the signals used for PCIe communication are assigned to one row.

[0042] Even when using two rows R3 and R4 to communicate according to the PCIe standard, the control signal used to control PCIe communication is assigned to row R1. In this case, the control signal assigned to row R1 can be shared by the two rows R3 and R4.

[0043] In row R3, one terminal of terminal group PA3 is assigned the power terminal VDD3. The power terminal VDD3 of row R3 can be supplied with the power voltage VDD3. The power terminal VDD3 of terminal group PA3 can be shared by rows R3 and R4. The power voltage VDD3 can be used to determine whether the memory card SD2 communicates in a first mode compliant with the SD standard or in a second mode compliant with the PCIe standard.

[0044] Furthermore, in each row R3 and R4, a GND terminal with ground potential is assigned so that it is flanked by the terminals to which differential signals are assigned. For example, in row R3, the received differential signals RX0N, RX0P, TX0N, and TX0P are assigned to the 2nd, 3rd, 6th, and 7th terminals from the right. At this time, the ground potential GND is assigned to the 1st, 4th, 5th, and 8th terminals from the right of row R3.

[0045] However, the memory card may have the configuration shown in Figure 3, in which a power supply terminal is placed in place of one of the two GND terminals surrounding the differential signal terminal, compared to the configuration shown in Figure 2. The power supply terminal can be a power supply terminal that is compatible with a stable power supply. Figure 3 is a plan view showing another schematic configuration of the memory card according to the second embodiment.

[0046] Here, by assigning a ground potential (GND) to the terminals flanking the terminals to which differential signals are assigned, a return path can be secured for each differential signal, thereby reducing mutual interference between differential signals.

[0047] In the example shown in Figure 2 or Figure 3, a method was described in which a ground potential GND is independently assigned to each differential signal. However, if there is sufficient noise margin against mutual interference between differential signals, adjacent terminals to which a ground potential GND is assigned may be shared. For example, in row R3, either the fourth or fifth terminal from the right to which a ground potential GND is assigned may be omitted. This reduces the number of terminals provided in each row R3 and R4, and makes it easy to accommodate limitations on the number of terminals that can be placed in one row of the memory card SD2.

[0048] Furthermore, although the example in Figure 2 or Figure 3 describes a method of providing rows R3 and R4 on the memory card SD2, row R4 may be omitted.

[0049] Furthermore, while the example in Figure 2 or Figure 3 describes a method of providing two rows R3 and R4 in addition to rows R1 and R2, it is also possible to provide three or more rows in addition to rows R1 and R2. For example, rows R5 and R6 may be added. Here, since the memory card SD2 supports PCIe communication, the number of lanes can be increased by increasing the number of rows, and thus it is possible to easily accommodate increased data transfer speeds.

[0050] In other words, N (where N is an integer greater than or equal to 2) rows can be provided on the surface of the memory card. The first row can communicate data in a first mode compliant with the SD standard, while the second to the Nth row can communicate data using the PCIe standard. The second row may be allocated as a PCIe lane, but it does not have to be used because the shape of the pads is different from the third row onward. If the number of PCIe lanes is X, then data communication can be performed using X lanes according to the PCIe standard, and for example, the maximum transfer speed of the PCIe 3.0 standard can be achieved at X × 2 GB / sec (bidirectional).

[0051] (Third embodiment) Figure 4A is a plan view showing the schematic configuration of a memory card according to the third embodiment.

[0052] In the microSD form factor, there are three possible combinations: one with and one without row R2, and one with and one without rows R3 and R4.

[0053] (1) Case with row R2, but without rows R3 and R4 (Case shown in Figure 1) Row R2 is assigned either a UHS-II differential signal or one PCIe differential signal lane. Which is supported is identified during initialization (both may be supported). Furthermore, row R2 may or may not have a power terminal VDD3; if VDD3 is present, 1.2V is applied. If VDD3 is absent, power terminal VDD2 is used, and 1.8V or 1.2V is applied to VDD2.

[0054] (2) Case without row R2, with rows R3 and R4 (Case shown in Figure 4A) Rows R3 and R4 are allocated two differential signal lanes according to the PCIe standard. The power supply voltage VDD3 is located on row R3. UHS-II is not supported.

[0055] (3) Case with row R2, row R3 and R4 (Case shown in Figure 2) Row R2 is assigned to UHS-II differential signals, while rows R3 and R4 are assigned two lanes of PCIe differential signals. Furthermore, row R2 may or may not have a power terminal VDD3. If power terminal VDD3 is present, 1.2V is applied. If power terminal VDD3 is absent, power terminal VDD2 may be used, or the power terminal VDD3 of row R3 may be used. If power terminal VDD2 is used, 1.8V or 1.2V is applied. In addition, in the second mode compliant with the PCIe standard, row R2 can be used as an interface for other purposes.

[0056] Rows R1, R3, and R4 of memory card SD3 can be used in the same way as rows R1, R3, and R4 of memory card SD2 in Figure 2.

[0057] By removing row R2 from memory card SD2, the available space on the card surface of memory card SD3 can be increased. This can be used, for example, as a contact area for heat dissipation.

[0058] (Fourth Embodiment) Figure 4C is a plan view showing the schematic configuration of a memory card according to the fourth embodiment.

[0059] In Figure 4C, rows R1, R3, and R4 are provided on the card surface of the memory card SD5. A terminal group PC1 is provided on row R1. Signals used for communication in the first mode, which is compliant with the SD standard, are assigned to row R1. At this time, on row R1, terminal 4 is assigned the power supply VDD, terminals 3 and 6 are assigned the ground potential VSS, terminal 2 is assigned the command CMD, terminal 5 is assigned the clock CLK, and terminals 1, 9, 8, and 7 are assigned the data DAT[3:0].

[0060] Rows R3 and R4 are provided with terminal groups PC3 and PC4, respectively, allowing for a two-lane configuration. The form factor of this memory card SD5 can be made compatible with standard-sized SD cards. In this case, the vertical dimension A2 of the memory card SD5 can be set to 32mm, the horizontal dimension B2 to 24mm, and the thickness to 2.1mm.

[0061] The R1, R3 / R4 rows of the SD5 memory card can be used in the same way as the R1, R3, and R4 rows of the SD2 memory card. This allows the SD5 memory card to support communication in a second mode compliant with the PCIe standard, even when its form factor is compatible with standard-sized SD cards, thereby increasing data transfer speeds.

[0062] (Fifth embodiment) Figure 4B is a plan view showing the schematic configuration of a memory card according to the fifth embodiment.

[0063] In Figure 4B, rows R1, R3, and R4 are provided on the card surface of the Moricard SD4. A terminal group PB1 is provided on row R1. Signals used for communication in the first mode, compliant with the SD standard, are assigned to row R1. The terminal group PB1 in Figure 4B is shown as an example where it has the same shape as the terminal group PA1 in Figure 4A, but the shape of the terminal group PB1 may be the same as, or a similar small pad shape to, the terminal shapes of rows R3 and R4. By using an adapter, it is possible to maintain compatibility by converting to the form factor of Figure 4C.

[0064] Rows R3 and R4 are provided with terminal groups PB3 and PB4, respectively. The form factor of this memory card SD4 can volumetrically encompass the form factor of a microSD card and volumetrically encompass the form factor of a standard-sized SD card. In this case, the vertical dimension A3 of the memory card SD4 can be set in the range of 16mm to 20mm, the horizontal dimension B3 in the range of 12mm to 16mm, and the thickness in the range of 1.4mm to 1.6mm.

[0065] Here, the form factor of the memory card SD4, by volumetrically encompassing the form factor of a microSD card, allows the NAND flash memory to be housed in the memory card SD4 even when the chip size of the NAND flash memory increases, thus accommodating the increase in storage capacity of the NAND flash memory.

[0066] Furthermore, the form factor of the SD4 memory card is volumetrically contained within the form factor of a standard-sized SD card, thus suppressing an increase in the size of the SD4 memory card. This ensures the compactness of the SD4 memory card, allowing it to be used in mobile devices such as smartphones and digital cameras.

[0067] Rows R1, R3, and R4 of the SD4 memory card can be used in the same way as rows R1, R3, and R4 of the SD5 memory card and rows R1, R3, and R4 of the SD3 memory card. This allows for PCIe communication support even when the form factor of the SD4 memory card differs from that of microSD cards and standard-sized SD cards, enabling access to the memory area regardless of the form factor.

[0068] Furthermore, the dimensions, shape, and spacing of the terminals located on rows R3 and R4 can be standardized across memory cards SD2 to SD5. This allows the connectors that make contact with the terminals located on rows R3 and R4 to be standardized across memory cards SD2 to SD5.

[0069] (Sixth Embodiment) Figure 5 is a block diagram illustrating the schematic configuration of a memory card according to the sixth embodiment. Note that the configuration in Figure 5 can be used for any of the memory cards SD1 to SD5 shown in Figures 1, 2, and 4A to 4C. In the following description, we will use the case where the configuration in Figure 5 is applied to the memory card SD2 in Figure 2 as an example.

[0070] In Figure 5, the memory card SD2 is provided with regulators 11 and 12, a comparator 13, a card controller 14, a memory interface circuit 15, and a memory 16. The memory 16 can use NAND flash memory. The card controller 14 can perform read / write control to the memory 16 and control communication with the outside world. This communication control can include protocol control corresponding to a first mode compliant with the SD standard and protocol control corresponding to the PCIe standard. The card controller 14 is provided with an IO cell 17, a physical layer interface 18, and a card interface circuit 19.

[0071] IO cell 17 can handle single-ended signals. IO cell 17 can handle signals assigned to row R1. IO cell 17 is provided with input buffers V1 and V3 and output buffer V2. Input buffer V1 can accept a clock CLK. Input buffer V3 can accept a command CMD and data DAT[3:0]. Output buffer V2 can output a response to the command CMD and data DAT[3:0]. Input buffer V3 and output buffer V2 can be provided for each command CMD and data DAT[3:0].

[0072] The physical layer interface 18 can handle differential signals. The physical layer interface 18 can handle signals assigned to rows R2, R3, and R4. The physical layer interface 18 is provided with a receiver RE and a transmitter TR. The receiver RE can receive the received differential signals RX0P and RX0N from rows R2 and R3, and the received differential signals RX1P and RX1N from row R4. The transmitter TR can output the transmitted differential signals TX0P and TX0N from rows R2 and R3, and the transmitted differential signals TX1P and TX1N from row R4. The receiver RE and transmitter TR can be provided for each of the rows R2, R3, and R4. For row R2, the physical layer interface 18 can have the same configuration whether it is a second mode compliant with the UHS-II standard or a second mode compliant with the PCIe standard.

[0073] The IO cell 17 and the physical layer interface 18 are connected to the card interface circuit 19. The card controller 14 is connected to the memory 16 via the memory interface circuit 15. In order for the memory card SD2 to support the PCIe standard, the card controller 14 can be provided with a PCIe standard physical layer interface 18, as well as a PCIe standard data link layer and transaction layer. The physical layer interface 18 can perform serial / parallel conversion, parallel / serial conversion, and data symbolization. This symbolization is a process that limits the number of consecutive occurrences of the same value when data consists of consecutive 0s or 1s to a predetermined value or less. This symbolization can suppress voltage level bias during data transmission. Furthermore, by using symbols that do not amplify harmonics of specific frequencies, EMI (Electromagnetic Interference) can also be suppressed.

[0074] Furthermore, the PCIe transaction layer allows for data to be packetized and commands and other information to be added to the packet header. The PCIe data link layer allows for the addition of sequence numbers and CRC (Cyclic Redundancy Check) codes to packets received from the transaction layer. Sequence numbers can be used for purposes such as confirming packet delivery.

[0075] The power supply voltage VDD1 is supplied to the regulator 11, the card controller 14, the memory interface circuit 15, and the memory 16. The power supply voltage VDD1 supplied to the regulator 11 is converted to the power supply voltage VDDL and supplied to the card controller 14 and the memory interface circuit 15. The power supply voltage VDDL is determined according to the technology of the card controller. The memory interface circuit 15 is a level shifter circuit if the interface voltage of the card controller 14 and the interface voltage of the memory 16 are different.

[0076] In the first mode (DS, HS, or UHS-I) compliant with the SD standard, the card is configured to operate with only the power supply voltage VDD1. In UHS-7 mode, the card controller 14 and memory interface circuit 15 can use a power supply voltage VDDL of 1.8V. In this case, the IO cell 17 can switch the output signal voltage and input threshold according to the power supply voltages VDD1 and VDDL. Voltage VDD2 can be supplied optionally.

[0077] The power supply voltage VDD3 is supplied to the regulator 12 and the comparator 13. The power supply voltage VDD3 supplied to the regulator 12 is converted to the power supply voltage VDDPHY required to operate the physical layer interface 18 and supplied to the physical layer interface 18.

[0078] The power supply voltage VDD3 supplied to the comparator 13 is compared with a reference voltage. Based on the comparison result, the application of the power supply voltage VDD3 is detected, and the detection signal VDD3SP is output to the card controller 14. Although not shown in the diagram, similarly when using power supply voltage VDD2, power supply voltage VDD2 is supplied to regulator 12 and comparator 13, converted to power supply voltage VDDPHY required to operate the physical layer interface 18, supplied to the physical layer interface 18, and the detection signal VDD3SP is output to card controller 14.

[0079] If the comparator 13 does not detect the application of the power supply voltage VDD3, the memory card SD2 communicates in a first mode compliant with the SD standard. At this time, the clock CLK sent from the host device to the memory card SD2 is transmitted to the card interface circuit 19 via the input buffer V1. The command CMD and data DAT[3:0] sent from the host device to the memory card SD2 are transmitted to the card interface circuit 19 via the input buffer V3. The response to the command CMD and data DAT[3:0] sent from the card interface circuit 19 are transmitted to the host device via the output buffer V2.

[0080] When comparator 13 detects the application of power supply voltage VDD2 or power supply voltage VDD3, memory card SD2 communicates in a second mode compliant with the PCIe standard. At this time, memory card SD2 can communicate data via rows R3 and R4, and control signals via row R1. The control signals assigned to row R1 are the reference differential clock signal REFCLKp / n, the reset signal PERST, the power management control signal CLKREQ, and the wake-up signal PEWAKE, instead of the command CMD and data DAT[3:0]. However, implementation of the wake-up signal PEWAKE is not mandatory.

[0081] When the host device transmits the serial receive differential signals RX0P, RX0N, RX1P, and RX1N to the memory card SD2, the receiver RE converts them into the parallel data receive signal Rx and transmits them to the card interface circuit 19. When the card interface circuit 19 transmits the parallel data transmit signal Tx to the transmitter TR, the transmit signal Tx is converted into the serial transmit differential signals TX0P, TX0N, TX1P, and TX1N and transmits them to the host device.

[0082] (Seventh Embodiment) Figure 6 is a block diagram showing a schematic configuration of a host device equipped with a memory card according to the seventh embodiment.

[0083] In Figure 6, the host device is equipped with a system controller 21 and a system memory 27. The system controller 21 is equipped with a root complex 22, an SD host controller 23, a first row switch 24, a connector 25, and a memory controller 26. The memory controller 26 is connected to the system memory 27.

[0084] The root complex 22 can control access to system memory by arbitrating multiple PCIe lanes. It can also arbitrate data transfer between devices connected to PCIe lanes and system memory. When the root complex 22 has multiple PCIe lanes, it can connect multiple PCIe devices (including memory cards) in a star-star configuration. Multiple lanes can also be assigned to a single device. The SD host controller 23 can be used to control the memory card SD2 in a first mode compliant with the SD standard. The first row switch 24 can switch whether row R1 is used for communication in a first mode compliant with the SD standard or for communication in a second mode compliant with the PCIe standard, based on the selection signal R1SEL.

[0085] Connector 25 can make contact with the memory card SD2. In this case, the form factor of connector 25 can be made compatible with a microSD card. Connector 25 can be provided with a group of connector contact terminals corresponding to the card terminals of the memory card SD2 in order to make contact with the memory card SD2. The card terminals of the memory card SD2 are the terminals PA1 to PA4 in Figure 2. Connector 25 also has a group of connector terminals for connecting to a host controller. In the following explanation, in order to distinguish between the terminals on the memory card and the terminals on the connector, the terminals on the memory card will be referred to as the card terminals, and the terminals on the connector will be referred to as the connector terminals.

[0086] The power supply voltage VDD3 is applied to connector 25, and if power supply voltage VDD3 is not applied, power supply voltage VDD2 is applied. The memory controller 26 can control the operation of the system memory 27.

[0087] The root complex 22 is provided with physical layer interfaces 22A, 22C, and 22E, and I / O cells 22B, 22D, and 22F. Each physical layer interface 22A, 22C, and 22E is a PCIe standard differential signal interface, while I / O cells 22B, 22D, and 22F are PCIe standard single-ended signal and differential reference clock interfaces.

[0088] The physical layer interface 22A and IO cell 22B are connected to the SD host controller 23. At this time, the root complex 22 can communicate with the SD host controller 23 using differential signal DS1 and control signal CS1. The physical layer interface 22C is connected to connector 25. IO cell 22D is connected to the first row switch 24. The physical layer interface 22E and IO cell 22F are connected to the M.2 slot. M.2 supports SATA (Serial Advanced Technology Attachment) and PCIe standards, allowing connection of various PCIe devices. The SD host controller 23 is connected to connector 25 via the first row switch 24.

[0089] When the selection signal R1SEL selects communication in the first mode compliant with the SD standard, the first row switch 24 switches row R1 of the memory card SD2 to the SD host controller 23 side. Then, the SD bus signal BS output from the SD host controller 23 is assigned to row R1, and communication between the SD host controller 23 and the memory card SD2 takes place in the first mode compliant with the SD standard. The SD bus signal BS can include the command CMD, clock CLK, and data DAT[3:0].

[0090] If the selection signal R1SEL selects the second mode of communication compliant with the PCIe standard, the first row switch 24 switches row R1 of the memory card SD2 to the IO cell 22D side. Then, the control signal CS2 is assigned to row R1. This control signal CS2 may include the reference differential clock signal REFCLKp / n, the reset signal PERST, and the power management control signal CLKREQ. In addition, this control signal CS2 may also include the wake-up signal PEWAKE.

[0091] Furthermore, differential signals DS2 are transmitted and received between the physical layer interface 22C and rows R3 and R4 of the memory card SD2. These differential signals DS2 can include received differential signals RX0P, RX0N, RX1P, RX1N and transmitted differential signals TX0P, TX0N, TX1P, TX1N. This allows the root complex 22 and the memory card SD2 to communicate in a second mode compliant with the PCIe standard.

[0092] The selection signal R1SEL can be set based on whether power supply voltage VDD2 or VDD3 is applied. The initialization state can be controlled by detecting the change point (off to on, on to off) in power supply voltage VDD2 or VDD3. Alternatively, a register may be provided in the system controller 21 or the like, and the selection signal R1SEL may be set based on the value stored in this register. By setting the selection signal R1SEL based on the value stored in the register, it is possible to switch between communication in a first mode compliant with the SD standard and communication in a second mode compliant with the PCIe standard, regardless of whether the power supply voltage VDD3 is used or not.

[0093] In the embodiment shown in Figure 6, a configuration is shown in which a connector 25 capable of inserting memory card SD2 is implemented on the host device. However, connectors capable of inserting memory cards SD1, SD3 to SD5 may also be implemented on the host device. The form factor of the connectors capable of inserting memory cards SD1 and SD3 can be made compatible with microSD cards. The form factor of the connector capable of inserting memory card SD4 can encompass the form factor compatible with microSD cards and be encompassed within the form factor compatible with standard-sized SD cards. The form factor of the connector capable of inserting memory card SD5 can be made compatible with standard-sized SD cards and can encompass the form factor compatible with microSD cards and the form factor of card SD4.

[0094] (Eighth embodiment) Figure 7 is a block diagram showing a schematic configuration of an interface card with a memory card installed according to the eighth embodiment.

[0095] In Figure 7, the interface card 31 is provided with a bridge 32, an SD host controller 33, a first row switch 34, and a connector 35.

[0096] The bridge 32 can switch to a second mode of communication compliant with the PCIe standard by installing an interface card 31 in a PCIe slot or M.2 slot. The SD host controller 33, first row switch 34, and connector 35 can be configured in the same way as the SD host controller 23, first row switch 24, and connector 25 in Figure 6.

[0097] Bridge 32 is provided with physical layer interfaces 32A and 32C and I / O cells 32B and 32D. Each physical layer interface 32A and 32C can interface with PCIe standard differential signals. I / O cells 32B and 32D can interface with PCIe standard single-ended signals and differential reference clocks.

[0098] The physical layer interface 32A and IO cell 32B are connected to the SD host controller 33. At this time, the bridge 32 can communicate with the SD host controller 33 using the differential signal DS1 and the control signal CS1. The physical layer interface 32C is connected to the connector 35. The IO cell 32D is connected to the first row switch 34.

[0099] When the selection signal R1SEL selects communication in the first mode compliant with the SD standard, the first row switch 34 switches row R1 of the memory card SD2 to the SD host controller 33. Then, the SD bus signal BS output from the SD host controller 33 is assigned to row R1, and communication between the SD host controller 33 and the memory card SD2 takes place in the first mode compliant with the SD standard.

[0100] When the selection signal R1SEL indicates that communication in the second mode compliant with the PCIe standard is selected, the first row switch 34 switches row R1 of the memory card SD2 to the IO cell 32D side. Then, the control signal CS2 is assigned to row R1. In addition, the differential signal DS2 is transmitted and received between the physical layer interface 32C and rows R3 and R4 of the memory card SD2. Then, communication between the bridge 32 and the memory card SD2 takes place in the second mode compliant with the PCIe standard.

[0101] (Ninth Embodiment) Figure 8 is a flowchart showing the operation of the host device when the bus mode of the memory card according to the ninth embodiment is set. Note that this method for setting the bus mode of the memory card can be used for any of the memory cards SD1 to SD5 shown in Figures 1, 2, and 4A to 4C.

[0102] In Figure 8, the host device supplies power voltages VDD1 and VDD3 to the memory card (S1). Power voltage VDD1 can be supplied to the power terminal VDD of row R1 of the memory card. As shown in Figure 1, if the memory card only has rows R1 and R2, power voltage VDD3 can be supplied to the power terminal VDD3 of row R2 of the memory card, or to power terminal VDD2 if there is no power terminal VDD3. As shown in Figure 2 or Figures 4A to 4C, if the memory card has row R3, power voltage VDD3 can be supplied to the power terminal VDD3 of row R3 of the memory card.

[0103] Although not shown in the diagram, if the power supply voltage VDD3 is not supported, power supply voltage VDD2 is supplied to power supply terminal VDD2 instead.

[0104] At this time, the host device can detect whether a card is installed by monitoring the rise time of the voltage at terminals R3 and R4, to which the transmit differential signals TX0P, TX0N, TX1P, and TX1N are assigned. The host device and the card are connected by an AC coupling capacitor, and charging current flows to the capacitor only when a card is installed. Therefore, when a memory card is installed in the host device, the rise time is longer than when a memory card is not installed in the host device. Accordingly, it is possible to determine whether a memory card is installed in the host device based on this rise time. If it consists of multiple lanes, it is also possible to determine how many lanes are available for communication. And, if a memory card is installed in the host device, the host device can start communication with the memory card.

[0105] Next, the host device selects row R1 as the third bus mode (S2). The third bus mode is a second mode of communication that complies with the PCIe standard.

[0106] Next, the host device sends a symbol to row R2, R3, or R4 (S3) that identifies whether the memory card supports the PCIe standard.

[0107] Then, if a response to the symbol in S3 is sent from the memory card within the specified time (Yes in S4), the host device executes the training sequence (S5). This training sequence allows for the determination of the maximum performance operating frequency supported by both the memory card and the host device.

[0108] Next, the host device sets the communication method with the memory card to the third bus mode (S6).

[0109] On the other hand, if a response to the symbol in S3 is not sent from the memory card within the specified time (No in S4), the host device stops supplying power voltage VDD3 (S7) and supplies power voltage VDD2 to the memory card (S8). Power voltage VDD2 can be supplied to the power terminal VDD2 of row R2 of the memory card.

[0110] Next, the host device selects row R1 as the control terminal for UHS-II mode (S9). Specifically, the differential reference clock is assigned to the two terminals.

[0111] Next, the host device sends a symbol to row R2 that identifies whether the memory card supports UHS-II (S10).

[0112] Then, if a response to the symbol in S10 is sent from the memory card within the specified time (Yes in S11), the host device performs UHS-II mode initialization (S12). This UHS-II mode initialization determines the maximum performance operating frequency supported by both the memory card and the host device.

[0113] Next, the host device sets the communication method with the memory card to the second bus mode (S13). The second bus mode is UHS-II communication.

[0114] On the other hand, if a response to the symbol in S10 is not sent from the memory card within the specified time (No in S11), the host device stops supplying the power voltage VDD2 (S14). Note that stopping the supply of the power voltage VDD2 is optional.

[0115] Next, the host device selects row R1 as the signal terminal for the first mode compliant with the SD standard (S15).

[0116] Next, the host device sends a command to row R1 to perform initialization of the first mode compliant with the SD standard (S16).

[0117] Then, if a response to the command in S16 is sent from the memory card within the specified time (Yes in S17), the host device performs initialization of the first mode compliant with the SD standard (S18). In this initialization of the first mode compliant with the SD standard, the maximum performance SD bus mode and operating frequency supported by both the memory card and the host device can be determined.

[0118] Next, the host device sets the communication method with the memory card to the first bus mode (S19). The first bus mode is a first mode of communication that corresponds to the SD standard.

[0119] On the other hand, if a response to the S16 command is not sent from the memory card within the specified time (S17 No), the host device determines an error and stops the initialization of the first mode compliant with the SD standard (S20). S20 also includes cases where a card other than an SD card is connected.

[0120] For example, suppose the process in Figure 8 is applied to memory card SD1 in Figure 1. At this time, the power supply voltage VDD3 is supplied to the power terminal VDD3 of row R2 of memory card SD1 (S1). If memory card SD1 supports the PCIe standard, there is a response from memory card SD1 when a symbol is sent to row R2 of memory card SD1 (S3) (Yes in S4). Therefore, the host device sets the communication method with memory card SD1 to a second mode that supports the PCIe standard (S6).

[0121] On the other hand, if memory card SD1 supports UHS-II, when a symbol is sent to row R2 of memory card SD1 (S3), there is no response from memory card SD1 (No in S4). Therefore, the power supply voltage VDD3 at the power terminal VDD3 of row R2 of memory card SD1 is stopped (S7), and the power supply voltage VDD2 is supplied to the power terminal VDD2 of row R2 of memory card SD1 (S8). Then, when a symbol is sent to row R2 of memory card SD1 (S10), there is a response from memory card SD1 (Yes in S11). Therefore, the host device sets the communication method with memory card SD1 to UHS-II (S13).

[0122] On the other hand, if memory card SD1 does not support UHS-II, when a symbol is sent to row R2 of memory card SD1 (S10), there is no response from memory card SD1 (No in S11). Then, when a command is sent to row R1 of memory card SD1 (S16), if there is a response from memory card SD1, the host device sets the communication method with memory card SD1 to the first mode that corresponds to the SD standard (S19).

[0123] As another example, the process in Figure 8 is applied to memory card SD3 in Figure 4A. At this time, the power supply voltage VDD3 is supplied to the power terminal VDD3 of row R3 of memory card SD3 (S1). Since memory card SD3 supports the PCIe standard, when a symbol is sent to row R3 of memory card SD3 (S3), there is a response from memory card SD3 (Yes in S4). For this reason, the host device sets the communication method with memory card SD1 to the second mode which is compatible with the PCIe standard (S6).

[0124] On the other hand, when operating memory card SD3 in the first mode compatible with the SD standard, in S1, the power supply voltage VDD3 is not supplied to the power terminal VDD3 of row R3 of memory card SD3. In this case, when a symbol is sent to row R3 of memory card SD3 (S3), there is no response from memory card SD3 (No in S4). Also, since memory card SD3 does not have row R2, when a symbol is sent to row R2 of memory card SD3 (S10), there is no response from memory card SD3 (No in S11). Since memory card SD3 supports the SD standard, when a command is sent to row R1 of memory card SD3 (S16), there is a response from memory card SD3 (Yes in S17). For this reason, the host device sets the communication method with memory card SD3 to the first mode compatible with the SD standard (S19).

[0125] (Tenth embodiment) Figure 9 is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to the 10th embodiment.

[0126] In Figure 9, the host device is provided with a system board 81 and a system controller 83. The system board 81 is provided with a connector 82 and a physical layer interface 84. The physical layer interface 84 is provided with a receiver RE1 and a transmitter TR1. The receiver RE1 can receive the transmit differential signals TX0P and TX0N transmitted from row R2 of the memory card SD1. The transmitter TR1 can output the receive differential signals RX0P and RX0N received at row R2 of the memory card SD1.

[0127] The transmitter TR1 and connector 82 are connected via a differential transmission line TP1. In this configuration, the differential transmission line TP1 can connect the transmitter TR1 and connector 82 via AC coupling capacitors C1 and C2. A switch WT is connected to the AC coupling capacitors C1 and C2. The switch WT can short-circuit the AC coupling capacitors C1 and C2. The implementation of the switch WT is optional.

[0128] Receiver RE1 and connector 82 are connected via differential transmission line TP2. In this configuration, differential transmission line TP2 can connect receiver RE1 and connector 82 via AC coupling capacitors C3 and C4. A switch WR is connected to AC coupling capacitors C3 and C4. The switch WR can short-circuit AC coupling capacitors C3 and C4. The implementation of the switch WR is optional.

[0129] The memory card SD1 is provided with a physical layer interface 85. The physical layer interface 85 can support either the UHS-II standard or the PCIe standard, but not both. The physical layer interface 85 is provided with a receiver RE2 and a transmitter TR2. The receiver RE2 can receive the received differential signals RX0P and RX0N received at row R2 of the memory card SD1 as input. The transmitter TR2 can output the transmitted differential signals TX0P and TX0N transmitted from row R2 of the memory card SD1.

[0130] Receiver RE2 is connected to differential transmission line TP3. Transmitter TR2 is connected to differential transmission line TP4. By inserting memory card SD1 into connector 82, differential transmission lines TP1 and TP3 can be connected to each other, as can differential transmission lines TP2 and TP4.

[0131] If memory card SD1 supports the UHS-II standard, system controller 83 can turn on switches WT and WR and short-circuit AC coupling capacitors C1 to C4.

[0132] On the other hand, if the memory card SD1 supports the PCIe standard, the system controller 83 can turn off switches WT and WR and DC-isolate the physical layer interfaces 84 and 85.

[0133] This allows the system board 81 to be compatible with both UHS-II and PCIe standard memory cards without needing to replace the SD1 memory card itself.

[0134] In the second mode, which complies with the PCIe standard, connecting physical layer interfaces 84 and 85 via AC coupling capacitors C1 to C4 allows for DC isolation between the transmitting and receiving sides of differential signals, enabling independent design of the common voltage levels of physical layer interfaces 84 and 85 for the transmitting and receiving sides (they do not affect each other). On the other hand, if DC coupling is used without AC coupling capacitors, fluctuations in the ground level will affect the signal voltages of both sides, requiring a design that suppresses ground level fluctuations.

[0135] Furthermore, AC coupling capacitors require a capacitance of approximately 200nF, and their size makes it difficult to mount them within the microSD form factor. Therefore, by providing AC coupling capacitors C1 to C4 on the system board 81, it becomes unnecessary to provide AC coupling capacitors C3 and C4 on the memory card SD1, making it easier to manufacture the slim memory card SD1.

[0136] (11th embodiment) Figure 10A is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to the 11th embodiment.

[0137] In Figure 10A, the host device is provided with a system board 81'. The system board 81' is provided with a connector 82 and a physical layer interface 84. The physical layer interface 84 is provided with a receiver RE1 and a transmitter TR1.

[0138] The differential transmission path TP1 from the transmitter TR1 and connector 82 is connected via AC coupling capacitors C1 and C2.

[0139] Receiver RE1 and connector 82 are connected via differential transmission line TP2. In this case, differential transmission line TP2 can directly connect receiver RE1 and connector 82.

[0140] The memory card SD5 is provided with a physical layer interface 85'. The physical layer interface 85' can support the PCIe standard. The physical layer interface 85' is provided with a receiver RE2' and a transmitter TR2'. The receiver RE2' can receive the received differential signals RX0P and RX0N received at row R3 of the memory card SD5 as input. The transmitter TR2' can output the transmitted differential signals TX0P and TX0N transmitted from row R3 of the memory card SD5.

[0141] The receiver RE2' is connected to the differential transmission line TP3. The transmitter TR2' and the differential transmission line TP4 are shown connected via AC coupling capacitors C3 and C4. This is a common implementation method for PCIe devices.

[0142] However, the capacitance range of the AC coupling capacitor is fixed, and it is too large to be implemented in the microSD form factor. In other words, the configuration in Figure 10A is not suitable for application in small removable cards with a thin form factor.

[0143] (12th embodiment) Figure 10B is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to the 12th embodiment.

[0144] In Figure 10B, the host device is provided with a system board 81''. The system board 81'' is provided with a connector 82'' and a physical layer interface 84. The physical layer interface 84 is provided with a receiver RE1 and a transmitter TR1. The connector 82'' is provided with AC coupling capacitors C3 and C4. The AC coupling capacitors C3 and C4 can be electrically inserted between the connector terminal on the memory card SD1 side of the connector 82'' and the connection terminal connected to the physical layer interface 84 of the host device.

[0145] The differential transmission path TP1 from the transmitter TR1 and connector 82' is connected via AC coupling capacitors C1 and C2. The AC coupling capacitors C1 and C2 may also be placed inside the connector 82', which would eliminate the need to reserve space on the PCB for placing C1 and C2.

[0146] Receiver RE1 and connector 82' are connected via differential transmission line TP2. In this case, differential transmission line TP2 can directly connect receiver RE1 and connector 82'. The differential transmission line TP2 on the host device side and the differential transmission line TP4 on the card side are connected within connector 82' via AC coupling capacitors C3 and C4.

[0147] Figure 10B shows a case where AC coupling capacitors C3 and C4 are placed inside the connector. However, AC coupling capacitors C3 and C4 may also be inserted between the receiver RE1 and the differential transmission path TP2 from connector 82' instead of being placed inside the connector. In this case, it is necessary to reserve space on the PCB (Printed Circuit Board) to place the AC coupling capacitors C3 and C4.

[0148] By inserting the memory card SD1 into connector 82', the differential transmission path (transmitting differential transmission path of the host device) TP1 and the differential transmission path (receiving differential transmission path of the memory card SD1) TP3 are connected to each other, and the differential transmission path (receiving differential transmission path of the host device) TP2 and the differential transmission path (transmitting differential transmission path of the memory card SD1) TP4 are connected to each other via AC coupling capacitors C3 and C4.

[0149] By placing the AC coupling capacitors C3 and C4 on connector 82', it becomes unnecessary to place them on the memory card SD1, making it possible to support small removable cards with a thin form factor, such as microSD memory cards. Naturally, it can also be applied to larger form factors.

[0150] (13th Embodiment) Figure 11A is a perspective view showing an example of a schematic configuration of a connector used in a memory card according to the 13th embodiment, and Figure 11B is a cross-sectional view showing an example of a schematic configuration of a connector used in a memory card according to the 13th embodiment. Note that in Figure 11B, two pogo pins of Figure 11A are shown.

[0151] In Figure 11A, this connector can be used to make contact with the terminal groups PA3-PC3 and PA4-PC4 of rows R3 and R4 of memory cards SD2-SD5. This connector is provided with pogo pins 40. The pogo pins 40 can be arranged to correspond to the terminal arrangement of rows R3 and R4.

[0152] As shown in Figure 11B, the pogo pin 40 is provided with a pin 44. The pin 44 is housed in a cylinder 43. Within the cylinder 43, a spring 45 is provided at the bottom of the pin 44, and the pin 44 is supported via the spring 45 in a state where it can move up and down. The pogo pin 40 is supported in an upright position by a housing 42. The housing 42 can be installed on a base 41.

[0153] For example, when making contact with row R3 of memory card SD2, each terminal of the PA3 terminal group of memory card SD2 is pressed against the tip of pin 44. At this time, as pin 44 is pressed down, spring 45 pushes pin 44 upward. As a result, pin 44 can be firmly pressed against the terminal, improving shock resistance. Consequently, even when memory card SD2 is used in environments subject to strong vibrations and shocks, such as automobiles and drones, it is possible to prevent unstable operation of memory card SD2.

[0154] (14th Embodiment) Figure 12A is a cross-sectional view showing an example of the schematic configuration of the connector before the memory card of the 14th embodiment is inserted, Figure 12B is a plan view showing an example of the schematic configuration of the connector before the memory card of the 14th embodiment is inserted, Figure 12C is a cross-sectional view showing an example of the schematic configuration of the connector after the memory card of the 14th embodiment is inserted, and Figure 12D is a plan view showing an example of the schematic configuration of the connector after the memory card of the 14th embodiment is inserted.

[0155] Figures 12B and 12D show the connector with the cover removed. In this embodiment, the connector that makes contact with the memory card SD4 in Figure 4B is used as an example.

[0156] In Figures 12A and 12B, the connector CN1 is provided with a base 51 and a cover 52. The ends of the base 51 and the ends of the cover 52 are connected via a pin 53. At this time, the cover 52 can be opened and closed by rotating the cover 52 around the pin 53 as the axis of rotation.

[0157] A recess 54 is provided in the center of the base 51, extending laterally. A heat dissipation sheet 55 is installed in the recess 54. The heat dissipation sheet 55 can be made of a material with high thermal conductivity and flexibility. For example, an acrylic resin can be used as the material for the heat dissipation sheet 55. In this case, the dimensions of the heat dissipation sheet 55 can be set so that it extends laterally from the base 51. The heat dissipation sheet 55 that extends laterally from the base 51 can be brought into contact with the mounting surface of the connector CN1. The mounting surface of the connector CN1 is, for example, the housing of the host device.

[0158] The base 51 has a connector row R1 terminal group 58 and a connector row R3 / R4 terminal group 59 that connect to the host side, and a connector row R1 contact group and a connector row R3 / R4 contact group that protrude from the surface of the base 51 and connect to the card side, and has lead pins 56 and pogo pins 57 embedded in it. The lead pins 56 can be arranged to correspond to the terminal arrangement of row R1 of the memory card SD4. The pogo pins 57 can be arranged to correspond to the terminal arrangement of rows R3 and R4 of the memory card SD4. The connector row R1 contact group of the lead pins 56 is wired to the connector row R1 terminal group 58 and can be connected to the host device. The connector row R3 / R4 contact group of the pogo pins 57 is wired to the connector row R3 / R4 terminal group 59 and can be connected to the host device.

[0159] When inserting the memory card SD4 into connector CN1, the memory card SD4 is placed on the base 51 with the cover 52 open. Then, by closing the cover 52, the memory card SD4 can be secured to connector CN1.

[0160] At this time, as shown in Figures 12C and 12D, the terminal group PB1 of row R1 of memory card SD4 can be crimped to the lead pin 56, and the terminal groups PB3 and PB4 of rows R3 and R4 of memory card SD4 can be crimped to the pogo pin 57. In addition, the empty space between row R1 and rows R3 and R4 on the card surface of memory card SD4 can be crimped to the heat dissipation sheet 55.

[0161] Here, by using pogo pins 57 to make contact with terminal groups PB3 and PB4 of rows R3 and R4 of the memory card SD4, lateral displacement during contact between terminal groups PB3 and PB4 and pogo pins 57 can be reduced. Therefore, while accommodating the reduction in size of each terminal of terminal groups PB3 and PB4, reliable contact between terminal groups PB3 and PB4 and pogo pins 57 can be ensured.

[0162] Furthermore, by providing a heat dissipation sheet 55 on the connector CN1, the heat generated by the memory card SD4 can be efficiently dissipated to the host device via the heat dissipation sheet 55, thereby improving the heat dissipation performance of the memory card SD4.

[0163] In the above-described embodiment, a method of installing a heat dissipation sheet 55 in the recess 54 of the base 51 was explained, but instead of a heat dissipation sheet 55, a Peltier element may be installed in the recess 54 of the base 51. By using a Peltier element, it becomes possible to forcibly cool the memory card SD4.

[0164] (15th Embodiment) Figure 13A is a cross-sectional view showing an example of the schematic configuration of the adapter before the memory card of the 15th embodiment is inserted, Figure 13B is a plan view showing an example of the schematic configuration of the adapter before the memory card of the 15th embodiment is inserted, Figure 13C is a cross-sectional view showing an example of the schematic configuration of the adapter after the memory card of the 15th embodiment is inserted, and Figure 13D is a plan view showing an example of the schematic configuration of the adapter after the memory card of the 15th embodiment is inserted.

[0165] In this embodiment, an adapter is shown that converts the form factor of memory card SD1 in Figure 1 to the form factor of memory card SD4 in Figure 4B.

[0166] In Figures 13A and 13B, the adapter AP1 is provided with an insertion section IE1 into which the memory card SD1 is inserted. The entrance to the insertion section IE1 can be provided at the rear end of the adapter AP1.

[0167] The surface of adapter AP1 is provided with terminal group DA1, which is the adapter row R1 terminal group that connects to the connector, and terminal groups DA3 and DA4, which are the adapter row R3 / R4 terminal groups. Each terminal in terminal groups DA1, DA3, and DA4 can be arranged to correspond to the terminal arrangement of rows R1, R3, and R4 of memory card SD4, respectively.

[0168] On the inner surface of the insertion section IE1 of adapter AP1, lead pins IA1, which are the adapter row R1 contact group that connects to the memory card side, and lead pins IA2, which are the adapter row R2 contact group. Lead pins IA1 can be arranged in accordance with the terminal arrangement of row R1 of memory card SD1. Lead pins IA2 can be arranged in accordance with the terminal positions of the terminals to which the transmit differential signals TX0P, TX0N, receive differential signals RX0P, RX0N, and power supply VDD of row R2 of memory card SD1 are assigned.

[0169] The adapter row R1 contact group of lead pin IA1 can be wired to the adapter row R1 terminal group of terminal group DA1 and connected to the connector. The adapter row R2 contact group of lead pin IA2 can be wired to the connector row R4 terminal group of terminal group DA4 (or the connector row R3 terminal group of terminal group DA3) and connected to the connector. Figure 5 shows an example of connection to row R4. The wiring of the power terminal VDD3 and data lines is shown with dashed lines, but the wiring to the GND terminal is omitted for clarity.

[0170] Terminal groups DA1, DA3, and DA4 can be used as adapter terminals of adapter AP1. Lead pins IA1 and IA2 can be used as adapter contacts of adapter AP1. The adapter terminals can make contact with the connector contacts when adapter AP1 is mounted on the connector. The adapter contacts can make contact with the card terminals when memory card SD1 is inserted into adapter AP1.

[0171] Lead pin IA1 is connected one-to-one with each terminal of terminal group DA1 via wiring HA1. Lead pin IA2 is connected one-to-one with each terminal of terminal group DA4 (or DA3) via wiring HA2. The host device can recognize whether the card is connected to terminal group DA3 or DA4 during the initialization sequence, so it can be connected to either. Connecting to terminal group DA4 results in shorter wiring, and this example is illustrated.

[0172] When inserting memory card SD1 into adapter AP1, insert memory card SD1 into insertion port IE1 from the rear end of adapter AP1.

[0173] At this time, as shown in Figures 13C and 13D, each terminal of the PA1 terminal group of row R1 of memory card SD1 can be brought into contact with the lead pin IA1, and each terminal of the PA2 terminal group of row R2 of memory card SD1 can be brought into contact with the lead pin IA2. This makes it possible to convert the form factor of memory card SD1 to the form factor of memory card SD4.

[0174] (16th Embodiment) Figure 14A is a cross-sectional view showing an example of the schematic configuration of the adapter before the memory card of the 16th embodiment is inserted, Figure 14B is a plan view showing an example of the schematic configuration of the adapter before the memory card of the 16th embodiment is inserted, Figure 14C is a cross-sectional view showing an example of the schematic configuration of the adapter after the memory card of the 16th embodiment is inserted, and Figure 14D is a plan view showing an example of the schematic configuration of the adapter after the memory card of the 16th embodiment is inserted.

[0175] In this embodiment, an adapter is shown that converts the form factor of memory card SD3 in Figure 4A to the form factor of memory card SD4 in Figure 4B.

[0176] In Figures 14A and 14B, the adapter AP3 is provided with an insertion section IE2 into which the memory card SD3 is inserted. The entrance to the insertion section IE2 can be provided at the rear end of the adapter AP3. The insertion section IE2 is provided with a notch IK2 that, when the memory card SD3 is inserted into the insertion section IE2, exposes the terminal groups PA3 and PA4 of the rows R3 and R4 of the memory card SD3 to the surface of the adapter AP3.

[0177] The position of the insertion slot IE2 can be set so that when memory card SD3 is inserted into the insertion slot IE2, the positions of the terminal groups PA3 and PA4 on rows R3 and R4 of memory card SD3 correspond to the positions of the terminal groups PB3 and PB4 on rows R3 and R4 of memory card SD4.

[0178] The surface of the adapter AP3 is provided with a terminal group DA1. Each terminal of the terminal group DA1 can be arranged to correspond to the terminal arrangement of row R1 of the memory card SD4.

[0179] A lead pin IA1 is provided on the inner surface of the insertion part IE2 of adapter AP3. The lead pin IA1 can be positioned to correspond to the terminal arrangement of row R1 of memory card SD3. The lead pin IA1 is connected one-to-one with each terminal of terminal group DA1 via wiring HA1.

[0180] When inserting a memory card SD3 into adapter AP3, insert the memory card SD3 into the insertion port IE2 from the rear end of adapter AP3.

[0181] At this time, as shown in Figures 14C and 14D, each terminal of the PA1 terminal group on row R1 of memory card SD3 can be brought into contact with the lead pin IA1. Furthermore, when each terminal of the PA1 terminal group on row R1 of memory card SD3 is brought into contact with the lead pin IA1, the arrangement of the DA1 terminal group on adapter AP3 and the PA3 and PA4 terminal groups on memory card SD3 can be made to match the arrangement of the PB1, PB3, and PB4 terminal groups on memory card SD4. This makes it possible to convert the form factor of memory card SD3 to the form factor of memory card SD4.

[0182] Here, when the memory card SD3 is inserted into the adapter AP3, the terminals PA3 and PA4 of the memory card SD3 are exposed on the surface of the adapter AP3, allowing contact to be made with the terminals PA3 and PA4 of the memory card SD3 without the adapter AP3's terminals acting as an intermediary. Therefore, even when the form factor of the memory card SD3 is converted to the form factor of the memory card SD4, it is no longer necessary for the terminals PA3 and PA4 of the memory card SD3 to come into contact with the adapter AP3. As a result, when the memory card SD3 is inserted into the adapter AP3, the deterioration of the electrical characteristics of the terminals PA3 and PA4 of the memory card SD3 can be eliminated.

[0183] (17th Embodiment) Figure 15A is a cross-sectional view showing an example of the schematic configuration of the adapter before the memory card of the 17th embodiment is inserted, Figure 15B is a plan view showing an example of the schematic configuration of the adapter before the memory card of the 17th embodiment is inserted, Figure 15C is a cross-sectional view showing an example of the schematic configuration of the adapter after the memory card of the 17th embodiment is inserted, and Figure 15D is a plan view showing an example of the schematic configuration of the adapter after the memory card of the 17th embodiment is inserted.

[0184] In this embodiment, an adapter is shown that converts the form factor of memory card SD4 in Figure 4B to the form factor of memory card SD5 in Figure 4C.

[0185] In Figures 15A and 15B, the adapter AP4 is provided with an insertion section IE3 into which the memory card SD4 is inserted. The entrance to the insertion section IE3 can be provided on the surface of the adapter AP4. The entrance to the insertion section IE3 allows the terminal groups PB3 and PB4 of the rows R3 and R4 of the memory card SD4 to be exposed on the surface of the adapter AP4 when the memory card SD4 is inserted into the insertion section IE3.

[0186] The position of the insertion slot IE3 can be set so that when a memory card SD4 is inserted into the insertion slot IE3, the positions of the terminals PB3 and PB4 on rows R3 and R4 of the memory card SD4 correspond to the positions of the terminals PC3 and PC4 on rows R3 and R4 of the memory card SD5.

[0187] The surface of the adapter AP4 is provided with a terminal group DB1. Each terminal in the terminal group DB1 can be arranged to correspond to the terminal arrangement of row R1 of the memory card SD5.

[0188] A lead pin IB1 is provided on the inner surface of the insertion section IE3 of the adapter AP4. The lead pin IB1 can be positioned to correspond to the terminal arrangement of row R1 of the memory card SD4. The lead pin IB1 is connected one-to-one with each terminal of the terminal group DB1 via wiring HB1.

[0189] When inserting an SD4 memory card into the AP4 adapter, insert the SD4 memory card into the insertion slot IE3 from the surface of the AP4 adapter.

[0190] At this time, as shown in Figures 15C and 15D, each terminal of the terminal group PB1 of row R1 of memory card SD4 can be brought into contact with the lead pin IB1. Furthermore, when each terminal of the terminal group PB1 of row R1 of memory card SD4 is brought into contact with the lead pin IB1, the arrangement of the terminal group DB1 of adapter AP4 and the terminal groups PB3 and PB4 of memory card SD4 can be made to match the arrangement of the terminal groups PC1, PC3, and PC4 of memory card SD5. This makes it possible to convert the form factor of memory card SD4 to the form factor of memory card SD5.

[0191] Here, when the memory card SD4 is inserted into the adapter AP4, the terminals PB3 and PB4 of the memory card SD4 are exposed on the surface of the adapter AP4, allowing contact to be made with the terminals PB3 and PB4 of the memory card SD4 without the adapter AP4's terminals acting as an intermediary. Therefore, even when the form factor of the memory card SD4 is converted to the form factor of the memory card SD5, it is no longer necessary for the terminals PB3 and PB4 of the memory card SD4 to come into contact with the terminals of the adapter AP4. As a result, when the memory card SD4 is inserted into the adapter AP4, the deterioration of the electrical characteristics of the terminals PB3 and PB4 of the memory card SD4 can be eliminated.

[0192] (18th embodiment) Figure 16A is a perspective view showing the schematic configuration of a memory card according to the 18th embodiment. Figure 16A shows a modified example of the memory card SD4 in Figure 4B.

[0193] In Figure 16A, the memory card SD4' is provided with terminal group PB1' instead of terminal group PB1 of the memory card SD4. Each terminal of terminal group PB1' is arranged on the memory card SD4' from the front surface to the front end surface. This allows contact to be made from the tip of the memory card SD4' to the terminal of row R1 of the memory card SD4'.

[0194] (19th embodiment) Figure 16B is a cross-sectional view showing an example of the schematic configuration of the adapter before the memory card is inserted according to the 19th embodiment. Figure 16B shows a modified example of the adapter AP4 shown in Figures 15A to 15D.

[0195] In Figure 16B, adapter AP4' is provided with an insertion part IE3', a pogo pin 62, and a wiring HB2 instead of the insertion part IE3, lead pin IB1, and wiring HB1 of adapter AP4. The pogo pin 62 is embedded in the side of the tip of the insertion part IE3'. The pogo pin 62 is connected one-to-one with each terminal of terminal group DB1 via wiring HB2.

[0196] When inserting the memory card SD4' into the adapter AP4', insert the memory card SD4' into the insertion section IE3' from the surface of the adapter AP4'. At this time, a stable contact can be achieved by crimping the tips of each terminal of the row R1 terminal group PB1' of the memory card SD4' onto the pogo pin 62.

[0197] As shown in Figure 15C, when the memory card SD4 is attached to the adapter AP4, a step is created between the terminal group DB1 of the adapter AP4 and the terminal groups PB3 and PB4 of the memory card SD4. When making contact with these terminal groups DB1, PB3, and PB4, it is necessary to use a connector to absorb this step.

[0198] On the other hand, when the memory card SD4' is attached to the adapter AP4', the height difference between the terminal group DB1 of the adapter AP4' and the terminal groups PB3 and PB4 of the memory card SD4' can be almost completely eliminated. Therefore, it is not necessary to absorb the height difference with the connector that makes contact with terminal groups DB1, PB3, and PB4, and the complexity of the connector structure can be prevented.

[0199] (20th embodiment) Figure 16C is a perspective view showing the schematic configuration of a memory card according to the 20th embodiment, and Figure 16D is a cross-sectional view showing the state of the adapter after the memory card of Figure 16C has been inserted. Figure 16C shows a modified example of the memory card SD4 of Figure 4B.

[0200] In Figure 16C, a step 61 is provided at the tip of the memory card SD4''. In this case, the terminal group PB1 can be positioned at a height lower by the height of the step 61.

[0201] When inserting the memory card SD4'' into the adapter AP4, insert the memory card SD4'' into the insertion section IE3 from the surface of the adapter AP4. At this time, each terminal of the row R1 terminal group PB1 of the memory card SD4'' can be brought into contact with the lead pin IB1.

[0202] Here, as shown in Figure 15C, when the memory card SD4 is attached to the adapter AP4, a step is created between the terminal group DB1 of the adapter AP4 and the terminal groups PB3 and PB4 of the memory card SD4.

[0203] On the other hand, when the memory card SD4'' is attached to the adapter AP4, the height difference between the terminal group DB1 of the adapter AP4 and the terminal groups PB3 and PB4 of the memory card SD4'' can be almost completely eliminated. Therefore, it is not necessary to absorb the height difference with the connector that makes contact with terminal groups DB1, PB3, and PB4, and the complexity of the connector structure can be prevented.

[0204] (21st Embodiment) Figure 17 is a plan view showing an example of the schematic configuration of the adapter after the memory card has been inserted according to the 21st embodiment. Figure 17 shows a modified example of the adapter AP1 shown in Figures 13A to 13D.

[0205] In Figure 17, a semiconductor chip 71 is provided on the adapter AP1'. The semiconductor chip 71 can be mounted in any location other than those shown in the figure; it can be embedded in any available space on the adapter AP1'. The semiconductor chip 71 is connected to lead pin IA2 in Figures 13A and 13B.

[0206] The semiconductor chip 71 can be equipped with functions such as a wireless module, proximity wireless module, security module, and sensors for odor, light, etc.

[0207] Wireless modules can support standards such as 11a, 11b, 11g, 11n, 11ad, and WiGig. Proximity wireless modules can support standards such as NFC, Zwave, ZigBee, and TransferJet. Secure modules can support standards such as TEE (Trusted Execution Environment), TCG (Trusted Computing Group), and OPAL.

[0208] When the memory card SD2 is inserted into the adapter AP1', it connects to the host device via rows R3 and R4 of the memory card SD2, and the semiconductor chip 71 can connect to the memory card using the terminal group of row R2 on the memory card SD2. As a result, by attaching the adapter AP1' with the memory card SD2 inserted to the host device, the host device can be equipped with functions such as a wireless module, secure module, or sensor.

[0209] (22nd Embodiment) Figure 18 is a plan view showing the schematic configuration of a memory card according to the 22nd embodiment. Figure 18 shows a modified example of the memory card SD4 of Figure 4B.

[0210] In Figure 18, the memory card SD6 has the terminal group PB1 of row R1 of the memory card SD4 removed. Rows R3 and R4 are provided in the position of row R1 of the memory card SD4. On rows R3 and R4 of the memory card SD6, terminal groups PB3' and PB4' are added to the differential signal terminal groups PB3 and PB4 of the memory card SD4, respectively, as replacements for the control signal terminals that used row R1. The shape and number of terminals of terminal groups PB3' and PB4' may differ, but compatibility can be maintained by inheriting the function of row R1. In other words, the memory card SD6 can be converted to a memory card SD5 using an adapter.

[0211] The SD6 memory card can be equipped with a second mode of communication functionality compliant with the PCIe standard. In this case, control signals used to control communication in the second mode compliant with the PCIe standard are assigned to terminal groups PB3' and PB4'. These control signals can be the reference differential clock signal REFCLKp / n, the reset signal PERST, and the power management control signal CLKREQ. In addition, the wake-up signal PEWAKE may also be used as one of these control signals.

[0212] Here, by removing the PB1 terminal group on row R1 of memory card SD4 and providing terminal groups PB3, PB3', PB4, and PB4' on rows R3 and R4 of memory card SD6, it is possible to increase the available space on the card surface of memory card SD6 while giving it a second mode of communication function compliant with the PCIe standard. As a result, it becomes possible to easily increase the number of rows on memory card SD6, and thus easily increase the number of lanes compliant with the PCIe standard, thereby easily improving the data transfer speed of memory card SD6.

[0213] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0214] SD1~SD5 Memory card, PA1~PA4 Terminal group, R1~R4 Row, 11, 12 Regulator, 13 Comparator, 14 Card controller, 15 Memory interface circuit, 16 Memory, 17 IO cell, 18 Physical layer, 19 Card interface circuit

Claims

1. A connector that can connect to a memory card, having a first surface including a first row and a second row, a second surface facing the opposite side from the first surface, a first group of terminals arranged in the first row, and a second group of terminals arranged in the second row. A transmitter that transmits a first differential data signal compliant with the PCIe standard to the connector via a first transmission line, A receiver that receives a second differential data signal compliant with the PCIe standard from the connector via a second transmission line, A first AC coupling capacitor provided in the first transmission line, A second AC coupling capacitor is provided in the second transmission line, Equipped with, The aforementioned connector is A first group of connector contacts that can be connected to the first group of terminals, A second group of connector contacts that can be connected to the second group of terminals, Includes, The first contact group of the connector is, A terminal to which a differential clock signal compliant with the PCIe standard is assigned, Terminals to which single-ended signals are assigned, The terminal to which the first power supply voltage is assigned, Includes, The second contact group of the connector is The two terminals to which the first differential data signal is assigned, The two terminals to which the second differential data signal is assigned, Multiple terminals to which ground is assigned, including Host device.

2. The two terminals to which the first differential data signal is assigned are located adjacent to each other. The two terminals to which the second differential data signal is assigned are located adjacent to each other. The two terminals to which the first differential data signal is assigned are located between two of the terminals to which the ground is assigned. The two terminals to which the second differential data signal is assigned are positioned between two of the terminals to which the ground is assigned. The host device according to claim 1.

3. When communicating with the memory card in the first mode, a data signal compliant with the SD standard is transmitted using a plurality of first terminals included in the first contact group of the connector, and a clock signal compliant with the SD standard is transmitted using a second terminal included in the first terminal group. When communicating with the memory card in the second mode, the plurality of first terminals included in the first connector contact group are used to transmit a differential clock signal compliant with the PCIe standard, and the two terminals included in the second connector contact group to which the first differential data signal is assigned are used to transmit a differential data signal compliant with the PCIe standard. The host device according to claim 1.

4. When communicating with the memory card in the second mode, the PCIe-compliant differential data signal is received using two terminals to which the second differential data signal included in the second contact group of the connector is assigned. The host device according to claim 3.

5. The second group of connector contacts includes terminals to which the second power supply voltage is assigned. When communicating with the memory card in the second mode, a first voltage is applied to the terminal to which the first power supply voltage is assigned, and a second voltage lower than the first voltage is applied to the terminal to which the second power supply voltage is assigned. The host device according to claim 4.

6. The first voltage is 3.3V, and the second voltage is 1.8V. The host device according to claim 5.

7. The memory card in question is a microSD card. The host device according to claim 1.

8. A first switch that shorts the terminals of the first AC coupling capacitor, A second switch that shorts the terminals of the second AC coupling capacitor, To further enhance The host device according to claim 1.

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