Semiconductor device and control method for a semiconductor device

Abstract

The present disclosure relates to a semiconductor device comprising: an n-type first semiconductor layer which is provided between a first main surface and a second main surface of a semiconductor substrate; a p-type second semiconductor layer which is provided between the first semiconductor layer and the first main surface; an n-type third semiconductor layer which is provided on the side of the second semiconductor layer that is toward the first main surface; a p-type fourth semiconductor layer which is provided between the first semiconductor layer and the second main surface; a first and a second trench which penetrate through the second semiconductor layer from the first main surface and which reach the inside of the first semiconductor layer; a first and a second control electrode which are embedded inside of the first and the second trench, respectively, with a first and a second gate insulating film therebetween; and an n-type fifth semiconductor layer which is the upper layer part of the first semiconductor layer below the second semiconductor layer and which is provided so as to be in contact with the second gate insulating film of the second trench, wherein the fifth semiconductor layer has a second impurity concentration higher than a first impurity concentration of the first semiconductor layer and is provided so as to not be in contact with the first gate insulating film of the first trench.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a double gate structure. [Background technology]

[0002] To improve the switching performance of insulated-gate bipolar transistors (IGBTs), double-gate IGBTs have been developed by applying a double-gate structure, such as the one disclosed in Patent Document 1, to IGBTs.

[0003] The double-gate IGBT disclosed in Figure 1 of Patent Document 1 adopts a configuration in which a normal gate electrode and a control gate electrode are alternately formed on the main surface on the emitter electrode side.

[0004] A normal gate electrode is electrically connected to a normal gate pad, and a control gate electrode is electrically connected to a control gate pad, with gate signals input to control each individually.

[0005] Typically, gate electrodes and control gate electrodes have a trench structure in which they are embedded within trenches extending in the thickness direction from the surface of a semiconductor substrate, via gate insulating films that cover the inner walls of the trenches.

[0006] The IGBT has a configuration in which a p-type base layer is provided on top of an n-type drift layer, and an n-type emitter layer is provided on top of the p-type base layer, with a trench provided so as to penetrate the emitter layer. The trench also penetrates the base layer, and its bottom surface reaches into the drift layer.

[0007] In a double-gate IGBT with this structure, turn-off losses can be reduced by blocking the control gate electrode before the normal gate electrode during turn-off operation. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] International Publication No. 2013 / 065247 [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] In the double-gate IGBT shown in Patent Document 1, the gate electrode and control gate electrode typically reach into the drift layer via the gate insulating film, so the gate electrode and control gate electrode are usually adjacent to the drift layer.

[0010] Increasing the donor concentration is effective in reducing the on-voltage of IGBTs, but increasing the donor concentration generates noise during turn-on, which presents a problem as there is a lower limit to how much the on-voltage of IGBTs can be reduced.

[0011] This disclosure is made to solve the problems described above and aims to provide a semiconductor device that improves the trade-off between turn-on noise and on-voltage. [Means for solving the problem]

[0012] The semiconductor device according to this disclosure is formed on a semiconductor substrate having a first main surface and a second main surface facing each other, and comprises: a first semiconductor layer of a first conductivity type provided between the first main surface and the second main surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first main surface; a third semiconductor layer of a first conductivity type selectively provided on the first main surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second main surface; a first main electrode provided on the first main surface and electrically connected to the second semiconductor layer and the third semiconductor layer; a second main electrode provided on the second main surface and electrically connected to the fourth semiconductor layer; and the second semiconductor layer provided on the first main surface. The semiconductor comprises: a first trench penetrating the body layer and reaching the interior of the first semiconductor layer; a second trench penetrating the second semiconductor layer from the first main surface and reaching the interior of the first semiconductor layer; a first control electrode embedded in the first trench via a first gate insulating film; a second control electrode embedded in the second trench via a second gate insulating film; and a fifth semiconductor layer of a first conductivity type selectively provided in the upper part of the first semiconductor layer below the second semiconductor layer, so as to be in contact with the second gate insulating film of the second trench, wherein the second impurity concentration of the fifth semiconductor layer is higher than the first impurity concentration of the first semiconductor layer, and the fifth semiconductor layer is provided so as not to be in contact with the first gate insulating film of the first trench. The third semiconductor layer is provided in contact with the first gate insulating film of the first trench. ru. [Effects of the Invention]

[0013] According to the semiconductor device described herein, a fifth semiconductor layer is provided so as not to be in contact with the first gate insulating film of the first trench, and the second impurity concentration of the fifth semiconductor layer is made higher than the first impurity concentration of the first semiconductor layer, thereby providing a semiconductor device that improves the trade-off between turn-on noise and on-voltage. [Brief explanation of the drawing]

[0014] [Figure 1]This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 2] This is a timing chart showing an example of turn-on control. [Figure 3] This timing chart shows another example of turn-on control. [Figure 4] This timing chart shows another example of turn-on control. [Figure 5] This is a cross-sectional view showing the configuration of a modified example 1 of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 6] This is a cross-sectional view showing the configuration of a modified example 2 of the semiconductor device of Embodiment 1 according to this disclosure. [Figure 7] This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 2 of this disclosure. [Figure 8] This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 3 of this disclosure. [Figure 9] This figure shows the donor concentration profile. [Figure 10] This figure shows the donor concentration profile. [Figure 11] This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 4 of this disclosure. [Figure 12] This is a cross-sectional view showing the configuration of a modified example of the semiconductor device of Embodiment 4 according to this disclosure. [Figure 13] This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 5 of this disclosure. [Figure 14] This is a cross-sectional view showing the configuration of Modified Example 1 of the semiconductor device of Embodiment 5 according to this disclosure. [Figure 15] This is a cross-sectional view showing the configuration of a modified example 2 of the semiconductor device according to Embodiment 5 of this disclosure. [Modes for carrying out the invention]

[0015] <Introduction> In the following description, n-type and p-type refer to the conductivity types of semiconductors. In this disclosure, the first conductivity type is described as n-type and the second conductivity type as p-type, but the first conductivity type may be described as p-type and the second conductivity type as n-type. - The n type indicates that the impurity concentration is lower than that of the n type. + The type indicates that the impurity concentration is higher than that of the n type. Similarly, p - The p-type indicates that the impurity concentration is lower than that of the p-type. + The type indicates that the impurity concentration is higher than that of the p-type.

[0016] Furthermore, the drawings are schematic representations, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be modified as appropriate. In the following explanation, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed explanations of these components may be omitted.

[0017] Furthermore, in the following description, terms such as "top," "bottom," "side," "front," and "back" may be used to indicate specific positions and directions. These terms are used for convenience to facilitate understanding of the embodiments and do not relate to the actual directions in which they are implemented.

[0018] <Embodiment 1> Figure 1 is a cross-sectional view showing the configuration of the double-gate IGBT 100 of Embodiment 1 according to this disclosure. Although the planar configuration is not shown, it can be configured in which multiple striped trench gates extend in one direction, similar to a general trench-gate type IGBT.

[0019] As shown in Figure 1, the double-gate IGBT 100 has an active gate electrode AG (first control electrode), a dummy electrode DE, and a control gate electrode CG (second control electrode) arranged on the first main surface side, which is the upper surface of the semiconductor substrate, with spacing between them.

[0020] The active gate electrode AG is buried in a trench 7 (first trench) formed in a semiconductor substrate via a gate insulating film 8 (first gate insulating film). The active gate electrode AG is electrically connected to a gate pad (not shown), and a gate signal is supplied to the active gate electrode AG. The gate insulating film 8 can be formed of, for example, a silicon oxide film (SiO2).

[0021] The control gate electrode CG is buried in a trench 7 (second trench) formed in the semiconductor substrate via a gate insulating film 8 (second gate insulating film). The control gate electrode CG is electrically connected to a control gate pad (not shown), and a control gate signal is supplied to the control gate electrode CG.

[0022] The dummy electrode DE is buried in a trench 7 (third trench) formed in the semiconductor substrate via a gate insulating film 8 (third gate insulating film). The dummy electrode DE is electrically connected to an emitter electrode 1 (first main electrode) provided on a first main surface, and its potential is stabilized when an emitter voltage is supplied thereto.

[0023] As shown in FIG. 1, the double-gate IGBT 100 includes n - -type drift layer 9 (first semiconductor layer). n - -type drift layer 9 is a semiconductor layer containing, as n-type impurities, for example, arsenic (As) or phosphorus (P), and the concentration of the n-type impurities is 1.0×10 12 / cm 3 to 1.0×10 16 / cm 3 .

[0024] n - -type drift layer 9, a p-type base layer 5 (second semiconductor layer) is provided in an upper layer portion serving as the first main surface side. The p-type base layer 5 is a semiconductor layer containing, as p-type impurities, for example, boron (B) or aluminum (Al), and the concentration of the p-type impurities is 1.0×10 12 / cm 3 to 1.0×10 19 / cm 3 The p-type base layer 5 is in contact with the gate insulating film 8 of the active gate electrode AG, the control gate electrode CG, and the dummy electrode DE.

[0025] The upper part of the p-type base layer 5 is in contact with the gate insulating film 8 of the active gate electrode AG and the control gate electrode CG, and n + A type source layer 3 (third semiconductor layer) is provided. + The n-type source layer 3 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0 × 10⁻⁶. 17 / cm 3 ~1.0×10 21 / cm 3 That is the case.

[0026] Furthermore, the upper part of the p-type base layer 5 contains n + Type source layer 3 is adjacent to p + A type contact layer 4 is provided. + The p-type contact layer 4 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10⁻⁶. 15 / cm 3 ~1.0×10 21 / cm 3 That is the case.

[0027] n below the p-type base layer 5 - Within the drift layer 9, n is placed in contact with the gate insulating film 8 of the control gate electrode CG. - An n-type carrier storage layer 6c (the fifth semiconductor layer) is provided, in which the concentration of n-type impurities is higher than that of the n-type drift layer 9. The n-type carrier storage layer 6c is a semiconductor layer having, for example, arsenic or phosphorus as n-type impurities, and the concentration of n-type impurities is 1.0 × 10⁻⁶. 13 / cm 3 ~1.0×10 18 / cm 3In addition, dummy electrodes DE are provided on both sides of the control gate electrode CG, and the n-type carrier storage layer 6c is provided between the control gate electrode CG and the dummy electrodes DE on both sides, so it is in contact with the gate insulating film 8 of the dummy electrodes DE, but it can also be provided so as not to be in contact with the gate insulating film 8 of the dummy electrodes DE.

[0028] Furthermore, on the second main surface, which is the lower surface of the semiconductor substrate, a p-type collector layer 11 (fourth semiconductor layer) and an n-type buffer layer 10 are provided in order from the second main surface, and a collector electrode 12 (second main electrode) is provided on the second main surface opposite to the emitter electrode 1.

[0029] The p-type collector layer 11 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10⁻⁶ 16 / cm 3 ~1.0×10 20 / cm 3 The p-type collector layer 11 constitutes the second main surface of the semiconductor substrate.

[0030] The n-type buffer layer 10 contains n-type impurities such as phosphorus or protons (H + It can be formed by injecting ) and can also be formed by injecting both phosphorus and protons. The concentration of n-type impurities in the n-type buffer layer 10 is 1.0 × 10⁻⁶ 12 / cm 3 ~1.0×10 18 / cm 3 That is the case.

[0031] The active gate electrode AG, dummy electrode DE, and control gate electrode CG can be made of polysilicon doped with n-type or p-type impurities.

[0032] The emitter electrode 1 can be formed from an aluminum alloy, such as an aluminum-silicon alloy (Al-Si alloy), or it can be composed of multiple layers of metal films formed on the aluminum alloy electrode by electroless plating or electrolytic plating. The plating film formed by electroless plating or electrolytic plating can be, for example, a nickel (Ni) plating film.

[0033] The collector electrode 12 can be formed by depositing aluminum-silicon alloy (Ai-Si alloy) or titanium (Ti) by PVD (physical vapor deposition) such as sputtering or vapor deposition, and can also be formed by layering multiple metals such as aluminum-silicon alloy, titanium, nickel, and gold. Furthermore, it can be constructed by forming another metal film on the metal film formed by PVD using electroless plating or electrolytic plating.

[0034] An interlayer insulating film 2 is provided on the active gate electrode AG, the dummy electrode DE, and the control gate electrode CG. The interlayer insulating film 2 can be formed from, for example, a silicon oxide film (SiO2).

[0035] A barrier metal 21 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 2 is not provided, and on the interlayer insulating film 2. The barrier metal 21 can be, for example, a conductor containing titanium (Ti), and can be, for example, titanium nitride or TiSi, which is an alloy of titanium and silicon (Si). The barrier metal 21 is n + Type source layer 3, p + The contact layer 4 and the dummy electrode DE are in ohmic contact, n + Type source layer 3, p + It is electrically connected to the type contact layer 4 and the dummy electrode DE.

[0036] The emitter electrode 1 is provided on the barrier metal 21, but if the barrier metal 21 is not provided, n +The emitter electrode 1 can also be provided on the type source layer 3. The barrier metal 21 and the emitter electrode 1 may together be referred to as an emitter electrode.

[0037] As described above, n - The concentration of n-type impurities in the type drift layer 9 is 1.0×10 12 / cm 3 ~1.0×10 16 / cm 3 , and the concentration of n-type impurities in the n-type carrier accumulation layer 6c is 1.0×10 13 / cm 3 ~1.0×10 18 / cm 3 , and where Nd is the donor concentration of the n - -type drift layer 9 (first impurity concentration) and N2 is the donor concentration of the n-type carrier accumulation layer 6c (second impurity concentration), the n-type impurity concentration is set such that Nd<N2.

[0038] Further, the n-type carrier accumulation layer 6c is provided so as to be adjacent to the control gate electrode CG but not adjacent to the active gate electrode AG.

[0039] The operation of the double-gate IGBT 100 having such a configuration will be described below. When turning on the double-gate IGBT 100, the gate signal and the control gate signal are controlled such that after the active gate electrode AG enters the turn-on operation, the control gate electrode CG enters the turn-on operation later than the active gate electrode AG.

[0040] <Operation Example 1> FIG. 2 is a timing chart showing an example of turn-on control. In FIG. 2, the horizontal axis represents elapsed time, the vertical axis represents gate voltage, and both are in arbitrary units.

[0041] In Figure 2, the solid line shows the time variation of the gate voltage of the active gate electrode AG, and the dashed line shows the time variation of the gate voltage of the control gate electrode CG. As shown in Figure 2, when an ON signal (first ON signal) is input to the active gate electrode AG and the gate voltage begins to increase, an ON signal (second ON signal) is input to the control gate electrode CG with a time delay t1 compared to the active gate electrode AG.

[0042] After the gate voltage of the active gate electrode AG increases and enters the Miller effect period, the gate voltage of the control gate electrode CG also enters the Miller effect period. The Miller effect period is a period during which the voltage remains nearly constant and corresponds to the period during which the gate-collector capacitance of the double-gate IGBT100 is charged and discharged. Discharge of the gate-collector capacitance is necessary to turn on the double-gate IGBT100, and the period for this discharge is the Miller effect period. The gate voltage of the active gate electrode AG increases again after the Miller effect period and finally becomes constant at the collector voltage.

[0043] The gate voltage of the control gate electrode CG also increases again after the Miller effect period and becomes constant at the collector voltage. The timing at which the gate voltage of the control gate electrode CG reaches the Miller voltage is later than that of the gate voltage of the active gate electrode AG, but the timing at which the Miller effect period ends is almost the same.

[0044] Thus, if an ON signal is input to the control gate electrode CG with a delay compared to the active gate electrode AG, n - The carrier concentration in the drift layer 9 increases. This is because the number of channels increases as the channels formed by the control gate electrode CG are added to the channels formed by the active gate electrode AG.

[0045] By inputting the ON signal to the control gate electrode CG later than the active gate electrode AG, the following further effects can be obtained: n-type carrier layer, i.e., n -When the donor concentrations in the n-type drift layer 9 and the n-type carrier storage layer 6c are high, negative capacitance at the gate is likely to occur, leading to increased noise. Since noise mainly occurs during the Miller effect period, noise can be suppressed by first turning on cells with an active gate electrode AG that has a low n-type carrier donor concentration, and then later turning on cells with a control gate electrode CG that has a high n-type carrier donor concentration, rather than simultaneously turning on all cells, including those with a high n-type carrier donor concentration.

[0046] Here, the cell having the active gate electrode AG does not have an n-type carrier storage layer 6c formed. - Since a channel is formed in the drift layer 9, the carrier concentration is low, and the noise generated when the cell is turned on is small. However, n - Because the concentration of n-type impurities (donors) in the drift layer 9 is low, it does not contribute to reducing the on-voltage, i.e., the collector-emitter voltage (VCE(sat)).

[0047] On the other hand, cells with a control gate electrode CG have an n-type carrier storage layer 6c formed therein, and since channels are formed in the n-type carrier storage layer 6c, the carrier concentration is high, and the noise generated when the cell is turned on is large. However, because the donor concentration of the n-type carrier storage layer 6c is high, the on-voltage can be reduced.

[0048] <Example of operation 2> Figure 3 is a timing chart showing another example of turn-on control. In Figure 3, the horizontal and vertical axes are the same as in Figure 2.

[0049] As shown in Figure 3, when an ON signal is input to the active gate electrode AG, the gate voltage begins to increase, and after entering the Miller effect period, an ON signal is input to the control gate electrode CG with a time delay of t2.

[0050] The gate voltage of the active gate electrode AG increases again after the Miller effect period and eventually becomes constant at the collector voltage. The gate voltage of the control gate electrode CG also increases again after the Miller effect period and eventually becomes constant at the collector voltage. The timing at which the gate voltage of the control gate electrode CG reaches the Miller voltage is later than that of the gate voltage of the active gate electrode AG, but the timing at which the Miller effect period ends is approximately the same.

[0051] The ON signal is input to the control gate electrode CG only after the gate voltage of the active gate electrode AG reaches the Miller voltage. Since noise mainly occurs during the Miller effect period, noise generation can be suppressed by turning on only the cells with the active gate electrode AG, i.e., cells with low noise generation during turn-on, until the Miller effect period has begun. Then, after the gate voltage of the active gate electrode AG enters the Miller effect period, the ON voltage can be reduced by turning on the cells with the control gate electrode CG, i.e., cells with low ON voltage.

[0052] <Example of operation 3> Figure 4 is a timing chart showing another example of turn-on control. In Figure 4, the horizontal and vertical axes are the same as in Figure 2.

[0053] As shown in Figure 4, when an ON signal is input to the active gate electrode AG, the gate voltage begins to increase, and after entering the Miller effect period, an ON signal is input to the control gate electrode CG with a time delay of t3.

[0054] The gate voltage of the active gate electrode AG increases again after the Miller effect period and eventually becomes constant at the gate-on voltage. When an ON signal is input to the control gate electrode CG, the gate voltage of the control gate electrode CG increases without undergoing the Miller effect period and becomes constant at the gate-on voltage.

[0055] Since noise mainly occurs before the Miller effect period, by turning on only cells having the active gate electrode AG, i.e., cells that generate small noise during turn-on, until the Miller effect period ends, the generation of noise is suppressed. Then, after the gate voltage of the active gate electrode AG passes the Miller effect period, cells having the control gate electrode CG, i.e., cells with a low on-voltage, are turned on, whereby the on-voltage can be reduced.

[0056] As described above, in the double-gate IGBT 100, by providing a time difference in the drive timing of the active gate electrode AG and the control gate electrode CG, it is possible to utilize the respective features, reduce noise while also reducing the on-voltage, and improve the trade-off between noise at turn-on of the IGBT and the on-voltage. In the above description, an example is shown in which a time difference is provided in the drive timing of the active gate electrode AG and the control gate electrode CG in the turn-on control of the IGBT, but a time difference may also be provided in the turn-off control, and a time difference may also be provided in both the turn-on control and the turn-off control. Here, in the turn-off control, there is no particular restriction on the turn-off order of the active gate electrode AG and the control gate electrode CG, that is, either may be cut off first. When a time difference is provided in both the turn-on control and the turn-off control, the time difference in the turn-on control (the delay time of the control gate electrode CG) is made shorter than the time difference in the turn-off control (the delay time of the active gate electrode AG or the control gate electrode CG). This makes it possible to relatively delay the turn-off timing of the electrode that is cut off later during turn-off, and allows the turn-off timing to be designed with a high degree of freedom.

[0057] Note that n - -type drift layer 9 has a donor concentration Nd, and when the donor concentration of the n-type carrier accumulation layer 6c is N2, the relationship with the donor concentration N0 at which noise occurs satisfies Nd < N0 ≦ N2, whereby the above-described effects can be obtained. As an example, 5×10 13 / cm 3 <1×10 17 / cm 3 ≤ 3 × 10 17 / cm 3 One could list these:

[0058] Furthermore, the time difference between the drive timing of the active gate electrode AG and the control gate electrode CG should be approximately 0.1 μsec to 10 μsec for a device with a voltage rating of 1200 V.

[0059] <Example 1> In the double-gate IGBT 100 described above, a dummy electrode DE is located between the active gate electrode AG and the control gate electrode CG. This arrangement allows for adjustment of the IGBT's gate capacitance, improving the design flexibility of the IGBT. However, the number of dummy electrodes DE is not limited to one. Furthermore, even without the dummy electrode DE, the effect of improving the trade-off between IGBT turn-on noise and on-voltage remains the same.

[0060] Figure 5 is a cross-sectional view showing the configuration of a double-gate IGBT 101, which is a modified example of Embodiment 1. In Figure 5, components identical to those of the double-gate IGBT 100 shown in Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted.

[0061] As shown in Figure 5, in the double gate IGBT 101, the active gate electrode AG and the control gate electrode CG are provided on the first main surface side, which is the upper surface of the semiconductor substrate, with a gap between them, and the n of adjacent active gate electrode AG and control gate electrode CG + In the upper part of the p-type base layer 5 between the type source layer 3, p + A type contact layer 4 is provided, n + The source layers 3 are electrically connected.

[0062] An n-type carrier storage layer 6c is provided adjacent to the control gate electrode CG, but is provided so as not to be adjacent to the active gate electrode AG.

[0063] Dummy electrodes DE are provided to adjust the capacitance of the gate electrode. To reduce the capacitance, the number of dummy electrodes DE is reduced, and to increase the capacitance, the number of dummy electrodes DE is increased. Therefore, the capacitance of the active gate electrode AG and control gate electrode CG is smaller in the double-gate IGBT 101 shown in Figure 5 than in the double-gate IGBT 100 shown in Figure 1. Reducing the capacitance can improve the responsiveness of IGBT switching and reduce switching losses, especially in situations where the cell pitch is constant.

[0064] <Modification 2> In the double-gate IGBT 100 shown in Figure 1, the control gate electrode CG was positioned so as to be sandwiched between dummy electrodes DE, but this arrangement is not the only one possible configuration.

[0065] Figure 6 is a cross-sectional view showing the configuration of a double-gate IGBT 102, which is a modified example 2 of Embodiment 1. In Figure 6, components identical to those of the double-gate IGBT 100 shown in Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted.

[0066] As shown in Figure 6, in the double-gate IGBT 102, the control gate electrode CG is positioned next to the active gate electrode AG, and the two dummy electrodes DE are positioned on the opposite side from the active gate electrode AG. Here, the dummy electrodes DE are adjacent to the control gate electrode CG, but Figure 6 shows a unit cell, and the active gate electrode AG is adjacent to the dummy electrodes DE (not shown).

[0067] An n-type carrier storage layer 6c is provided so as to be in contact with the gate insulating film 8 of the control gate electrode CG, but the n-type carrier storage layer 6c is provided so as not to be in contact with the gate insulating film 8 of the active gate electrode AG.

[0068] Even with this configuration, the effect of improving the trade-off between IGBT turn-on noise and on-voltage is the same as with the double-gate IGBT100. Furthermore, by placing the dummy electrode DE adjacent to the IGBT and not adjacent to either side of the active gate electrode AG, the gate capacitance can be reduced, improving the responsiveness of IGBT switching and reducing switching losses.

[0069] It goes without saying that the active gate electrode AG and the control gate electrode CG can be arranged alternately without the need for a dummy electrode DE.

[0070] <Embodiment 2> Figure 7 is a cross-sectional view showing the configuration of the double-gate IGBT 200 of Embodiment 2 according to this disclosure. In Figure 7, components identical to those of the double-gate IGBT 100 shown in Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted.

[0071] As shown in Figure 7, the double-gate IGBT200 has n below the p-type base layer 5. - Within the drift layer 9, n is placed in contact with the gate insulating film 8 of the control gate electrode CG. - An n-type carrier storage layer 6c is provided, which has a higher concentration of n-type impurities than the n-type drift layer 9, and an n-type carrier storage layer is provided so as to be in contact with the gate insulating film 8 of the active gate electrode AG. - An n-type carrier storage layer 6a (sixth semiconductor layer) is provided, in which the concentration of n-type impurities is higher than that of the n-type drift layer 9.

[0072] The n-type carrier storage layer 6a is a semi-hollow layer containing n-type impurities such as arsenic or phosphorus, and the concentration of the n-type impurities is 1.0 × 10⁻⁶. 13 / cm 3 ~1.0×10 18 / cm 3 Therefore, it is set lower than the concentration of n-type impurities in the n-type carrier storage layer 6a.

[0073] In other words, as explained earlier, n -The concentration of n-type impurities in the n-type drift layer 9 is 1.0×10 12 / cm 3 ~1.0×10 16 / cm 3 , and the concentration of n-type impurities in the n-type carrier accumulation layer 6c is 1.0×10 13 / cm 3 ~1.0×10 19 / cm 3 , letting n - be the donor concentration of the n-type drift layer 9 as Nd, the donor concentration of the n-type carrier accumulation layer 6a as N1 (third impurity concentration), and the donor concentration of the n-type carrier accumulation layer 6c as N2, the concentration of n-type impurities is set such that Nd<N1<N2. As an example, 5×10 13 / cm 3 <1×10 17 / cm 3 <3×10 17 / cm 3 can be mentioned.

[0074] The operation of the double-gate IGBT 200 having such a configuration is the same as the operation of the double-gate IGBT 100 described with reference to FIGS. 2 to 4. When the double-gate IGBT 200 is turned on, the gate signal and the control gate signal are controlled such that after the active gate electrode AG enters the turn-on operation, the control gate electrode CG enters the turn-on operation later than the active gate electrode AG.

[0075] Therefore, in the double-gate IGBT 200, by providing a time difference in the drive timings of the active gate electrode AG and the control gate electrode CG, utilizing the respective features, reducing noise while also reducing the on-voltage, the trade-off between noise at the time of turn-on of the IGBT and the on-voltage can be improved.

[0076] Note that by providing the n-type carrier storage layer 6a, a channel is formed in the n-type carrier storage layer 6a in a cell having the active gate electrode AG, which increases the carrier concentration and increases noise generated when the cell is turned on. However, since the concentration of n-type impurities (donors) in the n-type carrier storage layer 6a is n - higher than that of the n-type drift layer 9, the on-voltage, that is, the collector-emitter voltage (VCE(sat)) can be reduced. Therefore, the on-voltage can be reduced by about 15% compared to the double-gate IGBT 100 of the first embodiment.

[0077] Here, when the donor concentration of the n-type carrier storage layer 6a is N1 and the donor concentration of the n-type carrier storage layer 6c is N2, the above-described effects can be obtained by setting the relationship with the donor concentration N0 at which noise occurs as N1<N0≤N2. As an example, 5×10 16 / cm 3 <1×10 17 / cm 3 ≤3×10 17 / cm 3 can be mentioned.

[0078] Further, the time difference in drive timing between the active gate electrode AG and the control gate electrode CG is approximately 0.1 μsec to 10 μsec, for example, in a device with a withstand voltage of 1200 V.

[0079] In the double-gate IGBT 200 described above, the configuration has a dummy electrode DE in addition to the active gate electrode AG and the control gate electrode CG. However, even in a configuration without the dummy electrode DE, the effect of improving the trade-off between noise at turn-on of the IGBT and on-voltage remains unchanged. For example, as in the double-gate IGBT 101 shown in FIG. 5, a configuration without the dummy electrode DE can be employed. Note that as long as the n-type carrier storage layer 6c is not adjacent to the active gate electrode AG, the n-type carrier storage layer 6a and the n-type carrier storage layer 6c may or may not be in contact with each other.

[0080] Further, in the double gate IGBT 200 shown in FIG. 7, the control gate electrode CG is arranged so as to be sandwiched between the dummy electrodes DE. However, the arrangement is not limited to this, and for example, an arrangement like that of the double gate IGBT 102 shown in FIG. 6 may also be employed.

[0081] <Embodiment 3> FIG. 8 is a cross-sectional view showing a configuration of a double gate IGBT 300 according to Embodiment 3 of the present disclosure. In FIG. 8, the same components as those of the double gate IGBT 100 shown in FIG. 1 are denoted by the same reference signs, and overlapping descriptions are omitted.

[0082] As shown in FIG. 8, similar to the double gate IGBT 200 shown in FIG. 7, the double gate IGBT 300 is provided with an n-type carrier storage layer 6a and an n-type carrier storage layer 6c, and n - when the donor concentration of the type drift layer 9 is Nd, the donor concentration of the n-type carrier storage layer 6a is N1, and the donor concentration of the n-type carrier storage layer 6c is N2, the concentration of the n-type impurity is set so as to satisfy Nd<N1<N2.

[0083] A difference from the double gate IGBT 200 is that when p1 is the depth at which the donor concentration of the n-type carrier storage layer 6a reaches its maximum value (peak), and p2 is the depth at which the donor concentration of the n-type carrier storage layer 6c reaches its maximum value (peak), the donor implantation depths are different so as to satisfy p2<p1.

[0084] For this reason, as shown in FIG. 8, the thickness of the n-type carrier storage layer 6c is thinner than that of the n-type carrier storage layer 6a.

[0085] Figure 9 shows the donor concentration profiles of n-type carrier storage layers 6a and 6c, with depth on the horizontal axis and donor concentration on the vertical axis. Both are in arbitrary units. As shown in Figure 9, the peak depth p1 of profile PF1 of n-type carrier storage layer 6a is deeper than the peak depth p2 of profile PF2 of n-type carrier storage layer 6c. On the other hand, the peak of profile PF2 of n-type carrier storage layer 6c is higher than the peak of profile PF1 of n-type carrier storage layer 6a, and the profile width is narrower than the profile width of n-type carrier storage layer 6a. By creating such a profile, the thickness of n-type carrier storage layer 6c becomes thinner than that of n-type carrier storage layer 6a.

[0086] Thus, by changing the donor injection depth of the n-type carrier storage layers 6a and 6c, the design flexibility of the n-type carrier storage layers 6a and 6c is increased. Furthermore, the donor injection depth can be reversed between the n-type carrier storage layers 6a and 6c.

[0087] The operation of the double-gate IGBT300 with this configuration is the same as that of the double-gate IGBT100 described using Figures 2 to 4. When the double-gate IGBT300 is turned on, the gate signal and the control gate signal are controlled so that the control gate electrode CG turns on after the active gate electrode AG has turned on, with a delay compared to the active gate electrode AG.

[0088] Therefore, in the double-gate IGBT300, by creating a time difference in the drive timing of the active gate electrode AG and the control gate electrode CG, it is possible to leverage the characteristics of each, reduce noise while also reducing the on-voltage, thereby improving the trade-off between IGBT turn-on noise and on-voltage.

[0089] Furthermore, the effect of providing the n-type carrier storage layer 6a, which reduces the on-voltage by about 15% compared to the double-gate IGBT 100 of Embodiment 1, is the same as that of the double-gate IGBT 200 of Embodiment 2.

[0090] Here, when the thicknesses of the n-type carrier storage layer 6a and the n-type carrier storage layer 6c are made the same, as in the double-gate IGBT200 of Embodiment 2, the donor injection depths of the n-type carrier storage layer 6a and the n-type carrier storage layer 6c are made the same. Figure 10 shows the donor concentration profiles of the n-type carrier storage layer 6a and the n-type carrier storage layer 6c of the double-gate IGBT200, where the peak depth p1 of the profile PF1 of the n-type carrier storage layer 6a and the peak depth p1 of the profile PF2 of the n-type carrier storage layer 6c are the same, and the profile widths are also the same. By using such profiles, the thickness of the n-type carrier storage layer 6c and the thickness of the n-type carrier storage layer 6a can be made the same.

[0091] In the double-gate IGBT 300 described above, a dummy electrode DE was included in addition to the active gate electrode AG and control gate electrode CG. However, even in a configuration without the dummy electrode DE, the effect of improving the trade-off between IGBT turn-on noise and on-voltage remains the same. For example, a configuration without the dummy electrode DE can be used, as shown in Figure 5 for the double-gate IGBT 101. Note that, as long as the n-type carrier storage layer 6c is not adjacent to the active gate electrode AG, it does not matter whether the n-type carrier storage layer 6a and the n-type carrier storage layer 6c are in contact or not.

[0092] Furthermore, in the double-gate IGBT300 shown in Figure 8, the control gate electrode CG was positioned so as to be sandwiched between dummy electrodes DE. However, the arrangement is not limited to this configuration, and for example, an arrangement like that of the double-gate IGBT102 shown in Figure 6 is also possible.

[0093] <Embodiment 4> FIG. 11 is a cross-sectional view showing a configuration of a double-gate IGBT 400 according to a fourth embodiment of the present disclosure. In FIG. 11, the same components as those of the double-gate IGBT 100 shown in FIG. 1 are denoted by the same reference numerals, and overlapping descriptions are omitted.

[0094] As shown in FIG. 11, similar to the double-gate IGBT 200 shown in FIG. 7, the double-gate IGBT 400 is provided with an n-type carrier storage layer 6a and an n-type carrier storage layer 6c, and - when the donor concentration of the n-type drift layer 9 is Nd, the donor concentration of the n-type carrier storage layer 6a is N1, and the donor concentration of the n-type carrier storage layer 6c is N2, the concentration of the n-type impurity is set so as to satisfy Nd < N1 < N2.

[0095] The difference from the double-gate IGBT 200 is that the thickness from the lower end to the upper end of the n-type carrier storage layer 6c is larger than the thickness from the lower end to the upper end of the n-type carrier storage layer 6a. As a result, a distance d2 (a first distance) from the outermost surface of the p-type base layer 5c on the n-type carrier storage layer 6c to the upper end of the n-type carrier storage layer 6c is shorter than a distance d1 (a second distance) from the outermost surface of the p-type base layer 5a on the n-type carrier storage layer 6a to the upper end of the n-type carrier storage layer 6a. That is, the relationship d1 > d2 is satisfied. This means that the n-type carrier storage layer 6c is formed widely to be closer to the first main surface that is the upper surface of the semiconductor substrate. Note that, as the distance d1 and the distance d2, the distance d1 can be 1 μm and the distance d2 can be 0.8 μm.

[0096] As described above, by widely forming the n-type carrier storage layer 6c closer to the upper surface of the semiconductor substrate, the manufacturing process of the double-gate IGBT 400 can be simplified. That is, after forming the p-type base layers 5a and 5c under the same ion implantation conditions, the n-type carrier storage layers 6a and 6c are formed with the same ion implantation energy, but it is necessary to make the dose amount of n-type impurities in the n-type carrier storage layer 6c higher than the dose amount of n-type impurities in the n-type carrier storage layer 6a. This is for setting the donor concentration of the two layers to satisfy N1<N2. As a result, the n-type carrier storage layer 6c is widely formed closer to the upper surface of the semiconductor substrate, which consequently satisfies the relationship of d1>d2. In this way, the p-type base layers 5a and 5c can be formed under the same ion implantation conditions, and the manufacturing process of the double-gate IGBT 400 can be simplified.

[0097] Although FIG. 11 shows a configuration including the n-type carrier storage layer 6a, unlike the modification shown in FIG. 12, the n-type carrier storage layer 6a is not provided, and this portion is n - -type drift layer 9 in this configuration. In this case, the distance d1 is the distance from the outermost surface of the p-type base layer 5a on the n - -type drift layer 9 to the upper end of the n - -type drift layer 9.

[0098] The operation of the double-gate IGBT 400 having such a configuration is the same as that of the double-gate IGBT 100 described with reference to FIGS. 2 to 4. When turning on the double-gate IGBT 400, the gate signal and the control gate signal are controlled such that after the active gate electrode AG starts the turn-on operation, the control gate electrode CG starts the turn-on operation later than the active gate electrode AG.

[0099] Therefore, in the double-gate IGBT 400, by providing a time difference in the drive timing of the active gate electrode AG and the control gate electrode CG, the respective advantages can be utilized, noise can be reduced and the on-voltage can also be lowered, thereby improving the trade-off between noise at turn-on of the IGBT and on-voltage.

[0100] It should be noted that, by providing the n-type carrier storage layer 6a, the on-state voltage can be reduced by about 15% compared with the double-gate IGBT 100 according to Embodiment 1, and this effect is the same as that of the double-gate IGBT 200 according to Embodiment 2.

[0101] In the double-gate IGBT 400 described above, the configuration has a dummy electrode DE in addition to the active gate electrode AG and the control gate electrode CG. However, even in a configuration without the dummy electrode DE, the effect of improving the trade-off between noise at turn-on of the IGBT and on-state voltage remains unchanged. For example, like the double-gate IGBT 101 shown in FIG. 5, a configuration without providing the dummy electrode DE can be adopted. It should be noted that, as long as the n-type carrier storage layer 6c is not adjacent to the active gate electrode AG, the n-type carrier storage layer 6a and the n-type carrier storage layer 6c may or may not be in contact with each other.

[0102] In addition, in the double-gate IGBT 400 shown in FIG. 11, the control gate electrode CG is arranged so as to be sandwiched between the dummy electrodes DE, but the arrangement is not limited to this. For example, an arrangement like that of the double-gate IGBT 102 shown in FIG. 6 can also be adopted.

[0103] <Embodiment 5> FIG. 13 is a cross-sectional view showing a configuration of a double-gate IGBT 500 according to Embodiment 5 of the present disclosure. In FIG. 13, the same components as those of the double-gate IGBT 100 shown in FIG. 1 are denoted by the same reference numerals, and overlapping descriptions are omitted.

[0104] As shown in FIG. 13, similar to the double-gate IGBT 200 shown in FIG. 7, the double-gate IGBT 500 is provided with an n-type carrier storage layer 6a and an n-type carrier storage layer 6c, and n - when the donor concentration of the type drift layer 9 is Nd, the donor concentration of the n-type carrier storage layer 6a is N1, and the donor concentration of the n-type carrier storage layer 6c is N2, the concentration of the n-type impurity is set so as to satisfy Nd<N1<N2.

[0105] The difference from the double-gate IGBT200 is that the n below the n-type carrier storage layer 6c - The upper part of the drift layer 9 has a p-type impurity layer 13c (the seventh semiconductor layer). The p-type impurity layer 13c contains, for example, boron or aluminum as p-type impurities, and the concentration of the p-type impurities is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 18 / cm 3 That is the case.

[0106] By providing a p-type impurity layer 13c, the decrease in breakdown voltage of the double-gate IGBT 500 can be suppressed. Specifically, the breakdown voltage of the double-gate IGBT 500 is determined by the electric field at the bottom of the trench, but by providing a p-type impurity layer 13c near the bottom of the trench 7 containing the control gate electrode CG, the electric field at the bottom of the trench 7 is mitigated, and the decrease in breakdown voltage can be suppressed.

[0107] Furthermore, as shown in Modification 1 in Figure 14, the p-type impurity layer 13c can also be placed below the n-type carrier accumulation layer 6a. In this case, it becomes unnecessary to pattern the p-type impurity layer 13c, making manufacturing easier.

[0108] Furthermore, although Figure 13 shows a configuration with an n-type carrier storage layer 6a, as shown in Modification 2 in Figure 15, the n-type carrier storage layer 6a is omitted, and this part is n - It is also possible to have a configuration with a type drift layer 9. In this case as well, there is no need to pattern the p-type impurity layer 13c, making manufacturing easier.

[0109] The operation of the double-gate IGBT 500 with this configuration is the same as that of the double-gate IGBT 100 described using Figures 2 to 4. When the double-gate IGBT 500 is turned on, the gate signal and the control gate signal are controlled so that the control gate electrode CG turns on after the active gate electrode AG has turned on, with a delay compared to the active gate electrode AG.

[0110] Therefore, in the double-gate IGBT500, by creating a time difference in the drive timing of the active gate electrode AG and the control gate electrode CG, it is possible to leverage the characteristics of each, reduce noise while also reducing the on-voltage, thereby improving the trade-off between IGBT turn-on noise and on-voltage.

[0111] Furthermore, the effect of providing the n-type carrier storage layer 6a, which reduces the on-voltage by about 15% compared to the double-gate IGBT 100 of Embodiment 1, is the same as that of the double-gate IGBT 200 of Embodiment 2.

[0112] In the double-gate IGBT 500 described above, a dummy electrode DE was included in addition to the active gate electrode AG and control gate electrode CG. However, even in a configuration without the dummy electrode DE, the effect of improving the trade-off between IGBT turn-on noise and on-voltage remains the same. For example, a configuration without the dummy electrode DE can be used, as shown in Figure 5 for the double-gate IGBT 101. Note that, as long as the n-type carrier storage layer 6c is not adjacent to the active gate electrode AG, it does not matter whether the n-type carrier storage layer 6a and the n-type carrier storage layer 6c are in contact or not.

[0113] Furthermore, in the double-gate IGBT 500 shown in Figure 13, the control gate electrode CG was positioned so as to be sandwiched between dummy electrodes DE. However, the arrangement is not limited to this configuration, and for example, an arrangement like that of the double-gate IGBT 102 shown in Figure 6 is also possible.

[0114] Although this disclosure has been described in detail, the above description is illustrative in all respects and does not limit this disclosure. It is understood that countless variations not illustrated may be conceivable without falling outside the scope of this disclosure.

[0115] Furthermore, within the scope of this disclosure, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

Claims

1. A semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface facing each other, A first semiconductor layer of a first conductivity type is provided between the first main surface and the second main surface of the semiconductor substrate, A second semiconductor layer of a second conductivity type is provided between the first semiconductor layer and the first main surface, A third semiconductor layer of a first conductivity type is selectively provided on the first main surface side of the second semiconductor layer, A fourth semiconductor layer of second conductivity type is provided between the first semiconductor layer and the second main surface, A first main electrode is provided on the first main surface and is electrically connected to the second semiconductor layer and the third semiconductor layer, A second main electrode is provided on the second main surface and electrically connected to the fourth semiconductor layer, A first trench extending from the first main surface through the second semiconductor layer and reaching the interior of the first semiconductor layer, A second trench extending from the first main surface through the second semiconductor layer and reaching the interior of the first semiconductor layer, A first control electrode is embedded inside the first trench via a first gate insulating film, A second control electrode is embedded inside the second trench via a second gate insulating film, A fifth semiconductor layer of a first conductivity type is selectively provided in the upper part of the first semiconductor layer below the second semiconductor layer, so as to be in contact with the second gate insulating film of the second trench, The second impurity concentration in the fifth semiconductor layer is higher than the first impurity concentration in the first semiconductor layer. The fifth semiconductor layer is provided so as not to be in contact with the first gate insulating film of the first trench. A semiconductor device wherein the third semiconductor layer is provided so as to be in contact with the first gate insulating film of the first trench.

2. A semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface facing each other, A first semiconductor layer of a first conductivity type is provided between the first main surface and the second main surface of the semiconductor substrate, A second semiconductor layer of a second conductivity type is provided between the first semiconductor layer and the first main surface, A third semiconductor layer of a first conductivity type is selectively provided on the first main surface side of the second semiconductor layer, A fourth semiconductor layer of second conductivity type is provided between the first semiconductor layer and the second main surface, A first main electrode is provided on the first main surface and is electrically connected to the second semiconductor layer and the third semiconductor layer, A second main electrode is provided on the second main surface and electrically connected to the fourth semiconductor layer, A first trench extending from the first main surface through the second semiconductor layer and reaching the interior of the first semiconductor layer, A second trench extending from the first main surface through the second semiconductor layer and reaching the interior of the first semiconductor layer, A first control electrode is embedded inside the first trench via a first gate insulating film, A second control electrode is embedded inside the second trench via a second gate insulating film, A fifth semiconductor layer of a first conductivity type is selectively provided in the upper part of the first semiconductor layer below the second semiconductor layer, so as to be in contact with the second gate insulating film of the second trench, The second impurity concentration in the fifth semiconductor layer is higher than the first impurity concentration in the first semiconductor layer. The fifth semiconductor layer is provided so as not to be in contact with the first gate insulating film of the first trench. The present invention further comprises a sixth semiconductor layer of a first conductivity type, which is selectively provided in the upper part of the first semiconductor layer below the second semiconductor layer, so as to be in contact with the first gate insulating film of the first trench. A semiconductor device in which the third impurity concentration of the sixth semiconductor layer is higher than the first impurity concentration and lower than the second impurity concentration.

3. The first depth at which the second impurity concentration of the fifth semiconductor layer reaches its maximum value, The semiconductor device according to claim 2, wherein the second depth at which the third impurity concentration of the sixth semiconductor layer reaches its maximum value is different from the sixth depth.

4. The first distance from the outermost surface of the second semiconductor layer to the upper end of the fifth semiconductor layer is, The semiconductor device according to claim 2, wherein the distance from the outermost surface of the second semiconductor layer to the upper end of the sixth semiconductor layer is shorter than the distance from the outermost surface of the second semiconductor layer to the upper end of the sixth semiconductor layer.

5. A semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface facing each other, A first semiconductor layer of a first conductivity type is provided between the first main surface and the second main surface of the semiconductor substrate, A second semiconductor layer of a second conductivity type is provided between the first semiconductor layer and the first main surface, A third semiconductor layer of a first conductivity type is selectively provided on the first main surface side of the second semiconductor layer, A fourth semiconductor layer of second conductivity type is provided between the first semiconductor layer and the second main surface, A first main electrode is provided on the first main surface and is electrically connected to the second semiconductor layer and the third semiconductor layer, A second main electrode is provided on the second main surface and electrically connected to the fourth semiconductor layer, A first trench extending from the first main surface through the second semiconductor layer and reaching the interior of the first semiconductor layer, A second trench extending from the first main surface through the second semiconductor layer and reaching the interior of the first semiconductor layer, A first control electrode is embedded inside the first trench via a first gate insulating film, A second control electrode is embedded inside the second trench via a second gate insulating film, A fifth semiconductor layer of a first conductivity type is selectively provided in the upper part of the first semiconductor layer below the second semiconductor layer, so as to be in contact with the second gate insulating film of the second trench, The second impurity concentration in the fifth semiconductor layer is higher than the first impurity concentration in the first semiconductor layer. The fifth semiconductor layer is provided so as not to be in contact with the first gate insulating film of the first trench. The first distance from the outermost surface of the second semiconductor layer to the upper end of the fifth semiconductor layer is, A semiconductor device having a distance shorter than the second distance from the outermost surface of the second semiconductor layer to the upper end of the first semiconductor layer in the region where the first trench is provided.

6. The semiconductor device according to claim 2, further comprising a seventh semiconductor layer of a second conductivity type provided inside the first semiconductor layer below the fifth semiconductor layer.

7. The seventh semiconductor layer is The semiconductor device according to claim 6, further provided inside the first semiconductor layer below the sixth semiconductor layer.

8. A semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface facing each other, A first semiconductor layer of a first conductivity type is provided between the first main surface and the second main surface of the semiconductor substrate, A second semiconductor layer of a second conductivity type is provided between the first semiconductor layer and the first main surface, A third semiconductor layer of a first conductivity type is selectively provided on the first main surface side of the second semiconductor layer, A fourth semiconductor layer of second conductivity type is provided between the first semiconductor layer and the second main surface, A first main electrode is provided on the first main surface and is electrically connected to the second semiconductor layer and the third semiconductor layer, A second main electrode is provided on the second main surface and electrically connected to the fourth semiconductor layer, A first trench extending from the first main surface through the second semiconductor layer and reaching the interior of the first semiconductor layer, A second trench extending from the first main surface through the second semiconductor layer and reaching the interior of the first semiconductor layer, A first control electrode is embedded inside the first trench via a first gate insulating film, A second control electrode is embedded inside the second trench via a second gate insulating film, A fifth semiconductor layer of a first conductivity type is selectively provided in the upper part of the first semiconductor layer below the second semiconductor layer, so as to be in contact with the second gate insulating film of the second trench, The second impurity concentration in the fifth semiconductor layer is higher than the first impurity concentration in the first semiconductor layer. The fifth semiconductor layer is provided so as not to be in contact with the first gate insulating film of the first trench. A semiconductor device further comprising a seventh semiconductor layer of a second conductivity type provided inside the first semiconductor layer below the fifth semiconductor layer and inside the first semiconductor layer in the region where the first trench is provided.

9. A third trench extending from the first main surface through the second semiconductor layer and reaching the interior of the first semiconductor layer, A semiconductor device according to any one of claims 1 to 8, comprising: a dummy electrode embedded in the third trench via a third gate insulating film, which is not connected to the first control electrode and the second control electrode.

10. The dummy electrode is, The semiconductor device according to claim 9, electrically connected to the first main electrode.

11. The third trench is, The semiconductor device according to claim 9, provided between the first trench and the second trench.

12. The third trench is The semiconductor device according to claim 10, provided between the first trench and the second trench.

13. A method for controlling a semiconductor device according to any one of claims 1, 2, 5, and 8, In at least one of the turn-on and turn-off of the semiconductor device, A control method for a semiconductor device, which controls the device so that a second ON signal is input to the second control electrode after a first ON signal is input to the first control electrode.

14. The control method for the semiconductor device according to claim 13, wherein the control method for the semiconductor device is performed when the semiconductor device is turned on.

15. The control method for the semiconductor device according to claim 14, wherein the control method for the semiconductor device is also performed when the semiconductor device is turned off, and the delay time of the second control electrode during the turn-on is set to be shorter than the delay time during the turn-off.

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