Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

The semiconductor device (100) comprises a semiconductor body (10) having a top surface (11) and a bottom surface (19). A first main electrode (2) is disposed on the top surface, and a second main electrode (3) is disposed on the bottom surface. The semiconductor device comprises a gate electrode (4) and at least two trenches, namely, a first type trench (51) and a second type trench (52). The semiconductor body comprises a drift region (14) of a first conductivity type and at least three base regions (13a, 13b, 13c), each of a second conductivity type. The semiconductor body further comprises an implanted region (12) of the first conductivity type. The first main electrode is in electrical contact with the implanted region. The gate electrode extends into the first type trench. The second type trench does not have a gate electrode. A conductive layer (8) is disposed on the top surface above the third base region and is electrically connected to the electrodes. The conductive layer is located near the third base region so as to capacitively couple to the third base region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] There is a need for improved semiconductor devices, for example semiconductor devices with improved static and / or dynamic behavior. Furthermore, there is a need to provide a method for manufacturing such semiconductor devices.

Summary of Invention

Means for Solving the Problems

[0003] Embodiments of the present disclosure relate to a semiconductor device and a method for manufacturing a semiconductor device.

[0004] First, a semiconductor device is specified. According to one embodiment, the semiconductor device comprises a semiconductor body extending vertically between a top surface and a bottom surface. A first main electrode is located on the top surface, and a second main electrode is located on the bottom surface. Furthermore, the semiconductor device comprises a gate electrode and at least two trenches, namely a first type trench and a second type trench, each extending from the top surface into the semiconductor body. The semiconductor body comprises a drift region of a first conductivity type arranged vertically between the top surface and the bottom surface, and at least three base regions, namely first, second, and third base regions, each of a second conductivity type and each arranged vertically between the drift region and the top surface. The semiconductor body further comprises an injection region of a first conductivity type, separated vertically from the drift region by the first base region and adjacent to the first base region. The first base region, the first type trench, the second base region, the second type trench, and the third base region are arranged alternately in the first lateral direction in this order. The first main electrode is in electrical contact with the injection region. The gate electrode extends into the first type of trench, where it is isolated from the semiconductor body by a gate insulating layer. The second type of trench does not have a gate electrode.

[0005] The arrangement having a second type of trench, a second base region, and a third base region is particularly useful in protecting the first type of trench, especially the gate insulating layer within it, from, for example, electron avalanches during switching events.

[0006] The semiconductor devices described herein may be power semiconductor devices. For example, they may be configured to carry a current of at least 10A and / or to handle a voltage of at least 1000V or at least 3000V. The semiconductor devices may also be transistor devices, in particular gate-isolated transistor devices, in particular IGFETs.

[0007] The semiconductor body may be based on silicon or silicon carbide. The thickness of the semiconductor body, measured vertically, is, for example, at least 100 μm or at least 200 μm and / or at most 500 μm. The top and bottom surfaces are the faces of the semiconductor body and divide the semiconductor body vertically.

[0008] The first and / or second main electrodes may contain or consist of metal. Depending on the type of semiconductor device, the first electrode may also be referred to herein as the “emitter electrode” or “source electrode,” respectively, and the second main electrode may also be referred to as the “collector electrode” or “drain electrode,” respectively.

[0009] The gate electrode may contain metal and / or highly doped polysilicon. More specifically, the gate electrode is an insulating gate electrode, meaning it is electrically insulated from the semiconductor body. This may be achieved, for example, with the help of a gate insulating layer.

[0010] Trenches extend from the top surface of the semiconductor body into the semiconductor body and terminate within the semiconductor body, for example, in the drift region. Trenches may have the same depth when measured vertically. The depth of a trench may be at least 1 μm or at least 5 μm and / or at most 20 μm or at most 10 μm. Each trench may be elongated and each may extend laterally, the later direction being defined herein as the direction perpendicular to the vertical direction. More specifically, the later direction is the direction parallel to the main extension plane of the semiconductor body. For example, trenches may extend parallel to each other.

[0011] The first type of trench and the second type of trench may be spaced apart from each other in the first lateral direction. Each trench may extend in the second lateral direction perpendicular to the first lateral direction. The average distance between the first type of trench and the second type of trench is, for example, at least 100 nm or at least 500 nm and / or at most 2 μm. The distance between two trenches is defined herein, for example, as the pitch between trenches, i.e., the distance between the centers of the trenches. For example, no further trenches are located laterally between the first type of trench and the second type of trench.

[0012] The first type of trench is filled with a conductive material separated from the semiconductor body by a gate insulating layer. The conductive material is spatially and electrically isolated from the semiconductor body by the gate insulating layer. The gate insulating layer may be an oxide, for example, SiO2. The thickness of the gate insulating layer may be at least 10 nm and / or at most 200 nm. For example, the thickness of the gate insulating layer is between 50 nm and 150 nm.

[0013] In this specification, “electrically isolated” specifically means that there is no electrical contact between the two elements. Two electrically isolated elements are configured, for example, to be electrically biased or controlled independently. This means that they are configured to be at different potentials during the operation of the semiconductor device. Two electrically isolated elements may, in detail, be electrically insulated from each other, i.e., there is no possibility of current being generated between them.

[0014] The conductive material in the first type of trench may be a metal and / or highly doped polysilicon. The conductive material in the first type of trench is part of the gate electrode, i.e., electrically connected to the gate electrode. When two elements are electrically connected or in contact, this means that these two elements are not electrically biasable or controllable independently. Therefore, they are always at the same potential. The first type of trench is also referred to herein as an active trench.

[0015] For example, the conductive material in the first type of trench reaches the semiconductor body to at least the same depth as the first base region and / or the second base region.

[0016] The second type of trench has no gate electrode. That is, the second type of trench is a trench without a gate electrode. In other words, the second type of trench is electrically isolated from the gate electrode.

[0017] The second type of trench may also be filled with a conductive material that may be isolated from the semiconductor body by a gate insulating layer. However, this conductive material is electrically isolated from the gate electrode, i.e., not electrically connected to the gate electrode. The insulating layer may be the same as the gate insulating layer. In the second type of trench, the conductive material may reach into the semiconductor body to the same depth as the first and / or second base regions. The conductive material in the second type of trench may be a metal and / or highly doped polysilicon.

[0018] For example, the conductive material in the second type of trench is electrically connected to the first main electrode. In other words, the first main electrode may extend into the second type of trench.

[0019] Instead of being filled with conductive material, the second type of trench does not need to have conductive material; for example, it may be filled only with an electrically insulating material.

[0020] The second type of trench is also referred to herein as a “non-active trench.” The drift region of the semiconductor itself is of the first conductivity type. The first conductivity type is, for example, n-type, meaning the drift region is n-doped. The second conductivity type is the opposite of the first conductivity type and can therefore be p-type. However, the opposite case can also be realized, where the first conductivity type is p-type and the second conductivity type is n-type.

[0021] The drift region extends continuously across all base regions, for example. That is, when viewed from above the top surface, the drift region overlaps with all three base regions.

[0022] The first type of trench is located in the first lateral direction between a first base region and a second base region. For example, the first type of trench is adjacent to the first base region of one face and / or the second base region of another face.

[0023] The second base region is located in the first lateral direction between the first type of trench and the second type of trench. The second base region may be adjacent to the second type of trench. The second base region may extend continuously, for example, without interruption, from the first type of trench to the second type of trench.

[0024] The second type of trench is located in the first lateral direction between the second base region and the third base region. The second type of trench may be adjacent to the third base region.

[0025] The third base region may extend continuously, for example, without interruption, from the second type of trench to a further trench spaced laterally from the first type of trench. The further trench may be another second type of trench, i.e., each may be electrically isolated from the gate electrode or filled with the gate electrode.

[0026] A structure including a first base region and an adjacent implanted structure, a first-type trench, a second base region, a second-type trench, and a third base region may be repeated several times along the upper surface. A structure including at least a part (half) of the first base region together with an adjacent implanted region, the first-type trench, the second base region, the second-type trench, and a part (half) of the third base region is also referred to as a "half cell" or a "transistor half cell". A semiconductor device may include a plurality of such half cells that can be alternately arranged in a first lateral direction. Each two adjacent half cells may be mirror-symmetrical with respect to a mirror plane. The mirror plane extends perpendicularly in a first vertical direction, for example. The mirror plane may intersect the first and / or third base region at half of a respective extension in the first lateral direction.

[0027] A semiconductor body includes an implanted region of a first conductivity type. The implanted region is vertically spaced apart from a drift region by the first base region and adjacent to the first base region. The implanted region reaches the upper surface, for example. The implanted region may be incorporated in the first base region. For example, the implanted region is adjacent to the first-type trench on the same side where the first base region is adjacent to the first-type trench. Each half cell may include exactly one such implanted region. The implanted region is also referred to as a source region.

[0028] The implanted region is in electrical contact with a first main electrode, for example, it is adjacent to the first main electrode. During operation of the semiconductor device in a (static) transistor mode, charge carriers of a first type, for example electrons, are injected from the first main electrode into the implanted region. The semiconductor device is configured such that, by applying a specific potential to a gate electrode, the first base region adjacent to the first-type trench is depleted, as a result of which a path for charge carriers of the first type from the implanted region toward the drift region is formed, and said path extends vertically along the first-type trench.

[0029] The second base region may form part of the upper surface, for example, the entire portion of the upper surface located laterally between the first type of trench and the second type of trench. For example, the semiconductor body is arranged vertically between the second base region and the upper surface, and does not have a (implantation) region of the first conductivity type adjacent to the second base region.

[0030] The third base region may also form part of the upper surface, for example, the entire portion of the upper surface located laterally between two trenches that laterally delimit the third base region. The semiconductor body is arranged vertically between the third base region and the upper surface, and does not have a (implantation) region of the first conductivity type adjacent to the third base region.

[0031] According to a further embodiment, the semiconductor body comprises a conductive layer arranged on the upper surface of the semiconductor body above the third base region. The conductive layer is electrically connected to an electrode of the semiconductor device that is different from the gate electrode. This means that the conductive layer is configured to be electrically biased / controlled independently of the gate electrode, i.e., it can be set to a potential different from the potential of the gate electrode.

[0032] The conductive layer on the upper surface above the third base region may comprise or consist of metal and / or highly doped polysilicon. For example, the conductive layer is electrically connected to the first main electrode, or connected to an electrode that can be controlled / biased independently of the first main electrode.

[0033] Viewed from above the upper surface, the conductive layer and the third base region at least partially overlap each other. That is, viewed from above the upper surface, the conductive layer covers at least a part of the third base region. The conductive layer may be a continuous layer, or may be formed from a plurality of segments spaced apart from each other in at least one lateral direction. Specifically, the conductive layer extends parallel to the upper surface of the semiconductor body and / or parallel to the main extension plane.

[0034] According to a further embodiment, since the conductive layer is located very close to the third base region, a strong capacitive coupling between the third base region and the conductive layer can be achieved by electrically biasing the conductive layer, such that free charge carriers in the third base region are thereby affected. "Affected" means, for example, that the free charge carriers are attracted to or repelled by the conductive layer. In detail, the free charge carriers are second-type charge carriers depending on the conductivity type of the third base region. Thus, if the third base region is p-doped, the free charge carriers can be holes.

[0035] Such conductive layers can improve the operation of semiconductor devices. For example, during static operation, the conductive layer can repel free charge carriers in a third base region to maintain a high electron-hole plasma within the semiconductor body or to shift it toward the gate electrode in a first type trench. When switching semiconductor devices, the conductive layer can attract second type charge carriers to pull the electron-hole plasma away from the first type trench. This reduces the risk, for example, of damage to the gate insulating layer in the first type trench due to electron avalanches. For example, the density of second type free charge carriers in the upper third base region is at least 10% or at least 20% lower during static operation than when such a conductive layer is not used.

[0036] The maximum distance between the third base region and the conductive layer required to achieve such strong capacitive coupling depends on several factors, such as the potential applied to the conductive layer and the material perpendicularly positioned between the conductive layer and the semiconductor body on its lateral extension. For example, the maximum perpendicular distance between the conductive layer and the third base region is approximately the same as the thickness of the gate insulating layer.

[0037] In a further embodiment, the conductive layer is separated from the upper surface of the semiconductor body by an electrically insulating layer positioned perpendicularly between the upper surface and the conductive layer. The electrically insulating layer may be an oxide. For example, it may be made of the same material as the gate insulating layer. For example, the electrically insulating layer may be made of SiO2.

[0038] For example, the conductive layer is separated from the top surface only by the electrical insulating layer. That is, the vertical distance between the top surface and the conductive layer is determined by the thickness of the electrical insulating layer. The electrical insulating layer may fill most of the space between the conductive layer and the top surface of the semiconductor body. For example, at least 70%, 80%, or 90% of the volume between the conductive layer and the top surface may be filled by the electrical insulating layer.

[0039] In a further embodiment, the thickness of the electrical insulation layer is at most 5 times, at most 3 times, or at most 1.5 times greater than the thickness of the gate insulation layer. This is one method for achieving strong capacitive coupling.

[0040] In a further embodiment, the vertical distance between the conductive layer and the third base region is at most 500 nm, at most 300 nm, or at most 150 nm. Additionally or alternatively, the vertical distance between the conductive layer and the third base region may be at least 10 nm or at least 50 nm. This minimum distance exists in at least a specific region of the conductive layer. This is one method for achieving strong capacitive coupling.

[0041] In a further embodiment, the conductive layer and the third base region are electrically isolated from each other. That is, the semiconductor device does not have a (direct) electrical connection between the conductive layer and the third base region. For example, the electrical insulating layer then extends continuously and uninterrupted between the conductive layer and the upper surface of the semiconductor body, extending over the entire lateral extension of the conductive layer.

[0042] In a further embodiment, an electrical connection is formed between the conductive layer and the third base region. For example, the conductive layer is in electrical contact with the third base region in one or more contact regions of the third base region. In these contact regions, the conductive layer may be adjacent to the third base region. Viewed from above the top surface, the total area of ​​the contact regions is, for example, at most 50%, at most 30%, or at most 10% of the area of ​​the conductive layer. The remaining portion of the conductive layer, i.e., outside the contact regions, is separated from the semiconductor body by, for example, an electrical insulating layer.

[0043] According to further embodiments, when viewed from above the top surface, the conductive layer covers most of the third base region. For example, in this plan view, the conductive layer covers at least 60%, at least 80%, or at least 90% of the third base region. Additionally or alternatively, in this top view, the conductive layer does not overlap with the second type of trench and / or any of the trenches that laterally divide the third base region. In this top view, the conductive layer may overlap with either the second type of trench or one of the trenches that laterally divide the third base region, but may not extend laterally beyond this / these trenches.

[0044] In a further embodiment, the conductive layer is positioned perpendicularly between the top surface of the semiconductor body and a portion of the emitter electrode. For example, when viewed from above the top surface, the portion of the emitter electrode and the conductive layer overlap each other. For example, in this top view, the portion of the emitter electrode completely covers the conductive layer.

[0045] In a further embodiment, the vertical distance between the conductive layer and the third base region is at most half, at most one-fifth, or at most one-tenth of the vertical distance between a portion of the emitter electrode and the upper surface of the semiconductor body. In particular, since the portion of the emitter electrode is far away from the third base region, it does not capacitively couple to the third base region.

[0046] For example, the vertical distance between a portion of the emitter electrode and the top surface is at least 800 nm, or at least 1 μm, or at least 1.5 μm.

[0047] A further electrical insulating layer may exist, positioned perpendicularly between the top surface of the semiconductor body and a portion of the emitter electrode. The thickness of this further insulating layer may define the distance between the portion of the emitter electrode and the top surface. This further insulating layer may be an oxide such as SiO2. It is also referred to herein as a field insulating layer.

[0048] According to further embodiments, the semiconductor device is capable of operating in a first mode in which free charge carriers in a third base region, particularly second-type charge carriers, such as holes, are repelled by a conductive layer. For example, in the first mode, the conductive layer is at a positive potential.

[0049] According to further embodiments, the semiconductor device is capable of operating in a second mode in which free charge carriers in a third base region, particularly second-type charge carriers, such as holes, are attracted by the conductive layer. For example, in the second mode, the conductive layer is at a negative potential.

[0050] In a further embodiment, the first mode is transistor mode and / or the second mode is diode mode. That is, in the first mode, the semiconductor device operates as a transistor, and in the second mode, the semiconductor device operates as a diode.

[0051] For example, in the first mode, the gate electrode and the first main electrode are at different potentials. In transistor mode, the first main electrode can be at a positive potential relative to the second main electrode. In diode mode, this can be reversed, i.e., the first main electrode is at a negative potential relative to the second main electrode.

[0052] In a further embodiment, the third base region comprises at least one contact region that is electrically in contact with an electrode of a semiconductor device different from the gate electrode, for example, a contact region that is controllable / biasable independently of the gate electrode.

[0053] During operation, charge carriers can be extracted from the semiconductor body through contact regions. Therefore, contact regions are sometimes called “extraction regions.” Such extraction regions can be advantageous during switching events, for example, during transistor mode turn-off, as they help rapidly reduce the plasma concentration within the semiconductor body. That is, the contact regions constitute a plasma control mechanism. On the other hand, when the semiconductor device operates in diode mode, the electrical contact between the electrodes in the contact regions and the semiconductor body provides (further) charge carrier pathways that reduce on-state losses in diode mode. Since the contact regions are electrically in contact with electrodes different from the gate electrode, the pathways for charge carriers are independent of the gate electrode potential. The location of the contact regions in the third base region, i.e., separated from the first type trench by the second type trench, helps protect the gate insulating layer in the first type trench during switching events, as it reduces the generation of electron avalanches within the region of the first type trench.

[0054] For example, the electrode to which the third base region is electrically connected within the contact region is located on the upper surface. The electrode may be the first main electrode, or another electrode that can be controlled independently of the first main electrode.

[0055] The contact region belongs to the third base region and is therefore also referred to herein as the third contact region. The contact region may form part of the top surface. The third base region may be adjacent to the electrode over the entire area of ​​the contact region. Viewed from above the top surface, the area of ​​the contact region is, in detail, smaller than the area of ​​the third base region. For example, in this top view, the area of ​​the contact region is at most 50%, at most 10%, at most 5%, or at most 1% of the area of ​​the third base region. For some contact regions, all features disclosed for one contact region are also disclosed for the other contact regions.

[0056] According to further embodiments, the semiconductor device is an RC-IGBT, i.e., a reverse-conducting IGBT, or a MISFET, particularly a MOSFET.

[0057] RC-IGBTs and MOSFETs are semiconductor devices that can operate in diode mode. In such devices, as described above, the contact region in which the third base region is electrically in contact with the electrode is particularly beneficial.

[0058] In a further embodiment, at least one contact region and conductive layer are electrically connected to the same electrode, for example, a first main electrode.

[0059] According to a further embodiment, the conductive layer comprises at least two sections spaced apart from each other in the lateral direction.

[0060] In a further embodiment, at least one contact area is positioned laterally between two sections of the conductive layer. For example, when viewed from above on the top surface, at least two sections do not overlap the contact area. The contact may be located within the gap between the two sections when viewed in this top view.

[0061] According to further embodiments, the third base region comprises a plurality of (third) contact regions. The third base region is in electrical contact with an electrode in each of these contact regions. For example, the contact regions of the third base region are spaced apart from each other in at least one lateral direction, for example, a first lateral direction. All features disclosed in relation to one contact region of the third base region are also disclosed for all other contact regions of the third base region.

[0062] The contact areas of the third base region may each be formed, for example, as a second laterally extending stripe.

[0063] Each of the two contact regions of the third base region may be spaced apart from one another. Outside the contact regions, there is no direct electrical contact between the electrode and the third base region. In particular, outside the contact regions, the electrode is not adjacent to the third base region. For example, when viewed from above, the multiple contact regions of the third base region are arranged in a rectangular pattern. For instance, in this top view, at most 50% and / or at least 10% of the area of ​​the third base region is formed by the contact regions.

[0064] According to a further embodiment, when viewed from above the top surface, at least one contact region and a conductive layer within the third base region overlap each other. For example, in the contact region, the third base region is electrically connected to the conductive layer.

[0065] Alternatively, holes may be formed through a conductive layer induced by an electrode in contact with a third base region within the contact region. Within the hole, the electrode may be separated from the conductive layer by, for example, an electrical insulating layer.

[0066] In a further embodiment, the third base region extends into the semiconductor body from the top surface to at least the same depth as the second type of trench and / or the first type of trench. For example, the third base region extends deeper into the semiconductor body than the second type of trench and / or the first type of trench. Such a design has been found to significantly reduce the intensity of electron avalanches near the first type of trench.

[0067] According to further embodiments, the first type of trench and the second type of trench may have the same depth. Alternatively, the second type of trench may extend deeper into the semiconductor than the first type of trench. Such deeper second type trenches have been found to be even more helpful in keeping electron avalanches away from the first type of trench.

[0068] According to a further embodiment, the third base region extends beneath the second type of trench toward the first type of trench. Thus, when viewed from above the top surface, the second type of trench and the third base region may overlap each other.

[0069] In a further embodiment, the second base region comprises at least one contact region in which the second base region is electrically in contact with an electrode of a semiconductor device different from the gate electrode. This electrode may be the same electrode that is electrically in contact with the third base region within each (third) contact region. The contact region of the second base region, also referred to herein as the second contact region, may form part of the top surface. The second contact region may have a smaller area than the area of ​​the second base region when viewed from above the top surface. The same relative sizes disclosed in relation to the (third) contact region of the third base region may also apply here.

[0070] The contact region of the second base region provides further flexibility for optimizing charge carrier extraction, for example, during transistor mode turn-off and / or diode mode.

[0071] In a further embodiment, the first base region comprises at least one contact region in which the first base region is electrically in contact with an electrode of a semiconductor device different from the gate electrode. This electrode may also be the same electrode that is electrically in contact with the third base region within each (third) contact region. The contact region of the first base region, also referred to herein as the first contact region, may be adjacent to the top surface and / or injection region.

[0072] The contact region of the first base region provides another degree of freedom for optimizing charge carrier extraction, for example, during transistor mode turn-off and / or diode mode.

[0073] In either case, the contact regions are part of each base region and therefore represent a second conductivity type. In each base region, at least one contact region may be spaced apart from the trenches that laterally separate each base region.

[0074] Next, a method for manufacturing semiconductor devices is specified. For example, the semiconductor devices specified herein can be manufactured by this method. Thus, all features disclosed in relation to semiconductor devices are also disclosed in relation to the method, and vice versa.

[0075] According to one embodiment, a method for manufacturing a semiconductor device includes the step of providing a semiconductor body having a top surface and a bottom surface. Then, at least two trenches, namely a first type trench and a second type trench, are formed within the semiconductor body, each trench extending from the top surface into the semiconductor body. Furthermore, a first main electrode is formed on the top surface and a second main electrode is formed on the bottom surface of the semiconductor body. A gate electrode is formed such that the gate electrode extends into the first type trench, where it is separated from the semiconductor body by a gate insulating layer. The second type trench is kept without a gate electrode. The semiconductor device is formed such that the semiconductor body comprises a drift region of a first conductivity type perpendicularly positioned between the top surface and the bottom surface, and at least three base regions, namely first, second, and third base regions, each of a second conductivity type and each perpendicularly positioned between the drift region and the top surface. The semiconductor body is separated perpendicularly from the drift region by a first base region and further comprises an injection region of a first conductivity type adjacent to the first base region. The first base region, the first type of trench, the second base region, the second type of trench, and the third base region are arranged alternately in the first lateral direction in this order. The first main electrode is in electrical contact with the injection region.

[0076] Trenches may form within the semiconductor body before the base region and injection region are formed. Alternatively, the base region may be formed, at least partially, before the trench is formed.

[0077] In a further embodiment, a conductive layer is formed on the upper surface. The conductive layer is positioned above the third base region and is electrically connected to an electrode of a semiconductor device different from the gate electrode. Because the conductive layer is located very close to the third base region, a strong capacitive coupling between the third base region and the conductive layer can be achieved by electrically biasing the conductive layer, such that free charge carriers within the third base region are thereby affected.

[0078] The semiconductor devices and methods for manufacturing them are described in more detail below with reference to drawings based on exemplary embodiments. The accompanying figures are included for further understanding. In the figures, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. The description of each of the following figures is not repeated to the extent that elements or components correspond to each other in terms of their function in different figures. For clarity, elements may not appear with corresponding reference symbols in all figures. [Brief explanation of the drawing]

[0079] [Figure 1] These are different diagrams illustrating different exemplary embodiments of semiconductor devices. [Figure 2] These are different diagrams illustrating different exemplary embodiments of semiconductor devices. [Figure 3] These are different diagrams illustrating different exemplary embodiments of semiconductor devices. [Figure 4] These are different diagrams illustrating different exemplary embodiments of semiconductor devices. [Figure 5] These are different diagrams illustrating different exemplary embodiments of semiconductor devices. [Figure 6] These are different diagrams illustrating different exemplary embodiments of semiconductor devices. [Figure 7] These are different diagrams illustrating different exemplary embodiments of semiconductor devices. [Figure 8] These are different diagrams illustrating different exemplary embodiments of semiconductor devices. [Figure 9] This figure shows different locations in an exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 10] This figure shows different locations in an exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 11]This figure shows different locations in an exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 12] These are different diagrams illustrating different exemplary embodiments of semiconductor devices. [Modes for carrying out the invention]

[0080] Figure 1 shows a cross-sectional view of a first exemplary embodiment of the semiconductor device 100. In this case, the semiconductor device 100 is an RC-IGBT. It comprises a semiconductor body 10 having a top surface 11 and a bottom surface 19 that are positioned vertically opposite to each other. The semiconductor body 10 is based on, for example, Si or SiC.

[0081] On the bottom surface 19, the semiconductor body 10 comprises alternatingly arranged first-type regions 15 and second-type regions 16. Regions 15 and 16 are in electrical contact with a second main electrode 3, i.e., a collector electrode 3, on the bottom surface 19. The collector electrode 3 is formed from, for example, a metal.

[0082] The first type region 15 is a first conductivity type, which is n-type below, and the second type region 16 is a second conductivity type, which is p-type below. The drift region 14 is located between the top surface 11 and the bottom surface 19. The drift region 14 is of the first conductivity type, i.e., n-type. The drift region 14 is adjacent to the first type region 15 and the second type region 16.

[0083] Multiple trenches 51, 52 extend from the top surface into the semiconductor body 10 and into the drift region 14. Trench 51 is a first type of trench, also referred to herein as an active trench, and trench 52 is a second type of trench, also referred to herein as an inactive trench or dummy trench.

[0084] The first type of trench 51 is filled with a conductive material that is electrically isolated from the semiconductor body 10 by an electrical insulating layer 40, referred to herein as the “gate insulating layer”. Therefore, there is no direct electrical contact between the semiconductor body 10 and the conductive material in the first type of trench 51. The gate insulating layer 40 is formed from an oxide such as SiO2. The conductive material in the first type of trench 51 may be highly doped polysilicon. The conductive material in the first type of trench 51 is part of the gate electrode 4 of the semiconductor device 100.

[0085] The second type of trench 52 is similarly filled with a conductive material, such as highly doped polysilicon, which is electrically isolated from the semiconductor body 10 by the same electrical insulating layer as the gate insulating layer 40. The conductive material in the second type of trench 52 is part of the first main electrode 2, i.e., the emitter electrode 2, located on the upper surface 12.

[0086] The semiconductor body 10 comprises several base regions 13a, 13b, and 13c arranged vertically between the drift region 14 and the upper surface 11. The base regions 13a, 13b, and 13c are all of the second conductivity type, i.e., p-type, and are all adjacent to the drift region 14 and the upper surface 11. The first base region 13a and the second base region 13b are shallower (have a smaller vertical spread) than the trenches 51 and 52. The third base region 13c is deeper than the trenches 51 and 52, i.e., extends further into the semiconductor body 10.

[0087] The first base region 13a is adjacent to and electrically in contact with the emitter electrode 2 within the first contact region 6a, also called the "Rb prime region." The third base region 13c is adjacent to and electrically in contact with the emitter electrode 2 within the third contact region 6c. The functions of these contact regions 6a and 6c are further described below.

[0088] As seen in Figure 1, the semiconductor device 100 is subdivided into several so-called half-cells. One such half-cell is shown in more detail in Figure 2. A half-cell is the structure between the vertical dashed lines in Figure 2. In Figure 1, several such half-cells are arranged alternately in a first transverse direction extending from left to right. Two adjacent half-cells are mirror images of each other in a plane extending perpendicular to the first transverse direction through a third base region 13c (see the right vertical dashed line in Figure 2).

[0089] As shown in Figure 2, the half-cell comprises a portion (half) of the first base region 13c, a first type trench 51, a second base region 13b, a second type trench 52, and a portion (half) of the third base region 13c, which are arranged alternately in this order along the first lateral direction. The half-cell further comprises a first conductivity type, i.e., n-type injection region 12 (source region 12), which is positioned perpendicularly between the first base region 13c and the top surface 11. The injection region 12 is adjacent to the first base region 13c and the first type trench 51. The injection region 12 is further adjacent to and electrically in contact with the emitter electrode 2.

[0090] The operation of semiconductor devices may be as follows: In the so-called transistor mode, the emitter electrode 2 is set to ground and the collector electrode 3 is set to positive potential. The gate electrode 4 is set to positive potential such that the first base region 13a is depleted at the boundary with the first type of trench 51. A conductive path is created in the first base region 13c along the first type of trench 51. Electrons are then injected from the emitter electrode 2 into the injection region 12, travel along the conductive path, and can reach the drift region 14. On the bottom surface 19, holes are injected from the collector electrode 3 through the second type of region 16 and similarly travel into the drift region 14, resulting in the creation of an electron-hole plasma.

[0091] When the transistor mode is turned off, the electron-hole plasma can cause an electron avalanche within the region of the first type of trench 51. Such an electron avalanche can then damage the gate insulating layer 40, which can negatively impact the long-term performance stability of the semiconductor device 10. It has been found that the second type of inactive trench 52, and the third base region extending deeper into the semiconductor body than trenches 51, 52, help to divert the electron avalanche away from the active trench.

[0092] This effect is further enhanced by the electrical contact of the third base region 13c with the emitter electrode 2 within the third contact region 6c. Charge carriers, such as holes, can be dissipated through this third contact region 6c during turn-off.

[0093] Since the semiconductor device 100 is an RC-IGBT, it can also operate in reverse mode, so-called diode mode. In diode mode, the emitter electrode 2 is, for example, on ground, and the collector electrode 2 is at a negative potential. Electrons are injected from the collector electrode 3 into a first type region 15 and must recombine with holes from the emitter electrode 2.

[0094] If there is no third contact region 6c within the third base region, the only path is through the first contact region 6a to the first base region 13c. In the case of a positive gate-emitter potential, the diode on-state loss (Vf) increases. This is because the positive gate-emitter potential establishes a channel between the n-type injection region 12 and the n-type drift region 14, creating an electron path. Therefore, the electron path short-circuits the diode path, reducing hole injection into the first base region 13a, and consequently reducing the plasma concentration.

[0095] To keep diode on-state losses low, device 100 can be operated using a negative or short-circuited (Vg=0V) gate electrode. In this case, there should be no electron path. However, this limits the usefulness of the device because it requires the gate-controlled drive and system to be adapted (not standard) or specifically designed for the application to achieve the lowest possible losses.

[0096] In the exemplary embodiment shown in relation to Figures 1 and 2, the charge carrier path for diode operation is formed through the third base region 13c via a contact region 6c within the third base region 13c. Holes can be injected through the third contact region 6c. This charge carrier path is independent of the gate electrode potential, in particular, because the second type of trench 52 adjacent to the third base region 13c is at the emitter potential rather than the gate potential. Thus, operation with a conventional gate drive scheme is possible while keeping the reverse recovery charge and Erec low.

[0097] The semiconductor device 100 in Figures 1 and 2 further comprises a conductive layer 8 on the upper surface 11 above the third base region 13c. The conductive layer 8 is separated from the semiconductor body 10 by an electrical insulating layer 80, which in this case is the same as the gate insulating layer 40.

[0098] The conductive layer 8 is electrically connected to the emitter electrode 2 and is very close to the third base region 13c, thus capacitively coupling to the third base region 13c. With the help of the conductive layer 8, holes in the third base region 13c may be affected by the conductive layer 8, for example, being attracted or repelled. For example, during transistor mode turn-off, holes are attracted by the conductive layer 8. In diode mode, holes may be repelled by the conductive layer 8.

[0099] The conductive layer 8 may be formed from highly doped polysilicon or metal. The distance between the conductive layer 8 and the third base region 13c is determined by the thickness of the electrical insulating layer 80, which is, for example, at most 150 nm.

[0100] Figure 3 is similar to that of Figure 1, but here shows a further exemplary embodiment of the semiconductor device 100 in which the third contact region 6c is absent within the third base layer 13c. The conductive layer 8 is not directly electrically connected to the third base region 13c, but is electrically isolated from it. The function of the conductive layer 8 is the same as in Figures 1 and 2.

[0101] In the exemplary embodiment of Figure 4, the gate electrode 4 and its connections to different regions of the semiconductor device 100 are not shown for clarity of the figure. Instead, it is shown that a portion of the emitter electrode 2 extends over a third base region 13c. The portion of the emitter electrode 2 is separated from the top surface 11 of the semiconductor body 10 by a further electrical insulating layer 20, also referred to herein as the “field insulating layer 20”. The field insulating layer 20 may be formed from an oxide. The vertical distance between the emitter electrode 2 and the top surface 11 is defined by the thickness of the field insulating layer 20, which is much greater than the thickness of the insulating layer 80 that separates the conductive layer 8 from the top surface 11.

[0102] As can be seen further in Figure 4, a portion of the conductive layer 8 extends to the third base region 13c and is adjacent to the third base region 13c within the contact region 6c. In this way, electrical contact between the third base region 13c and the emitter electrode 2 is established via the conductive layer 8.

[0103] In the exemplary embodiment of Figure 5, the conductive layer 8 and the connection region 6c within the third base region 13c are electrically connected to an electrode 5 that is different from the gate electrode 4, as is the case with the emitter electrode 2. The additional electrode 5 is controllable / biasable independently of the gate electrode 4 and the emitter electrode 2. Such an electrode 5 allows for further optimization of different operating modes of the semiconductor device 100. For example, in static transistor mode, electrode 5 can be set to a positive potential to repel holes from the conductive layer 8, thereby shifting the electron-hole plasma toward the active trench 51. During the turn-off of transistor mode, the additional electrode 5 can be set to a negative potential to attract holes. In (static) diode mode, electrode 5 can be set to a positive potential again.

[0104] Figure 6 shows an exemplary embodiment of the semiconductor device 100 as viewed from above the top surface 11 of the semiconductor body 10. As can be seen from the figure, the conductive layer 8, indicated by the dashed line, comprises a plurality of holes, each of which overlaps with a contact region 6c of the third base region 13c. The contact region 6c is electrically connected to an electrode, such as the emitter electrode 2, through these holes in the conductive layer 8. The conductive layer 8 itself is formed continuously.

[0105] Figure 7 shows another exemplary embodiment of the semiconductor device 100, again viewed from above on the top surface 11. In this case, the conductive layer 8 (again shown by dashed lines) comprises two sections spaced apart laterally from each other. The gap between the two sections overlaps with the contact area 6c of the third base region 13c.

[0106] Figure 8, again in cross-sectional view, shows a further exemplary embodiment of the semiconductor device 100. In contrast to the previous exemplary embodiment, the third base region 13c here comprises a first set of laterally spaced contact regions 6c. Each of these contact regions 6c is in electrical contact with the emitter electrode 2.

[0107] Furthermore, each of the second base regions 13b includes a contact region 6b, also called a second contact region 6b, and the second base region 13b is in electrical contact with the emitter electrode 2 in each of these contact regions 6b.

[0108] The contact region 6b within the second base region 13b provides another degree of freedom for optimizing the operation of the semiconductor device 100.

[0109] Figure 9 shows a first location in an exemplary embodiment of a method for manufacturing a semiconductor device 100. This location is provided with a semiconductor body 10 having a top surface 11 and a bottom surface 19. The bottom surface 19 is formed by alternatingly arranged first type regions 15 and second type regions 16. The top surface 11 is formed by a base region 13 which is a second conductivity type. A drift region 14 is located between the bottom surface 19 and the base region 13, and the drift region 14 is a first conductivity type.

[0110] Figure 10 shows the location of the trenches 51 and 52 after they have been formed within the semiconductor body 10. The trenches 51 and 52 are filled with conductive material. The conductive material within the trenches 51 and 52 is electrically isolated from the semiconductor body 10 by an electrically insulating layer 40 (gate insulating layer 40) placed within the trenches 51 and 52.

[0111] Furthermore, the first base region 13a, the second base region 13b, and the third base region 13c are formed, for example, by ion implantation. In addition, the implantation region 12 is formed within the semiconductor body 10, for example, by ion implantation.

[0112] Figure 11 shows the location where the conductive layer 8 is formed on the upper surface 11 above the third base region 13c. This conductive layer 8 is electrically isolated from the third base region 13c by an electrical insulating layer 80 formed from the same material as the gate insulating layer 40.

[0113] Figure 12 shows the semiconductor device 100 after electrodes 2, 3, and 4 have been coated onto the semiconductor body 10. The conductive layer 8 is electrically connected to the emitter electrode 2.

[0114] The embodiments shown in Figures 1 to 12 described herein represent exemplary embodiments of improved semiconductor devices and improved methods for manufacturing semiconductor devices, and therefore they do not constitute a complete list of all embodiments of improved semiconductor devices by the improved methods. Actual semiconductor devices and methods may differ from the embodiments shown, for example, with respect to arrangement, elements, and the order of method steps. [Explanation of Symbols]

[0115] Reference sign 2. First main electrode / emitter electrode 3. Second main electrode / collector electrode 4 gate 5. Further electrodes 6a First contact area 6b Second contact area 6c Third contact area 8. Conductive layer 10 Semiconductor main unit 11 Top side 12 Injection area 13 Base area 13a First base region 13b Second base region 13c Third base region 14. Drift Region 15. The first type of domain 16. Second type of domain 19. Base 20 Electrical insulation layer / Field insulation layer 40 Electrical insulation layer / gate insulation layer 51. First type of trench 52. Second type of trench 80 Electrical insulation layer 100 Semiconductor Devices / RC-IGBT

Claims

1. A semiconductor device (100), - A semiconductor body (10) extending vertically between the top surface (11) and the bottom surface (19), - The first main electrode (2) on the upper surface (11) and the second main electrode (3) on the lower surface (19), -Gate (4), - At least two trenches, each extending from the upper surface (11) into the semiconductor body (10), namely a first type trench (51) and a second type trench (52) Equipped with, - The semiconductor body (10) - A first conductive drift region (14) is vertically positioned between the upper surface (11) and the lower surface (19), - Each of the two base regions is a second conductivity type, and each is vertically positioned between the drift region (14) and the upper surface (11), namely a first base region (13a), a second base region (13b), and a third base region (13c), - The first base region (13a) is separated vertically from the drift region (14), and the first conductive injection region (12) is adjacent to the first base region (13a) Equipped with, - The first base region (13a), the first type of trench (51), the second base region (13b), the second type of trench (52), and the third base region (13c) are arranged alternately in this order in the first lateral direction. - The first main electrode (2) is in electrical contact with the injection region (12), - The gate electrode (4) extends into the first type of trench (51), where it is separated from the semiconductor body (10) by the gate insulating layer (40), - The second type of trench (52) does not have the gate electrode (4), but is filled with a conductive material and electrically connected to the first main electrode (2), and the conductive material is separated from the semiconductor body (10) by an electrical insulating layer. - The conductive layer (8) is positioned on the upper surface (11) above the third base region (13c) and is electrically connected to a further electrode (5) of the semiconductor device (100), which is different from the gate electrode (4) and different from the first main electrode (2), and at least one contact region (6c) within the third base region (13c) is also electrically connected to the further electrode (5), - The conductive layer (8) is separated from the upper surface (11) by an electrical insulating layer (80) which is arranged vertically between the upper surface (11) and the conductive layer (8). - The thickness of the electrical insulating layer (80) is at most five times greater than the thickness of the gate insulating layer (40), and as a result, the conductive layer (8) is positioned very close to the third base region (13c) in order to be configured to electrically bias the conductive layer (8), so that a strong capacitive coupling is achieved between the third base region (13c) and the conductive layer (8), and the free charge carriers in the third base region (13c) are thereby affected. - A semiconductor device (100) in which the further electrode (5) to which the conductive layer (8) is electrically connected is controllable independently of the first main electrode (2).

2. - The semiconductor device (100) according to claim 1, wherein the vertical distance between the conductive layer (8) and the third base region (13c) is at least 50 nm, and the vertical distance between the conductive layer (8) and the third base region (13c) is defined by the thickness of the electrical insulating layer (80).

3. - The semiconductor device (100) according to claim 2, wherein the vertical distance between the conductive layer (8) and the third base region (13c) is at most 500 nm.

4. - The semiconductor device (100) according to any one of claims 1 to 3, wherein, when viewed from above the upper surface (11), the conductive layer (8) covers most of the third base region (13c).

5. - The conductive layer (8) is arranged vertically between the upper surface (11) of the semiconductor body (10) and a part of the first main electrode (2), - The semiconductor device (100) according to claim 2, wherein the vertical distance between the conductive layer (8) and the third base region (13c) is at most half the vertical distance between the part of the first main electrode (2) and the upper surface (11) of the semiconductor body (10).

6. - The semiconductor device (100) is capable of operating in a first mode in which the free charge carriers in the third base region (13c) are repelled by the conductive layer (8), - The semiconductor device (100) according to any one of claims 1 to 3, wherein the semiconductor device (100) is capable of operating in a second mode in which the free charge carrier in the third base region (13c) is attracted by the conductive layer (8).

7. - The semiconductor device (100) according to any one of claims 1 to 3, wherein the semiconductor device (100) is an RC-IGBT or a MISFET.

8. - The first mode is the transistor mode, - The semiconductor device (100) according to claim 6, wherein the second mode is the diode mode.

9. - The conductive layer (8) comprises at least two sections spaced apart from each other in the lateral direction, - The semiconductor device (100) according to any one of claims 1 to 3, wherein the at least one contact region (6c) is arranged laterally between the two sections of the conductive layer (8).

10. - The third base region (13c) comprises a plurality of contact regions (6c), and the third base region (13c) is in electrical contact with the further electrode (5) in each of these contact regions (6c), - The semiconductor device (100) according to any one of claims 1 to 3, wherein the contact regions (6c) within the third base region (13c) are spaced apart from each other in at least one lateral direction.

11. A manufacturing method for manufacturing a semiconductor device (100), - A semiconductor body (10) having an upper surface (11) and a lower surface (19) is provided, - Each of them forms at least two trenches extending from the upper surface (11) into the semiconductor body (10), namely a first type trench (51) and a second type trench (52), - To form the first main electrode (2) on the upper surface (11) and the second main electrode (3) on the bottom surface (19), - The gate electrode (4) is formed such that it extends into the first type of trench (51) and is separated from the semiconductor body by the gate insulating layer (40), - The second type of trench (52) is kept without the gate electrode (4), but is filled with a conductive material and electrically connected to the first main electrode (2), and the conductive material is separated from the semiconductor body (10) by an electrical insulating layer, - Forming a conductive layer (8) on the upper surface (11) Includes, - The semiconductor device (100) is such that the semiconductor body (10) is - A first conductive drift region (14) is vertically positioned between the upper surface (11) and the lower surface (19), - Each of the two base regions is a second conductivity type, and each is vertically positioned between the drift region (14) and the upper surface (11), namely a first base region (13a), a second base region (13b), and a third base region (13c), - The first base region (13a) is separated vertically from the drift region (14), and the first conductive injection region (12) is adjacent to the first base region (13a) Formed to include, - The first base region (13a), the first type of trench (51), the second base region (13b), the second type of trench (52), and the third base region (13c) are arranged alternately in this order in the first lateral direction. - The first main electrode (2) is in electrical contact with the injection region (12), - The conductive layer (8) is positioned above the third base region (13c) and is electrically connected to a further electrode (5) of the semiconductor device (100), which is different from the gate electrode (4) and different from the first main electrode (2), and the contact region (6c) within the third base region (13c) is also electrically connected to the further electrode (5), - The conductive layer (8) is separated from the upper surface (11) by an electrical insulating layer (80) which is arranged vertically between the upper surface (11) and the conductive layer (8). - The thickness of the electrical insulating layer (80) is at most five times greater than the thickness of the gate insulating layer (40), and as a result, the conductive layer (8) is positioned very close to the third base region (13c) in order to be configured to electrically bias the conductive layer (8), so that a strong capacitive coupling is achieved between the third base region (13c) and the conductive layer (8), and the free charge carriers in the third base region (13c) are thereby affected. - A method in which the further electrode (5) to which the conductive layer (8) is electrically connected is controllable independently of the first main electrode (2).

12. A method of operation in which a semiconductor device (100) according to any one of claims 1 to 3 is operated by this method, - In static transistor mode, the additional electrode (5) is set to a positive potential to repel holes from the conductive layer (8), thereby shifting the electron-hole plasma toward the first type of trench (51). - During the turn-off of the static transistor mode, the additional electrode (5) is set to a negative potential to attract the holes. - In diode mode, the further electrode (5) is set to a positive potential.

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