Internal spacer liner for gate-all-around devices

Abstract

Semiconductor devices (e.g., gate-all-around (GAA) devices), processing tools for fabricating GAA devices, methods for fabricating GAA devices, and internal spacer liners and internal spacers for GAA devices are described. The methods include performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and internal spacers within a superlattice structure formed on an upper surface of a semiconductor substrate. The superlattice structure has multiple semiconductor material layers (e.g., silicon germanium (SiGe)) and corresponding multiple channel layers (e.g., silicon (Si)). The amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layers and corresponding multiple channel layers, and the internal spacers are formed directly on the amorphous silicon liner. One or more steps of the methods described herein are performed in situ in an integrated processing tool system.

Description

[Technical Field]

[0001] Embodiments of this disclosure relate, in general terms, to semiconductor devices. More specifically, embodiments of this disclosure relate to gate-all-around (GAA) devices and methods for forming GAA devices having internal spacer liners. [Background technology]

[0002] Transistors are essential components of most integrated circuits. Since the drive current, and therefore the speed, of a transistor is proportional to its gate width, faster transistors generally require larger gate widths. Thus, there is a trade-off between transistor size and speed, and to address the conflicting goals of maximum drive current and minimum size, "fin" field-effect transistors (finFETs) were developed. FinFETs feature a fin-shaped channel region that significantly increases transistor size without substantially increasing the transistor's mounting area, and are now used in many integrated circuits. However, FinFETs have inherent drawbacks.

[0003] To achieve increased circuit density and higher performance, the size of transistor device features continues to shrink, necessitating improvements to transistor device structures to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage current. Examples of transistor device structures include planar structures, Finn field-effect transistor (FinFET) structures, and horizontal gate-all-around (hGAA) structures. An hGAA device structure includes multiple lattice-matched channels suspended by a stacked configuration and connected by source / drain regions. hGAA structures offer good electrostatic control and can be widely used in complementary metal oxide semiconductor (CMOS) wafer manufacturing.

[0004] One of the challenges in CMOS wafer manufacturing (and GAA formation) is reducing parasitic capacitance. The selective etching process used to form recesses / cavities for internal spacer formation is extremely difficult, and as a result of this process, silicon (Si) loss at the corners of the recesses / cavities in the semiconductor material layer is unavoidable. Silicon (Si) loss reduces the current path and can even lead to current concentration if silicon (Si) loss at the corners is not properly handled. Furthermore, silicon (Si) loss significantly degrades DC performance. DC performance deteriorates even further as the channel layer becomes thinner.

[0005] Therefore, there is a need for methods to reduce the amount of silicon (Si) loss in gate-all-around (GAA) devices. [Overview of the Initiative]

[0006] One or more embodiments of the present disclosure relate to methods for manufacturing electronic devices. In some embodiments, the method includes forming a superlattice structure on the upper surface of a semiconductor substrate, the superlattice structure comprising several semiconductor material layers and corresponding channel layers arranged alternately by several stacked pairs; forming a recessed semiconductor material layer by recessing portions of the several semiconductor material layers; forming a conformally amorphous silicon liner along an electronic device, including along the recessed semiconductor material layer and the corresponding channel layers; and forming internal spacers directly on the amorphous silicon liner, the internal spacers being adjacent to source and drain regions.

[0007] Further embodiments of this disclosure relate to methods for manufacturing gate-all-around (GAA) devices. In some embodiments, the method includes pre-cleaning a semiconductor substrate, the semiconductor substrate having a superlattice structure formed on its upper surface. The superlattice structure includes a plurality of recessed semiconductor material layers and a plurality of corresponding channel layers, arranged alternately by a plurality of stacked pairs. The plurality of semiconductor material layers include silicon germanium (SiGe), and the plurality of corresponding channel layers include silicon (Si). The method further includes performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and internal spacers within the lattice structure. In some embodiments, the amorphous silicon liner is conformally formed along the GAA device, including being along the recessed semiconductor material layers and the corresponding plurality of channel layers, and the internal spacers are formed directly on the amorphous silicon liner, the internal spacers being adjacent to the source and drain regions. This method further includes etching a portion of the internal spacer, removing the replacement metal gate and recessed semiconductor material layer from the semiconductor substrate, and then etching the inner sidewall portion of the amorphous silicon liner.

[0008] Further embodiments of the present disclosure relate to processing tools. In some embodiments, the processing tool comprises a central transfer station including a robot configured to move a semiconductor substrate; a plurality of processing stations, each processing station connected to the central transfer station and providing a processing area separated from the processing areas of adjacent processing stations, the plurality of processing stations including a pre-cleaning chamber and a chemical vapor deposition (CVD) chamber; and a controller connected to the central transfer station and the plurality of processing stations. The controller is configured to operate the robot to move the semiconductor substrate between the processing stations and to control processing cycles for forming an amorphous silicon liner for a gate-all-around (GAA) device. The processing cycle comprises pre-cleaning the semiconductor substrate, wherein the semiconductor substrate has a superlattice structure formed on its upper surface, the superlattice structure comprising a plurality of recessed semiconductor material layers and corresponding channel layers arranged alternately by a plurality of stacked pairs, the plurality of semiconductor material layers comprising silicon germanium (SiGe) and the corresponding plurality of channel layers comprising silicon (Si). The processing cycle involves performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and internal spacers within the scope of a superlattice structure, wherein the amorphous silicon liner is conformally formed along the GAA device, including along a recessed semiconductor material layer and a plurality of corresponding channel layers, and the internal spacers are formed directly on the amorphous silicon liner, further comprising forming amorphous silicon liners and internal spacers adjacent to source and drain regions.

[0009] To gain a more detailed understanding of the features of this disclosure described above, a more specific description of this disclosure, which is briefly summarized above, can be obtained by referring to the embodiments. Some of these embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate typical embodiments of this disclosure and should not be considered to limit the scope of this disclosure, as this disclosure may allow for other equally valid embodiments. [Brief explanation of the drawing]

[0010] [Figure 1] This diagram shows a process flow chart for a method of forming one or more electronic devices according to one or more embodiments. [Figure 2A] A schematic cross-sectional view of one or more electronic devices according to one embodiment is shown. [Figure 2B] A schematic cross-sectional view of one or more electronic devices according to one embodiment is shown. [Figure 2C] A schematic cross-sectional view of one or more electronic devices according to one embodiment is shown. [Figure 2D] A schematic cross-sectional view of one or more electronic devices according to one embodiment is shown. [Figure 2E] A schematic cross-sectional view of one or more electronic devices according to one embodiment is shown. [Figure 2F] A schematic cross-sectional view of one or more electronic devices according to one embodiment is shown. [Figure 2G] A schematic cross-sectional view of one or more electronic devices according to one embodiment is shown. [Figure 2H] A schematic cross-sectional view of one or more electronic devices according to one embodiment is shown. [Figure 2I] A schematic cross-sectional view of one or more electronic devices according to one embodiment is shown. [Figure 2J] A schematic cross-sectional view of one or more electronic devices according to one embodiment is shown. [Figure 3] A schematic top view is shown of an exemplary multi-chamber processing system for forming an electronic device according to one or more embodiments. [Modes for carrying out the invention]

[0011] For ease of understanding, the same reference numerals have been used to indicate identical elements common to the figures where possible. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be usefully incorporated into other embodiments without further description.

[0012] Before describing some exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the configurations or processing steps described in the following specification. Other embodiments of this disclosure are possible and can be practiced or implemented in various ways.

[0013] In this specification and the appended claims, the term “substrate” refers to a surface or portion of a surface on which a process is performed. Those skilled in the art will also understand that when a substrate is mentioned, it may refer only to a portion of the substrate unless otherwise explicitly stated in the context. Furthermore, a reference to deposition on a substrate may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0014] As used herein, the term "substrate" refers to any substrate on which a film treatment is performed during a manufacturing process, or a material surface formed on a substrate. For example, depending on the application, the substrate surface on which the treatment may be performed may be made of materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, and sapphire, as well as any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. The substrate includes, but is not limited to, a semiconductor wafer, and may be referred to as a "semiconductor substrate". The substrate may be exposed to a pretreatment process of polishing, etching, reduction, oxidation, hydroxylation (or otherwise generating or grafting target chemical moieties to impart chemical functionality), annealing, and / or baking the substrate surface. In addition to performing film treatment directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film treatment steps may also be performed on an underlayer formed on the substrate, which is disclosed in more detail below. The term "substrate surface", as context indicates, is intended to include such underlayers. Accordingly, for example, when a film / layer or a partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface comprises will depend on the film being deposited and the specific chemistry used.

[0015] In this specification and the appended claims, terms such as "precursor", "reactant", and "reactive gas" are used interchangeably to refer to any gas species capable of reacting with a substrate surface.

[0016] As used herein, the term "in situ" refers to a process that is performed entirely within the same processing chamber or within various processing chambers connected as part of an integrated processing system, such that each process is performed without vacuum break. As used herein, the term "ex situ" refers to a process that is performed in at least two different processing chambers, such that one or more processes are performed with interruption by vacuum break. In some embodiments, the process is performed without vacuum break and without exposure to ambient air.

[0017] A transistor is a circuit component or circuit element that is often formed on a semiconductor device. In accordance with a circuit design, transistors are formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions comprise doped regions of a substrate and exhibit doping profiles suitable for a particular application. The gate is disposed over the channel region and includes a gate dielectric interposed between the gate electrode and the channel region in the substrate.

[0018] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement-mode field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field in the device generated by the voltage difference between the body of the device and the gate. The three terminals of a FET are the source (S), through which carriers enter the channel, the drain (D), through which carriers exit the channel, and the gate (G), which modulates the conductivity of the channel. Conventionally, the current entering the channel at the source (S) is I S , and the current entering the channel at the drain (D) is I D and is referred to as. The drain-source voltage is V DSIt is called a gate (G). By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D It is possible to control ).

[0019] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the device's conductivity is determined by the voltage across the insulated gate. This ability to change conductivity depending on the amount of applied voltage is used to amplify or switch electronic signals. A MOSFET is based on the change in charge concentration due to the capacitance of the metal-oxide-semiconductor (MOS) between the body electrodes and the gate electrode, which is located above the body and insulated from all other device regions by the gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each of which is connected to a separate, highly doped region separated by the body region. These regions can be p-type or n-type, but both are the same type, the opposite type to the body region. The source and drain are highly doped (unlike the body), and the doping type is indicated by a "+" symbol.

[0020] If a MOSFET is an n-channel or nMOS FET, the source and drain are in the n+ region, and the body is in the p region. If a MOSFET is a p-channel or pMOS FET, the source and drain are in the p+ region, and the body is in the n region. The source is so named because it is the source of charge carriers (electrons in the case of n-channels, holes in the case of p-channels) flowing through the channel, and similarly, the drain is where the charge carriers exit the channel.

[0021] In this specification, the term "fin field-effect transistor (FinFET)" refers to a MOSFET transistor fabricated on a substrate in which the gate is located on two or three sides of the channel, forming a double-gate or triple-gate structure. FinFET devices are given the general name FinFET because the channel region forms "fins" on the substrate. FinFET devices have fast switching times and high current densities.

[0022] In this specification, the term “gate all-around (GAA)” is used to refer to electronic devices, such as transistors, in which the gate material surrounds the entire channel region. The channel region of a GAA transistor may include nanowires or nanoslabs, or nanosheets, rod-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of vertically spaced horizontal nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0023] In this specification, the term "nanowire" refers to a wire with a diameter of nanometers (10⁻¹⁰ -9This refers to nanostructures on the order of meters. Nanowires can also be defined as structures with a length-to-width ratio greater than 1000. Alternatively, nanowires can be defined as structures whose thickness or diameter is limited to tens of nanometers or less, but whose length is not limited. Nanowires are used in transistors and some laser applications, and in one or more embodiments, they are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. In this specification, the term “nanosheet” refers to two-dimensional nanostructures having a thickness in the range of about 0.1 nm to about 1000 nm.

[0024] Embodiments of the present disclosure are illustrated by drawings showing devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The illustrated processes are merely illustrative examples of possible uses of the disclosed processes, and those skilled in the art will see that the disclosed processes are not limited to the illustrated uses.

[0025] Figure 1 shows a process flow diagram of Method 100 for forming an electronic device (e.g., a gate-all-around (GAA) device) according to several embodiments of the present disclosure. Method 100 is described below with reference to Figures 2A to 2J, which show the manufacturing steps of a semiconductor structure according to several embodiments of the present disclosure. Figures 2A to 2J show cross-sectional views of a GAA device according to one or more embodiments. Method 100 may be part of a multi-step manufacturing process for a semiconductor device. Thus, Method 100 may be performed in any suitable processing chamber coupled to a cluster tool such as the processing system 400 shown in Figure 3. The processing system 400 may include processing chambers for manufacturing a semiconductor device, such as chambers configured for pre-cleaning, etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD) such as thermal CVD, epitaxial growth, oxidation, or any other suitable chambers used for manufacturing a semiconductor device.

[0026] Figure 2A shows a semiconductor substrate 200 having a top surface 202. In this specification, the terms “semiconductor substrate 200” and “substrate 200” may be used interchangeably. Optionally, method 100 includes one or more etching processes (step 102) further described below to form the substrate 200 shown in Figure 2A. In some embodiments, the substrate 200 may be a bulk semiconductor substrate. In this specification, the term “bulk semiconductor substrate” refers to a substrate whose entirety is made of semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor material may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 200 includes a semiconductor material, for example, silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 200 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While some examples of materials that can form substrates are described herein, the concept and scope of this disclosure may include any material that can serve as a basis for constructing passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices).

[0027] In some embodiments, the semiconductor material may be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. Herein, the term “n-type” refers to a semiconductor produced by administering an electron donor element to an intrinsic semiconductor during manufacturing. The term “n-type” derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. Herein, the term “p-type” refers to the positive charge of wells (or holes). Compared to n-type semiconductors, p-type semiconductors have a higher hole concentration than electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof. In some embodiments, the substrate 200 may be doped to provide a high dose of dopant at a first location on the surface of the substrate 200 in order to prevent the turn-on of a parasitic bottom device.

[0028] At least one superlattice structure 204 is formed on the upper surface 202 of the substrate 200. The superlattice structure 204 includes a plurality of semiconductor material layers 226 and a plurality of corresponding channel layers 224, which are alternately arranged in a plurality of stacked pairs. In this specification, the terms “semiconductor material layer 226” and “dummy semiconductor layer 226” may be used interchangeably. In some embodiments, the plurality of stacked layers include silicon (Si), germanium (Ge), and silicon-germanium (SiGe) groups. In some embodiments, the silicon-germanium (SiGe) may contain germanium (Ge) in a mole fraction ranging from 0% to 50%. In some embodiments, the plurality of semiconductor material layers 226 include silicon-germanium (SiGe), and the plurality of channel layers 224 include silicon (Si). In some embodiments, the plurality of semiconductor material layers 226 and the corresponding plurality of channel layers 224 include any number of lattice-matched material pairs suitable for forming a superlattice structure 204. In some embodiments, the plurality of semiconductor material layers 226 and the corresponding plurality of channel layers 224 include about 2 to about 50 pairs of lattice-matched material. In some embodiments, the plurality of channel layers 224 may be doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0029] In one or more embodiments, the thicknesses of the multiple semiconductor material layers 226 and the multiple channel layers 224 are in the range of about 2 nm to about 50 nm, including any subrange and values ​​within that range, for example, in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm.

[0030] Figure 2A also shows a substitution gate structure (e.g., a dummy gate structure 209) formed and patterned on the superlattice structure 204. The dummy gate structure 209 defines the channel region of the transistor device. The dummy gate structure 209 can be formed using any suitable conventional deposition and patterning process known in the art. The dummy gate structure 209 may include any suitable material known to those skilled in the art. In some embodiments, the dummy gate structure 209 may include one or more of a sacrificial oxide layer 210 and a dummy gate polysilicon layer 212. In some embodiments, a sidewall spacer 214 is formed along the outer sidewall of the dummy gate structure 209. The sidewall spacer 214 in some embodiments includes a suitable insulating material known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, or silicon carbide. In some embodiments, the sidewall spacer 214 is formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0031] Referring to Figure 2B, in step 104, in some embodiments, the source trench 232 and the drain trench 234 are formed adjacent to the superlattice structure 204 on both sides of the superlattice structure 204. In some embodiments, the source trench 232 is formed adjacent to a first end face of the superlattice structure 204, and the drain trench 234 is formed adjacent to a second end face on the opposite side of the superlattice structure. In the embodiments shown in Figure 2B, one of the source trench 232 or the drain trench 234 is not shown on the front of the superlattice structure 204. The other end face of the superlattice structure 204 has the other of the source trench 232 or the drain trench 234. In some embodiments, the source trench 232 and the drain trench 234 include a source region and a drain region formed in the source trench 232 and the drain trench 234, respectively. In other words, in some embodiments, the source region is formed in the source trench 232 and the drain region is formed in the drain trench 234. In some embodiments, the source region and / or drain region are formed from any suitable semiconductor material, including but not limited to silicon, germanium, silicon germanium, silicon phosphorus, or silicon arsenic. In some embodiments, the source region and drain region may be separately doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga). In some embodiments, the source region and drain region may be formed using any suitable deposition process, such as an epitaxial deposition process.

[0032] Referring to Figure 2C, in step 106, a portion of the semiconductor material layer 226 is isotropically cavity etched to form a recessed semiconductor material layer 226'. In one or more embodiments, the openings may be formed by isotropically etching under the superlattice structure 204. In some embodiments, the superlattice structure 204 comprises alternating layers of silicon (Si) (e.g., multiple channel layers 224) and silicon germanium (SiGe) (e.g., multiple semiconductor material layers 226), which are isotropically etched to form cavity openings under the superlattice structure 204, for example, by a dry etching process, a wet etching process, a RIE process, or a combination thereof. In some embodiments, the dry etching process includes using fluorine-based etchants such as HF, CF4, SF6, CH2F2, CHF3, C2F6, other fluorine-containing etchants, or a combination thereof. In some embodiments, the wet etching process includes using an etchant comprising nitric acid (HNO3), ammonium hydroxide (NH3OH), ammonium fluoride (NH4F), hydrogen peroxide (H2O2), other suitable etchants, or a combination thereof. In some embodiments, the etching process is controlled by factors such as duration, temperature, pressure, source power, bias voltage, bias power, etchant flow rate, and / or other suitable parameters to remove a desired amount of semiconductor material layer 226. In some embodiments, the amount of semiconductor material layer 226 removed in step 106 is controlled by the duration of the etching process so as to ensure that a channel length L sufficient to form a metal gate stack in a subsequent processing step is maintained.

[0033] In some embodiments, after cavity etching of the semiconductor material layer in step 106, and before the formation of the internal spacer liner and internal spacer in step 108, a pre-cleaning process may be performed. The pre-cleaning process may include any suitable pre-cleaning process known to those skilled in the art. In some embodiments, the pre-cleaning process includes etching a portion of several semiconductor material layers 226 with dilute hydrofluoric acid (dilute hydrogen fluoride (HF)) (including dilute hydrogen fluoride (HF) at a ratio greater than 100:1, e.g., 130:1) to etch away native oxides on the substrate and form a hydrophobic surface. In some embodiments, the pre-cleaning process may include conventional plasma etching or a remote plasma-assisted dry etching process (e.g., the SiCoNi® etching process available from Applied Materials, Inc., Santa Clara, California). In the SiCoNi® etching process, the device is exposed to plasma species of H2, NF3, and / or NH3 (e.g., plasma-excited hydrogen and fluorine species). For example, in some embodiments, the device may be simultaneously exposed to H2, NF3, and NH3 plasma. The SiCoNi® etching process can be performed in a SiCoNi® pre-cleaning chamber, which can be incorporated into one of a variety of multi-processing platforms, including, for example, the Centura®, Dual ACP, Producer® GT, and Endura® platforms available from Applied Materials (P).

[0034] The wet etching process may include a hydrofluoric acid (HF) final process (i.e., a so-called "HF last" process) in which HF etching of the surface is performed, thereby leaving the surface hydrogen-terminated. Alternatively, any other liquid-based pre-epitaxial pre-cleaning process may be employed. In some embodiments, the process includes sublimation etching for the removal of native oxides. The etching process may be plasma-based or heat-based. The plasma treatment may be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0035] As shown in Figure 2D, in step 110, method 100 includes performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner 250 and an internal spacer 260. In one or more embodiments, the CVD process is a thermal CVD process. The internal spacer liner 250 is particularly useful in nMOS FET structures, pMOS FET structures, and GAA devices, and will be described in that context, but the internal spacer liner 250 is not limited to these applications.

[0036] Embodiments of this disclosure relate to internal spacer liners that improve the overall performance of GAA devices. Some embodiments relate to forming the internal spacer liner before the formation of the internal spacer to compensate for silicon (Si) corner losses during recess / cavity etching. Some embodiments advantageously provide complete recovery of ion / current losses by forming the internal spacer liner before the formation of the internal spacer.

[0037] Embodiments of this disclosure have high resistance to dry etching processes and wet etching processes, while having lower overall effective capacitance (C). effThe present invention relates to internal spacer liner configurations that have an advantage in terms of ). Several embodiments are internal spacer liner configurations for GAA device dimensions less than 3 nm, which have an overall lower effective capacitance (C) compared to conventional internal spacers that do not have an internal spacer liner in the GAA device being compared. eff This article focuses on internal spacer liner configurations that have an advantage in this regard. The presence of internal spacer liners along the side walls improves the wire-release process window, which is expected to be an advantage for static random-access memory (SRAM) yield.

[0038] In some embodiments, the amorphous silicon liner 250 is formed before the internal spacer 260 is deposited, and the amorphous silicon liner 250 and the internal spacer 260 are formed in a single step by the same deposition process. Herein, “amorphous silicon” or “a-Si” refers to a silicon-containing layer / film deposited without a crystalline structure. In one or more embodiments, the amorphous silicon liner 250 and the internal spacer 260 are formed by flowing any suitable silicon precursor. While the amorphous silicon liner 250 is deposited, the flow of a second precursor source, such as a carbon source, an oxygen source, and / or a nitrogen source, is stopped. While the internal spacer 260 is deposited, the flow of the second precursor source, such as a carbon source, an oxygen source, and / or a nitrogen source, is turned on to form an internal spacer containing a low dielectric material, such as one or more of silicon oxycarbide (SiOC) or silicon oxynitride (SiON). In one or more embodiments, the chemical vapor deposition (CVD) process is carried out at a temperature in the range of 400°C to 650°C. In one or more embodiments, the amorphous silicon liner 250 and the internal spacer 260 are formed at different temperatures in the range of 400°C to 650°C.

[0039] In some embodiments, the amorphous silicon liner 250 is formed along the GAA device, including along the recessed semiconductor material layer 226' and the corresponding multiple channel layers 224. In some embodiments, the internal spacers 260 are formed directly on the amorphous silicon liner 250. In some embodiments, the amorphous silicon liner 250 is formed conformally along the recessed semiconductor material layer 226' and the corresponding multiple channel layers 224, and along the sidewall spacers 214. In some embodiments, the internal spacers 260 are adjacent to the source trench 232 and the drain trench 234.

[0040] The thermal CVD (chemical vapor deposition) process of step 108 may be carried out until the amorphous silicon liner 250 and the internal spacer 260 are formed to the desired thickness. In some embodiments, the amorphous silicon liner 250 has a thickness in the range of 0.5 nm to 3 nm, including all partial ranges and values ​​within that range. In some embodiments, the thickness of the amorphous silicon liner 250 varies according to the silicon (Si) loss amount, which will be further described below.

[0041] The internal spacer 260 may include any suitable insulating material known in the art, such as a low-kappa dielectric material. In one or more embodiments, the low-kappa dielectric material has a kappa value in the range of 3 to 5. In some embodiments, the low-kappa dielectric material of the internal spacer 260 includes one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or spin-on dielectrics. In some embodiments, the low-kappa dielectric material of the internal spacer 260 includes one or more of silicon oxycarbide (SiOC) or silicon oxynitride (SiON). In some embodiments, the internal spacer 260 includes a thickness in the range of 2 nm to 5 nm, including any partial range and value therein.

[0042] In some embodiments, the amorphous silicon liner 250 has a thickness in the range of 0.5 nm to 3 nm, and the internal spacer 260 has a thickness in the range of 2 nm to 5 nm, including any partial range and value in between. In one or more embodiments, the amorphous silicon liner 250 and the internal spacer 260 are formed in situ within an integrated processing tool. In some embodiments, the amorphous silicon liner 250 is formed before the internal spacer 260 is deposited, and the amorphous silicon liner 250 and the internal spacer 260 are formed in a single step by the same deposition process (e.g., the CVD process of step 110 of method 100).

[0043] In some embodiments, the amorphous silicon liner 250 is formed conformally along the recessed semiconductor material layer 226' and the corresponding multiple channel layers 224, and along the sidewall spacers 214. Herein, the term “conformal” means that the layer conforms to the contour of a feature or a layer. The conformality of a layer is typically quantified by the ratio of the average thickness of a layer deposited on the sidewall of a feature to the average thickness of the same deposited layer on the field (or top surface) of the substrate. In some embodiments, one or more of the amorphous silicon liner 250 and the internal spacers 260 have conformality in the range of 70% to 90%. In this regard, conformality within the range of 70% to 90% means that the ratio of the average thickness of the above-mentioned layer deposited on the sidewall of a certain feature to the average thickness of the same deposited layer on the field (or top surface) of the substrate is within the range of 70% to 90%.

[0044] The amorphous silicon liner 250 and the internal spacer 260 can define any suitable shape, including but not limited to circular, square, rectangular, or other polygonal shapes.

[0045] In some embodiments, the amorphous silicon liner 250 and the internal spacer 260 are substantially free of seams and / or voids. In this regard, "substantially free" means that, on an atomic basis, seams and / or voids are present in amounts less than 5%, 4%, 3%, 2%, 1%, 0.5%, and 0.1% of the total composition of the amorphous silicon liner 250 and the internal spacer 260, respectively.

[0046] Referring to Figure 2E, in step 112, method 100 includes etching a portion of the internal spacer 260 to form an etched internal spacer 260'. The etching process in step 112 may include, but is not limited to, any suitable etching process including the pre-cleaning process, wet etching process, or dry etching process described herein. In one or more embodiments, the internal spacer 260 and the amorphous silicon liner for forming the etched internal spacer 260' are etched from the sidewall spacer 214.

[0047] Referring to Figure 2F, Method 100 includes a source / drain epitaxial growth and interlayer dielectric formation process (step 114) and substitution metal gate formation and polysilicon removal (step 116). In Figure 2F, the GAA device includes a highly doped epitaxy source / drain junction 270, a protective dielectric layer 272 on the highly doped epitaxy source / drain junction 270, such as silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof, and an interlayer dielectric 274 formed on the protective dielectric layer 272. Such processes and layers shown in Figure 2F are known to those skilled in the art.

[0048] In some embodiments, in step 116, the dummy gate structure 209 is removed to expose the channel region of the superlattice structure 204. The layers 270, 272, and 274 protect the source / drain trench 232 / 234 while the dummy gate structure 209 is removed. The dummy gate structure 209 can be removed using any conventional etching process, such as the pre-cleaning process, wet etching process, or dry etching process described herein. In some embodiments, the dummy gate structure 209 includes one or more of the sacrificial oxide layer 210 and the dummy gate polysilicon layer 212, and the entire dummy gate structure 209 is removed by a selective etching process. In embodiments, if the dummy gate structure 209 includes sidewall spacers such as sidewall spacers 214, the sidewall spacers 214 are not removed in step 112.

[0049] Referring to Figure 2G, in step 118, method 100 includes removing a recessed semiconductor material layer 226' within the superlattice structure 204. In step 118, the recessed semiconductor material layer 226' is selectively etched among a plurality of channel layers 224 within the superlattice structure 204. For example, if the superlattice structure 204 is composed of silicon (Si) layers and silicon germanium (SiGe) layers, the silicon germanium (SiGe) is selectively etched to form channel nanowires. The recessed semiconductor material layer 226', for example containing silicon germanium (SiGe), can be removed using any well-known etchant that is selective to the plurality of channel layers 224, where the etchant etches the recessed semiconductor material layer 226' at a much faster rate than the plurality of channel layers 224. In some embodiments, a pre-cleaning process, a selective dry etching process, or a wet etching process as described herein may be used. In some embodiments, when multiple channel layers 224 are silicon (Si) and the recessed semiconductor material layer 226' is silicon germanium (SiGe), the silicon germanium layer can be selectively removed using wet etchants such as, but not limited to, aqueous carboxylic acid / nitric acid / HF aqueous solution and aqueous citric acid / nitric acid / HF aqueous solution.

[0050] In one or more embodiments, as shown in Figure 2G, the removal of multiple semiconductor material layers 226 (and / or recessed semiconductor material layers 226') leaves voids between multiple channel layers 224. The voids between the multiple channel layers 224 have a thickness of approximately 3 nm to approximately 20 nm, including any partial range and value between them. The remaining channel layers 224 form a vertical array of channel nanowires coupled to the source / drain regions within source / drain trenches 232, 234. The channel nanowires extend parallel to the upper surface 202 of the substrate 200 and are aligned with each other to form a single row of channel nanowires.

[0051] Referring to Figure 2H, in step 120, method 100 includes etching a portion of the amorphous silicon liner 250 to form an etched amorphous silicon liner 250'. In one or more embodiments, the portion of the amorphous silicon liner 250 etched in step 120 is a portion previously formed along a recessed semiconductor material layer 226', which is removed in step 118 shown in Figure 2G. In one or more embodiments, the portion of the amorphous silicon liner 250 formed along the recessed semiconductor material layer 226' (removed in step 118 shown in Figure 2G) may be referred to as an inner sidewall or inner sidewall portion. The portion of the amorphous silicon liner 250 formed along a plurality of channel layers 224 is not etched.

[0052] In step 120, the portion of the amorphous silicon liner 250 formed along the inner sidewall is etched to form the etched amorphous silicon liner 250', thereby improving the effective capacitance (C) of the GAA device, as measured by fF / μm (femtofarads per micrometer), compared to a GAA device without an internal spacer liner. eff It was found to be advantageous that ) would be reduced.

[0053] For example, in some embodiments, the amorphous silicon liner 250 has a thickness of about 1 nm, and the internal spacer 260 comprises a low dielectric constant dielectric material having a κ value of 4 when there is a silicon (Si) loss of about 1 nm. In a particular embodiment, where the amorphous silicon liner 250 has a thickness of about 1 nm, the internal spacer 260 comprises a low dielectric constant dielectric material having a κ value of 4 when there is a silicon (Si) loss of about 1 nm, and a portion of the amorphous silicon liner 250 formed along the inner sidewall is etched in step 116 to form an etched amorphous silicon liner 250', the GAA device has an effective capacitance (C) measured in fF / μm compared to a GAA device without an internal spacer liner.eff ) is reduced.

[0054] In another embodiment, the amorphous silicon liner 250 has a thickness of about 2 nm, and the inner spacer 260 comprises a low-k dielectric material having a κ value of 4 when there is about 1 nm of silicon (Si) loss. In a specific embodiment where the amorphous silicon liner 250 has a thickness of about 2 nm, the inner spacer 260 comprises a low-k dielectric material having a κ value of 4 when there is about 1 nm of silicon (Si) loss, and the portion of the amorphous silicon liner 250 formed along the inner sidewall is etched in step 116 to form an etched amorphous silicon liner 250', the GAA device has a DC performance gain compared to a GAA device without an inner spacer liner.

[0055] With a GAA device having the etched amorphous silicon liner 250', at the same effective capacitance (C eff ) measured in fF / μm, it has been advantageously found that, as a result, DC performance is improved by about 40% in a GAA device having the amorphous silicon liner 250.

[0056] In some embodiments, the amorphous silicon liner 250 has a thickness in the range of 0.5 nm to 3 nm, including all subranges and values therebetween. It has been found that an amorphous silicon liner having a thickness greater than 3 nm has an overall larger effective capacitance (C eff ) compared to the amorphous silicon liner 250 described herein.

[0057] Referring to Figure 2I, in step 122, method 100 includes forming an interlayer dielectric (ILD) 276 on each of the remaining channel layers 224. In some embodiments, the ILD 276 seals the remaining channel layers 224 and covers all portions of the channel layers 224 except for the portion covered by the etched amorphous silicon liner 250'. The ILD 276 can be deposited using conventional chemical vapor deposition methods (e.g., plasma-enhanced chemical vapor deposition and low-pressure chemical vapor deposition). In one or more embodiments, the ILD 276 is formed from any suitable dielectric material, including, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride.

[0058] Referring to Figure 2J, in step 124, method 100 includes one or more processes known to those skilled in the art for completing the hGAA device, e.g., substitution metal gate formation. In one or more embodiments, a high-kappa dielectric 278 is formed on the ILD 276. The high-kappa dielectric 278 can be any suitable high-kappa dielectric material deposited by any suitable deposition technique known to those skilled in the art. In some embodiments, the high-kappa dielectric 278 includes hafnium oxide. In some embodiments, a conductive material such as titanium nitride (TiN), tungsten (W), cobalt (Co), or aluminum (Al) is deposited on the high-kappa dielectric. The conductive material can be formed using any suitable deposition process, such as atomic layer deposition (ALD), but is not limited to, ensuring that a layer of uniform thickness is formed around each of the multiple channel layers 224.

[0059] Additional embodiments of this disclosure, as shown in Figure 3, relate to a processing system 400 for forming amorphous silicon liners 250 and internal spacers 260 of electronic devices (e.g., GAA devices), and the method described herein. Examples of processing systems that can be appropriately modified in accordance with the teachings provided herein include the Centura®, Dual ACP, Producer® GT, and Endura® platforms, available from Applied Materials®, Inc., Santa Clara, California, and other processing systems may also be available. It is envisioned that other processing systems (including those from other manufacturers) may be adapted to benefit from the embodiments described herein.

[0060] The processing system 400 may include any dielectric deposition product (DDP) available from Applied Materials®, Inc., Santa Clara, California. In some embodiments, the processing system 400 includes a low dielectric constant silicon oxycarbide (SiOC) dielectric chemical vapor deposition (CVD) chamber. In some embodiments, the processing system 400 includes an advanced unit process solution by combining the low dielectric constant silicon oxycarbide (SiOC) dielectric chemical vapor deposition (CVD) chamber with a Sym3® etching system available from Applied Materials®, Inc., Santa Clara, California, providing an integrated tool solution (e.g., an integrated cyclic CVD deposition and etching system).

[0061] In some embodiments, one or more steps of the method disclosed herein are performed in situ as described herein. In some embodiments, one or more steps of the method disclosed herein are performed ex situ as described herein. In some embodiments, one or more steps of method 100 are performed in situ within an integrated processing tool, for example, within a processing system 400. Hereinafter, the terms “integrated processing tool,” “integrated tool system,” “cluster tool,” “processing tool,” and “processing system 400” may be used interchangeably to refer to the processing system 400 shown in Figure 3, unless otherwise specified.

[0062] One or more steps of Method 100 are performed in-house by an integrated module within an integrated processing tool system, for example, within a processing system 400. Unless otherwise specified, the integrated modules described herein are performed in-house within an integrated processing tool system, for example, within a processing system 400.

[0063] In some embodiments, the processing system 400 includes an integrated module for performing a pre-cleaning process before the formation of the internal spacer liner and internal spacers (step 108 of Method 100), and for performing a thermal CVD process to form the amorphous silicon liner and internal spacers within the superlattice structure (step 110 of Method 100).

[0064] In some embodiments, the processing system 400 includes an integrated module for performing a pre-cleaning process before forming the internal spacer liner and internal spacers (step 108 of Method 100), for performing a thermal CVD process to form the amorphous silicon liner and internal spacers within the superlattice structure (step 110 of Method 100), and for etching a portion of the internal spacers (step 112 of Method 100).

[0065] In some embodiments, the processing system 400 is also particularly useful for forming contact / sidewall spacers in applications of horizontal word lines in 3D memory.

[0066] In some embodiments, the steps of the method described herein are performed in the same processing chamber. In some embodiments, the steps of the method described herein are performed in different processing chambers. In some embodiments, various processing chambers are connected as part of a processing system. In some embodiments, the steps of the method described herein are performed without vacuum breakage.

[0067] Figure 3 is a schematic top view of an example of a multi-chamber processing system 400 according to an embodiment of the present disclosure. The processing system 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 having transfer robots 412, 414 respectively, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As described in detail herein, wafers in the processing system 400 can be processed in various chambers and transferred between various chambers without exposing the wafers to the ambient environment outside the processing system 400 (e.g., the atmospheric environment that may be present in the factory). For example, wafers can be processed in various chambers and transferred between various chambers without disrupting the low-pressure or vacuum environment during various processes performed on the wafers in the processing system 400 in a low-pressure (e.g., about 300 Torr or less) or vacuum environment. Thus, the processing system 400 can provide an integrated solution for any processing of wafers.

[0068] In the example shown in Figure 3, the factory interface 402 includes a docking station 440 and a factory interface robot 442 to facilitate substrate transfer. The docking station 440 is configured to accommodate one or more front-opening unified pods (FOUPs) 444. In some examples, each factory interface robot 442 generally includes a blade 448, which is located at one end of each factory interface robot 442 and configured to transfer wafers from the factory interface 402 to the load lock chambers 404, 406.

[0069] Load lock chambers 404 and 406 have ports 450 and 452, respectively, connected to the factory interface 402, and ports 454 and 456, respectively, connected to the transfer chamber 408. Transfer chamber 408 further has ports 458 and 460, respectively, connected to the holding chambers 416 and 418, and ports 462 and 464, respectively, connected to the processing chambers 420 and 422. Similarly, transfer chamber 410 has ports 466 and 468, respectively, connected to the holding chambers 416 and 418, and ports 470, 472, 474, and 476, respectively, connected to the processing chambers 424, 426, 428, and 430. Ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, and 476 may be slit valve openings, for example, for passing wafers by transfer robots 412 and 414, and for providing seals between each chamber to prevent gas from passing between each chamber. Generally, any port is open for wafer transfer; otherwise, the port is closed.

[0070] The load lock chambers 404, 406, transfer chambers 408, 410, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430 may be fluidically coupled to a gas and pressure control system (not shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), a gas source, various valves, and conduits fluidly coupled to the various chambers. During operation, the factory interface robot 442 transfers wafers from the FOUP 444 to the load lock chamber 404 or 406 via port 450 or 452. The gas and pressure control system then pumps down (vacuums) the load lock chamber 404 or 406. The gas and pressure control system further maintains the transfer chambers 408, 410 and the holding chambers 416, 418 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, pumping down the load lock chamber 404 or 406 facilitates passing the wafer between, for example, the atmospheric environment of the factory interface 402 and the low-pressure or vacuum environment of the transfer chamber 408.

[0071] With the wafer in the load lock chamber 404 or 406 being pumped down, the transfer robot 412 transfers the wafer from the load lock chamber 404 or 406 to the transfer chamber 408 via port 454 or 456. The transfer robot 412 can then transfer the wafer to and / or between the processing chambers 420 and 422 via their respective ports 462 and 464 for processing, and can transfer the wafer to the holding chambers 416 and 418 via their respective ports 458 and 460 for holding in awaiting further transfer. Similarly, the transfer robot 414 can access wafers in the holding chamber 416 or 418 via port 466 or 468, and can transfer wafers to and / or between the processing chambers 424, 426, 428, and 430 via their respective ports 470, 472, 474, and 476 for processing, and can transfer wafers to the holding chambers 416 and 418 via their respective ports 466 and 468 for holding in awaiting further transfer. The transfer and holding of wafers within and between the various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0072] Processing chambers 420, 422, 424, 426, 428, and 430 can be any suitable chamber for processing wafers. In some embodiments, processing chambers 420, 422, 424, 426, 428, and 430 include a pre-cleaning chamber, a chemical vapor deposition (CVD) chamber, and an etching chamber. In some embodiments, processing chamber 420 can perform an annealing process, processing chamber 422 can perform a cleaning process, and processing chambers 424, 426, 428, and 430 can perform epitaxial growth processes. In some examples, processing chamber 422 can perform a cleaning process, processing chamber 420 can perform an etching process, and processing chambers 424, 426, 428, and 430 can perform their respective epitaxial growth processes. Processing chamber 422 may be a SiCoNi® pre-cleaning chamber available from Applied Materials, Inc. of Santa Clara, California. The processing chamber 420 may be a Selectra® etching chamber, available from Applied Materials, Inc. in Santa Clara, California.

[0073] The system controller 490 is connected to the processing system 400 to control the processing system 400 or its components. For example, the system controller 490 can control the operation of the processing system 400 by using direct control of the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, and 430 of the processing system 400, or by controlling controllers associated with the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, and 430. During operation, the system controller 490 enables data collection and feedback from each chamber to adjust the performance of the processing system 400.

[0074] The system controller 490 generally includes a central processing unit (CPU) 492, memory 494, and support circuitry 496. The CPU 492 may be one of any form of general-purpose processor available for use in an industrial environment. Memory 494, or non-temporary computer-readable media, is accessible by the CPU 492 and may be one or more memories such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or other forms of local or remote digital storage. Support circuitry 496 is connected to the CPU 492 and may include a cache, clock circuitry, input / output subsystems, and power supply, etc. Various methods disclosed herein can generally be executed by the CPU 492, under the control of the CPU 492, for example, by executing computer instruction code stored in memory 494 (or memory of a particular process chamber) as a software routine. When computer instruction code is executed by the CPU 492, the CPU 492 controls the chamber to execute the process according to various methods.

[0075] Other processing systems may have different configurations. For example, more or fewer processing chambers may be connected to the transfer device. In the illustrated example, the transfer device includes transfer chambers 408, 410 and holding chambers 416, 418. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as transfer devices within the processing system.

[0076] The process may generally be stored in the memory of the system controller 490 as a software routine that, when executed by a processor, causes a processing chamber to execute the process of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown) located separately from the hardware controlled by the processor. Some or all of the method of the present disclosure may also be executed in hardware. Thus, the process may be implemented in software and executed using a computer system with hardware, for example, as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software routine transforms a general-purpose computer into an application-specific computer (controller) that controls the processing of the chamber so that the process can be executed.

[0077] One or more embodiments of the present disclosure relate to a non-transient computer-readable medium containing instructions which, when executed by a controller of a processing chamber, causes the processing chamber to perform the methods described herein, for example, method 100.

[0078] In the context of describing the materials and methods discussed herein (particularly in the context of the following claims), the terms “a” and “an” and “the,” as well as the use of similar referents, should be interpreted as covering both singular and plural forms unless otherwise stated herein or unless the context clearly contradicts this. Numerical ranges described herein are intended merely as abbreviations to refer individually to each distinct value falling within that range, unless otherwise indicated herein, and each distinct value is incorporated into the specification as if it were individually described herein. All methods described herein may be performed in any appropriate order unless otherwise indicated herein or unless the context clearly contradicts this. Any and all examples or illustrative language provided herein (e.g., “such as”) are intended merely to better describe the materials and methods and do not impose any limitation of scope unless specifically asserted. No language herein should be interpreted as indicating an element not claimed as essential to the practice of the disclosed materials and methods.

[0079] Throughout this specification, any reference to “one embodiment,” “certain embodiments,” “one or more embodiments,” or “an embodiment” means that a particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, phrases such as “in one or more embodiments,” “in certain embodiments,” “in one embodiment,” or “in an embodiment” found in various parts of this specification do not necessarily refer to the same embodiment of this disclosure. Furthermore, particular features, structures, materials, or properties can be combined in any suitable way in one or more embodiments.

[0080] While the disclosures herein are described with reference to specific embodiments, those skilled in the art will understand that the embodiments described are merely illustrative of the principles and uses of this disclosure. It will be apparent to those skilled in the art that various modifications and changes can be made to the methods and apparatuses described herein without departing from the spirit and scope of this disclosure. Accordingly, this disclosure may include modifications and changes that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing electronic devices, The method involves forming a superlattice structure on the upper surface of a semiconductor substrate, wherein the superlattice structure includes a plurality of semiconductor material layers and a plurality of corresponding channel layers arranged alternately by a plurality of stacked pairs. The process involves creating recesses in portions of the aforementioned multiple semiconductor material layers to form a recessed semiconductor material layer, Forming an amorphous silicon liner conformally along the electronic device, including along the recessed semiconductor material layer and the corresponding plurality of channel layers, The method involves directly forming internal spacers on the amorphous silicon liner, wherein the internal spacers are adjacent to the source region and the drain region. Methods that include...

2. The method according to claim 1, further comprising pre-cleaning the semiconductor substrate before forming the amorphous silicon liner and the internal spacer.

3. The method according to claim 2, wherein the pre-cleaning of the semiconductor substrate, the formation of the amorphous silicon liner, and the formation of the internal spacer are performed within an integrated tool system without vacuum breakage.

4. The method according to claim 1, wherein the amorphous silicon liner has a thickness in the range of 0.5 nm to 3 nm.

5. The method according to claim 1, wherein the amorphous silicon liner and the internal spacer are formed by a chemical vapor deposition (CVD) process at a temperature in the range of 400°C to 650°C.

6. The method according to claim 1, wherein the internal spacer includes a low dielectric constant dielectric material.

7. The method according to claim 6, wherein the low dielectric constant dielectric material has a κ value in the range of 3 to 5.

8. The method according to claim 6, wherein the low dielectric constant dielectric material comprises one or more of silicon oxycarbide (SiOC) or silicon oxynitride (SiON).

9. The method according to claim 1, wherein each of the amorphous silicon liner and the internal spacer is substantially free of seams and / or voids.

10. The method according to claim 1, wherein the plurality of semiconductor material layers include silicon germanium (SiGe), and the corresponding plurality of channel layers include silicon (Si).

11. The method according to claim 1, further comprising etching a portion of the internal spacer.

12. A method for manufacturing a gate-all-around (GAA) device, The pre-cleaning of a semiconductor substrate, wherein the semiconductor substrate has a superlattice structure formed on its upper surface, and the superlattice structure includes a plurality of recessed semiconductor material layers and a plurality of corresponding channel layers arranged alternately by a plurality of stacked pairs. The process involves performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and internal spacers within the scope of the superlattice structure, wherein the amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layer and the corresponding plurality of channel layers, and the internal spacers are formed directly on the amorphous silicon liner, and the amorphous silicon liner and internal spacers are formed within the scope of the superlattice structure adjacent to the source region and drain region. Etching a portion of the aforementioned internal spacer, The replacement metal gate and the recessed semiconductor material layer are removed from the semiconductor substrate, and then the inner sidewall portion of the amorphous silicon liner is etched. Methods that include...

13. The method according to claim 12, wherein the pre-cleaning of the semiconductor substrate, the formation of the amorphous silicon liner, and the formation of the internal spacer are performed within an integrated tool system without vacuum breakage.

14. The method according to claim 12, wherein the amorphous silicon liner and the internal spacer are formed at a temperature in the range of 400°C to 650°C.

15. The method according to claim 12, wherein each of the amorphous silicon liner and the internal spacer is substantially free of seams and / or voids.

16. The method according to claim 12, wherein the amorphous silicon liner has a thickness in the range of 0.5 nm to 3 nm.

17. The method according to claim 12, wherein the internal spacer comprises a low dielectric constant dielectric material having a κ value in the range of 3 to 5.

18. The method according to claim 17, wherein the low dielectric constant dielectric material comprises one or more of silicon oxycarbide (SiOC) or silicon oxynitride (SiON).

19. It is a processing tool, A central transfer station including a robot configured to move semiconductor substrates, A plurality of processing stations, each processing station connected to the central transfer station and providing a processing area separated from the processing area of ​​an adjacent processing station, the plurality of processing stations including a pre-washing chamber and a chemical vapor deposition (CVD) chamber, A controller connected to the central transfer station and the plurality of processing stations, configured to operate a robot to move the semiconductor substrate between processing stations and to control the processing cycle for forming an amorphous silicon liner for a gate-all-around (GAA) device, The processing cycle includes, The pre-cleaning of the semiconductor substrate, wherein the semiconductor substrate has a superlattice structure formed on its upper surface, and the superlattice structure includes a plurality of recessed semiconductor material layers and a plurality of corresponding channel layers arranged alternately by a plurality of stacked pairs, The method involves performing a chemical vapor deposition (CVD) process to form amorphous silicon liners and internal spacers within the scope of the superlattice structure, wherein the amorphous silicon liners are conformally formed along the GAA device, including along the recessed semiconductor material layer and the corresponding plurality of channel layers, and the internal spacers are formed directly on the amorphous silicon liners, and the internal spacers are adjacent to the source region and drain region, thereby forming amorphous silicon liners and internal spacers. Processing tools, including...

20. The processing tool according to claim 19, wherein the plurality of processing stations further include etching chambers for etching a portion of the internal spacers.

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